from:"Albion Fung via Phabricator via cfe\-commits"

[PATCH] D112680: [OpenMP] Lower printf to __llvm_omp_vprintf

2021-11-08 Thread Albion Fung via Phabricator via cfe-commits

Conanap added a comment.

thanks for reverting!


Repository:
  rG LLVM Github Monorepo

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[PATCH] D112680: [OpenMP] Lower printf to __llvm_omp_vprintf

2021-11-08 Thread Albion Fung via Phabricator via cfe-commits

Conanap added a comment.

Hello,

looks like this commit might be causing some failures on PowerPC buildbots, 
would you be able to take a quick look? Failing test case is `Clang :: 
OpenMP/nvptx_target_printf_codegen.c`.

Buildbot link: 
https://lab.llvm.org/buildbot/#/builders/105/builds/17248/steps/7/logs/FAIL__Clang__nvptx_target_printf_codegen_c

Thanks!


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[PATCH] D111258: [PowerPC] Emit dcbt and dcbtst in place of their extended mnemonics on AIX

2021-10-12 Thread Albion Fung via Phabricator via cfe-commits

This revision was automatically updated to reflect the committed changes.
Closed by commit rGb4b9f9b4b3cf: [PowerPC] Emit dcbt and dcbtst in place of 
their extended mnemonics on AIX (authored by Conanap).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D111258/new/

https://reviews.llvm.org/D111258

Files:
  llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-prefetch.ll


Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-prefetch.ll
===
--- llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-prefetch.ll
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-prefetch.ll
@@ -26,14 +26,14 @@
 ; CHECK-AIX:   # %bb.0: # %entry
 ; CHECK-AIX-NEXT:lwz 3, L..C0(2) # @vpa
 ; CHECK-AIX-NEXT:lwz 3, 0(3)
-; CHECK-AIX-NEXT:dcbtstt 0, 3
+; CHECK-AIX-NEXT:dcbtst 0, 3, 16
 ; CHECK-AIX-NEXT:blr
 ;
 ; CHECK-AIX64-LABEL: test_dcbtstt:
 ; CHECK-AIX64:   # %bb.0: # %entry
 ; CHECK-AIX64-NEXT:ld 3, L..C0(2) # @vpa
 ; CHECK-AIX64-NEXT:ld 3, 0(3)
-; CHECK-AIX64-NEXT:dcbtstt 0, 3
+; CHECK-AIX64-NEXT:dcbtst 0, 3, 16
 ; CHECK-AIX64-NEXT:blr
 entry:
   %0 = load i8*, i8** @vpa, align 8
@@ -55,14 +55,14 @@
 ; CHECK-AIX:   # %bb.0: # %entry
 ; CHECK-AIX-NEXT:lwz 3, L..C0(2) # @vpa
 ; CHECK-AIX-NEXT:lwz 3, 0(3)
-; CHECK-AIX-NEXT:dcbtt 0, 3
+; CHECK-AIX-NEXT:dcbt 0, 3, 16
 ; CHECK-AIX-NEXT:blr
 ;
 ; CHECK-AIX64-LABEL: test_dcbtt:
 ; CHECK-AIX64:   # %bb.0: # %entry
 ; CHECK-AIX64-NEXT:ld 3, L..C0(2) # @vpa
 ; CHECK-AIX64-NEXT:ld 3, 0(3)
-; CHECK-AIX64-NEXT:dcbtt 0, 3
+; CHECK-AIX64-NEXT:dcbt 0, 3, 16
 ; CHECK-AIX64-NEXT:blr
 entry:
   %0 = load i8*, i8** @vpa, align 8
Index: llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp
===
--- llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp
+++ llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp
@@ -158,7 +158,10 @@
   //dcbt ra, rb, th [server]
   //dcbt th, ra, rb [embedded]
   //  where th can be omitted when it is 0. dcbtst is the same.
-  if (MI->getOpcode() == PPC::DCBT || MI->getOpcode() == PPC::DCBTST) {
+  // On AIX, only emit the extended mnemonics for dcbt and dcbtst if
+  // the "modern assembler" is available.
+  if ((MI->getOpcode() == PPC::DCBT || MI->getOpcode() == PPC::DCBTST) &&
+  (!TT.isOSAIX() || STI.getFeatureBits()[PPC::FeatureModernAIXAs])) {
 unsigned char TH = MI->getOperand(0).getImm();
 O << "\tdcbt";
 if (MI->getOpcode() == PPC::DCBTST)


Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-prefetch.ll
===
--- llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-prefetch.ll
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-prefetch.ll
@@ -26,14 +26,14 @@
 ; CHECK-AIX:   # %bb.0: # %entry
 ; CHECK-AIX-NEXT:lwz 3, L..C0(2) # @vpa
 ; CHECK-AIX-NEXT:lwz 3, 0(3)
-; CHECK-AIX-NEXT:dcbtstt 0, 3
+; CHECK-AIX-NEXT:dcbtst 0, 3, 16
 ; CHECK-AIX-NEXT:blr
 ;
 ; CHECK-AIX64-LABEL: test_dcbtstt:
 ; CHECK-AIX64:   # %bb.0: # %entry
 ; CHECK-AIX64-NEXT:ld 3, L..C0(2) # @vpa
 ; CHECK-AIX64-NEXT:ld 3, 0(3)
-; CHECK-AIX64-NEXT:dcbtstt 0, 3
+; CHECK-AIX64-NEXT:dcbtst 0, 3, 16
 ; CHECK-AIX64-NEXT:blr
 entry:
   %0 = load i8*, i8** @vpa, align 8
@@ -55,14 +55,14 @@
 ; CHECK-AIX:   # %bb.0: # %entry
 ; CHECK-AIX-NEXT:lwz 3, L..C0(2) # @vpa
 ; CHECK-AIX-NEXT:lwz 3, 0(3)
-; CHECK-AIX-NEXT:dcbtt 0, 3
+; CHECK-AIX-NEXT:dcbt 0, 3, 16
 ; CHECK-AIX-NEXT:blr
 ;
 ; CHECK-AIX64-LABEL: test_dcbtt:
 ; CHECK-AIX64:   # %bb.0: # %entry
 ; CHECK-AIX64-NEXT:ld 3, L..C0(2) # @vpa
 ; CHECK-AIX64-NEXT:ld 3, 0(3)
-; CHECK-AIX64-NEXT:dcbtt 0, 3
+; CHECK-AIX64-NEXT:dcbt 0, 3, 16
 ; CHECK-AIX64-NEXT:blr
 entry:
   %0 = load i8*, i8** @vpa, align 8
Index: llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp
===
--- llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp
+++ llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp
@@ -158,7 +158,10 @@
   //dcbt ra, rb, th [server]
   //dcbt th, ra, rb [embedded]
   //  where th can be omitted when it is 0. dcbtst is the same.
-  if (MI->getOpcode() == PPC::DCBT || MI->getOpcode() == PPC::DCBTST) {
+  // On AIX, only emit the extended mnemonics for dcbt and dcbtst if
+  // the "modern assembler" is available.
+  if ((MI->getOpcode() == PPC::DCBT || MI->getOpcode() == PPC::DCBTST) &&
+  (!TT.isOSAIX() || STI.getFeatureBits()[PPC::FeatureModernAIXAs])) {
 unsigned char TH = MI->getOperand(0).getImm();
 O << "\tdcbt";
 if (MI->getOpcode() == PPC::DCBTST)
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[PATCH] D111258: [PowerPC] Emit dcbt and dcbtst in place of their extended mnemonics on AIX

2021-10-07 Thread Albion Fung via Phabricator via cfe-commits

Conanap updated this revision to Diff 378015.
Conanap marked 2 inline comments as done.
Conanap added a comment.

Added mordern assembler check


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D111258/new/

https://reviews.llvm.org/D111258

Files:
  llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-prefetch.ll


Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-prefetch.ll
===
--- llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-prefetch.ll
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-prefetch.ll
@@ -26,14 +26,14 @@
 ; CHECK-AIX:   # %bb.0: # %entry
 ; CHECK-AIX-NEXT:lwz 3, L..C0(2) # @vpa
 ; CHECK-AIX-NEXT:lwz 3, 0(3)
-; CHECK-AIX-NEXT:dcbtstt 0, 3
+; CHECK-AIX-NEXT:dcbtst 0, 3, 16
 ; CHECK-AIX-NEXT:blr
 ;
 ; CHECK-AIX64-LABEL: test_dcbtstt:
 ; CHECK-AIX64:   # %bb.0: # %entry
 ; CHECK-AIX64-NEXT:ld 3, L..C0(2) # @vpa
 ; CHECK-AIX64-NEXT:ld 3, 0(3)
-; CHECK-AIX64-NEXT:dcbtstt 0, 3
+; CHECK-AIX64-NEXT:dcbtst 0, 3, 16
 ; CHECK-AIX64-NEXT:blr
 entry:
   %0 = load i8*, i8** @vpa, align 8
@@ -55,14 +55,14 @@
 ; CHECK-AIX:   # %bb.0: # %entry
 ; CHECK-AIX-NEXT:lwz 3, L..C0(2) # @vpa
 ; CHECK-AIX-NEXT:lwz 3, 0(3)
-; CHECK-AIX-NEXT:dcbtt 0, 3
+; CHECK-AIX-NEXT:dcbt 0, 3, 16
 ; CHECK-AIX-NEXT:blr
 ;
 ; CHECK-AIX64-LABEL: test_dcbtt:
 ; CHECK-AIX64:   # %bb.0: # %entry
 ; CHECK-AIX64-NEXT:ld 3, L..C0(2) # @vpa
 ; CHECK-AIX64-NEXT:ld 3, 0(3)
-; CHECK-AIX64-NEXT:dcbtt 0, 3
+; CHECK-AIX64-NEXT:dcbt 0, 3, 16
 ; CHECK-AIX64-NEXT:blr
 entry:
   %0 = load i8*, i8** @vpa, align 8
Index: llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp
===
--- llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp
+++ llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp
@@ -158,7 +158,10 @@
   //dcbt ra, rb, th [server]
   //dcbt th, ra, rb [embedded]
   //  where th can be omitted when it is 0. dcbtst is the same.
-  if (MI->getOpcode() == PPC::DCBT || MI->getOpcode() == PPC::DCBTST) {
+  // On AIX, only emit the extended mnemonics for dcbt and dcbtst if
+  // the "modern assembler" is available.
+  if ((MI->getOpcode() == PPC::DCBT || MI->getOpcode() == PPC::DCBTST) &&
+  (!TT.isOSAIX() || STI.getFeatureBits()[PPC::FeatureModernAIXAs])) {
 unsigned char TH = MI->getOperand(0).getImm();
 O << "\tdcbt";
 if (MI->getOpcode() == PPC::DCBTST)


Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-prefetch.ll
===
--- llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-prefetch.ll
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-prefetch.ll
@@ -26,14 +26,14 @@
 ; CHECK-AIX:   # %bb.0: # %entry
 ; CHECK-AIX-NEXT:lwz 3, L..C0(2) # @vpa
 ; CHECK-AIX-NEXT:lwz 3, 0(3)
-; CHECK-AIX-NEXT:dcbtstt 0, 3
+; CHECK-AIX-NEXT:dcbtst 0, 3, 16
 ; CHECK-AIX-NEXT:blr
 ;
 ; CHECK-AIX64-LABEL: test_dcbtstt:
 ; CHECK-AIX64:   # %bb.0: # %entry
 ; CHECK-AIX64-NEXT:ld 3, L..C0(2) # @vpa
 ; CHECK-AIX64-NEXT:ld 3, 0(3)
-; CHECK-AIX64-NEXT:dcbtstt 0, 3
+; CHECK-AIX64-NEXT:dcbtst 0, 3, 16
 ; CHECK-AIX64-NEXT:blr
 entry:
   %0 = load i8*, i8** @vpa, align 8
@@ -55,14 +55,14 @@
 ; CHECK-AIX:   # %bb.0: # %entry
 ; CHECK-AIX-NEXT:lwz 3, L..C0(2) # @vpa
 ; CHECK-AIX-NEXT:lwz 3, 0(3)
-; CHECK-AIX-NEXT:dcbtt 0, 3
+; CHECK-AIX-NEXT:dcbt 0, 3, 16
 ; CHECK-AIX-NEXT:blr
 ;
 ; CHECK-AIX64-LABEL: test_dcbtt:
 ; CHECK-AIX64:   # %bb.0: # %entry
 ; CHECK-AIX64-NEXT:ld 3, L..C0(2) # @vpa
 ; CHECK-AIX64-NEXT:ld 3, 0(3)
-; CHECK-AIX64-NEXT:dcbtt 0, 3
+; CHECK-AIX64-NEXT:dcbt 0, 3, 16
 ; CHECK-AIX64-NEXT:blr
 entry:
   %0 = load i8*, i8** @vpa, align 8
Index: llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp
===
--- llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp
+++ llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp
@@ -158,7 +158,10 @@
   //dcbt ra, rb, th [server]
   //dcbt th, ra, rb [embedded]
   //  where th can be omitted when it is 0. dcbtst is the same.
-  if (MI->getOpcode() == PPC::DCBT || MI->getOpcode() == PPC::DCBTST) {
+  // On AIX, only emit the extended mnemonics for dcbt and dcbtst if
+  // the "modern assembler" is available.
+  if ((MI->getOpcode() == PPC::DCBT || MI->getOpcode() == PPC::DCBTST) &&
+  (!TT.isOSAIX() || STI.getFeatureBits()[PPC::FeatureModernAIXAs])) {
 unsigned char TH = MI->getOperand(0).getImm();
 O << "\tdcbt";
 if (MI->getOpcode() == PPC::DCBTST)
___
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[PATCH] D111258: [PowerPC] Emit dcbt and dcbtst in place of their extended mnemonics on AIX

2021-10-06 Thread Albion Fung via Phabricator via cfe-commits

Conanap created this revision.
Conanap added reviewers: nemanjai, jsji, PowerPC.
Conanap added projects: clang, LLVM, PowerPC.
Herald added subscribers: kbarton, hiraditya.
Conanap requested review of this revision.

On AIX, the system assembler does not support the extended mnemonics
`dcbtt` and `dcbtstt`. This patch stops them from being emitted on
AIX and emits the base mnemonics instead, `dcbt X, X, 16` and
`dcbtstt X, X, 16` respectively.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D111258

Files:
  llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-prefetch.ll


Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-prefetch.ll
===
--- llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-prefetch.ll
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-prefetch.ll
@@ -26,14 +26,14 @@
 ; CHECK-AIX:   # %bb.0: # %entry
 ; CHECK-AIX-NEXT:lwz 3, L..C0(2) # @vpa
 ; CHECK-AIX-NEXT:lwz 3, 0(3)
-; CHECK-AIX-NEXT:dcbtstt 0, 3
+; CHECK-AIX-NEXT:dcbtst 0, 3, 16
 ; CHECK-AIX-NEXT:blr
 ;
 ; CHECK-AIX64-LABEL: test_dcbtstt:
 ; CHECK-AIX64:   # %bb.0: # %entry
 ; CHECK-AIX64-NEXT:ld 3, L..C0(2) # @vpa
 ; CHECK-AIX64-NEXT:ld 3, 0(3)
-; CHECK-AIX64-NEXT:dcbtstt 0, 3
+; CHECK-AIX64-NEXT:dcbtst 0, 3, 16
 ; CHECK-AIX64-NEXT:blr
 entry:
   %0 = load i8*, i8** @vpa, align 8
@@ -55,14 +55,14 @@
 ; CHECK-AIX:   # %bb.0: # %entry
 ; CHECK-AIX-NEXT:lwz 3, L..C0(2) # @vpa
 ; CHECK-AIX-NEXT:lwz 3, 0(3)
-; CHECK-AIX-NEXT:dcbtt 0, 3
+; CHECK-AIX-NEXT:dcbt 0, 3, 16
 ; CHECK-AIX-NEXT:blr
 ;
 ; CHECK-AIX64-LABEL: test_dcbtt:
 ; CHECK-AIX64:   # %bb.0: # %entry
 ; CHECK-AIX64-NEXT:ld 3, L..C0(2) # @vpa
 ; CHECK-AIX64-NEXT:ld 3, 0(3)
-; CHECK-AIX64-NEXT:dcbtt 0, 3
+; CHECK-AIX64-NEXT:dcbt 0, 3, 16
 ; CHECK-AIX64-NEXT:blr
 entry:
   %0 = load i8*, i8** @vpa, align 8
Index: llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp
===
--- llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp
+++ llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp
@@ -158,7 +158,10 @@
   //dcbt ra, rb, th [server]
   //dcbt th, ra, rb [embedded]
   //  where th can be omitted when it is 0. dcbtst is the same.
-  if (MI->getOpcode() == PPC::DCBT || MI->getOpcode() == PPC::DCBTST) {
+  // TODO: AIX still requires dcbtt and dcbtstt implementation,
+  // remove AIX OS check when dcbtt and dcbtstt become available.
+  if ((MI->getOpcode() == PPC::DCBT || MI->getOpcode() == PPC::DCBTST) &&
+  !TT.isOSAIX()) {
 unsigned char TH = MI->getOperand(0).getImm();
 O << "\tdcbt";
 if (MI->getOpcode() == PPC::DCBTST)


Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-prefetch.ll
===
--- llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-prefetch.ll
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-prefetch.ll
@@ -26,14 +26,14 @@
 ; CHECK-AIX:   # %bb.0: # %entry
 ; CHECK-AIX-NEXT:lwz 3, L..C0(2) # @vpa
 ; CHECK-AIX-NEXT:lwz 3, 0(3)
-; CHECK-AIX-NEXT:dcbtstt 0, 3
+; CHECK-AIX-NEXT:dcbtst 0, 3, 16
 ; CHECK-AIX-NEXT:blr
 ;
 ; CHECK-AIX64-LABEL: test_dcbtstt:
 ; CHECK-AIX64:   # %bb.0: # %entry
 ; CHECK-AIX64-NEXT:ld 3, L..C0(2) # @vpa
 ; CHECK-AIX64-NEXT:ld 3, 0(3)
-; CHECK-AIX64-NEXT:dcbtstt 0, 3
+; CHECK-AIX64-NEXT:dcbtst 0, 3, 16
 ; CHECK-AIX64-NEXT:blr
 entry:
   %0 = load i8*, i8** @vpa, align 8
@@ -55,14 +55,14 @@
 ; CHECK-AIX:   # %bb.0: # %entry
 ; CHECK-AIX-NEXT:lwz 3, L..C0(2) # @vpa
 ; CHECK-AIX-NEXT:lwz 3, 0(3)
-; CHECK-AIX-NEXT:dcbtt 0, 3
+; CHECK-AIX-NEXT:dcbt 0, 3, 16
 ; CHECK-AIX-NEXT:blr
 ;
 ; CHECK-AIX64-LABEL: test_dcbtt:
 ; CHECK-AIX64:   # %bb.0: # %entry
 ; CHECK-AIX64-NEXT:ld 3, L..C0(2) # @vpa
 ; CHECK-AIX64-NEXT:ld 3, 0(3)
-; CHECK-AIX64-NEXT:dcbtt 0, 3
+; CHECK-AIX64-NEXT:dcbt 0, 3, 16
 ; CHECK-AIX64-NEXT:blr
 entry:
   %0 = load i8*, i8** @vpa, align 8
Index: llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp
===
--- llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp
+++ llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp
@@ -158,7 +158,10 @@
   //dcbt ra, rb, th [server]
   //dcbt th, ra, rb [embedded]
   //  where th can be omitted when it is 0. dcbtst is the same.
-  if (MI->getOpcode() == PPC::DCBT || MI->getOpcode() == PPC::DCBTST) {
+  // TODO: AIX still requires dcbtt and dcbtstt implementation,
+  // remove AIX OS check when dcbtt and dcbtstt become available.
+  if ((MI->getOpcode() == PPC::DCBT || MI->getOpcode() == PPC::DCBTST) &&
+  !TT.isOSAIX()) {
 unsigned char TH = MI->getOperand(0).getImm();
 O << "\tdcbt";
 if (MI->getOpcode() == PPC::DCBTST)

[PATCH] D110858: [PowerPC] Implement vector float and vector double version for vec_orc builtin

2021-10-06 Thread Albion Fung via Phabricator via cfe-commits

This revision was automatically updated to reflect the committed changes.
Closed by commit rG13d3cd37e278: [PowerPC] Implement vector float and vector 
double version for vec_orc builtin (authored by Conanap).

Changed prior to commit:
  https://reviews.llvm.org/D110858?vs=376273=377453#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D110858/new/

https://reviews.llvm.org/D110858

Files:
  clang/lib/Headers/altivec.h
  clang/test/CodeGen/builtins-ppc-p8vector.c


Index: clang/test/CodeGen/builtins-ppc-p8vector.c
===
--- clang/test/CodeGen/builtins-ppc-p8vector.c
+++ clang/test/CodeGen/builtins-ppc-p8vector.c
@@ -35,7 +35,9 @@
 vector unsigned __int128 vux = { 1 };
 
 vector float vfa = { 1.e-4f, -132.23f, -22.1, 32.00f };
+vector float vfb = { 1.e-4f, -132.23f, -22.1, 32.00f };
 vector double vda = { 1.e-11, -132.23e10 };
+vector double vdb = { 1.e-11, -132.23e10 };
 
 int res_i;
 double res_d;
@@ -1067,6 +1069,12 @@
 // CHECK: [[T1:%.+]] = xor <4 x i32> {{%.+}}, 
 // CHECK: or <4 x i32> {{%.+}}, [[T1]]
 // CHECK-LE: [[T1:%.+]] = xor <4 x i32> {{%.+}}, 
+// CHECK-LE: or <4 x i32> {{%.+}}, [[T1]]
+
+  res_vf = vec_orc(vfa, vfb);
+// CHECK: [[T1:%.+]] = xor <4 x i32> {{%.+}}, 
+// CHECK: or <4 x i32> {{%.+}}, [[T1]]
+// CHECK-LE: [[T1:%.+]] = xor <4 x i32> {{%.+}}, 
 // CHECK-LE: or <4 x i32> {{%.+}}, [[T1]]
 
   res_vsll = vec_orc(vsll, vsll);
@@ -1121,6 +1129,12 @@
 // CHECK: [[T1:%.+]] = xor <2 x i64> {{%.+}}, 
 // CHECK: or <2 x i64> {{%.+}}, [[T1]]
 // CHECK-LE: [[T1:%.+]] = xor <2 x i64> {{%.+}}, 
+// CHECK-LE: or <2 x i64> {{%.+}}, [[T1]]
+
+  res_vd = vec_orc(vda, vdb);
+// CHECK: [[T1:%.+]] = xor <2 x i64> {{%.+}}, 
+// CHECK: or <2 x i64> {{%.+}}, [[T1]]
+// CHECK-LE: [[T1:%.+]] = xor <2 x i64> {{%.+}}, 
 // CHECK-LE: or <2 x i64> {{%.+}}, [[T1]]
 
   /* vec_sub */
Index: clang/lib/Headers/altivec.h
===
--- clang/lib/Headers/altivec.h
+++ clang/lib/Headers/altivec.h
@@ -7109,6 +7109,11 @@
   return (vector float)((vector unsigned int)__a | ~__b);
 }
 
+static __inline__ vector float __ATTRS_o_ai vec_orc(vector float __a,
+vector float __b) {
+  return (vector float)((vector unsigned int)__a | ~(vector unsigned int)__b);
+}
+
 static __inline__ vector signed long long __ATTRS_o_ai
 vec_orc(vector signed long long __a, vector signed long long __b) {
   return __a | ~__b;
@@ -7153,6 +7158,12 @@
 vec_orc(vector bool long long __a, vector double __b) {
   return (vector double)(__a | ~(vector unsigned long long)__b);
 }
+
+static __inline__ vector double __ATTRS_o_ai vec_orc(vector double __a,
+ vector double __b) {
+  return (vector double)((vector bool long long)__a |
+ ~(vector unsigned long long)__b);
+}
 #endif
 
 /* vec_vor */


Index: clang/test/CodeGen/builtins-ppc-p8vector.c
===
--- clang/test/CodeGen/builtins-ppc-p8vector.c
+++ clang/test/CodeGen/builtins-ppc-p8vector.c
@@ -35,7 +35,9 @@
 vector unsigned __int128 vux = { 1 };
 
 vector float vfa = { 1.e-4f, -132.23f, -22.1, 32.00f };
+vector float vfb = { 1.e-4f, -132.23f, -22.1, 32.00f };
 vector double vda = { 1.e-11, -132.23e10 };
+vector double vdb = { 1.e-11, -132.23e10 };
 
 int res_i;
 double res_d;
@@ -1067,6 +1069,12 @@
 // CHECK: [[T1:%.+]] = xor <4 x i32> {{%.+}}, 
 // CHECK: or <4 x i32> {{%.+}}, [[T1]]
 // CHECK-LE: [[T1:%.+]] = xor <4 x i32> {{%.+}}, 
+// CHECK-LE: or <4 x i32> {{%.+}}, [[T1]]
+
+  res_vf = vec_orc(vfa, vfb);
+// CHECK: [[T1:%.+]] = xor <4 x i32> {{%.+}}, 
+// CHECK: or <4 x i32> {{%.+}}, [[T1]]
+// CHECK-LE: [[T1:%.+]] = xor <4 x i32> {{%.+}}, 
 // CHECK-LE: or <4 x i32> {{%.+}}, [[T1]]
 
   res_vsll = vec_orc(vsll, vsll);
@@ -1121,6 +1129,12 @@
 // CHECK: [[T1:%.+]] = xor <2 x i64> {{%.+}}, 
 // CHECK: or <2 x i64> {{%.+}}, [[T1]]
 // CHECK-LE: [[T1:%.+]] = xor <2 x i64> {{%.+}}, 
+// CHECK-LE: or <2 x i64> {{%.+}}, [[T1]]
+
+  res_vd = vec_orc(vda, vdb);
+// CHECK: [[T1:%.+]] = xor <2 x i64> {{%.+}}, 
+// CHECK: or <2 x i64> {{%.+}}, [[T1]]
+// CHECK-LE: [[T1:%.+]] = xor <2 x i64> {{%.+}}, 
 // CHECK-LE: or <2 x i64> {{%.+}}, [[T1]]
 
   /* vec_sub */
Index: clang/lib/Headers/altivec.h
===
--- clang/lib/Headers/altivec.h
+++ clang/lib/Headers/altivec.h
@@ -7109,6 +7109,11 @@
   return (vector float)((vector unsigned int)__a | ~__b);
 }
 
+static __inline__ vector float __ATTRS_o_ai vec_orc(vector float __a,
+vector float __b) {
+  return (vector float)((vector unsigned int)__a | ~(vector unsigned int)__b);
+}
+
 static __inline__ vector signed long long __ATTRS_o_ai
 vec_orc(vector signed long long __a, vector signed long long __b) {

[PATCH] D110273: [PowerPC] Fix lharx and lbarx builtin signatures

2021-09-30 Thread Albion Fung via Phabricator via cfe-commits

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG29bb877499ce: [PowerPC] Fix lharx and lbarx builtin 
signatures (authored by Conanap).

Changed prior to commit:
  https://reviews.llvm.org/D110273?vs=374908=376417#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D110273/new/

https://reviews.llvm.org/D110273

Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond.c


Index: clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond.c
===
--- clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond.c
+++ clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond.c
@@ -24,7 +24,7 @@
   return __lharx(a);
 }
 
-char test_lbarx(volatile unsigned char *a) {
+char test_lbarx(volatile char *a) {
   // CHECK-LABEL: @test_lbarx
   // CHECK: %0 = tail call i8 asm sideeffect "lbarx $0, ${1:y}", 
"=r,*Z,~{memory}"(i8* %a)
   // CHECK-NON-PWR8-ERR:  error: this builtin is only valid on POWER8 or later 
CPUs
@@ -46,3 +46,18 @@
   // CHECK-NON-PWR8-ERR:  error: this builtin is only valid on POWER8 or later 
CPUs
   return __sthcx(a, val);
 }
+
+// Extra test cases that previously caused error during usage.
+int test_lharx_intret(volatile short *a) {
+  // CHECK-LABEL: @test_lharx_intret
+  // CHECK: %0 = tail call i16 asm sideeffect "lharx $0, ${1:y}", 
"=r,*Z,~{memory}"(i16* %a)
+  // CHECK-NON-PWR8-ERR:  error: this builtin is only valid on POWER8 or later 
CPUs
+  return __lharx(a);
+}
+
+int test_lbarx_intret(volatile char *a) {
+  // CHECK-LABEL: @test_lbarx_intret
+  // CHECK: %0 = tail call i8 asm sideeffect "lbarx $0, ${1:y}", 
"=r,*Z,~{memory}"(i8* %a)
+  // CHECK-NON-PWR8-ERR:  error: this builtin is only valid on POWER8 or later 
CPUs
+  return __lbarx(a);
+}
Index: clang/include/clang/Basic/BuiltinsPPC.def
===
--- clang/include/clang/Basic/BuiltinsPPC.def
+++ clang/include/clang/Basic/BuiltinsPPC.def
@@ -74,8 +74,8 @@
 BUILTIN(__builtin_ppc_fetch_and_swaplp, "ULiULiD*ULi", "")
 BUILTIN(__builtin_ppc_ldarx, "LiLiD*", "")
 BUILTIN(__builtin_ppc_lwarx, "iiD*", "")
-BUILTIN(__builtin_ppc_lharx, "isD*", "")
-BUILTIN(__builtin_ppc_lbarx, "UiUcD*", "")
+BUILTIN(__builtin_ppc_lharx, "ssD*", "")
+BUILTIN(__builtin_ppc_lbarx, "ccD*", "")
 BUILTIN(__builtin_ppc_stdcx, "iLiD*Li", "")
 BUILTIN(__builtin_ppc_stwcx, "iiD*i", "")
 BUILTIN(__builtin_ppc_sthcx, "isD*s", "")


Index: clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond.c
===
--- clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond.c
+++ clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond.c
@@ -24,7 +24,7 @@
   return __lharx(a);
 }
 
-char test_lbarx(volatile unsigned char *a) {
+char test_lbarx(volatile char *a) {
   // CHECK-LABEL: @test_lbarx
   // CHECK: %0 = tail call i8 asm sideeffect "lbarx $0, ${1:y}", "=r,*Z,~{memory}"(i8* %a)
   // CHECK-NON-PWR8-ERR:  error: this builtin is only valid on POWER8 or later CPUs
@@ -46,3 +46,18 @@
   // CHECK-NON-PWR8-ERR:  error: this builtin is only valid on POWER8 or later CPUs
   return __sthcx(a, val);
 }
+
+// Extra test cases that previously caused error during usage.
+int test_lharx_intret(volatile short *a) {
+  // CHECK-LABEL: @test_lharx_intret
+  // CHECK: %0 = tail call i16 asm sideeffect "lharx $0, ${1:y}", "=r,*Z,~{memory}"(i16* %a)
+  // CHECK-NON-PWR8-ERR:  error: this builtin is only valid on POWER8 or later CPUs
+  return __lharx(a);
+}
+
+int test_lbarx_intret(volatile char *a) {
+  // CHECK-LABEL: @test_lbarx_intret
+  // CHECK: %0 = tail call i8 asm sideeffect "lbarx $0, ${1:y}", "=r,*Z,~{memory}"(i8* %a)
+  // CHECK-NON-PWR8-ERR:  error: this builtin is only valid on POWER8 or later CPUs
+  return __lbarx(a);
+}
Index: clang/include/clang/Basic/BuiltinsPPC.def
===
--- clang/include/clang/Basic/BuiltinsPPC.def
+++ clang/include/clang/Basic/BuiltinsPPC.def
@@ -74,8 +74,8 @@
 BUILTIN(__builtin_ppc_fetch_and_swaplp, "ULiULiD*ULi", "")
 BUILTIN(__builtin_ppc_ldarx, "LiLiD*", "")
 BUILTIN(__builtin_ppc_lwarx, "iiD*", "")
-BUILTIN(__builtin_ppc_lharx, "isD*", "")
-BUILTIN(__builtin_ppc_lbarx, "UiUcD*", "")
+BUILTIN(__builtin_ppc_lharx, "ssD*", "")
+BUILTIN(__builtin_ppc_lbarx, "ccD*", "")
 BUILTIN(__builtin_ppc_stdcx, "iLiD*Li", "")
 BUILTIN(__builtin_ppc_stwcx, "iiD*i", "")
 BUILTIN(__builtin_ppc_sthcx, "isD*s", "")
___
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[PATCH] D109902: [PowerPC] Improved codegen related to xscvdpsxws/xscvdpuxws

2021-09-30 Thread Albion Fung via Phabricator via cfe-commits

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG4195ed995993: [PowerPC] Improved codegen related to 
xscvdpsxws/xscvdpuxws (authored by Conanap).

Changed prior to commit:
  https://reviews.llvm.org/D109902?vs=375780=376327#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D109902/new/

https://reviews.llvm.org/D109902

Files:
  llvm/lib/Target/PowerPC/PPCInstrVSX.td
  llvm/test/CodeGen/PowerPC/test-vector-insert.ll
  llvm/test/CodeGen/PowerPC/vec_conv_fp64_to_i32_elts.ll

Index: llvm/test/CodeGen/PowerPC/vec_conv_fp64_to_i32_elts.ll
===
--- llvm/test/CodeGen/PowerPC/vec_conv_fp64_to_i32_elts.ll
+++ llvm/test/CodeGen/PowerPC/vec_conv_fp64_to_i32_elts.ll
@@ -13,12 +13,8 @@
 ; CHECK-P8-LABEL: test2elt:
 ; CHECK-P8:   # %bb.0: # %entry
 ; CHECK-P8-NEXT:xxswapd vs0, v2
-; CHECK-P8-NEXT:xscvdpuxws f1, v2
-; CHECK-P8-NEXT:xscvdpuxws f0, f0
-; CHECK-P8-NEXT:mffprwz r3, f1
-; CHECK-P8-NEXT:mtvsrwz v2, r3
-; CHECK-P8-NEXT:mffprwz r4, f0
-; CHECK-P8-NEXT:mtvsrwz v3, r4
+; CHECK-P8-NEXT:xscvdpuxws v2, v2
+; CHECK-P8-NEXT:xscvdpuxws v3, f0
 ; CHECK-P8-NEXT:vmrghw v2, v2, v3
 ; CHECK-P8-NEXT:xxswapd vs0, v2
 ; CHECK-P8-NEXT:mffprd r3, f0
@@ -26,26 +22,18 @@
 ;
 ; CHECK-P9-LABEL: test2elt:
 ; CHECK-P9:   # %bb.0: # %entry
-; CHECK-P9-NEXT:xscvdpuxws f0, v2
-; CHECK-P9-NEXT:mffprwz r3, f0
 ; CHECK-P9-NEXT:xxswapd vs0, v2
-; CHECK-P9-NEXT:mtvsrwz v3, r3
-; CHECK-P9-NEXT:xscvdpuxws f0, f0
-; CHECK-P9-NEXT:mffprwz r3, f0
-; CHECK-P9-NEXT:mtvsrwz v2, r3
+; CHECK-P9-NEXT:xscvdpuxws v3, v2
+; CHECK-P9-NEXT:xscvdpuxws v2, f0
 ; CHECK-P9-NEXT:vmrghw v2, v3, v2
 ; CHECK-P9-NEXT:mfvsrld r3, v2
 ; CHECK-P9-NEXT:blr
 ;
 ; CHECK-BE-LABEL: test2elt:
 ; CHECK-BE:   # %bb.0: # %entry
-; CHECK-BE-NEXT:xscvdpuxws f0, v2
-; CHECK-BE-NEXT:mffprwz r3, f0
 ; CHECK-BE-NEXT:xxswapd vs0, v2
-; CHECK-BE-NEXT:mtvsrwz v3, r3
-; CHECK-BE-NEXT:xscvdpuxws f0, f0
-; CHECK-BE-NEXT:mffprwz r3, f0
-; CHECK-BE-NEXT:mtvsrwz v2, r3
+; CHECK-BE-NEXT:xscvdpuxws v3, v2
+; CHECK-BE-NEXT:xscvdpuxws v2, f0
 ; CHECK-BE-NEXT:vmrgow v2, v3, v2
 ; CHECK-BE-NEXT:mfvsrd r3, v2
 ; CHECK-BE-NEXT:blr
@@ -305,12 +293,8 @@
 ; CHECK-P8-LABEL: test2elt_signed:
 ; CHECK-P8:   # %bb.0: # %entry
 ; CHECK-P8-NEXT:xxswapd vs0, v2
-; CHECK-P8-NEXT:xscvdpsxws f1, v2
-; CHECK-P8-NEXT:xscvdpsxws f0, f0
-; CHECK-P8-NEXT:mffprwz r3, f1
-; CHECK-P8-NEXT:mtvsrwz v2, r3
-; CHECK-P8-NEXT:mffprwz r4, f0
-; CHECK-P8-NEXT:mtvsrwz v3, r4
+; CHECK-P8-NEXT:xscvdpsxws v2, v2
+; CHECK-P8-NEXT:xscvdpsxws v3, f0
 ; CHECK-P8-NEXT:vmrghw v2, v2, v3
 ; CHECK-P8-NEXT:xxswapd vs0, v2
 ; CHECK-P8-NEXT:mffprd r3, f0
@@ -318,26 +302,18 @@
 ;
 ; CHECK-P9-LABEL: test2elt_signed:
 ; CHECK-P9:   # %bb.0: # %entry
-; CHECK-P9-NEXT:xscvdpsxws f0, v2
-; CHECK-P9-NEXT:mffprwz r3, f0
 ; CHECK-P9-NEXT:xxswapd vs0, v2
-; CHECK-P9-NEXT:mtvsrwz v3, r3
-; CHECK-P9-NEXT:xscvdpsxws f0, f0
-; CHECK-P9-NEXT:mffprwz r3, f0
-; CHECK-P9-NEXT:mtvsrwz v2, r3
+; CHECK-P9-NEXT:xscvdpsxws v3, v2
+; CHECK-P9-NEXT:xscvdpsxws v2, f0
 ; CHECK-P9-NEXT:vmrghw v2, v3, v2
 ; CHECK-P9-NEXT:mfvsrld r3, v2
 ; CHECK-P9-NEXT:blr
 ;
 ; CHECK-BE-LABEL: test2elt_signed:
 ; CHECK-BE:   # %bb.0: # %entry
-; CHECK-BE-NEXT:xscvdpsxws f0, v2
-; CHECK-BE-NEXT:mffprwz r3, f0
 ; CHECK-BE-NEXT:xxswapd vs0, v2
-; CHECK-BE-NEXT:mtvsrwz v3, r3
-; CHECK-BE-NEXT:xscvdpsxws f0, f0
-; CHECK-BE-NEXT:mffprwz r3, f0
-; CHECK-BE-NEXT:mtvsrwz v2, r3
+; CHECK-BE-NEXT:xscvdpsxws v3, v2
+; CHECK-BE-NEXT:xscvdpsxws v2, f0
 ; CHECK-BE-NEXT:vmrgow v2, v3, v2
 ; CHECK-BE-NEXT:mfvsrd r3, v2
 ; CHECK-BE-NEXT:blr
Index: llvm/test/CodeGen/PowerPC/test-vector-insert.ll
===
--- llvm/test/CodeGen/PowerPC/test-vector-insert.ll
+++ llvm/test/CodeGen/PowerPC/test-vector-insert.ll
@@ -17,8 +17,8 @@
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
 ; RUN:  -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
 ; RUN:  -mcpu=pwr9 < %s | FileCheck %s --check-prefix=CHECK-BE-P9
-; xscvdpsxws and uxws is only available on Power7 and above
-; Codgen is different for LE Power7 and Power8
+; xscvdpsxws and xscvdpsxws is only available on Power7 and above
+; Codgen is different for Power7, Power8, and Power9.
 
 define dso_local <4 x i32> @test(<4 x i32> %a, double %b) {
 ; CHECK-LE-P7-LABEL: test:
@@ -38,20 +38,16 @@
 ;
 ; CHECK-LE-P8-LABEL: test:
 ; CHECK-LE-P8:   # %bb.0: # %entry
-; CHECK-LE-P8-NEXT:xscvdpsxws f0, f1
+; CHECK-LE-P8-NEXT:xscvdpsxws v3, f1
 ; CHECK-LE-P8-NEXT:addis r3,

[PATCH] D110858: [PowerPC] Implement vector float and vector double version for vec_orc builtin

2021-09-30 Thread Albion Fung via Phabricator via cfe-commits

Conanap created this revision.
Conanap added reviewers: PowerPC, nemanjai, kamaub, saghir.
Conanap added projects: LLVM, clang, PowerPC.
Herald added a subscriber: kbarton.
Conanap requested review of this revision.

The builtin for vec_orc has support for the following two signatures,
but currently the compiler marks it ambiguous:
`vector float vec_orc(vector float, vector float)`
`vector double vec_orc(vector double, vector double)`

This patch implements these two builtins.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D110858

Files:
  clang/lib/Headers/altivec.h
  clang/test/CodeGen/builtins-ppc-p8vector.c


Index: clang/test/CodeGen/builtins-ppc-p8vector.c
===
--- clang/test/CodeGen/builtins-ppc-p8vector.c
+++ clang/test/CodeGen/builtins-ppc-p8vector.c
@@ -35,7 +35,9 @@
 vector unsigned __int128 vux = { 1 };
 
 vector float vfa = { 1.e-4f, -132.23f, -22.1, 32.00f };
+vector float vfb = { 1.e-4f, -132.23f, -22.1, 32.00f };
 vector double vda = { 1.e-11, -132.23e10 };
+vector double vdb = { 1.e-11, -132.23e10 };
 
 int res_i;
 double res_d;
@@ -1067,6 +1069,12 @@
 // CHECK: [[T1:%.+]] = xor <4 x i32> {{%.+}}, 
 // CHECK: or <4 x i32> {{%.+}}, [[T1]]
 // CHECK-LE: [[T1:%.+]] = xor <4 x i32> {{%.+}}, 
+// CHECK-LE: or <4 x i32> {{%.+}}, [[T1]]
+
+  res_vf = vec_orc(vfa, vfb);
+// CHECK: [[T1:%.+]] = xor <4 x i32> {{%.+}}, 
+// CHECK: or <4 x i32> {{%.+}}, [[T1]]
+// CHECK-LE: [[T1:%.+]] = xor <4 x i32> {{%.+}}, 
 // CHECK-LE: or <4 x i32> {{%.+}}, [[T1]]
 
   res_vsll = vec_orc(vsll, vsll);
@@ -1121,6 +1129,12 @@
 // CHECK: [[T1:%.+]] = xor <2 x i64> {{%.+}}, 
 // CHECK: or <2 x i64> {{%.+}}, [[T1]]
 // CHECK-LE: [[T1:%.+]] = xor <2 x i64> {{%.+}}, 
+// CHECK-LE: or <2 x i64> {{%.+}}, [[T1]]
+
+  res_vd = vec_orc(vda, vdb);
+// CHECK: [[T1:%.+]] = xor <2 x i64> {{%.+}}, 
+// CHECK: or <2 x i64> {{%.+}}, [[T1]]
+// CHECK-LE: [[T1:%.+]] = xor <2 x i64> {{%.+}}, 
 // CHECK-LE: or <2 x i64> {{%.+}}, [[T1]]
 
   /* vec_sub */
Index: clang/lib/Headers/altivec.h
===
--- clang/lib/Headers/altivec.h
+++ clang/lib/Headers/altivec.h
@@ -7109,6 +7109,11 @@
   return (vector float)((vector unsigned int)__a | ~__b);
 }
 
+static __inline__ vector float __ATTRS_o_ai
+vec_orc(vector float __a, vector float __b) {
+  return (vector float) ((vector unsigned int)__a | ~(vector unsigned int)__b);
+}
+
 static __inline__ vector signed long long __ATTRS_o_ai
 vec_orc(vector signed long long __a, vector signed long long __b) {
   return __a | ~__b;
@@ -7153,6 +7158,11 @@
 vec_orc(vector bool long long __a, vector double __b) {
   return (vector double)(__a | ~(vector unsigned long long)__b);
 }
+
+static __inline__ vector double __ATTRS_o_ai
+vec_orc(vector double __a, vector double __b) {
+  return (vector double)((vector bool long long)__a | ~(vector unsigned long 
long)__b);
+}
 #endif
 
 /* vec_vor */


Index: clang/test/CodeGen/builtins-ppc-p8vector.c
===
--- clang/test/CodeGen/builtins-ppc-p8vector.c
+++ clang/test/CodeGen/builtins-ppc-p8vector.c
@@ -35,7 +35,9 @@
 vector unsigned __int128 vux = { 1 };
 
 vector float vfa = { 1.e-4f, -132.23f, -22.1, 32.00f };
+vector float vfb = { 1.e-4f, -132.23f, -22.1, 32.00f };
 vector double vda = { 1.e-11, -132.23e10 };
+vector double vdb = { 1.e-11, -132.23e10 };
 
 int res_i;
 double res_d;
@@ -1067,6 +1069,12 @@
 // CHECK: [[T1:%.+]] = xor <4 x i32> {{%.+}}, 
 // CHECK: or <4 x i32> {{%.+}}, [[T1]]
 // CHECK-LE: [[T1:%.+]] = xor <4 x i32> {{%.+}}, 
+// CHECK-LE: or <4 x i32> {{%.+}}, [[T1]]
+
+  res_vf = vec_orc(vfa, vfb);
+// CHECK: [[T1:%.+]] = xor <4 x i32> {{%.+}}, 
+// CHECK: or <4 x i32> {{%.+}}, [[T1]]
+// CHECK-LE: [[T1:%.+]] = xor <4 x i32> {{%.+}}, 
 // CHECK-LE: or <4 x i32> {{%.+}}, [[T1]]
 
   res_vsll = vec_orc(vsll, vsll);
@@ -1121,6 +1129,12 @@
 // CHECK: [[T1:%.+]] = xor <2 x i64> {{%.+}}, 
 // CHECK: or <2 x i64> {{%.+}}, [[T1]]
 // CHECK-LE: [[T1:%.+]] = xor <2 x i64> {{%.+}}, 
+// CHECK-LE: or <2 x i64> {{%.+}}, [[T1]]
+
+  res_vd = vec_orc(vda, vdb);
+// CHECK: [[T1:%.+]] = xor <2 x i64> {{%.+}}, 
+// CHECK: or <2 x i64> {{%.+}}, [[T1]]
+// CHECK-LE: [[T1:%.+]] = xor <2 x i64> {{%.+}}, 
 // CHECK-LE: or <2 x i64> {{%.+}}, [[T1]]
 
   /* vec_sub */
Index: clang/lib/Headers/altivec.h
===
--- clang/lib/Headers/altivec.h
+++ clang/lib/Headers/altivec.h
@@ -7109,6 +7109,11 @@
   return (vector float)((vector unsigned int)__a | ~__b);
 }
 
+static __inline__ vector float __ATTRS_o_ai
+vec_orc(vector float __a, vector float __b) {
+  return (vector float) ((vector unsigned int)__a | ~(vector unsigned int)__b);
+}
+
 static __inline__ vector signed long long __ATTRS_o_ai
 vec_orc(vector signed long long __a, vector signed long long __b) {
   return __a | ~__b;
@@ -7153,6 +7158,11 @@

[PATCH] D109902: [PowerPC] Improved codegen related to xscvdpsxws/xscvdpuxws

2021-09-28 Thread Albion Fung via Phabricator via cfe-commits

Conanap updated this revision to Diff 375780.
Conanap marked an inline comment as done.
Conanap added a comment.

Updated correct version of the patch


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D109902/new/

https://reviews.llvm.org/D109902

Files:
  llvm/lib/Target/PowerPC/PPCInstrVSX.td
  llvm/test/CodeGen/PowerPC/test-vector-insert.ll
  llvm/test/CodeGen/PowerPC/vec_conv_fp64_to_i32_elts.ll

Index: llvm/test/CodeGen/PowerPC/vec_conv_fp64_to_i32_elts.ll
===
--- llvm/test/CodeGen/PowerPC/vec_conv_fp64_to_i32_elts.ll
+++ llvm/test/CodeGen/PowerPC/vec_conv_fp64_to_i32_elts.ll
@@ -13,12 +13,8 @@
 ; CHECK-P8-LABEL: test2elt:
 ; CHECK-P8:   # %bb.0: # %entry
 ; CHECK-P8-NEXT:xxswapd vs0, v2
-; CHECK-P8-NEXT:xscvdpuxws f1, v2
-; CHECK-P8-NEXT:xscvdpuxws f0, f0
-; CHECK-P8-NEXT:mffprwz r3, f1
-; CHECK-P8-NEXT:mtvsrwz v2, r3
-; CHECK-P8-NEXT:mffprwz r4, f0
-; CHECK-P8-NEXT:mtvsrwz v3, r4
+; CHECK-P8-NEXT:xscvdpuxws v2, v2
+; CHECK-P8-NEXT:xscvdpuxws v3, f0
 ; CHECK-P8-NEXT:vmrghw v2, v2, v3
 ; CHECK-P8-NEXT:xxswapd vs0, v2
 ; CHECK-P8-NEXT:mffprd r3, f0
@@ -26,26 +22,18 @@
 ;
 ; CHECK-P9-LABEL: test2elt:
 ; CHECK-P9:   # %bb.0: # %entry
-; CHECK-P9-NEXT:xscvdpuxws f0, v2
-; CHECK-P9-NEXT:mffprwz r3, f0
 ; CHECK-P9-NEXT:xxswapd vs0, v2
-; CHECK-P9-NEXT:mtvsrwz v3, r3
-; CHECK-P9-NEXT:xscvdpuxws f0, f0
-; CHECK-P9-NEXT:mffprwz r3, f0
-; CHECK-P9-NEXT:mtvsrwz v2, r3
+; CHECK-P9-NEXT:xscvdpuxws v3, v2
+; CHECK-P9-NEXT:xscvdpuxws v2, f0
 ; CHECK-P9-NEXT:vmrghw v2, v3, v2
 ; CHECK-P9-NEXT:mfvsrld r3, v2
 ; CHECK-P9-NEXT:blr
 ;
 ; CHECK-BE-LABEL: test2elt:
 ; CHECK-BE:   # %bb.0: # %entry
-; CHECK-BE-NEXT:xscvdpuxws f0, v2
-; CHECK-BE-NEXT:mffprwz r3, f0
 ; CHECK-BE-NEXT:xxswapd vs0, v2
-; CHECK-BE-NEXT:mtvsrwz v3, r3
-; CHECK-BE-NEXT:xscvdpuxws f0, f0
-; CHECK-BE-NEXT:mffprwz r3, f0
-; CHECK-BE-NEXT:mtvsrwz v2, r3
+; CHECK-BE-NEXT:xscvdpuxws v3, v2
+; CHECK-BE-NEXT:xscvdpuxws v2, f0
 ; CHECK-BE-NEXT:vmrgow v2, v3, v2
 ; CHECK-BE-NEXT:mfvsrd r3, v2
 ; CHECK-BE-NEXT:blr
@@ -305,12 +293,8 @@
 ; CHECK-P8-LABEL: test2elt_signed:
 ; CHECK-P8:   # %bb.0: # %entry
 ; CHECK-P8-NEXT:xxswapd vs0, v2
-; CHECK-P8-NEXT:xscvdpsxws f1, v2
-; CHECK-P8-NEXT:xscvdpsxws f0, f0
-; CHECK-P8-NEXT:mffprwz r3, f1
-; CHECK-P8-NEXT:mtvsrwz v2, r3
-; CHECK-P8-NEXT:mffprwz r4, f0
-; CHECK-P8-NEXT:mtvsrwz v3, r4
+; CHECK-P8-NEXT:xscvdpsxws v2, v2
+; CHECK-P8-NEXT:xscvdpsxws v3, f0
 ; CHECK-P8-NEXT:vmrghw v2, v2, v3
 ; CHECK-P8-NEXT:xxswapd vs0, v2
 ; CHECK-P8-NEXT:mffprd r3, f0
@@ -318,26 +302,18 @@
 ;
 ; CHECK-P9-LABEL: test2elt_signed:
 ; CHECK-P9:   # %bb.0: # %entry
-; CHECK-P9-NEXT:xscvdpsxws f0, v2
-; CHECK-P9-NEXT:mffprwz r3, f0
 ; CHECK-P9-NEXT:xxswapd vs0, v2
-; CHECK-P9-NEXT:mtvsrwz v3, r3
-; CHECK-P9-NEXT:xscvdpsxws f0, f0
-; CHECK-P9-NEXT:mffprwz r3, f0
-; CHECK-P9-NEXT:mtvsrwz v2, r3
+; CHECK-P9-NEXT:xscvdpsxws v3, v2
+; CHECK-P9-NEXT:xscvdpsxws v2, f0
 ; CHECK-P9-NEXT:vmrghw v2, v3, v2
 ; CHECK-P9-NEXT:mfvsrld r3, v2
 ; CHECK-P9-NEXT:blr
 ;
 ; CHECK-BE-LABEL: test2elt_signed:
 ; CHECK-BE:   # %bb.0: # %entry
-; CHECK-BE-NEXT:xscvdpsxws f0, v2
-; CHECK-BE-NEXT:mffprwz r3, f0
 ; CHECK-BE-NEXT:xxswapd vs0, v2
-; CHECK-BE-NEXT:mtvsrwz v3, r3
-; CHECK-BE-NEXT:xscvdpsxws f0, f0
-; CHECK-BE-NEXT:mffprwz r3, f0
-; CHECK-BE-NEXT:mtvsrwz v2, r3
+; CHECK-BE-NEXT:xscvdpsxws v3, v2
+; CHECK-BE-NEXT:xscvdpsxws v2, f0
 ; CHECK-BE-NEXT:vmrgow v2, v3, v2
 ; CHECK-BE-NEXT:mfvsrd r3, v2
 ; CHECK-BE-NEXT:blr
Index: llvm/test/CodeGen/PowerPC/test-vector-insert.ll
===
--- llvm/test/CodeGen/PowerPC/test-vector-insert.ll
+++ llvm/test/CodeGen/PowerPC/test-vector-insert.ll
@@ -38,20 +38,16 @@
 ;
 ; CHECK-LE-P8-LABEL: test:
 ; CHECK-LE-P8:   # %bb.0: # %entry
-; CHECK-LE-P8-NEXT:xscvdpsxws f0, f1
+; CHECK-LE-P8-NEXT:xscvdpsxws v3, f1
 ; CHECK-LE-P8-NEXT:addis r3, r2, .LCPI0_0@toc@ha
 ; CHECK-LE-P8-NEXT:addi r3, r3, .LCPI0_0@toc@l
-; CHECK-LE-P8-NEXT:lvx v3, 0, r3
-; CHECK-LE-P8-NEXT:mffprwz r4, f0
-; CHECK-LE-P8-NEXT:mtvsrwz v4, r4
-; CHECK-LE-P8-NEXT:vperm v2, v4, v2, v3
+; CHECK-LE-P8-NEXT:lvx v4, 0, r3
+; CHECK-LE-P8-NEXT:vperm v2, v3, v2, v4
 ; CHECK-LE-P8-NEXT:blr
 ;
 ; CHECK-LE-P9-LABEL: test:
 ; CHECK-LE-P9:   # %bb.0: # %entry
 ; CHECK-LE-P9-NEXT:xscvdpsxws f0, f1
-; CHECK-LE-P9-NEXT:mffprwz r3, f0
-; CHECK-LE-P9-NEXT:mtfprwz f0, r3
 ; CHECK-LE-P9-NEXT:xxinsertw v2, vs0, 0
 ; CHECK-LE-P9-NEXT:blr
 ;
@@ -70,9 +66,7 @@
 ;
 ; CHECK-BE-P8-LABEL: test:
 ; CHECK-BE-P8:   # %bb.0: # %entry
-; CHECK-BE-P8-NEXT:xscvdpsxws f0, f1
-;

[PATCH] D109902: [PowerPC] Improved codegen related to xscvdpsxws/xscvdpuxws

2021-09-28 Thread Albion Fung via Phabricator via cfe-commits

Conanap marked 2 inline comments as done.
Conanap added inline comments.



Comment at: llvm/lib/Target/PowerPC/PPCInstrVSX.td:4150
+0))>;
+def : Pat<(v4i32 (insertelt v4i32:$VEC, DblToUInt.A, 0)),
+  (v4i32 (XXINSERTW v4i32:$VEC,

nemanjai wrote:
> What am I missing here? It appears to me that this pattern is exactly the 
> same as the one above it. The same appears to be the case for all of these. 
> Also, why the change in naming convention?
This one is for the unsigned version, the above is for the signed version. 
Originally, using `DblToInt.A` gave me problems as `$A` are now used in two 
places, so I've changed the other variable names instead. I'll use `DblToInt.B` 
instead to match the convention, thanks!


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[PATCH] D109902: [PowerPC] Improved codegen related to xscvdpsxws/xscvdpuxws

2021-09-28 Thread Albion Fung via Phabricator via cfe-commits

Conanap updated this revision to Diff 375667.
Conanap added a comment.

Added context, changed var names in aptterns


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D109902/new/

https://reviews.llvm.org/D109902

Files:
  llvm/lib/Target/PowerPC/PPCInstrVSX.td
  llvm/test/CodeGen/PowerPC/test-vector-insert.ll
  llvm/test/CodeGen/PowerPC/vec_conv_fp64_to_i32_elts.ll

Index: llvm/test/CodeGen/PowerPC/vec_conv_fp64_to_i32_elts.ll
===
--- llvm/test/CodeGen/PowerPC/vec_conv_fp64_to_i32_elts.ll
+++ llvm/test/CodeGen/PowerPC/vec_conv_fp64_to_i32_elts.ll
@@ -13,12 +13,8 @@
 ; CHECK-P8-LABEL: test2elt:
 ; CHECK-P8:   # %bb.0: # %entry
 ; CHECK-P8-NEXT:xxswapd vs0, v2
-; CHECK-P8-NEXT:xscvdpuxws f1, v2
-; CHECK-P8-NEXT:xscvdpuxws f0, f0
-; CHECK-P8-NEXT:mffprwz r3, f1
-; CHECK-P8-NEXT:mtvsrwz v2, r3
-; CHECK-P8-NEXT:mffprwz r4, f0
-; CHECK-P8-NEXT:mtvsrwz v3, r4
+; CHECK-P8-NEXT:xscvdpuxws v2, v2
+; CHECK-P8-NEXT:xscvdpuxws v3, f0
 ; CHECK-P8-NEXT:vmrghw v2, v2, v3
 ; CHECK-P8-NEXT:xxswapd vs0, v2
 ; CHECK-P8-NEXT:mffprd r3, f0
@@ -26,26 +22,18 @@
 ;
 ; CHECK-P9-LABEL: test2elt:
 ; CHECK-P9:   # %bb.0: # %entry
-; CHECK-P9-NEXT:xscvdpuxws f0, v2
-; CHECK-P9-NEXT:mffprwz r3, f0
 ; CHECK-P9-NEXT:xxswapd vs0, v2
-; CHECK-P9-NEXT:mtvsrwz v3, r3
-; CHECK-P9-NEXT:xscvdpuxws f0, f0
-; CHECK-P9-NEXT:mffprwz r3, f0
-; CHECK-P9-NEXT:mtvsrwz v2, r3
+; CHECK-P9-NEXT:xscvdpuxws v3, v2
+; CHECK-P9-NEXT:xscvdpuxws v2, f0
 ; CHECK-P9-NEXT:vmrghw v2, v3, v2
 ; CHECK-P9-NEXT:mfvsrld r3, v2
 ; CHECK-P9-NEXT:blr
 ;
 ; CHECK-BE-LABEL: test2elt:
 ; CHECK-BE:   # %bb.0: # %entry
-; CHECK-BE-NEXT:xscvdpuxws f0, v2
-; CHECK-BE-NEXT:mffprwz r3, f0
 ; CHECK-BE-NEXT:xxswapd vs0, v2
-; CHECK-BE-NEXT:mtvsrwz v3, r3
-; CHECK-BE-NEXT:xscvdpuxws f0, f0
-; CHECK-BE-NEXT:mffprwz r3, f0
-; CHECK-BE-NEXT:mtvsrwz v2, r3
+; CHECK-BE-NEXT:xscvdpuxws v3, v2
+; CHECK-BE-NEXT:xscvdpuxws v2, f0
 ; CHECK-BE-NEXT:vmrgow v2, v3, v2
 ; CHECK-BE-NEXT:mfvsrd r3, v2
 ; CHECK-BE-NEXT:blr
@@ -305,12 +293,8 @@
 ; CHECK-P8-LABEL: test2elt_signed:
 ; CHECK-P8:   # %bb.0: # %entry
 ; CHECK-P8-NEXT:xxswapd vs0, v2
-; CHECK-P8-NEXT:xscvdpsxws f1, v2
-; CHECK-P8-NEXT:xscvdpsxws f0, f0
-; CHECK-P8-NEXT:mffprwz r3, f1
-; CHECK-P8-NEXT:mtvsrwz v2, r3
-; CHECK-P8-NEXT:mffprwz r4, f0
-; CHECK-P8-NEXT:mtvsrwz v3, r4
+; CHECK-P8-NEXT:xscvdpsxws v2, v2
+; CHECK-P8-NEXT:xscvdpsxws v3, f0
 ; CHECK-P8-NEXT:vmrghw v2, v2, v3
 ; CHECK-P8-NEXT:xxswapd vs0, v2
 ; CHECK-P8-NEXT:mffprd r3, f0
@@ -318,26 +302,18 @@
 ;
 ; CHECK-P9-LABEL: test2elt_signed:
 ; CHECK-P9:   # %bb.0: # %entry
-; CHECK-P9-NEXT:xscvdpsxws f0, v2
-; CHECK-P9-NEXT:mffprwz r3, f0
 ; CHECK-P9-NEXT:xxswapd vs0, v2
-; CHECK-P9-NEXT:mtvsrwz v3, r3
-; CHECK-P9-NEXT:xscvdpsxws f0, f0
-; CHECK-P9-NEXT:mffprwz r3, f0
-; CHECK-P9-NEXT:mtvsrwz v2, r3
+; CHECK-P9-NEXT:xscvdpsxws v3, v2
+; CHECK-P9-NEXT:xscvdpsxws v2, f0
 ; CHECK-P9-NEXT:vmrghw v2, v3, v2
 ; CHECK-P9-NEXT:mfvsrld r3, v2
 ; CHECK-P9-NEXT:blr
 ;
 ; CHECK-BE-LABEL: test2elt_signed:
 ; CHECK-BE:   # %bb.0: # %entry
-; CHECK-BE-NEXT:xscvdpsxws f0, v2
-; CHECK-BE-NEXT:mffprwz r3, f0
 ; CHECK-BE-NEXT:xxswapd vs0, v2
-; CHECK-BE-NEXT:mtvsrwz v3, r3
-; CHECK-BE-NEXT:xscvdpsxws f0, f0
-; CHECK-BE-NEXT:mffprwz r3, f0
-; CHECK-BE-NEXT:mtvsrwz v2, r3
+; CHECK-BE-NEXT:xscvdpsxws v3, v2
+; CHECK-BE-NEXT:xscvdpsxws v2, f0
 ; CHECK-BE-NEXT:vmrgow v2, v3, v2
 ; CHECK-BE-NEXT:mfvsrd r3, v2
 ; CHECK-BE-NEXT:blr
Index: llvm/test/CodeGen/PowerPC/test-vector-insert.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/test-vector-insert.ll
@@ -0,0 +1,219 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:  -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
+; RUN:  -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE-P8
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:  -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
+; RUN:  -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-LE-P7
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN:  -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
+; RUN:  -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-BE-P7
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN:  -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
+; RUN:  -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-BE-P8
+; xscvdpsxws and uxws is only available on Power7 and above
+; Codgen is different for LE Power7 and Power8
+
+define dso_local <4 x i32> @test(<4 x

[PATCH] D110273: [PowerPC] Fix lharx and lbarx builtin signatures

2021-09-24 Thread Albion Fung via Phabricator via cfe-commits

Conanap updated this revision to Diff 374908.
Conanap added a comment.

Fixed an old test case


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D110273/new/

https://reviews.llvm.org/D110273

Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond.c


Index: clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond.c
===
--- clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond.c
+++ clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond.c
@@ -24,7 +24,7 @@
   return __lharx(a);
 }
 
-char test_lbarx(volatile unsigned char *a) {
+char test_lbarx(volatile char *a) {
   // CHECK-LABEL: @test_lbarx
   // CHECK: %0 = tail call i8 asm sideeffect "lbarx $0, ${1:y}", 
"=r,*Z,~{memory}"(i8* %a)
   // CHECK-NON-PWR8-ERR:  error: this builtin is only valid on POWER8 or later 
CPUs
@@ -46,3 +46,18 @@
   // CHECK-NON-PWR8-ERR:  error: this builtin is only valid on POWER8 or later 
CPUs
   return __sthcx(a, val);
 }
+
+// extra test cases that previously caused error during usage
+int test_lharx_intret(volatile short *a) {
+  // CHECK-LABEL: @test_lharx_intret
+  // CHECK: %0 = tail call i16 asm sideeffect "lharx $0, ${1:y}", 
"=r,*Z,~{memory}"(i16* %a)
+  // CHECK-NON-PWR8-ERR:  error: this builtin is only valid on POWER8 or later 
CPUs
+  return __lharx(a);
+}
+
+int test_lbarx_intret(volatile char *a) {
+  // CHECK-LABEL: @test_lbarx_intret
+  // CHECK: %0 = tail call i8 asm sideeffect "lbarx $0, ${1:y}", 
"=r,*Z,~{memory}"(i8* %a)
+  // CHECK-NON-PWR8-ERR:  error: this builtin is only valid on POWER8 or later 
CPUs
+  return __lbarx(a);
+}
Index: clang/include/clang/Basic/BuiltinsPPC.def
===
--- clang/include/clang/Basic/BuiltinsPPC.def
+++ clang/include/clang/Basic/BuiltinsPPC.def
@@ -74,8 +74,8 @@
 BUILTIN(__builtin_ppc_fetch_and_swaplp, "ULiULiD*ULi", "")
 BUILTIN(__builtin_ppc_ldarx, "LiLiD*", "")
 BUILTIN(__builtin_ppc_lwarx, "iiD*", "")
-BUILTIN(__builtin_ppc_lharx, "isD*", "")
-BUILTIN(__builtin_ppc_lbarx, "UiUcD*", "")
+BUILTIN(__builtin_ppc_lharx, "ssD*", "")
+BUILTIN(__builtin_ppc_lbarx, "ccD*", "")
 BUILTIN(__builtin_ppc_stdcx, "iLiD*Li", "")
 BUILTIN(__builtin_ppc_stwcx, "iiD*i", "")
 BUILTIN(__builtin_ppc_sthcx, "isD*s", "")


Index: clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond.c
===
--- clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond.c
+++ clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond.c
@@ -24,7 +24,7 @@
   return __lharx(a);
 }
 
-char test_lbarx(volatile unsigned char *a) {
+char test_lbarx(volatile char *a) {
   // CHECK-LABEL: @test_lbarx
   // CHECK: %0 = tail call i8 asm sideeffect "lbarx $0, ${1:y}", "=r,*Z,~{memory}"(i8* %a)
   // CHECK-NON-PWR8-ERR:  error: this builtin is only valid on POWER8 or later CPUs
@@ -46,3 +46,18 @@
   // CHECK-NON-PWR8-ERR:  error: this builtin is only valid on POWER8 or later CPUs
   return __sthcx(a, val);
 }
+
+// extra test cases that previously caused error during usage
+int test_lharx_intret(volatile short *a) {
+  // CHECK-LABEL: @test_lharx_intret
+  // CHECK: %0 = tail call i16 asm sideeffect "lharx $0, ${1:y}", "=r,*Z,~{memory}"(i16* %a)
+  // CHECK-NON-PWR8-ERR:  error: this builtin is only valid on POWER8 or later CPUs
+  return __lharx(a);
+}
+
+int test_lbarx_intret(volatile char *a) {
+  // CHECK-LABEL: @test_lbarx_intret
+  // CHECK: %0 = tail call i8 asm sideeffect "lbarx $0, ${1:y}", "=r,*Z,~{memory}"(i8* %a)
+  // CHECK-NON-PWR8-ERR:  error: this builtin is only valid on POWER8 or later CPUs
+  return __lbarx(a);
+}
Index: clang/include/clang/Basic/BuiltinsPPC.def
===
--- clang/include/clang/Basic/BuiltinsPPC.def
+++ clang/include/clang/Basic/BuiltinsPPC.def
@@ -74,8 +74,8 @@
 BUILTIN(__builtin_ppc_fetch_and_swaplp, "ULiULiD*ULi", "")
 BUILTIN(__builtin_ppc_ldarx, "LiLiD*", "")
 BUILTIN(__builtin_ppc_lwarx, "iiD*", "")
-BUILTIN(__builtin_ppc_lharx, "isD*", "")
-BUILTIN(__builtin_ppc_lbarx, "UiUcD*", "")
+BUILTIN(__builtin_ppc_lharx, "ssD*", "")
+BUILTIN(__builtin_ppc_lbarx, "ccD*", "")
 BUILTIN(__builtin_ppc_stdcx, "iLiD*Li", "")
 BUILTIN(__builtin_ppc_stwcx, "iiD*i", "")
 BUILTIN(__builtin_ppc_sthcx, "isD*s", "")
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[PATCH] D109902: [PowerPC] Improved codegen related to xscvdpsxws/xscvdpuxws

2021-09-24 Thread Albion Fung via Phabricator via cfe-commits

Conanap updated this revision to Diff 374906.
Conanap added a comment.

This modifies a test case introduced in this commit: 
https://github.com/llvm/llvm-project/commit/3678df5ae6618eec656ae0ea0dab3be09d73bc9a


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D109902/new/

https://reviews.llvm.org/D109902

Files:
  llvm/lib/Target/PowerPC/PPCInstrVSX.td
  llvm/test/CodeGen/PowerPC/test-vector-insert.ll
  llvm/test/CodeGen/PowerPC/vec_conv_fp64_to_i32_elts.ll

Index: llvm/test/CodeGen/PowerPC/vec_conv_fp64_to_i32_elts.ll
===
--- llvm/test/CodeGen/PowerPC/vec_conv_fp64_to_i32_elts.ll
+++ llvm/test/CodeGen/PowerPC/vec_conv_fp64_to_i32_elts.ll
@@ -13,12 +13,8 @@
 ; CHECK-P8-LABEL: test2elt:
 ; CHECK-P8:   # %bb.0: # %entry
 ; CHECK-P8-NEXT:xxswapd vs0, v2
-; CHECK-P8-NEXT:xscvdpuxws f1, v2
-; CHECK-P8-NEXT:xscvdpuxws f0, f0
-; CHECK-P8-NEXT:mffprwz r3, f1
-; CHECK-P8-NEXT:mtvsrwz v2, r3
-; CHECK-P8-NEXT:mffprwz r4, f0
-; CHECK-P8-NEXT:mtvsrwz v3, r4
+; CHECK-P8-NEXT:xscvdpuxws v2, v2
+; CHECK-P8-NEXT:xscvdpuxws v3, f0
 ; CHECK-P8-NEXT:vmrghw v2, v2, v3
 ; CHECK-P8-NEXT:xxswapd vs0, v2
 ; CHECK-P8-NEXT:mffprd r3, f0
@@ -26,26 +22,18 @@
 ;
 ; CHECK-P9-LABEL: test2elt:
 ; CHECK-P9:   # %bb.0: # %entry
-; CHECK-P9-NEXT:xscvdpuxws f0, v2
-; CHECK-P9-NEXT:mffprwz r3, f0
 ; CHECK-P9-NEXT:xxswapd vs0, v2
-; CHECK-P9-NEXT:mtvsrwz v3, r3
-; CHECK-P9-NEXT:xscvdpuxws f0, f0
-; CHECK-P9-NEXT:mffprwz r3, f0
-; CHECK-P9-NEXT:mtvsrwz v2, r3
+; CHECK-P9-NEXT:xscvdpuxws v3, v2
+; CHECK-P9-NEXT:xscvdpuxws v2, f0
 ; CHECK-P9-NEXT:vmrghw v2, v3, v2
 ; CHECK-P9-NEXT:mfvsrld r3, v2
 ; CHECK-P9-NEXT:blr
 ;
 ; CHECK-BE-LABEL: test2elt:
 ; CHECK-BE:   # %bb.0: # %entry
-; CHECK-BE-NEXT:xscvdpuxws f0, v2
-; CHECK-BE-NEXT:mffprwz r3, f0
 ; CHECK-BE-NEXT:xxswapd vs0, v2
-; CHECK-BE-NEXT:mtvsrwz v3, r3
-; CHECK-BE-NEXT:xscvdpuxws f0, f0
-; CHECK-BE-NEXT:mffprwz r3, f0
-; CHECK-BE-NEXT:mtvsrwz v2, r3
+; CHECK-BE-NEXT:xscvdpuxws v3, v2
+; CHECK-BE-NEXT:xscvdpuxws v2, f0
 ; CHECK-BE-NEXT:vmrgow v2, v3, v2
 ; CHECK-BE-NEXT:mfvsrd r3, v2
 ; CHECK-BE-NEXT:blr
@@ -305,12 +293,8 @@
 ; CHECK-P8-LABEL: test2elt_signed:
 ; CHECK-P8:   # %bb.0: # %entry
 ; CHECK-P8-NEXT:xxswapd vs0, v2
-; CHECK-P8-NEXT:xscvdpsxws f1, v2
-; CHECK-P8-NEXT:xscvdpsxws f0, f0
-; CHECK-P8-NEXT:mffprwz r3, f1
-; CHECK-P8-NEXT:mtvsrwz v2, r3
-; CHECK-P8-NEXT:mffprwz r4, f0
-; CHECK-P8-NEXT:mtvsrwz v3, r4
+; CHECK-P8-NEXT:xscvdpsxws v2, v2
+; CHECK-P8-NEXT:xscvdpsxws v3, f0
 ; CHECK-P8-NEXT:vmrghw v2, v2, v3
 ; CHECK-P8-NEXT:xxswapd vs0, v2
 ; CHECK-P8-NEXT:mffprd r3, f0
@@ -318,26 +302,18 @@
 ;
 ; CHECK-P9-LABEL: test2elt_signed:
 ; CHECK-P9:   # %bb.0: # %entry
-; CHECK-P9-NEXT:xscvdpsxws f0, v2
-; CHECK-P9-NEXT:mffprwz r3, f0
 ; CHECK-P9-NEXT:xxswapd vs0, v2
-; CHECK-P9-NEXT:mtvsrwz v3, r3
-; CHECK-P9-NEXT:xscvdpsxws f0, f0
-; CHECK-P9-NEXT:mffprwz r3, f0
-; CHECK-P9-NEXT:mtvsrwz v2, r3
+; CHECK-P9-NEXT:xscvdpsxws v3, v2
+; CHECK-P9-NEXT:xscvdpsxws v2, f0
 ; CHECK-P9-NEXT:vmrghw v2, v3, v2
 ; CHECK-P9-NEXT:mfvsrld r3, v2
 ; CHECK-P9-NEXT:blr
 ;
 ; CHECK-BE-LABEL: test2elt_signed:
 ; CHECK-BE:   # %bb.0: # %entry
-; CHECK-BE-NEXT:xscvdpsxws f0, v2
-; CHECK-BE-NEXT:mffprwz r3, f0
 ; CHECK-BE-NEXT:xxswapd vs0, v2
-; CHECK-BE-NEXT:mtvsrwz v3, r3
-; CHECK-BE-NEXT:xscvdpsxws f0, f0
-; CHECK-BE-NEXT:mffprwz r3, f0
-; CHECK-BE-NEXT:mtvsrwz v2, r3
+; CHECK-BE-NEXT:xscvdpsxws v3, v2
+; CHECK-BE-NEXT:xscvdpsxws v2, f0
 ; CHECK-BE-NEXT:vmrgow v2, v3, v2
 ; CHECK-BE-NEXT:mfvsrd r3, v2
 ; CHECK-BE-NEXT:blr
Index: llvm/test/CodeGen/PowerPC/test-vector-insert.ll
===
--- llvm/test/CodeGen/PowerPC/test-vector-insert.ll
+++ llvm/test/CodeGen/PowerPC/test-vector-insert.ll
@@ -38,20 +38,16 @@
 ;
 ; CHECK-LE-P8-LABEL: test:
 ; CHECK-LE-P8:   # %bb.0: # %entry
-; CHECK-LE-P8-NEXT:xscvdpsxws f0, f1
+; CHECK-LE-P8-NEXT:xscvdpsxws v3, f1
 ; CHECK-LE-P8-NEXT:addis r3, r2, .LCPI0_0@toc@ha
 ; CHECK-LE-P8-NEXT:addi r3, r3, .LCPI0_0@toc@l
-; CHECK-LE-P8-NEXT:lvx v3, 0, r3
-; CHECK-LE-P8-NEXT:mffprwz r4, f0
-; CHECK-LE-P8-NEXT:mtvsrwz v4, r4
-; CHECK-LE-P8-NEXT:vperm v2, v4, v2, v3
+; CHECK-LE-P8-NEXT:lvx v4, 0, r3
+; CHECK-LE-P8-NEXT:vperm v2, v3, v2, v4
 ; CHECK-LE-P8-NEXT:blr
 ;
 ; CHECK-LE-P9-LABEL: test:
 ; CHECK-LE-P9:   # %bb.0: # %entry
 ; CHECK-LE-P9-NEXT:xscvdpsxws f0, f1
-; CHECK-LE-P9-NEXT:mffprwz r3, f0
-; CHECK-LE-P9-NEXT:mtfprwz f0, r3
 ; CHECK-LE-P9-NEXT:xxinsertw v2, vs0, 0
 ; CHECK-LE-P9-NEXT:blr
 ;
@@ -70,9 +66,7 @@
 ;
 ; CHECK-BE-P8-LABEL: test:
 ; CHECK-BE-P8:   # %bb.0:

[PATCH] D110282: [PowerPC] SemaChecking for darn family of builtins

2021-09-23 Thread Albion Fung via Phabricator via cfe-commits

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG840afbde48e9: [PowerPC] SemaChecking for darn family of 
builtins (authored by Conanap).

Changed prior to commit:
  https://reviews.llvm.org/D110282?vs=374565=374726#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D110282/new/

https://reviews.llvm.org/D110282

Files:
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/builtins-ppc-xlcompat-darn.c
  clang/test/CodeGen/builtins-ppc-xlcompat-error.c
  clang/test/CodeGen/builtins-ppc.c

Index: clang/test/CodeGen/builtins-ppc.c
===
--- clang/test/CodeGen/builtins-ppc.c
+++ clang/test/CodeGen/builtins-ppc.c
@@ -36,16 +36,3 @@
   // CHECK: call double @llvm.ppc.setflm(double %1)
   res = __builtin_setflm(res);
 }
-
-void test_builtin_ppc_darn() {
-  volatile long res;
-  volatile int x;
-  // CHECK: call i64 @llvm.ppc.darn()
-  res = __builtin_darn();
-
-  // CHECK: call i64 @llvm.ppc.darnraw()
-  res = __builtin_darn_raw();
-
-  // CHECK: call i32 @llvm.ppc.darn32()
-  x = __builtin_darn_32();
-}
Index: clang/test/CodeGen/builtins-ppc-xlcompat-error.c
===
--- clang/test/CodeGen/builtins-ppc-xlcompat-error.c
+++ clang/test/CodeGen/builtins-ppc-xlcompat-error.c
@@ -96,6 +96,14 @@
 unsigned long long testdivdeu(unsigned long long dividend, unsigned long long divisor) {
   return __divdeu(dividend, divisor); //expected-error {{this builtin is only available on 64-bit targets}}
 }
+
+int test_darn() {
+  return __darn(); //expected-error {{this builtin is only available on 64-bit targets}}
+}
+
+int test_darn_raw() {
+  return __darn_raw(); //expected-error {{this builtin is only available on 64-bit targets}}
+}
 #endif
 
 unsigned long test_mfspr(void) {
Index: clang/test/CodeGen/builtins-ppc-xlcompat-darn.c
===
--- clang/test/CodeGen/builtins-ppc-xlcompat-darn.c
+++ clang/test/CodeGen/builtins-ppc-xlcompat-darn.c
@@ -1,10 +1,13 @@
 // REQUIRES: powerpc-registered-target
 // RUN: %clang_cc1 -triple powerpc64-unknown-unknown \
-// RUN:-emit-llvm %s -o -  -target-cpu pwr9 | FileCheck %s
+// RUN:-emit-llvm %s -o -  -target-cpu pwr9 | \
+// RUN:FileCheck %s --check-prefix=CHECK-64
 // RUN: %clang_cc1 -triple powerpc64le-unknown-unknown \
-// RUN:   -emit-llvm %s -o -  -target-cpu pwr9 | FileCheck %s
+// RUN:   -emit-llvm %s -o -  -target-cpu pwr9 | \
+// RUN:FileCheck %s --check-prefix=CHECK-64
 // RUN: %clang_cc1 -triple powerpc64-unknown-aix \
-// RUN:-emit-llvm %s -o -  -target-cpu pwr9 | FileCheck %s
+// RUN:-emit-llvm %s -o -  -target-cpu pwr9 | \
+// RUN:FileCheck %s --check-prefix=CHECK-64
 // RUN: %clang_cc1 -triple powerpc-unknown-unknown \
 // RUN:-emit-llvm %s -o -  -target-cpu pwr9 | FileCheck %s
 // RUN: %clang_cc1 -triple powerpcle-unknown-unknown \
@@ -15,21 +18,23 @@
 // The darn class of builtins are Power 9 and up and only darn_32 works in
 // 32 bit mode.
 
-// CHECK-LABEL: @testdarn(
-// CHECK: [[TMP0:%.*]] = call i64 @llvm.ppc.darn()
-// CHECK-NEXT:ret i64 [[TMP0]]
+#ifdef __PPC64__
+// CHECK-64-LABEL: @testdarn(
+// CHECK-64: [[TMP0:%.*]] = call i64 @llvm.ppc.darn()
+// CHECK-64-NEXT:ret i64 [[TMP0]]
 //
 long long testdarn(void) {
   return __darn();
 }
 
-// CHECK-LABEL: @testdarn_raw(
-// CHECK: [[TMP0:%.*]] = call i64 @llvm.ppc.darnraw()
-// CHECK-NEXT:ret i64 [[TMP0]]
+// CHECK-64-LABEL: @testdarn_raw(
+// CHECK-64: [[TMP0:%.*]] = call i64 @llvm.ppc.darnraw()
+// CHECK-64-NEXT:ret i64 [[TMP0]]
 //
 long long testdarn_raw(void) {
   return __darn_raw();
 }
+#endif
 
 // CHECK-LABEL: @testdarn_32(
 // CHECK: [[TMP0:%.*]] = call i32 @llvm.ppc.darn32()
Index: clang/lib/Sema/SemaChecking.cpp
===
--- clang/lib/Sema/SemaChecking.cpp
+++ clang/lib/Sema/SemaChecking.cpp
@@ -3295,6 +3295,8 @@
   case PPC::BI__builtin_ppc_insert_exp:
   case PPC::BI__builtin_ppc_extract_sig:
   case PPC::BI__builtin_ppc_addex:
+  case PPC::BI__builtin_darn:
+  case PPC::BI__builtin_darn_raw:
 return true;
   }
   return false;
@@ -3478,6 +3480,11 @@
   case PPC::BI__builtin_altivec_vcntmbw:
   case PPC::BI__builtin_altivec_vcntmbd:
 return SemaBuiltinConstantArgRange(TheCall, 1, 0, 1);
+  case PPC::BI__builtin_darn:
+  case PPC::BI__builtin_darn_raw:
+  case PPC::BI__builtin_darn_32:
+return SemaFeatureCheck(*this, TheCall, "isa-v30-instructions",
+diag::err_ppc_builtin_only_on_arch, "9");
 #define CUSTOM_BUILTIN(Name, Intr, Types, Acc) \
   case PPC::BI__builtin_##Name: \
 return SemaBuiltinPPCMMACall(TheCall, Types);
___
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[PATCH] D109902: [PowerPC] Improved codegen related to xscvdpsxws/xscvdpuxws

2021-09-23 Thread Albion Fung via Phabricator via cfe-commits

Conanap updated this revision to Diff 374614.
Conanap added a comment.

Added P7  and P8  run 
lines for BE


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D109902/new/

https://reviews.llvm.org/D109902

Files:
  llvm/lib/Target/PowerPC/PPCInstrVSX.td
  llvm/test/CodeGen/PowerPC/test-vector-insert.ll
  llvm/test/CodeGen/PowerPC/vec_conv_fp64_to_i32_elts.ll

Index: llvm/test/CodeGen/PowerPC/vec_conv_fp64_to_i32_elts.ll
===
--- llvm/test/CodeGen/PowerPC/vec_conv_fp64_to_i32_elts.ll
+++ llvm/test/CodeGen/PowerPC/vec_conv_fp64_to_i32_elts.ll
@@ -13,12 +13,8 @@
 ; CHECK-P8-LABEL: test2elt:
 ; CHECK-P8:   # %bb.0: # %entry
 ; CHECK-P8-NEXT:xxswapd vs0, v2
-; CHECK-P8-NEXT:xscvdpuxws f1, v2
-; CHECK-P8-NEXT:xscvdpuxws f0, f0
-; CHECK-P8-NEXT:mffprwz r3, f1
-; CHECK-P8-NEXT:mtvsrwz v2, r3
-; CHECK-P8-NEXT:mffprwz r4, f0
-; CHECK-P8-NEXT:mtvsrwz v3, r4
+; CHECK-P8-NEXT:xscvdpuxws v2, v2
+; CHECK-P8-NEXT:xscvdpuxws v3, f0
 ; CHECK-P8-NEXT:vmrghw v2, v2, v3
 ; CHECK-P8-NEXT:xxswapd vs0, v2
 ; CHECK-P8-NEXT:mffprd r3, f0
@@ -26,26 +22,18 @@
 ;
 ; CHECK-P9-LABEL: test2elt:
 ; CHECK-P9:   # %bb.0: # %entry
-; CHECK-P9-NEXT:xscvdpuxws f0, v2
-; CHECK-P9-NEXT:mffprwz r3, f0
 ; CHECK-P9-NEXT:xxswapd vs0, v2
-; CHECK-P9-NEXT:mtvsrwz v3, r3
-; CHECK-P9-NEXT:xscvdpuxws f0, f0
-; CHECK-P9-NEXT:mffprwz r3, f0
-; CHECK-P9-NEXT:mtvsrwz v2, r3
+; CHECK-P9-NEXT:xscvdpuxws v3, v2
+; CHECK-P9-NEXT:xscvdpuxws v2, f0
 ; CHECK-P9-NEXT:vmrghw v2, v3, v2
 ; CHECK-P9-NEXT:mfvsrld r3, v2
 ; CHECK-P9-NEXT:blr
 ;
 ; CHECK-BE-LABEL: test2elt:
 ; CHECK-BE:   # %bb.0: # %entry
-; CHECK-BE-NEXT:xscvdpuxws f0, v2
-; CHECK-BE-NEXT:mffprwz r3, f0
 ; CHECK-BE-NEXT:xxswapd vs0, v2
-; CHECK-BE-NEXT:mtvsrwz v3, r3
-; CHECK-BE-NEXT:xscvdpuxws f0, f0
-; CHECK-BE-NEXT:mffprwz r3, f0
-; CHECK-BE-NEXT:mtvsrwz v2, r3
+; CHECK-BE-NEXT:xscvdpuxws v3, v2
+; CHECK-BE-NEXT:xscvdpuxws v2, f0
 ; CHECK-BE-NEXT:vmrgow v2, v3, v2
 ; CHECK-BE-NEXT:mfvsrd r3, v2
 ; CHECK-BE-NEXT:blr
@@ -305,12 +293,8 @@
 ; CHECK-P8-LABEL: test2elt_signed:
 ; CHECK-P8:   # %bb.0: # %entry
 ; CHECK-P8-NEXT:xxswapd vs0, v2
-; CHECK-P8-NEXT:xscvdpsxws f1, v2
-; CHECK-P8-NEXT:xscvdpsxws f0, f0
-; CHECK-P8-NEXT:mffprwz r3, f1
-; CHECK-P8-NEXT:mtvsrwz v2, r3
-; CHECK-P8-NEXT:mffprwz r4, f0
-; CHECK-P8-NEXT:mtvsrwz v3, r4
+; CHECK-P8-NEXT:xscvdpsxws v2, v2
+; CHECK-P8-NEXT:xscvdpsxws v3, f0
 ; CHECK-P8-NEXT:vmrghw v2, v2, v3
 ; CHECK-P8-NEXT:xxswapd vs0, v2
 ; CHECK-P8-NEXT:mffprd r3, f0
@@ -318,26 +302,18 @@
 ;
 ; CHECK-P9-LABEL: test2elt_signed:
 ; CHECK-P9:   # %bb.0: # %entry
-; CHECK-P9-NEXT:xscvdpsxws f0, v2
-; CHECK-P9-NEXT:mffprwz r3, f0
 ; CHECK-P9-NEXT:xxswapd vs0, v2
-; CHECK-P9-NEXT:mtvsrwz v3, r3
-; CHECK-P9-NEXT:xscvdpsxws f0, f0
-; CHECK-P9-NEXT:mffprwz r3, f0
-; CHECK-P9-NEXT:mtvsrwz v2, r3
+; CHECK-P9-NEXT:xscvdpsxws v3, v2
+; CHECK-P9-NEXT:xscvdpsxws v2, f0
 ; CHECK-P9-NEXT:vmrghw v2, v3, v2
 ; CHECK-P9-NEXT:mfvsrld r3, v2
 ; CHECK-P9-NEXT:blr
 ;
 ; CHECK-BE-LABEL: test2elt_signed:
 ; CHECK-BE:   # %bb.0: # %entry
-; CHECK-BE-NEXT:xscvdpsxws f0, v2
-; CHECK-BE-NEXT:mffprwz r3, f0
 ; CHECK-BE-NEXT:xxswapd vs0, v2
-; CHECK-BE-NEXT:mtvsrwz v3, r3
-; CHECK-BE-NEXT:xscvdpsxws f0, f0
-; CHECK-BE-NEXT:mffprwz r3, f0
-; CHECK-BE-NEXT:mtvsrwz v2, r3
+; CHECK-BE-NEXT:xscvdpsxws v3, v2
+; CHECK-BE-NEXT:xscvdpsxws v2, f0
 ; CHECK-BE-NEXT:vmrgow v2, v3, v2
 ; CHECK-BE-NEXT:mfvsrd r3, v2
 ; CHECK-BE-NEXT:blr
Index: llvm/test/CodeGen/PowerPC/test-vector-insert.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/test-vector-insert.ll
@@ -0,0 +1,219 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:  -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
+; RUN:  -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE-P8
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:  -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
+; RUN:  -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-LE-P7
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN:  -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
+; RUN:  -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-BE-P7
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN:  -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
+; RUN:  -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-BE-P8
+; xscvdpsxws and uxws is only available on Power7 and above
+; Codgen is different for LE Power7 and

[PATCH] D109902: [PowerPC] Improved codegen related to xscvdpsxws/xscvdpuxws

2021-09-23 Thread Albion Fung via Phabricator via cfe-commits

Conanap marked 3 inline comments as done.
Conanap added inline comments.



Comment at: llvm/test/CodeGen/PowerPC/test-vector-insert.ll:8
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN:  -mcpu=pwr7 < %s | FileCheck %s
+

kamaub wrote:
> It seems like this run line is redundant, it produces the same assembly as 
> the big endian specific line above. Maybe the `-mcpu=pwr7` can be moved to 
> the first Little-endian specific run line? That line currently only test the 
> target cpu of the test machine.
good point, thanks!


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D109902/new/

https://reviews.llvm.org/D109902

___
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[PATCH] D109902: [PowerPC] Improved codegen related to xscvdpsxws/xscvdpuxws

2021-09-23 Thread Albion Fung via Phabricator via cfe-commits

Conanap updated this revision to Diff 374578.
Conanap added a comment.

Updated test cases, fixed a typo


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D109902/new/

https://reviews.llvm.org/D109902

Files:
  llvm/lib/Target/PowerPC/PPCInstrVSX.td
  llvm/test/CodeGen/PowerPC/test-vector-insert.ll
  llvm/test/CodeGen/PowerPC/vec_conv_fp64_to_i32_elts.ll

Index: llvm/test/CodeGen/PowerPC/vec_conv_fp64_to_i32_elts.ll
===
--- llvm/test/CodeGen/PowerPC/vec_conv_fp64_to_i32_elts.ll
+++ llvm/test/CodeGen/PowerPC/vec_conv_fp64_to_i32_elts.ll
@@ -13,12 +13,8 @@
 ; CHECK-P8-LABEL: test2elt:
 ; CHECK-P8:   # %bb.0: # %entry
 ; CHECK-P8-NEXT:xxswapd vs0, v2
-; CHECK-P8-NEXT:xscvdpuxws f1, v2
-; CHECK-P8-NEXT:xscvdpuxws f0, f0
-; CHECK-P8-NEXT:mffprwz r3, f1
-; CHECK-P8-NEXT:mtvsrwz v2, r3
-; CHECK-P8-NEXT:mffprwz r4, f0
-; CHECK-P8-NEXT:mtvsrwz v3, r4
+; CHECK-P8-NEXT:xscvdpuxws v2, v2
+; CHECK-P8-NEXT:xscvdpuxws v3, f0
 ; CHECK-P8-NEXT:vmrghw v2, v2, v3
 ; CHECK-P8-NEXT:xxswapd vs0, v2
 ; CHECK-P8-NEXT:mffprd r3, f0
@@ -26,26 +22,18 @@
 ;
 ; CHECK-P9-LABEL: test2elt:
 ; CHECK-P9:   # %bb.0: # %entry
-; CHECK-P9-NEXT:xscvdpuxws f0, v2
-; CHECK-P9-NEXT:mffprwz r3, f0
 ; CHECK-P9-NEXT:xxswapd vs0, v2
-; CHECK-P9-NEXT:mtvsrwz v3, r3
-; CHECK-P9-NEXT:xscvdpuxws f0, f0
-; CHECK-P9-NEXT:mffprwz r3, f0
-; CHECK-P9-NEXT:mtvsrwz v2, r3
+; CHECK-P9-NEXT:xscvdpuxws v3, v2
+; CHECK-P9-NEXT:xscvdpuxws v2, f0
 ; CHECK-P9-NEXT:vmrghw v2, v3, v2
 ; CHECK-P9-NEXT:mfvsrld r3, v2
 ; CHECK-P9-NEXT:blr
 ;
 ; CHECK-BE-LABEL: test2elt:
 ; CHECK-BE:   # %bb.0: # %entry
-; CHECK-BE-NEXT:xscvdpuxws f0, v2
-; CHECK-BE-NEXT:mffprwz r3, f0
 ; CHECK-BE-NEXT:xxswapd vs0, v2
-; CHECK-BE-NEXT:mtvsrwz v3, r3
-; CHECK-BE-NEXT:xscvdpuxws f0, f0
-; CHECK-BE-NEXT:mffprwz r3, f0
-; CHECK-BE-NEXT:mtvsrwz v2, r3
+; CHECK-BE-NEXT:xscvdpuxws v3, v2
+; CHECK-BE-NEXT:xscvdpuxws v2, f0
 ; CHECK-BE-NEXT:vmrgow v2, v3, v2
 ; CHECK-BE-NEXT:mfvsrd r3, v2
 ; CHECK-BE-NEXT:blr
@@ -305,12 +293,8 @@
 ; CHECK-P8-LABEL: test2elt_signed:
 ; CHECK-P8:   # %bb.0: # %entry
 ; CHECK-P8-NEXT:xxswapd vs0, v2
-; CHECK-P8-NEXT:xscvdpsxws f1, v2
-; CHECK-P8-NEXT:xscvdpsxws f0, f0
-; CHECK-P8-NEXT:mffprwz r3, f1
-; CHECK-P8-NEXT:mtvsrwz v2, r3
-; CHECK-P8-NEXT:mffprwz r4, f0
-; CHECK-P8-NEXT:mtvsrwz v3, r4
+; CHECK-P8-NEXT:xscvdpsxws v2, v2
+; CHECK-P8-NEXT:xscvdpsxws v3, f0
 ; CHECK-P8-NEXT:vmrghw v2, v2, v3
 ; CHECK-P8-NEXT:xxswapd vs0, v2
 ; CHECK-P8-NEXT:mffprd r3, f0
@@ -318,26 +302,18 @@
 ;
 ; CHECK-P9-LABEL: test2elt_signed:
 ; CHECK-P9:   # %bb.0: # %entry
-; CHECK-P9-NEXT:xscvdpsxws f0, v2
-; CHECK-P9-NEXT:mffprwz r3, f0
 ; CHECK-P9-NEXT:xxswapd vs0, v2
-; CHECK-P9-NEXT:mtvsrwz v3, r3
-; CHECK-P9-NEXT:xscvdpsxws f0, f0
-; CHECK-P9-NEXT:mffprwz r3, f0
-; CHECK-P9-NEXT:mtvsrwz v2, r3
+; CHECK-P9-NEXT:xscvdpsxws v3, v2
+; CHECK-P9-NEXT:xscvdpsxws v2, f0
 ; CHECK-P9-NEXT:vmrghw v2, v3, v2
 ; CHECK-P9-NEXT:mfvsrld r3, v2
 ; CHECK-P9-NEXT:blr
 ;
 ; CHECK-BE-LABEL: test2elt_signed:
 ; CHECK-BE:   # %bb.0: # %entry
-; CHECK-BE-NEXT:xscvdpsxws f0, v2
-; CHECK-BE-NEXT:mffprwz r3, f0
 ; CHECK-BE-NEXT:xxswapd vs0, v2
-; CHECK-BE-NEXT:mtvsrwz v3, r3
-; CHECK-BE-NEXT:xscvdpsxws f0, f0
-; CHECK-BE-NEXT:mffprwz r3, f0
-; CHECK-BE-NEXT:mtvsrwz v2, r3
+; CHECK-BE-NEXT:xscvdpsxws v3, v2
+; CHECK-BE-NEXT:xscvdpsxws v2, f0
 ; CHECK-BE-NEXT:vmrgow v2, v3, v2
 ; CHECK-BE-NEXT:mfvsrd r3, v2
 ; CHECK-BE-NEXT:blr
Index: llvm/test/CodeGen/PowerPC/test-vector-insert.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/test-vector-insert.ll
@@ -0,0 +1,184 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:  -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
+; RUN:  -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE-P8
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:  -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
+; RUN:  -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-LE-P7
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN:  -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
+; RUN:  -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-BE
+; xscvdpsxws and uxws is only available on Power7 and above
+; Codgen is different for LE Power7 and Power8
+
+define dso_local <4 x i32> @test(<4 x i32> %a, double %b) {
+; CHECK-LE-P8-LABEL: test:
+; CHECK-LE-P8:   # %bb.0: # %entry
+; CHECK-LE-P8-NEXT:xscvdpsxws v3, f1
+; CHECK-LE-P8-NEXT:addis r3, r2, .LCPI0_0@toc@ha
+; CHECK-LE-P8-NEXT:

[PATCH] D110282: [PowerPC] SemaChecking for darn family of builtins

2021-09-23 Thread Albion Fung via Phabricator via cfe-commits

Conanap updated this revision to Diff 374565.
Conanap added a comment.

Moved test case back to original file and use `#ifdef __PPC64__` instead


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D110282/new/

https://reviews.llvm.org/D110282

Files:
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/builtins-ppc-xlcompat-darn.c
  clang/test/CodeGen/builtins-ppc-xlcompat-error.c
  clang/test/CodeGen/builtins-ppc.c

Index: clang/test/CodeGen/builtins-ppc.c
===
--- clang/test/CodeGen/builtins-ppc.c
+++ clang/test/CodeGen/builtins-ppc.c
@@ -36,16 +36,3 @@
   // CHECK: call double @llvm.ppc.setflm(double %1)
   res = __builtin_setflm(res);
 }
-
-void test_builtin_ppc_darn() {
-  volatile long res;
-  volatile int x;
-  // CHECK: call i64 @llvm.ppc.darn()
-  res = __builtin_darn();
-
-  // CHECK: call i64 @llvm.ppc.darnraw()
-  res = __builtin_darn_raw();
-
-  // CHECK: call i32 @llvm.ppc.darn32()
-  x = __builtin_darn_32();
-}
Index: clang/test/CodeGen/builtins-ppc-xlcompat-error.c
===
--- clang/test/CodeGen/builtins-ppc-xlcompat-error.c
+++ clang/test/CodeGen/builtins-ppc-xlcompat-error.c
@@ -96,6 +96,14 @@
 unsigned long long testdivdeu(unsigned long long dividend, unsigned long long divisor) {
   return __divdeu(dividend, divisor); //expected-error {{this builtin is only available on 64-bit targets}}
 }
+
+int test_darn() {
+  return __darn(); //expected-error {{this builtin is only available on 64-bit targets}}
+}
+
+int test_darn_raw() {
+  return __darn_raw(); //expected-error {{this builtin is only available on 64-bit targets}}
+}
 #endif
 
 unsigned long test_mfspr(void) {
Index: clang/test/CodeGen/builtins-ppc-xlcompat-darn.c
===
--- clang/test/CodeGen/builtins-ppc-xlcompat-darn.c
+++ clang/test/CodeGen/builtins-ppc-xlcompat-darn.c
@@ -1,10 +1,13 @@
 // REQUIRES: powerpc-registered-target
 // RUN: %clang_cc1 -triple powerpc64-unknown-unknown \
-// RUN:-emit-llvm %s -o -  -target-cpu pwr9 | FileCheck %s
+// RUN:-emit-llvm %s -o -  -target-cpu pwr9 | \
+// RUN:FileCheck %s --check-prefix=CHECK-64
 // RUN: %clang_cc1 -triple powerpc64le-unknown-unknown \
-// RUN:   -emit-llvm %s -o -  -target-cpu pwr9 | FileCheck %s
+// RUN:   -emit-llvm %s -o -  -target-cpu pwr9 | \
+// RUN:FileCheck %s --check-prefix=CHECK-64
 // RUN: %clang_cc1 -triple powerpc64-unknown-aix \
-// RUN:-emit-llvm %s -o -  -target-cpu pwr9 | FileCheck %s
+// RUN:-emit-llvm %s -o -  -target-cpu pwr9 | \
+// RUN:FileCheck %s --check-prefix=CHECK-64
 // RUN: %clang_cc1 -triple powerpc-unknown-unknown \
 // RUN:-emit-llvm %s -o -  -target-cpu pwr9 | FileCheck %s
 // RUN: %clang_cc1 -triple powerpcle-unknown-unknown \
@@ -15,21 +18,23 @@
 // The darn class of builtins are Power 9 and up and only darn_32 works in
 // 32 bit mode.
 
-// CHECK-LABEL: @testdarn(
-// CHECK: [[TMP0:%.*]] = call i64 @llvm.ppc.darn()
-// CHECK-NEXT:ret i64 [[TMP0]]
+#ifdef __PPC64__
+// CHECK-64-LABEL: @testdarn(
+// CHECK-64: [[TMP0:%.*]] = call i64 @llvm.ppc.darn()
+// CHECK-64-NEXT:ret i64 [[TMP0]]
 //
 long long testdarn(void) {
   return __darn();
 }
 
-// CHECK-LABEL: @testdarn_raw(
-// CHECK: [[TMP0:%.*]] = call i64 @llvm.ppc.darnraw()
-// CHECK-NEXT:ret i64 [[TMP0]]
+// CHECK-64-LABEL: @testdarn_raw(
+// CHECK-64: [[TMP0:%.*]] = call i64 @llvm.ppc.darnraw()
+// CHECK-64-NEXT:ret i64 [[TMP0]]
 //
 long long testdarn_raw(void) {
   return __darn_raw();
 }
+#endif
 
 // CHECK-LABEL: @testdarn_32(
 // CHECK: [[TMP0:%.*]] = call i32 @llvm.ppc.darn32()
Index: clang/lib/Sema/SemaChecking.cpp
===
--- clang/lib/Sema/SemaChecking.cpp
+++ clang/lib/Sema/SemaChecking.cpp
@@ -3295,6 +3295,8 @@
   case PPC::BI__builtin_ppc_insert_exp:
   case PPC::BI__builtin_ppc_extract_sig:
   case PPC::BI__builtin_ppc_addex:
+  case PPC::BI__builtin_darn:
+  case PPC::BI__builtin_darn_raw:
 return true;
   }
   return false;
@@ -3473,6 +3475,11 @@
 return SemaFeatureCheck(*this, TheCall, "isa-v207-instructions",
 diag::err_ppc_builtin_only_on_arch, "8") ||
SemaBuiltinConstantArgRange(TheCall, 1, 1, 16);
+  case PPC::BI__builtin_darn:
+  case PPC::BI__builtin_darn_raw:
+  case PPC::BI__builtin_darn_32:
+return SemaFeatureCheck(*this, TheCall, "isa-v30-instructions",
+diag::err_ppc_builtin_only_on_arch, "9");
 #define CUSTOM_BUILTIN(Name, Intr, Types, Acc) \
   case PPC::BI__builtin_##Name: \
 return SemaBuiltinPPCMMACall(TheCall, Types);
___
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[PATCH] D110273: [PowerPC] Fix lharx and lbarx builtin signatures

2021-09-23 Thread Albion Fung via Phabricator via cfe-commits

Conanap updated this revision to Diff 374556.
Conanap added a comment.

Added test cases


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D110273/new/

https://reviews.llvm.org/D110273

Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond.c


Index: clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond.c
===
--- clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond.c
+++ clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond.c
@@ -46,3 +46,18 @@
   // CHECK-NON-PWR8-ERR:  error: this builtin is only valid on POWER8 or later 
CPUs
   return __sthcx(a, val);
 }
+
+// extra test cases that previously caused error during usage
+int test_lharx_intret(volatile short *a) {
+  // CHECK-LABEL: @test_lharx_intret
+  // CHECK: %0 = tail call i16 asm sideeffect "lharx $0, ${1:y}", 
"=r,*Z,~{memory}"(i16* %a)
+  // CHECK-NON-PWR8-ERR:  error: this builtin is only valid on POWER8 or later 
CPUs
+  return __lharx(a);
+}
+
+int test_lbarx_intret(volatile char *a) {
+  // CHECK-LABEL: @test_lbarx_intret
+  // CHECK: %0 = tail call i8 asm sideeffect "lbarx $0, ${1:y}", 
"=r,*Z,~{memory}"(i8* %a)
+  // CHECK-NON-PWR8-ERR:  error: this builtin is only valid on POWER8 or later 
CPUs
+  return __lbarx(a);
+}
Index: clang/include/clang/Basic/BuiltinsPPC.def
===
--- clang/include/clang/Basic/BuiltinsPPC.def
+++ clang/include/clang/Basic/BuiltinsPPC.def
@@ -74,8 +74,8 @@
 BUILTIN(__builtin_ppc_fetch_and_swaplp, "ULiULiD*ULi", "")
 BUILTIN(__builtin_ppc_ldarx, "LiLiD*", "")
 BUILTIN(__builtin_ppc_lwarx, "iiD*", "")
-BUILTIN(__builtin_ppc_lharx, "isD*", "")
-BUILTIN(__builtin_ppc_lbarx, "UiUcD*", "")
+BUILTIN(__builtin_ppc_lharx, "ssD*", "")
+BUILTIN(__builtin_ppc_lbarx, "ccD*", "")
 BUILTIN(__builtin_ppc_stdcx, "iLiD*Li", "")
 BUILTIN(__builtin_ppc_stwcx, "iiD*i", "")
 BUILTIN(__builtin_ppc_sthcx, "isD*s", "")


Index: clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond.c
===
--- clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond.c
+++ clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond.c
@@ -46,3 +46,18 @@
   // CHECK-NON-PWR8-ERR:  error: this builtin is only valid on POWER8 or later CPUs
   return __sthcx(a, val);
 }
+
+// extra test cases that previously caused error during usage
+int test_lharx_intret(volatile short *a) {
+  // CHECK-LABEL: @test_lharx_intret
+  // CHECK: %0 = tail call i16 asm sideeffect "lharx $0, ${1:y}", "=r,*Z,~{memory}"(i16* %a)
+  // CHECK-NON-PWR8-ERR:  error: this builtin is only valid on POWER8 or later CPUs
+  return __lharx(a);
+}
+
+int test_lbarx_intret(volatile char *a) {
+  // CHECK-LABEL: @test_lbarx_intret
+  // CHECK: %0 = tail call i8 asm sideeffect "lbarx $0, ${1:y}", "=r,*Z,~{memory}"(i8* %a)
+  // CHECK-NON-PWR8-ERR:  error: this builtin is only valid on POWER8 or later CPUs
+  return __lbarx(a);
+}
Index: clang/include/clang/Basic/BuiltinsPPC.def
===
--- clang/include/clang/Basic/BuiltinsPPC.def
+++ clang/include/clang/Basic/BuiltinsPPC.def
@@ -74,8 +74,8 @@
 BUILTIN(__builtin_ppc_fetch_and_swaplp, "ULiULiD*ULi", "")
 BUILTIN(__builtin_ppc_ldarx, "LiLiD*", "")
 BUILTIN(__builtin_ppc_lwarx, "iiD*", "")
-BUILTIN(__builtin_ppc_lharx, "isD*", "")
-BUILTIN(__builtin_ppc_lbarx, "UiUcD*", "")
+BUILTIN(__builtin_ppc_lharx, "ssD*", "")
+BUILTIN(__builtin_ppc_lbarx, "ccD*", "")
 BUILTIN(__builtin_ppc_stdcx, "iLiD*Li", "")
 BUILTIN(__builtin_ppc_stwcx, "iiD*i", "")
 BUILTIN(__builtin_ppc_sthcx, "isD*s", "")
___
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[PATCH] D110282: [PowerPC] SemaChecking for darn family of builtins

2021-09-23 Thread Albion Fung via Phabricator via cfe-commits

Conanap added inline comments.



Comment at: clang/test/CodeGen/builtins-ppc-xlcompat-darn-32.c:13
+int testdarn_32(void) {
+  return __darn_32();
+}

lei wrote:
> Isn't this valid for both 32 and 64bit?
> Maybe change one of the run lines above to a 64bit test.
It is indeed valid for both 32 bit and 64 bit; there is already a runline for 
64 bit in the `clang/test/CodeGen/builtins-ppc-xlcompat-darn.c` test case 
(which includes `__darn_32`, which is why I didn't include it here.


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[PATCH] D110282: [PowerPC] SemaChecking for darn family of builtins

2021-09-22 Thread Albion Fung via Phabricator via cfe-commits

Conanap updated this revision to Diff 374329.
Conanap added a comment.

Added error testing


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D110282/new/

https://reviews.llvm.org/D110282

Files:
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/builtins-ppc-xlcompat-darn-32.c
  clang/test/CodeGen/builtins-ppc-xlcompat-darn.c
  clang/test/CodeGen/builtins-ppc-xlcompat-error.c
  clang/test/CodeGen/builtins-ppc.c

Index: clang/test/CodeGen/builtins-ppc.c
===
--- clang/test/CodeGen/builtins-ppc.c
+++ clang/test/CodeGen/builtins-ppc.c
@@ -36,16 +36,3 @@
   // CHECK: call double @llvm.ppc.setflm(double %1)
   res = __builtin_setflm(res);
 }
-
-void test_builtin_ppc_darn() {
-  volatile long res;
-  volatile int x;
-  // CHECK: call i64 @llvm.ppc.darn()
-  res = __builtin_darn();
-
-  // CHECK: call i64 @llvm.ppc.darnraw()
-  res = __builtin_darn_raw();
-
-  // CHECK: call i32 @llvm.ppc.darn32()
-  x = __builtin_darn_32();
-}
Index: clang/test/CodeGen/builtins-ppc-xlcompat-error.c
===
--- clang/test/CodeGen/builtins-ppc-xlcompat-error.c
+++ clang/test/CodeGen/builtins-ppc-xlcompat-error.c
@@ -96,6 +96,14 @@
 unsigned long long testdivdeu(unsigned long long dividend, unsigned long long divisor) {
   return __divdeu(dividend, divisor); //expected-error {{this builtin is only available on 64-bit targets}}
 }
+
+int test_darn() {
+  return __darn(); //expected-error {{this builtin is only available on 64-bit targets}}
+}
+
+int test_darn_raw() {
+  return __darn_raw(); //expected-error {{this builtin is only available on 64-bit targets}}
+}
 #endif
 
 unsigned long test_mfspr(void) {
Index: clang/test/CodeGen/builtins-ppc-xlcompat-darn.c
===
--- clang/test/CodeGen/builtins-ppc-xlcompat-darn.c
+++ clang/test/CodeGen/builtins-ppc-xlcompat-darn.c
@@ -5,12 +5,6 @@
 // RUN:   -emit-llvm %s -o -  -target-cpu pwr9 | FileCheck %s
 // RUN: %clang_cc1 -triple powerpc64-unknown-aix \
 // RUN:-emit-llvm %s -o -  -target-cpu pwr9 | FileCheck %s
-// RUN: %clang_cc1 -triple powerpc-unknown-unknown \
-// RUN:-emit-llvm %s -o -  -target-cpu pwr9 | FileCheck %s
-// RUN: %clang_cc1 -triple powerpcle-unknown-unknown \
-// RUN:   -emit-llvm %s -o -  -target-cpu pwr9 | FileCheck %s
-// RUN: %clang_cc1 -triple powerpc-unknown-aix \
-// RUN:-emit-llvm %s -o -  -target-cpu pwr9 | FileCheck %s
 
 // The darn class of builtins are Power 9 and up and only darn_32 works in
 // 32 bit mode.
@@ -30,11 +24,3 @@
 long long testdarn_raw(void) {
   return __darn_raw();
 }
-
-// CHECK-LABEL: @testdarn_32(
-// CHECK: [[TMP0:%.*]] = call i32 @llvm.ppc.darn32()
-// CHECK-NEXT:ret i32 [[TMP0]]
-//
-int testdarn_32(void) {
-  return __darn_32();
-}
Index: clang/test/CodeGen/builtins-ppc-xlcompat-darn-32.c
===
--- /dev/null
+++ clang/test/CodeGen/builtins-ppc-xlcompat-darn-32.c
@@ -0,0 +1,14 @@
+// RUN: %clang_cc1 -triple powerpc-unknown-unknown \
+// RUN:-emit-llvm %s -o -  -target-cpu pwr9 | FileCheck %s
+// RUN: %clang_cc1 -triple powerpcle-unknown-unknown \
+// RUN:   -emit-llvm %s -o -  -target-cpu pwr9 | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc-unknown-aix \
+// RUN:-emit-llvm %s -o -  -target-cpu pwr9 | FileCheck %s
+
+// CHECK-LABEL: @testdarn_32(
+// CHECK: [[TMP0:%.*]] = call i32 @llvm.ppc.darn32()
+// CHECK-NEXT:ret i32 [[TMP0]]
+//
+int testdarn_32(void) {
+  return __darn_32();
+}
Index: clang/lib/Sema/SemaChecking.cpp
===
--- clang/lib/Sema/SemaChecking.cpp
+++ clang/lib/Sema/SemaChecking.cpp
@@ -3295,6 +3295,8 @@
   case PPC::BI__builtin_ppc_insert_exp:
   case PPC::BI__builtin_ppc_extract_sig:
   case PPC::BI__builtin_ppc_addex:
+  case PPC::BI__builtin_darn:
+  case PPC::BI__builtin_darn_raw:
 return true;
   }
   return false;
@@ -3473,6 +3475,11 @@
 return SemaFeatureCheck(*this, TheCall, "isa-v207-instructions",
 diag::err_ppc_builtin_only_on_arch, "8") ||
SemaBuiltinConstantArgRange(TheCall, 1, 1, 16);
+  case PPC::BI__builtin_darn:
+  case PPC::BI__builtin_darn_raw:
+  case PPC::BI__builtin_darn_32:
+return SemaFeatureCheck(*this, TheCall, "isa-v30-instructions",
+diag::err_ppc_builtin_only_on_arch, "9");
 #define CUSTOM_BUILTIN(Name, Intr, Types, Acc) \
   case PPC::BI__builtin_##Name: \
 return SemaBuiltinPPCMMACall(TheCall, Types);
___
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[PATCH] D110282: [PowerPC] SemaChecking for darn family of builtins

2021-09-22 Thread Albion Fung via Phabricator via cfe-commits

Conanap created this revision.
Conanap added reviewers: PowerPC, nemanjai, saghir, stefanp.
Conanap added projects: PowerPC, clang, LLVM.
Herald added a subscriber: kbarton.
Conanap requested review of this revision.

The `__darn` family of builtins are only available on Pwr9,
and only `__darn_32` is available on 32 bit, while the rest
are only available on 64 bit. The patch adds sema checking
for these builtins and separate the `__darn_32`'s 32 bit
test cases.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D110282

Files:
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/builtins-ppc-xlcompat-darn-32.c
  clang/test/CodeGen/builtins-ppc-xlcompat-darn.c
  clang/test/CodeGen/builtins-ppc.c


Index: clang/test/CodeGen/builtins-ppc.c
===
--- clang/test/CodeGen/builtins-ppc.c
+++ clang/test/CodeGen/builtins-ppc.c
@@ -36,16 +36,3 @@
   // CHECK: call double @llvm.ppc.setflm(double %1)
   res = __builtin_setflm(res);
 }
-
-void test_builtin_ppc_darn() {
-  volatile long res;
-  volatile int x;
-  // CHECK: call i64 @llvm.ppc.darn()
-  res = __builtin_darn();
-
-  // CHECK: call i64 @llvm.ppc.darnraw()
-  res = __builtin_darn_raw();
-
-  // CHECK: call i32 @llvm.ppc.darn32()
-  x = __builtin_darn_32();
-}
Index: clang/test/CodeGen/builtins-ppc-xlcompat-darn.c
===
--- clang/test/CodeGen/builtins-ppc-xlcompat-darn.c
+++ clang/test/CodeGen/builtins-ppc-xlcompat-darn.c
@@ -5,12 +5,6 @@
 // RUN:   -emit-llvm %s -o -  -target-cpu pwr9 | FileCheck %s
 // RUN: %clang_cc1 -triple powerpc64-unknown-aix \
 // RUN:-emit-llvm %s -o -  -target-cpu pwr9 | FileCheck %s
-// RUN: %clang_cc1 -triple powerpc-unknown-unknown \
-// RUN:-emit-llvm %s -o -  -target-cpu pwr9 | FileCheck %s
-// RUN: %clang_cc1 -triple powerpcle-unknown-unknown \
-// RUN:   -emit-llvm %s -o -  -target-cpu pwr9 | FileCheck %s
-// RUN: %clang_cc1 -triple powerpc-unknown-aix \
-// RUN:-emit-llvm %s -o -  -target-cpu pwr9 | FileCheck %s
 
 // The darn class of builtins are Power 9 and up and only darn_32 works in
 // 32 bit mode.
@@ -30,11 +24,3 @@
 long long testdarn_raw(void) {
   return __darn_raw();
 }
-
-// CHECK-LABEL: @testdarn_32(
-// CHECK: [[TMP0:%.*]] = call i32 @llvm.ppc.darn32()
-// CHECK-NEXT:ret i32 [[TMP0]]
-//
-int testdarn_32(void) {
-  return __darn_32();
-}
Index: clang/test/CodeGen/builtins-ppc-xlcompat-darn-32.c
===
--- /dev/null
+++ clang/test/CodeGen/builtins-ppc-xlcompat-darn-32.c
@@ -0,0 +1,14 @@
+// RUN: %clang_cc1 -triple powerpc-unknown-unknown \
+// RUN:-emit-llvm %s -o -  -target-cpu pwr9 | FileCheck %s
+// RUN: %clang_cc1 -triple powerpcle-unknown-unknown \
+// RUN:   -emit-llvm %s -o -  -target-cpu pwr9 | FileCheck %s
+// RUN: %clang_cc1 -triple powerpc-unknown-aix \
+// RUN:-emit-llvm %s -o -  -target-cpu pwr9 | FileCheck %s
+
+// CHECK-LABEL: @testdarn_32(
+// CHECK: [[TMP0:%.*]] = call i32 @llvm.ppc.darn32()
+// CHECK-NEXT:ret i32 [[TMP0]]
+//
+int testdarn_32(void) {
+  return __darn_32();
+}
Index: clang/lib/Sema/SemaChecking.cpp
===
--- clang/lib/Sema/SemaChecking.cpp
+++ clang/lib/Sema/SemaChecking.cpp
@@ -3295,6 +3295,8 @@
   case PPC::BI__builtin_ppc_insert_exp:
   case PPC::BI__builtin_ppc_extract_sig:
   case PPC::BI__builtin_ppc_addex:
+  case PPC::BI__builtin_darn:
+  case PPC::BI__builtin_darn_raw:
 return true;
   }
   return false;
@@ -3473,6 +3475,11 @@
 return SemaFeatureCheck(*this, TheCall, "isa-v207-instructions",
 diag::err_ppc_builtin_only_on_arch, "8") ||
SemaBuiltinConstantArgRange(TheCall, 1, 1, 16);
+  case PPC::BI__builtin_darn:
+  case PPC::BI__builtin_darn_raw:
+  case PPC::BI__builtin_darn_32:
+return SemaFeatureCheck(*this, TheCall, "isa-v30-instructions",
+diag::err_ppc_builtin_only_on_arch, "9");
 #define CUSTOM_BUILTIN(Name, Intr, Types, Acc) \
   case PPC::BI__builtin_##Name: \
 return SemaBuiltinPPCMMACall(TheCall, Types);


Index: clang/test/CodeGen/builtins-ppc.c
===
--- clang/test/CodeGen/builtins-ppc.c
+++ clang/test/CodeGen/builtins-ppc.c
@@ -36,16 +36,3 @@
   // CHECK: call double @llvm.ppc.setflm(double %1)
   res = __builtin_setflm(res);
 }
-
-void test_builtin_ppc_darn() {
-  volatile long res;
-  volatile int x;
-  // CHECK: call i64 @llvm.ppc.darn()
-  res = __builtin_darn();
-
-  // CHECK: call i64 @llvm.ppc.darnraw()
-  res = __builtin_darn_raw();
-
-  // CHECK: call i32 @llvm.ppc.darn32()
-  x = __builtin_darn_32();
-}
Index: clang/test/CodeGen/builtins-ppc-xlcompat-darn.c
===
--- clang/test/CodeGen/builtins-ppc-xlcompat-darn.c
+++

[PATCH] D110273: [PowerPC] Fix lharx and lbarx builtin signatures

2021-09-22 Thread Albion Fung via Phabricator via cfe-commits

Conanap created this revision.
Conanap added reviewers: PowerPC, nemanjai, stefanp, saghir.
Conanap added projects: clang, LLVM, PowerPC.
Herald added subscribers: steven.zhang, kbarton.
Conanap requested review of this revision.

The signatures for the PowerPC builtins `lharx` and
`lbarx` are incorrect, and causes issues when in a function
that requiers the return of the builtin to be promoted.
This patch fixes these signatures.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D110273

Files:
  clang/include/clang/Basic/BuiltinsPPC.def


Index: clang/include/clang/Basic/BuiltinsPPC.def
===
--- clang/include/clang/Basic/BuiltinsPPC.def
+++ clang/include/clang/Basic/BuiltinsPPC.def
@@ -74,8 +74,8 @@
 BUILTIN(__builtin_ppc_fetch_and_swaplp, "ULiULiD*ULi", "")
 BUILTIN(__builtin_ppc_ldarx, "LiLiD*", "")
 BUILTIN(__builtin_ppc_lwarx, "iiD*", "")
-BUILTIN(__builtin_ppc_lharx, "isD*", "")
-BUILTIN(__builtin_ppc_lbarx, "UiUcD*", "")
+BUILTIN(__builtin_ppc_lharx, "ssD*", "")
+BUILTIN(__builtin_ppc_lbarx, "ccD*", "")
 BUILTIN(__builtin_ppc_stdcx, "iLiD*Li", "")
 BUILTIN(__builtin_ppc_stwcx, "iiD*i", "")
 BUILTIN(__builtin_ppc_sthcx, "isD*s", "")


Index: clang/include/clang/Basic/BuiltinsPPC.def
===
--- clang/include/clang/Basic/BuiltinsPPC.def
+++ clang/include/clang/Basic/BuiltinsPPC.def
@@ -74,8 +74,8 @@
 BUILTIN(__builtin_ppc_fetch_and_swaplp, "ULiULiD*ULi", "")
 BUILTIN(__builtin_ppc_ldarx, "LiLiD*", "")
 BUILTIN(__builtin_ppc_lwarx, "iiD*", "")
-BUILTIN(__builtin_ppc_lharx, "isD*", "")
-BUILTIN(__builtin_ppc_lbarx, "UiUcD*", "")
+BUILTIN(__builtin_ppc_lharx, "ssD*", "")
+BUILTIN(__builtin_ppc_lbarx, "ccD*", "")
 BUILTIN(__builtin_ppc_stdcx, "iLiD*Li", "")
 BUILTIN(__builtin_ppc_stwcx, "iiD*i", "")
 BUILTIN(__builtin_ppc_sthcx, "isD*s", "")
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[PATCH] D109902: [PowerPC] Improved codegen related to xscvdpsxws/xscvdpuxws

2021-09-21 Thread Albion Fung via Phabricator via cfe-commits

Conanap updated this revision to Diff 374059.
Conanap marked an inline comment as done.
Conanap added a comment.

Removed AIX test line as it has the same code gen as BE


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D109902/new/

https://reviews.llvm.org/D109902

Files:
  llvm/lib/Target/PowerPC/PPCInstrVSX.td
  llvm/test/CodeGen/PowerPC/test-vector-insert.ll
  llvm/test/CodeGen/PowerPC/vec_conv_fp64_to_i32_elts.ll

Index: llvm/test/CodeGen/PowerPC/vec_conv_fp64_to_i32_elts.ll
===
--- llvm/test/CodeGen/PowerPC/vec_conv_fp64_to_i32_elts.ll
+++ llvm/test/CodeGen/PowerPC/vec_conv_fp64_to_i32_elts.ll
@@ -13,12 +13,8 @@
 ; CHECK-P8-LABEL: test2elt:
 ; CHECK-P8:   # %bb.0: # %entry
 ; CHECK-P8-NEXT:xxswapd vs0, v2
-; CHECK-P8-NEXT:xscvdpuxws f1, v2
-; CHECK-P8-NEXT:xscvdpuxws f0, f0
-; CHECK-P8-NEXT:mffprwz r3, f1
-; CHECK-P8-NEXT:mtvsrwz v2, r3
-; CHECK-P8-NEXT:mffprwz r4, f0
-; CHECK-P8-NEXT:mtvsrwz v3, r4
+; CHECK-P8-NEXT:xscvdpsxws v2, v2
+; CHECK-P8-NEXT:xscvdpsxws v3, f0
 ; CHECK-P8-NEXT:vmrghw v2, v2, v3
 ; CHECK-P8-NEXT:xxswapd vs0, v2
 ; CHECK-P8-NEXT:mffprd r3, f0
@@ -26,26 +22,18 @@
 ;
 ; CHECK-P9-LABEL: test2elt:
 ; CHECK-P9:   # %bb.0: # %entry
-; CHECK-P9-NEXT:xscvdpuxws f0, v2
-; CHECK-P9-NEXT:mffprwz r3, f0
 ; CHECK-P9-NEXT:xxswapd vs0, v2
-; CHECK-P9-NEXT:mtvsrwz v3, r3
-; CHECK-P9-NEXT:xscvdpuxws f0, f0
-; CHECK-P9-NEXT:mffprwz r3, f0
-; CHECK-P9-NEXT:mtvsrwz v2, r3
+; CHECK-P9-NEXT:xscvdpsxws v3, v2
+; CHECK-P9-NEXT:xscvdpsxws v2, f0
 ; CHECK-P9-NEXT:vmrghw v2, v3, v2
 ; CHECK-P9-NEXT:mfvsrld r3, v2
 ; CHECK-P9-NEXT:blr
 ;
 ; CHECK-BE-LABEL: test2elt:
 ; CHECK-BE:   # %bb.0: # %entry
-; CHECK-BE-NEXT:xscvdpuxws f0, v2
-; CHECK-BE-NEXT:mffprwz r3, f0
 ; CHECK-BE-NEXT:xxswapd vs0, v2
-; CHECK-BE-NEXT:mtvsrwz v3, r3
-; CHECK-BE-NEXT:xscvdpuxws f0, f0
-; CHECK-BE-NEXT:mffprwz r3, f0
-; CHECK-BE-NEXT:mtvsrwz v2, r3
+; CHECK-BE-NEXT:xscvdpsxws v3, v2
+; CHECK-BE-NEXT:xscvdpsxws v2, f0
 ; CHECK-BE-NEXT:vmrgow v2, v3, v2
 ; CHECK-BE-NEXT:mfvsrd r3, v2
 ; CHECK-BE-NEXT:blr
@@ -305,12 +293,8 @@
 ; CHECK-P8-LABEL: test2elt_signed:
 ; CHECK-P8:   # %bb.0: # %entry
 ; CHECK-P8-NEXT:xxswapd vs0, v2
-; CHECK-P8-NEXT:xscvdpsxws f1, v2
-; CHECK-P8-NEXT:xscvdpsxws f0, f0
-; CHECK-P8-NEXT:mffprwz r3, f1
-; CHECK-P8-NEXT:mtvsrwz v2, r3
-; CHECK-P8-NEXT:mffprwz r4, f0
-; CHECK-P8-NEXT:mtvsrwz v3, r4
+; CHECK-P8-NEXT:xscvdpsxws v2, v2
+; CHECK-P8-NEXT:xscvdpsxws v3, f0
 ; CHECK-P8-NEXT:vmrghw v2, v2, v3
 ; CHECK-P8-NEXT:xxswapd vs0, v2
 ; CHECK-P8-NEXT:mffprd r3, f0
@@ -318,26 +302,18 @@
 ;
 ; CHECK-P9-LABEL: test2elt_signed:
 ; CHECK-P9:   # %bb.0: # %entry
-; CHECK-P9-NEXT:xscvdpsxws f0, v2
-; CHECK-P9-NEXT:mffprwz r3, f0
 ; CHECK-P9-NEXT:xxswapd vs0, v2
-; CHECK-P9-NEXT:mtvsrwz v3, r3
-; CHECK-P9-NEXT:xscvdpsxws f0, f0
-; CHECK-P9-NEXT:mffprwz r3, f0
-; CHECK-P9-NEXT:mtvsrwz v2, r3
+; CHECK-P9-NEXT:xscvdpsxws v3, v2
+; CHECK-P9-NEXT:xscvdpsxws v2, f0
 ; CHECK-P9-NEXT:vmrghw v2, v3, v2
 ; CHECK-P9-NEXT:mfvsrld r3, v2
 ; CHECK-P9-NEXT:blr
 ;
 ; CHECK-BE-LABEL: test2elt_signed:
 ; CHECK-BE:   # %bb.0: # %entry
-; CHECK-BE-NEXT:xscvdpsxws f0, v2
-; CHECK-BE-NEXT:mffprwz r3, f0
 ; CHECK-BE-NEXT:xxswapd vs0, v2
-; CHECK-BE-NEXT:mtvsrwz v3, r3
-; CHECK-BE-NEXT:xscvdpsxws f0, f0
-; CHECK-BE-NEXT:mffprwz r3, f0
-; CHECK-BE-NEXT:mtvsrwz v2, r3
+; CHECK-BE-NEXT:xscvdpsxws v3, v2
+; CHECK-BE-NEXT:xscvdpsxws v2, f0
 ; CHECK-BE-NEXT:vmrgow v2, v3, v2
 ; CHECK-BE-NEXT:mfvsrd r3, v2
 ; CHECK-BE-NEXT:blr
Index: llvm/test/CodeGen/PowerPC/test-vector-insert.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/test-vector-insert.ll
@@ -0,0 +1,118 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; xscvdpsxws and uxws is only available on Power7 and above
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:  -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN:  -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-BE
+
+define dso_local <4 x i32> @test(<4 x i32> %a, double %b) {
+; CHECK-LE-LABEL: test:
+; CHECK-LE:   # %bb.0: # %entry
+; CHECK-LE-NEXT:xscvdpsxws 35, 1
+; CHECK-LE-NEXT:addis 3, 2, .LCPI0_0@toc@ha
+; CHECK-LE-NEXT:addi 3, 3, .LCPI0_0@toc@l
+; CHECK-LE-NEXT:lvx 4, 0, 3
+; CHECK-LE-NEXT:vperm 2, 3, 2, 4
+; CHECK-LE-NEXT:blr
+;
+; CHECK-BE-LABEL: test:
+; CHECK-BE:   # %bb.0: # %entry
+; CHECK-BE-NEXT:xscvdpsxws 0, 1
+; CHECK-BE-NEXT:addi 3, 1, -4
+; CHECK-BE-NEXT:stfiwx 0, 0, 3
+; CHECK-BE-NEXT:

[PATCH] D110084: [PowerPC] Support for vector bool int128 on vector comparison builtins

2021-09-21 Thread Albion Fung via Phabricator via cfe-commits

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGb93359ea3fe5: [PowerPC] Support for vector bool int128 on 
vector comparison builtins (authored by Conanap).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D110084/new/

https://reviews.llvm.org/D110084

Files:
  clang/lib/Headers/altivec.h
  clang/test/CodeGen/builtins-ppc-p10vector.c

Index: clang/test/CodeGen/builtins-ppc-p10vector.c
===
--- clang/test/CodeGen/builtins-ppc-p10vector.c
+++ clang/test/CodeGen/builtins-ppc-p10vector.c
@@ -19,6 +19,7 @@
 vector unsigned long long vulla, vullb, vullc;
 vector signed __int128 vsi128a, vsi128b, vsi128c;
 vector unsigned __int128 vui128a, vui128b, vui128c;
+vector bool __int128 vbi128a, vbi128b;
 vector float vfa, vfb;
 vector double vda, vdb;
 float fa;
@@ -1637,6 +1638,13 @@
   return vec_cmpeq(vui128a, vui128b);
 }
 
+vector bool __int128 test_vec_cmpeq_bool_int128(void) {
+  // CHECK-LABEL: @test_vec_cmpeq_bool_int128(
+  // CHECK: call <1 x i128> @llvm.ppc.altivec.vcmpequq(<1 x i128>
+  // CHECK-NEXT: ret <1 x i128>
+  return vec_cmpeq(vbi128a, vbi128b);
+}
+
 vector bool __int128 test_vec_cmpne_s128(void) {
   // CHECK-LABEL: @test_vec_cmpne_s128(
   // CHECK: call <1 x i128> @llvm.ppc.altivec.vcmpequq(<1 x i128>
@@ -1653,6 +1661,14 @@
   return vec_cmpne(vui128a, vui128b);
 }
 
+vector bool __int128 test_vec_cmpne_bool_int128(void) {
+  // CHECK-LABEL: @test_vec_cmpne_bool_int128(
+  // CHECK: call <1 x i128> @llvm.ppc.altivec.vcmpequq(<1 x i128>
+  // CHECK-NEXT: %neg.i = xor <1 x i128> %4, 
+  // CHECK-NEXT: ret <1 x i128>
+  return vec_cmpne(vbi128a, vbi128b);
+}
+
 vector bool __int128 test_vec_cmpgt_s128(void) {
   // CHECK-LABEL: @test_vec_cmpgt_s128(
   // CHECK: call <1 x i128> @llvm.ppc.altivec.vcmpgtsq(<1 x i128>
@@ -1727,6 +1743,13 @@
   return vec_any_eq(vsi128a, vsi128b);
 }
 
+int test_vec_any_eq_bool_int128(void) {
+  // CHECK-LABEL: @test_vec_any_eq_bool_int128(
+  // CHECK: call i32 @llvm.ppc.altivec.vcmpequq.p(i32 1, <1 x i128> %2, <1 x i128> %3)
+  // CHECK-NEXT: ret i32
+  return vec_any_eq(vbi128a, vbi128b);
+}
+
 int test_vec_any_ne_s128(void) {
   // CHECK-LABEL: @test_vec_any_ne_s128(
   // CHECK: call i32 @llvm.ppc.altivec.vcmpequq.p(i32 3, <1 x i128> %2, <1 x i128> %3)
@@ -1741,6 +1764,13 @@
   return vec_any_ne(vui128a, vui128b);
 }
 
+int test_vec_any_ne_bool_int128(void) {
+  // CHECK-LABEL: @test_vec_any_ne_bool_int128(
+  // CHECK: call i32 @llvm.ppc.altivec.vcmpequq.p(i32 3, <1 x i128> %2, <1 x i128> %3)
+  // CHECK-NEXT: ret i32
+  return vec_any_ne(vbi128a, vbi128b);
+}
+
 int test_vec_any_lt_s128(void) {
   // CHECK-LABEL: @test_vec_any_lt_s128(
   // CHECK: call i32 @llvm.ppc.altivec.vcmpgtsq.p(i32 1, <1 x i128> %2, <1 x i128> %3)
@@ -1811,6 +1841,13 @@
   return vec_all_eq(vui128a, vui128b);
 }
 
+int test_vec_all_eq_bool_int128(void) {
+  // CHECK-LABEL: @test_vec_all_eq_bool_int128
+  // CHECK: call i32 @llvm.ppc.altivec.vcmpequq.p(i32 2, <1 x i128> %2, <1 x i128> %3)
+  // CHECK-NEXT: ret i32
+  return vec_all_eq(vbi128a, vbi128b);
+}
+
 int test_vec_all_ne_s128(void) {
   // CHECK-LABEL: @test_vec_all_ne_s128(
   // CHECK: call i32 @llvm.ppc.altivec.vcmpequq.p(i32 0, <1 x i128> %2, <1 x i128> %3)
@@ -1825,6 +1862,13 @@
   return vec_all_ne(vui128a, vui128b);
 }
 
+int test_vec_all_ne_bool_int128(void) {
+  // CHECK-LABEL: test_vec_all_ne_bool_int128
+  // CHECK: call i32 @llvm.ppc.altivec.vcmpequq.p(i32 0, <1 x i128> %2, <1 x i128> %3)
+  // CHECK-NEXT: ret i32
+  return vec_all_ne(vbi128a, vbi128b);
+}
+
 int test_vec_all_lt_s128(void) {
   // CHECK-LABEL: @test_vec_all_lt_s128(
   // CHECK: call i32 @llvm.ppc.altivec.vcmpgtsq.p(i32 2, <1 x i128> %2, <1 x i128> %3)
Index: clang/lib/Headers/altivec.h
===
--- clang/lib/Headers/altivec.h
+++ clang/lib/Headers/altivec.h
@@ -1810,6 +1810,11 @@
   return (vector bool __int128)__builtin_altivec_vcmpequq(
   (vector bool __int128)__a, (vector bool __int128)__b);
 }
+
+static __inline__ vector bool __int128 __ATTRS_o_ai
+vec_cmpeq(vector bool __int128 __a, vector bool  __int128 __b) {
+  return (vector bool __int128)__builtin_altivec_vcmpequq(__a, __b);
+}
 #endif
 
 #ifdef __POWER9_VECTOR__
@@ -1887,6 +1892,11 @@
   return (vector bool __int128) ~(__builtin_altivec_vcmpequq(
   (vector bool __int128)__a, (vector bool __int128)__b));
 }
+
+static __inline__ vector bool __int128 __ATTRS_o_ai
+vec_cmpne(vector bool __int128 __a, vector bool __int128 __b) {
+  return (vector bool __int128) ~(__builtin_altivec_vcmpequq(__a, __b));
+}
 #endif
 
 /* vec_cmpnez */
@@ -14870,6 +14880,11 @@
   vector unsigned __int128 __b) {
   return __builtin_altivec_vcmpequq_p(__CR6_LT, __a, __b);
 }
+
+static __inline__ int

[PATCH] D109780: [PowerPC] Add range check for vec_genpcvm builtins

2021-09-20 Thread Albion Fung via Phabricator via cfe-commits

Conanap accepted this revision.
Conanap added a comment.
This revision is now accepted and ready to land.

lgtm


Repository:
  rG LLVM Github Monorepo

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[PATCH] D109996: [PowerPC] Fix signature of lxvp and stxvp builtins

2021-09-20 Thread Albion Fung via Phabricator via cfe-commits

Conanap accepted this revision as: Conanap.
Conanap added a comment.
This revision is now accepted and ready to land.

lgtm


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[PATCH] D109652: [PowerPC] Restrict various P10 options to P10 only.

2021-09-20 Thread Albion Fung via Phabricator via cfe-commits

Conanap accepted this revision.
Conanap added a comment.
This revision is now accepted and ready to land.

LGTM


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[PATCH] D110084: [PowerPC] Support for vector bool int128 on vector comparison builtins

2021-09-20 Thread Albion Fung via Phabricator via cfe-commits

Conanap created this revision.
Conanap added reviewers: PowerPC, saghir, nemanjai.
Conanap added projects: PowerPC, clang, LLVM.
Herald added a subscriber: kbarton.
Conanap requested review of this revision.

This patch implements support for the type `vector bool int128`
for arguments on vector comparison builtins, which would
otherwise crash due to ambiguity.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D110084

Files:
  clang/lib/Headers/altivec.h
  clang/test/CodeGen/builtins-ppc-p10vector.c

Index: clang/test/CodeGen/builtins-ppc-p10vector.c
===
--- clang/test/CodeGen/builtins-ppc-p10vector.c
+++ clang/test/CodeGen/builtins-ppc-p10vector.c
@@ -19,6 +19,7 @@
 vector unsigned long long vulla, vullb, vullc;
 vector signed __int128 vsi128a, vsi128b, vsi128c;
 vector unsigned __int128 vui128a, vui128b, vui128c;
+vector bool __int128 vbi128a, vbi128b;
 vector float vfa, vfb;
 vector double vda, vdb;
 float fa;
@@ -1637,6 +1638,13 @@
   return vec_cmpeq(vui128a, vui128b);
 }
 
+vector bool __int128 test_vec_cmpeq_bool_int128(void) {
+  // CHECK-LABEL: @test_vec_cmpeq_bool_int128(
+  // CHECK: call <1 x i128> @llvm.ppc.altivec.vcmpequq(<1 x i128>
+  // CHECK-NEXT: ret <1 x i128>
+  return vec_cmpeq(vbi128a, vbi128b);
+}
+
 vector bool __int128 test_vec_cmpne_s128(void) {
   // CHECK-LABEL: @test_vec_cmpne_s128(
   // CHECK: call <1 x i128> @llvm.ppc.altivec.vcmpequq(<1 x i128>
@@ -1653,6 +1661,14 @@
   return vec_cmpne(vui128a, vui128b);
 }
 
+vector bool __int128 test_vec_cmpne_bool_int128(void) {
+  // CHECK-LABEL: @test_vec_cmpne_bool_int128(
+  // CHECK: call <1 x i128> @llvm.ppc.altivec.vcmpequq(<1 x i128>
+  // CHECK-NEXT: %neg.i = xor <1 x i128> %4, 
+  // CHECK-NEXT: ret <1 x i128>
+  return vec_cmpne(vbi128a, vbi128b);
+}
+
 vector bool __int128 test_vec_cmpgt_s128(void) {
   // CHECK-LABEL: @test_vec_cmpgt_s128(
   // CHECK: call <1 x i128> @llvm.ppc.altivec.vcmpgtsq(<1 x i128>
@@ -1727,6 +1743,13 @@
   return vec_any_eq(vsi128a, vsi128b);
 }
 
+int test_vec_any_eq_bool_int128(void) {
+  // CHECK-LABEL: @test_vec_any_eq_bool_int128(
+  // CHECK: call i32 @llvm.ppc.altivec.vcmpequq.p(i32 1, <1 x i128> %2, <1 x i128> %3)
+  // CHECK-NEXT: ret i32
+  return vec_any_eq(vbi128a, vbi128b);
+}
+
 int test_vec_any_ne_s128(void) {
   // CHECK-LABEL: @test_vec_any_ne_s128(
   // CHECK: call i32 @llvm.ppc.altivec.vcmpequq.p(i32 3, <1 x i128> %2, <1 x i128> %3)
@@ -1741,6 +1764,13 @@
   return vec_any_ne(vui128a, vui128b);
 }
 
+int test_vec_any_ne_bool_int128(void) {
+  // CHECK-LABEL: @test_vec_any_ne_bool_int128(
+  // CHECK: call i32 @llvm.ppc.altivec.vcmpequq.p(i32 3, <1 x i128> %2, <1 x i128> %3)
+  // CHECK-NEXT: ret i32
+  return vec_any_ne(vbi128a, vbi128b);
+}
+
 int test_vec_any_lt_s128(void) {
   // CHECK-LABEL: @test_vec_any_lt_s128(
   // CHECK: call i32 @llvm.ppc.altivec.vcmpgtsq.p(i32 1, <1 x i128> %2, <1 x i128> %3)
@@ -1811,6 +1841,13 @@
   return vec_all_eq(vui128a, vui128b);
 }
 
+int test_vec_all_eq_bool_int128(void) {
+  // CHECK-LABEL: @test_vec_all_eq_bool_int128
+  // CHECK: call i32 @llvm.ppc.altivec.vcmpequq.p(i32 2, <1 x i128> %2, <1 x i128> %3)
+  // CHECK-NEXT: ret i32
+  return vec_all_eq(vbi128a, vbi128b);
+}
+
 int test_vec_all_ne_s128(void) {
   // CHECK-LABEL: @test_vec_all_ne_s128(
   // CHECK: call i32 @llvm.ppc.altivec.vcmpequq.p(i32 0, <1 x i128> %2, <1 x i128> %3)
@@ -1825,6 +1862,13 @@
   return vec_all_ne(vui128a, vui128b);
 }
 
+int test_vec_all_ne_bool_int128(void) {
+  // CHECK-LABEL: test_vec_all_ne_bool_int128
+  // CHECK: call i32 @llvm.ppc.altivec.vcmpequq.p(i32 0, <1 x i128> %2, <1 x i128> %3)
+  // CHECK-NEXT: ret i32
+  return vec_all_ne(vbi128a, vbi128b);
+}
+
 int test_vec_all_lt_s128(void) {
   // CHECK-LABEL: @test_vec_all_lt_s128(
   // CHECK: call i32 @llvm.ppc.altivec.vcmpgtsq.p(i32 2, <1 x i128> %2, <1 x i128> %3)
Index: clang/lib/Headers/altivec.h
===
--- clang/lib/Headers/altivec.h
+++ clang/lib/Headers/altivec.h
@@ -1805,6 +1805,11 @@
   return (vector bool __int128)__builtin_altivec_vcmpequq(
   (vector bool __int128)__a, (vector bool __int128)__b);
 }
+
+static __inline__ vector bool __int128 __ATTRS_o_ai
+vec_cmpeq(vector bool __int128 __a, vector bool  __int128 __b) {
+  return (vector bool __int128)__builtin_altivec_vcmpequq(__a, __b);
+}
 #endif
 
 #ifdef __POWER9_VECTOR__
@@ -1882,6 +1887,11 @@
   return (vector bool __int128) ~(__builtin_altivec_vcmpequq(
   (vector bool __int128)__a, (vector bool __int128)__b));
 }
+
+static __inline__ vector bool __int128 __ATTRS_o_ai
+vec_cmpne(vector bool __int128 __a, vector bool __int128 __b) {
+  return (vector bool __int128) ~(__builtin_altivec_vcmpequq(__a, __b));
+}
 #endif
 
 /* vec_cmpnez */
@@ -14865,6 +14875,11 @@
   vector unsigned __int128 __b) {
   return __builtin_altivec_vcmpequq_p(__CR6_LT,

[PATCH] D109437: [PowerPC] FP compare and test XL compat builtins.

2021-09-17 Thread Albion Fung via Phabricator via cfe-commits

Conanap added inline comments.



Comment at: clang/lib/Sema/SemaChecking.cpp:3490
+   SemaBuiltinConstantArgRange(TheCall, 1, 0, 127) ||
+   CheckPPCTestDataClassType(TheCall);
 #define CUSTOM_BUILTIN(Name, Intr, Types, Acc) \

If you're making a function anyways, it may be a good idea to just have a 
function with all the sema checking in it


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D109437/new/

https://reviews.llvm.org/D109437

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D109902: [PowerPC] Improved codegen related to xscvdpsxws/xscvdpuxws

2021-09-16 Thread Albion Fung via Phabricator via cfe-commits

Conanap updated this revision to Diff 373045.
Conanap edited the summary of this revision.
Conanap added a comment.

Removed complexity and restored a test case


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D109902/new/

https://reviews.llvm.org/D109902

Files:
  llvm/lib/Target/PowerPC/PPCInstrVSX.td
  llvm/test/CodeGen/PowerPC/test-vector-insert.ll
  llvm/test/CodeGen/PowerPC/vec_conv_fp64_to_i32_elts.ll

Index: llvm/test/CodeGen/PowerPC/vec_conv_fp64_to_i32_elts.ll
===
--- llvm/test/CodeGen/PowerPC/vec_conv_fp64_to_i32_elts.ll
+++ llvm/test/CodeGen/PowerPC/vec_conv_fp64_to_i32_elts.ll
@@ -13,12 +13,8 @@
 ; CHECK-P8-LABEL: test2elt:
 ; CHECK-P8:   # %bb.0: # %entry
 ; CHECK-P8-NEXT:xxswapd vs0, v2
-; CHECK-P8-NEXT:xscvdpuxws f1, v2
-; CHECK-P8-NEXT:xscvdpuxws f0, f0
-; CHECK-P8-NEXT:mffprwz r3, f1
-; CHECK-P8-NEXT:mtvsrwz v2, r3
-; CHECK-P8-NEXT:mffprwz r4, f0
-; CHECK-P8-NEXT:mtvsrwz v3, r4
+; CHECK-P8-NEXT:xscvdpsxws v2, v2
+; CHECK-P8-NEXT:xscvdpsxws v3, f0
 ; CHECK-P8-NEXT:vmrghw v2, v2, v3
 ; CHECK-P8-NEXT:xxswapd vs0, v2
 ; CHECK-P8-NEXT:mffprd r3, f0
@@ -26,26 +22,18 @@
 ;
 ; CHECK-P9-LABEL: test2elt:
 ; CHECK-P9:   # %bb.0: # %entry
-; CHECK-P9-NEXT:xscvdpuxws f0, v2
-; CHECK-P9-NEXT:mffprwz r3, f0
 ; CHECK-P9-NEXT:xxswapd vs0, v2
-; CHECK-P9-NEXT:mtvsrwz v3, r3
-; CHECK-P9-NEXT:xscvdpuxws f0, f0
-; CHECK-P9-NEXT:mffprwz r3, f0
-; CHECK-P9-NEXT:mtvsrwz v2, r3
+; CHECK-P9-NEXT:xscvdpsxws v3, v2
+; CHECK-P9-NEXT:xscvdpsxws v2, f0
 ; CHECK-P9-NEXT:vmrghw v2, v3, v2
 ; CHECK-P9-NEXT:mfvsrld r3, v2
 ; CHECK-P9-NEXT:blr
 ;
 ; CHECK-BE-LABEL: test2elt:
 ; CHECK-BE:   # %bb.0: # %entry
-; CHECK-BE-NEXT:xscvdpuxws f0, v2
-; CHECK-BE-NEXT:mffprwz r3, f0
 ; CHECK-BE-NEXT:xxswapd vs0, v2
-; CHECK-BE-NEXT:mtvsrwz v3, r3
-; CHECK-BE-NEXT:xscvdpuxws f0, f0
-; CHECK-BE-NEXT:mffprwz r3, f0
-; CHECK-BE-NEXT:mtvsrwz v2, r3
+; CHECK-BE-NEXT:xscvdpsxws v3, v2
+; CHECK-BE-NEXT:xscvdpsxws v2, f0
 ; CHECK-BE-NEXT:vmrgow v2, v3, v2
 ; CHECK-BE-NEXT:mfvsrd r3, v2
 ; CHECK-BE-NEXT:blr
@@ -305,12 +293,8 @@
 ; CHECK-P8-LABEL: test2elt_signed:
 ; CHECK-P8:   # %bb.0: # %entry
 ; CHECK-P8-NEXT:xxswapd vs0, v2
-; CHECK-P8-NEXT:xscvdpsxws f1, v2
-; CHECK-P8-NEXT:xscvdpsxws f0, f0
-; CHECK-P8-NEXT:mffprwz r3, f1
-; CHECK-P8-NEXT:mtvsrwz v2, r3
-; CHECK-P8-NEXT:mffprwz r4, f0
-; CHECK-P8-NEXT:mtvsrwz v3, r4
+; CHECK-P8-NEXT:xscvdpsxws v2, v2
+; CHECK-P8-NEXT:xscvdpsxws v3, f0
 ; CHECK-P8-NEXT:vmrghw v2, v2, v3
 ; CHECK-P8-NEXT:xxswapd vs0, v2
 ; CHECK-P8-NEXT:mffprd r3, f0
@@ -318,26 +302,18 @@
 ;
 ; CHECK-P9-LABEL: test2elt_signed:
 ; CHECK-P9:   # %bb.0: # %entry
-; CHECK-P9-NEXT:xscvdpsxws f0, v2
-; CHECK-P9-NEXT:mffprwz r3, f0
 ; CHECK-P9-NEXT:xxswapd vs0, v2
-; CHECK-P9-NEXT:mtvsrwz v3, r3
-; CHECK-P9-NEXT:xscvdpsxws f0, f0
-; CHECK-P9-NEXT:mffprwz r3, f0
-; CHECK-P9-NEXT:mtvsrwz v2, r3
+; CHECK-P9-NEXT:xscvdpsxws v3, v2
+; CHECK-P9-NEXT:xscvdpsxws v2, f0
 ; CHECK-P9-NEXT:vmrghw v2, v3, v2
 ; CHECK-P9-NEXT:mfvsrld r3, v2
 ; CHECK-P9-NEXT:blr
 ;
 ; CHECK-BE-LABEL: test2elt_signed:
 ; CHECK-BE:   # %bb.0: # %entry
-; CHECK-BE-NEXT:xscvdpsxws f0, v2
-; CHECK-BE-NEXT:mffprwz r3, f0
 ; CHECK-BE-NEXT:xxswapd vs0, v2
-; CHECK-BE-NEXT:mtvsrwz v3, r3
-; CHECK-BE-NEXT:xscvdpsxws f0, f0
-; CHECK-BE-NEXT:mffprwz r3, f0
-; CHECK-BE-NEXT:mtvsrwz v2, r3
+; CHECK-BE-NEXT:xscvdpsxws v3, v2
+; CHECK-BE-NEXT:xscvdpsxws v2, f0
 ; CHECK-BE-NEXT:vmrgow v2, v3, v2
 ; CHECK-BE-NEXT:mfvsrd r3, v2
 ; CHECK-BE-NEXT:blr
Index: llvm/test/CodeGen/PowerPC/test-vector-insert.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/test-vector-insert.ll
@@ -0,0 +1,172 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; xscvdpsxws and uxws is only available on Power7 and above
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:  < %s | FileCheck %s --check-prefix=CHECK-LE
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN:  -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-BE
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN:  -mcpu=pwr7 < %s | FileCheck %s
+
+define dso_local <4 x i32> @test(<4 x i32> %a, double %b) {
+; CHECK-LE-LABEL: test:
+; CHECK-LE:   # %bb.0: # %entry
+; CHECK-LE-NEXT:xscvdpsxws 35, 1
+; CHECK-LE-NEXT:addis 3, 2, .LCPI0_0@toc@ha
+; CHECK-LE-NEXT:addi 3, 3, .LCPI0_0@toc@l
+; CHECK-LE-NEXT:lvx 4, 0, 3
+; CHECK-LE-NEXT:vperm 2, 3, 2, 4
+; CHECK-LE-NEXT:blr
+;
+; CHECK-BE-LABEL: test:
+; CHECK-BE:   # %bb.0: # %entry
+; CHECK-BE-NEXT:xscvdpsxws 0, 1

[PATCH] D109902: [PowerPC] Improved codegen related to xscvdpsxws/xscvdpuxws

2021-09-16 Thread Albion Fung via Phabricator via cfe-commits

Conanap updated this revision to Diff 373009.
Conanap added a comment.

Removed unintended change, moved pattern to more appropriate location, reduced 
added complexity to 600 as it still works.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D109902/new/

https://reviews.llvm.org/D109902

Files:
  llvm/lib/Target/PowerPC/PPCInstrVSX.td
  llvm/test/CodeGen/PowerPC/build-vector-tests.ll
  llvm/test/CodeGen/PowerPC/test-vector-insert.ll
  llvm/test/CodeGen/PowerPC/vec_conv_fp64_to_i32_elts.ll

Index: llvm/test/CodeGen/PowerPC/vec_conv_fp64_to_i32_elts.ll
===
--- llvm/test/CodeGen/PowerPC/vec_conv_fp64_to_i32_elts.ll
+++ llvm/test/CodeGen/PowerPC/vec_conv_fp64_to_i32_elts.ll
@@ -13,12 +13,8 @@
 ; CHECK-P8-LABEL: test2elt:
 ; CHECK-P8:   # %bb.0: # %entry
 ; CHECK-P8-NEXT:xxswapd vs0, v2
-; CHECK-P8-NEXT:xscvdpuxws f1, v2
-; CHECK-P8-NEXT:xscvdpuxws f0, f0
-; CHECK-P8-NEXT:mffprwz r3, f1
-; CHECK-P8-NEXT:mtvsrwz v2, r3
-; CHECK-P8-NEXT:mffprwz r4, f0
-; CHECK-P8-NEXT:mtvsrwz v3, r4
+; CHECK-P8-NEXT:xscvdpsxws v2, v2
+; CHECK-P8-NEXT:xscvdpsxws v3, f0
 ; CHECK-P8-NEXT:vmrghw v2, v2, v3
 ; CHECK-P8-NEXT:xxswapd vs0, v2
 ; CHECK-P8-NEXT:mffprd r3, f0
@@ -26,26 +22,18 @@
 ;
 ; CHECK-P9-LABEL: test2elt:
 ; CHECK-P9:   # %bb.0: # %entry
-; CHECK-P9-NEXT:xscvdpuxws f0, v2
-; CHECK-P9-NEXT:mffprwz r3, f0
 ; CHECK-P9-NEXT:xxswapd vs0, v2
-; CHECK-P9-NEXT:mtvsrwz v3, r3
-; CHECK-P9-NEXT:xscvdpuxws f0, f0
-; CHECK-P9-NEXT:mffprwz r3, f0
-; CHECK-P9-NEXT:mtvsrwz v2, r3
+; CHECK-P9-NEXT:xscvdpsxws v3, v2
+; CHECK-P9-NEXT:xscvdpsxws v2, f0
 ; CHECK-P9-NEXT:vmrghw v2, v3, v2
 ; CHECK-P9-NEXT:mfvsrld r3, v2
 ; CHECK-P9-NEXT:blr
 ;
 ; CHECK-BE-LABEL: test2elt:
 ; CHECK-BE:   # %bb.0: # %entry
-; CHECK-BE-NEXT:xscvdpuxws f0, v2
-; CHECK-BE-NEXT:mffprwz r3, f0
 ; CHECK-BE-NEXT:xxswapd vs0, v2
-; CHECK-BE-NEXT:mtvsrwz v3, r3
-; CHECK-BE-NEXT:xscvdpuxws f0, f0
-; CHECK-BE-NEXT:mffprwz r3, f0
-; CHECK-BE-NEXT:mtvsrwz v2, r3
+; CHECK-BE-NEXT:xscvdpsxws v3, v2
+; CHECK-BE-NEXT:xscvdpsxws v2, f0
 ; CHECK-BE-NEXT:vmrgow v2, v3, v2
 ; CHECK-BE-NEXT:mfvsrd r3, v2
 ; CHECK-BE-NEXT:blr
@@ -305,12 +293,8 @@
 ; CHECK-P8-LABEL: test2elt_signed:
 ; CHECK-P8:   # %bb.0: # %entry
 ; CHECK-P8-NEXT:xxswapd vs0, v2
-; CHECK-P8-NEXT:xscvdpsxws f1, v2
-; CHECK-P8-NEXT:xscvdpsxws f0, f0
-; CHECK-P8-NEXT:mffprwz r3, f1
-; CHECK-P8-NEXT:mtvsrwz v2, r3
-; CHECK-P8-NEXT:mffprwz r4, f0
-; CHECK-P8-NEXT:mtvsrwz v3, r4
+; CHECK-P8-NEXT:xscvdpsxws v2, v2
+; CHECK-P8-NEXT:xscvdpsxws v3, f0
 ; CHECK-P8-NEXT:vmrghw v2, v2, v3
 ; CHECK-P8-NEXT:xxswapd vs0, v2
 ; CHECK-P8-NEXT:mffprd r3, f0
@@ -318,26 +302,18 @@
 ;
 ; CHECK-P9-LABEL: test2elt_signed:
 ; CHECK-P9:   # %bb.0: # %entry
-; CHECK-P9-NEXT:xscvdpsxws f0, v2
-; CHECK-P9-NEXT:mffprwz r3, f0
 ; CHECK-P9-NEXT:xxswapd vs0, v2
-; CHECK-P9-NEXT:mtvsrwz v3, r3
-; CHECK-P9-NEXT:xscvdpsxws f0, f0
-; CHECK-P9-NEXT:mffprwz r3, f0
-; CHECK-P9-NEXT:mtvsrwz v2, r3
+; CHECK-P9-NEXT:xscvdpsxws v3, v2
+; CHECK-P9-NEXT:xscvdpsxws v2, f0
 ; CHECK-P9-NEXT:vmrghw v2, v3, v2
 ; CHECK-P9-NEXT:mfvsrld r3, v2
 ; CHECK-P9-NEXT:blr
 ;
 ; CHECK-BE-LABEL: test2elt_signed:
 ; CHECK-BE:   # %bb.0: # %entry
-; CHECK-BE-NEXT:xscvdpsxws f0, v2
-; CHECK-BE-NEXT:mffprwz r3, f0
 ; CHECK-BE-NEXT:xxswapd vs0, v2
-; CHECK-BE-NEXT:mtvsrwz v3, r3
-; CHECK-BE-NEXT:xscvdpsxws f0, f0
-; CHECK-BE-NEXT:mffprwz r3, f0
-; CHECK-BE-NEXT:mtvsrwz v2, r3
+; CHECK-BE-NEXT:xscvdpsxws v3, v2
+; CHECK-BE-NEXT:xscvdpsxws v2, f0
 ; CHECK-BE-NEXT:vmrgow v2, v3, v2
 ; CHECK-BE-NEXT:mfvsrd r3, v2
 ; CHECK-BE-NEXT:blr
Index: llvm/test/CodeGen/PowerPC/test-vector-insert.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/test-vector-insert.ll
@@ -0,0 +1,172 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; xscvdpsxws and uxws is only available on Power7 and above
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:  < %s | FileCheck %s --check-prefix=CHECK-LE
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN:  -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-BE
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN:  -mcpu=pwr7 < %s | FileCheck %s
+
+define dso_local <4 x i32> @test(<4 x i32> %a, double %b) {
+; CHECK-LE-LABEL: test:
+; CHECK-LE:   # %bb.0: # %entry
+; CHECK-LE-NEXT:xscvdpsxws 35, 1
+; CHECK-LE-NEXT:addis 3, 2, .LCPI0_0@toc@ha
+; CHECK-LE-NEXT:addi 3, 3, .LCPI0_0@toc@l
+; CHECK-LE-NEXT:lvx 4, 0, 3
+; CHECK-LE-NEXT:vperm 2, 3, 2, 4
+; CHECK-LE-NEXT:blr
+;
+;

[PATCH] D109902: [PowerPC] Improved codegen related to xscvdpsxws/xscvdpuxws

2021-09-16 Thread Albion Fung via Phabricator via cfe-commits

Conanap created this revision.
Conanap added reviewers: PowerPC, nemanjai, saghir.
Conanap added projects: PowerPC, LLVM, clang.
Herald added subscribers: kbarton, hiraditya.
Conanap requested review of this revision.

This patch removes the uneccessary mf/mtvsr generated in conjunction
with xscvdpsxws/xscvdpuxws.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D109902

Files:
  llvm/lib/Target/PowerPC/PPCInstrVSX.td
  llvm/test/CodeGen/PowerPC/build-vector-tests.ll
  llvm/test/CodeGen/PowerPC/test-vector-insert.ll
  llvm/test/CodeGen/PowerPC/vec_conv_fp64_to_i32_elts.ll

Index: llvm/test/CodeGen/PowerPC/vec_conv_fp64_to_i32_elts.ll
===
--- llvm/test/CodeGen/PowerPC/vec_conv_fp64_to_i32_elts.ll
+++ llvm/test/CodeGen/PowerPC/vec_conv_fp64_to_i32_elts.ll
@@ -13,12 +13,8 @@
 ; CHECK-P8-LABEL: test2elt:
 ; CHECK-P8:   # %bb.0: # %entry
 ; CHECK-P8-NEXT:xxswapd vs0, v2
-; CHECK-P8-NEXT:xscvdpuxws f1, v2
-; CHECK-P8-NEXT:xscvdpuxws f0, f0
-; CHECK-P8-NEXT:mffprwz r3, f1
-; CHECK-P8-NEXT:mtvsrwz v2, r3
-; CHECK-P8-NEXT:mffprwz r4, f0
-; CHECK-P8-NEXT:mtvsrwz v3, r4
+; CHECK-P8-NEXT:xscvdpsxws v2, v2
+; CHECK-P8-NEXT:xscvdpsxws v3, f0
 ; CHECK-P8-NEXT:vmrghw v2, v2, v3
 ; CHECK-P8-NEXT:xxswapd vs0, v2
 ; CHECK-P8-NEXT:mffprd r3, f0
@@ -26,26 +22,18 @@
 ;
 ; CHECK-P9-LABEL: test2elt:
 ; CHECK-P9:   # %bb.0: # %entry
-; CHECK-P9-NEXT:xscvdpuxws f0, v2
-; CHECK-P9-NEXT:mffprwz r3, f0
 ; CHECK-P9-NEXT:xxswapd vs0, v2
-; CHECK-P9-NEXT:mtvsrwz v3, r3
-; CHECK-P9-NEXT:xscvdpuxws f0, f0
-; CHECK-P9-NEXT:mffprwz r3, f0
-; CHECK-P9-NEXT:mtvsrwz v2, r3
+; CHECK-P9-NEXT:xscvdpsxws v3, v2
+; CHECK-P9-NEXT:xscvdpsxws v2, f0
 ; CHECK-P9-NEXT:vmrghw v2, v3, v2
 ; CHECK-P9-NEXT:mfvsrld r3, v2
 ; CHECK-P9-NEXT:blr
 ;
 ; CHECK-BE-LABEL: test2elt:
 ; CHECK-BE:   # %bb.0: # %entry
-; CHECK-BE-NEXT:xscvdpuxws f0, v2
-; CHECK-BE-NEXT:mffprwz r3, f0
 ; CHECK-BE-NEXT:xxswapd vs0, v2
-; CHECK-BE-NEXT:mtvsrwz v3, r3
-; CHECK-BE-NEXT:xscvdpuxws f0, f0
-; CHECK-BE-NEXT:mffprwz r3, f0
-; CHECK-BE-NEXT:mtvsrwz v2, r3
+; CHECK-BE-NEXT:xscvdpsxws v3, v2
+; CHECK-BE-NEXT:xscvdpsxws v2, f0
 ; CHECK-BE-NEXT:vmrgow v2, v3, v2
 ; CHECK-BE-NEXT:mfvsrd r3, v2
 ; CHECK-BE-NEXT:blr
@@ -305,12 +293,8 @@
 ; CHECK-P8-LABEL: test2elt_signed:
 ; CHECK-P8:   # %bb.0: # %entry
 ; CHECK-P8-NEXT:xxswapd vs0, v2
-; CHECK-P8-NEXT:xscvdpsxws f1, v2
-; CHECK-P8-NEXT:xscvdpsxws f0, f0
-; CHECK-P8-NEXT:mffprwz r3, f1
-; CHECK-P8-NEXT:mtvsrwz v2, r3
-; CHECK-P8-NEXT:mffprwz r4, f0
-; CHECK-P8-NEXT:mtvsrwz v3, r4
+; CHECK-P8-NEXT:xscvdpsxws v2, v2
+; CHECK-P8-NEXT:xscvdpsxws v3, f0
 ; CHECK-P8-NEXT:vmrghw v2, v2, v3
 ; CHECK-P8-NEXT:xxswapd vs0, v2
 ; CHECK-P8-NEXT:mffprd r3, f0
@@ -318,26 +302,18 @@
 ;
 ; CHECK-P9-LABEL: test2elt_signed:
 ; CHECK-P9:   # %bb.0: # %entry
-; CHECK-P9-NEXT:xscvdpsxws f0, v2
-; CHECK-P9-NEXT:mffprwz r3, f0
 ; CHECK-P9-NEXT:xxswapd vs0, v2
-; CHECK-P9-NEXT:mtvsrwz v3, r3
-; CHECK-P9-NEXT:xscvdpsxws f0, f0
-; CHECK-P9-NEXT:mffprwz r3, f0
-; CHECK-P9-NEXT:mtvsrwz v2, r3
+; CHECK-P9-NEXT:xscvdpsxws v3, v2
+; CHECK-P9-NEXT:xscvdpsxws v2, f0
 ; CHECK-P9-NEXT:vmrghw v2, v3, v2
 ; CHECK-P9-NEXT:mfvsrld r3, v2
 ; CHECK-P9-NEXT:blr
 ;
 ; CHECK-BE-LABEL: test2elt_signed:
 ; CHECK-BE:   # %bb.0: # %entry
-; CHECK-BE-NEXT:xscvdpsxws f0, v2
-; CHECK-BE-NEXT:mffprwz r3, f0
 ; CHECK-BE-NEXT:xxswapd vs0, v2
-; CHECK-BE-NEXT:mtvsrwz v3, r3
-; CHECK-BE-NEXT:xscvdpsxws f0, f0
-; CHECK-BE-NEXT:mffprwz r3, f0
-; CHECK-BE-NEXT:mtvsrwz v2, r3
+; CHECK-BE-NEXT:xscvdpsxws v3, v2
+; CHECK-BE-NEXT:xscvdpsxws v2, f0
 ; CHECK-BE-NEXT:vmrgow v2, v3, v2
 ; CHECK-BE-NEXT:mfvsrd r3, v2
 ; CHECK-BE-NEXT:blr
Index: llvm/test/CodeGen/PowerPC/test-vector-insert.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/test-vector-insert.ll
@@ -0,0 +1,172 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; xscvdpsxws and uxws is only available on Power7 and above
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:  < %s | FileCheck %s --check-prefix=CHECK-LE
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN:  -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-BE
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN:  -mcpu=pwr7 < %s | FileCheck %s
+
+define dso_local <4 x i32> @test(<4 x i32> %a, double %b) {
+; CHECK-LE-LABEL: test:
+; CHECK-LE:   # %bb.0: # %entry
+; CHECK-LE-NEXT:xscvdpsxws 35, 1
+; CHECK-LE-NEXT:addis 3, 2, .LCPI0_0@toc@ha
+; CHECK-LE-NEXT:addi 3, 3, .LCPI0_0@toc@l
+; CHECK-LE-NEXT:

[PATCH] D107138: [PowerPC] Implement cmplxl builtins

2021-08-19 Thread Albion Fung via Phabricator via cfe-commits

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG9d4faa8ac3e7: [PowerPC] Implement cmplxl builtins (authored 
by Conanap).

Changed prior to commit:
  https://reviews.llvm.org/D107138?vs=365596=367695#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D107138/new/

https://reviews.llvm.org/D107138

Files:
  clang/lib/Basic/Targets/PPC.cpp
  clang/test/CodeGen/builtins-ppc-xlcompat-cmplx.c

Index: clang/test/CodeGen/builtins-ppc-xlcompat-cmplx.c
===
--- clang/test/CodeGen/builtins-ppc-xlcompat-cmplx.c
+++ clang/test/CodeGen/builtins-ppc-xlcompat-cmplx.c
@@ -226,3 +226,115 @@
 float _Complex testcmplxf(float real, float imag) {
   return __cmplxf(real, imag);
 }
+
+// 64BIT-LABEL: @test_xl_cmplxl(
+// 64BIT-NEXT:  entry:
+// 64BIT-NEXT:[[RETVAL:%.*]] = alloca { ppc_fp128, ppc_fp128 }, align 16
+// 64BIT-NEXT:[[LDA_ADDR:%.*]] = alloca ppc_fp128, align 16
+// 64BIT-NEXT:[[LDB_ADDR:%.*]] = alloca ppc_fp128, align 16
+// 64BIT-NEXT:store ppc_fp128 [[LDA:%.*]], ppc_fp128* [[LDA_ADDR]], align 16
+// 64BIT-NEXT:store ppc_fp128 [[LDB:%.*]], ppc_fp128* [[LDB_ADDR]], align 16
+// 64BIT-NEXT:[[TMP0:%.*]] = load ppc_fp128, ppc_fp128* [[LDA_ADDR]], align 16
+// 64BIT-NEXT:[[TMP1:%.*]] = load ppc_fp128, ppc_fp128* [[LDB_ADDR]], align 16
+// 64BIT-NEXT:[[RETVAL_REALP:%.*]] = getelementptr inbounds { ppc_fp128, ppc_fp128 }, { ppc_fp128, ppc_fp128 }* [[RETVAL]], i32 0, i32 0
+// 64BIT-NEXT:[[RETVAL_IMAGP:%.*]] = getelementptr inbounds { ppc_fp128, ppc_fp128 }, { ppc_fp128, ppc_fp128 }* [[RETVAL]], i32 0, i32 1
+// 64BIT-NEXT:store ppc_fp128 [[TMP0]], ppc_fp128* [[RETVAL_REALP]], align 16
+// 64BIT-NEXT:store ppc_fp128 [[TMP1]], ppc_fp128* [[RETVAL_IMAGP]], align 16
+// 64BIT-NEXT:[[TMP2:%.*]] = load { ppc_fp128, ppc_fp128 }, { ppc_fp128, ppc_fp128 }* [[RETVAL]], align 16
+// 64BIT-NEXT:ret { ppc_fp128, ppc_fp128 } [[TMP2]]
+//
+// 64BITLE-LABEL: @test_xl_cmplxl(
+// 64BITLE-NEXT:  entry:
+// 64BITLE-NEXT:[[RETVAL:%.*]] = alloca { ppc_fp128, ppc_fp128 }, align 16
+// 64BITLE-NEXT:[[LDA_ADDR:%.*]] = alloca ppc_fp128, align 16
+// 64BITLE-NEXT:[[LDB_ADDR:%.*]] = alloca ppc_fp128, align 16
+// 64BITLE-NEXT:store ppc_fp128 [[LDA:%.*]], ppc_fp128* [[LDA_ADDR]], align 16
+// 64BITLE-NEXT:store ppc_fp128 [[LDB:%.*]], ppc_fp128* [[LDB_ADDR]], align 16
+// 64BITLE-NEXT:[[TMP0:%.*]] = load ppc_fp128, ppc_fp128* [[LDA_ADDR]], align 16
+// 64BITLE-NEXT:[[TMP1:%.*]] = load ppc_fp128, ppc_fp128* [[LDB_ADDR]], align 16
+// 64BITLE-NEXT:[[RETVAL_REALP:%.*]] = getelementptr inbounds { ppc_fp128, ppc_fp128 }, { ppc_fp128, ppc_fp128 }* [[RETVAL]], i32 0, i32 0
+// 64BITLE-NEXT:[[RETVAL_IMAGP:%.*]] = getelementptr inbounds { ppc_fp128, ppc_fp128 }, { ppc_fp128, ppc_fp128 }* [[RETVAL]], i32 0, i32 1
+// 64BITLE-NEXT:store ppc_fp128 [[TMP0]], ppc_fp128* [[RETVAL_REALP]], align 16
+// 64BITLE-NEXT:store ppc_fp128 [[TMP1]], ppc_fp128* [[RETVAL_IMAGP]], align 16
+// 64BITLE-NEXT:[[TMP2:%.*]] = load { ppc_fp128, ppc_fp128 }, { ppc_fp128, ppc_fp128 }* [[RETVAL]], align 16
+// 64BITLE-NEXT:ret { ppc_fp128, ppc_fp128 } [[TMP2]]
+//
+// 64BITAIX-LABEL: @test_xl_cmplxl(
+// 64BITAIX-NEXT:  entry:
+// 64BITAIX-NEXT:[[RETVAL:%.*]] = alloca { double, double }, align 4
+// 64BITAIX-NEXT:[[LDA_ADDR:%.*]] = alloca double, align 8
+// 64BITAIX-NEXT:[[LDB_ADDR:%.*]] = alloca double, align 8
+// 64BITAIX-NEXT:store double [[LDA:%.*]], double* [[LDA_ADDR]], align 8
+// 64BITAIX-NEXT:store double [[LDB:%.*]], double* [[LDB_ADDR]], align 8
+// 64BITAIX-NEXT:[[TMP0:%.*]] = load double, double* [[LDA_ADDR]], align 8
+// 64BITAIX-NEXT:[[TMP1:%.*]] = load double, double* [[LDB_ADDR]], align 8
+// 64BITAIX-NEXT:[[RETVAL_REALP:%.*]] = getelementptr inbounds { double, double }, { double, double }* [[RETVAL]], i32 0, i32 0
+// 64BITAIX-NEXT:[[RETVAL_IMAGP:%.*]] = getelementptr inbounds { double, double }, { double, double }* [[RETVAL]], i32 0, i32 1
+// 64BITAIX-NEXT:store double [[TMP0]], double* [[RETVAL_REALP]], align 4
+// 64BITAIX-NEXT:store double [[TMP1]], double* [[RETVAL_IMAGP]], align 4
+// 64BITAIX-NEXT:[[TMP2:%.*]] = load { double, double }, { double, double }* [[RETVAL]], align 4
+// 64BITAIX-NEXT:ret { double, double } [[TMP2]]
+//
+// 32BIT-LABEL: @test_xl_cmplxl(
+// 32BIT-NEXT:  entry:
+// 32BIT-NEXT:[[LDA_ADDR:%.*]] = alloca ppc_fp128, align 16
+// 32BIT-NEXT:[[LDB_ADDR:%.*]] = alloca ppc_fp128, align 16
+// 32BIT-NEXT:store ppc_fp128 [[LDA:%.*]], ppc_fp128* [[LDA_ADDR]], align 16
+// 32BIT-NEXT:store ppc_fp128 [[LDB:%.*]], ppc_fp128* [[LDB_ADDR]], align 16
+// 32BIT-NEXT:[[TMP0:%.*]] = load ppc_fp128, ppc_fp128* [[LDA_ADDR]], align 16
+// 32BIT-NEXT:[[TMP1:%.*]] = load

[PATCH] D107138: [PowerPC] Implement cmplxl builtins

2021-08-10 Thread Albion Fung via Phabricator via cfe-commits

Conanap updated this revision to Diff 365596.
Conanap added a comment.

Removed unintended change


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D107138/new/

https://reviews.llvm.org/D107138

Files:
  clang/lib/Basic/Targets/PPC.cpp
  clang/test/CodeGen/builtins-ppc-xlcompat-cmplx.c

Index: clang/test/CodeGen/builtins-ppc-xlcompat-cmplx.c
===
--- clang/test/CodeGen/builtins-ppc-xlcompat-cmplx.c
+++ clang/test/CodeGen/builtins-ppc-xlcompat-cmplx.c
@@ -226,3 +226,115 @@
 float _Complex testcmplxf(float real, float imag) {
   return __cmplxf(real, imag);
 }
+
+// 64BIT-LABEL: @test_xl_cmplxl(
+// 64BIT-NEXT:  entry:
+// 64BIT-NEXT:[[RETVAL:%.*]] = alloca { ppc_fp128, ppc_fp128 }, align 16
+// 64BIT-NEXT:[[LDA_ADDR:%.*]] = alloca ppc_fp128, align 16
+// 64BIT-NEXT:[[LDB_ADDR:%.*]] = alloca ppc_fp128, align 16
+// 64BIT-NEXT:store ppc_fp128 [[LDA:%.*]], ppc_fp128* [[LDA_ADDR]], align 16
+// 64BIT-NEXT:store ppc_fp128 [[LDB:%.*]], ppc_fp128* [[LDB_ADDR]], align 16
+// 64BIT-NEXT:[[TMP0:%.*]] = load ppc_fp128, ppc_fp128* [[LDA_ADDR]], align 16
+// 64BIT-NEXT:[[TMP1:%.*]] = load ppc_fp128, ppc_fp128* [[LDB_ADDR]], align 16
+// 64BIT-NEXT:[[RETVAL_REALP:%.*]] = getelementptr inbounds { ppc_fp128, ppc_fp128 }, { ppc_fp128, ppc_fp128 }* [[RETVAL]], i32 0, i32 0
+// 64BIT-NEXT:[[RETVAL_IMAGP:%.*]] = getelementptr inbounds { ppc_fp128, ppc_fp128 }, { ppc_fp128, ppc_fp128 }* [[RETVAL]], i32 0, i32 1
+// 64BIT-NEXT:store ppc_fp128 [[TMP0]], ppc_fp128* [[RETVAL_REALP]], align 16
+// 64BIT-NEXT:store ppc_fp128 [[TMP1]], ppc_fp128* [[RETVAL_IMAGP]], align 16
+// 64BIT-NEXT:[[TMP2:%.*]] = load { ppc_fp128, ppc_fp128 }, { ppc_fp128, ppc_fp128 }* [[RETVAL]], align 16
+// 64BIT-NEXT:ret { ppc_fp128, ppc_fp128 } [[TMP2]]
+//
+// 64BITLE-LABEL: @test_xl_cmplxl(
+// 64BITLE-NEXT:  entry:
+// 64BITLE-NEXT:[[RETVAL:%.*]] = alloca { ppc_fp128, ppc_fp128 }, align 16
+// 64BITLE-NEXT:[[LDA_ADDR:%.*]] = alloca ppc_fp128, align 16
+// 64BITLE-NEXT:[[LDB_ADDR:%.*]] = alloca ppc_fp128, align 16
+// 64BITLE-NEXT:store ppc_fp128 [[LDA:%.*]], ppc_fp128* [[LDA_ADDR]], align 16
+// 64BITLE-NEXT:store ppc_fp128 [[LDB:%.*]], ppc_fp128* [[LDB_ADDR]], align 16
+// 64BITLE-NEXT:[[TMP0:%.*]] = load ppc_fp128, ppc_fp128* [[LDA_ADDR]], align 16
+// 64BITLE-NEXT:[[TMP1:%.*]] = load ppc_fp128, ppc_fp128* [[LDB_ADDR]], align 16
+// 64BITLE-NEXT:[[RETVAL_REALP:%.*]] = getelementptr inbounds { ppc_fp128, ppc_fp128 }, { ppc_fp128, ppc_fp128 }* [[RETVAL]], i32 0, i32 0
+// 64BITLE-NEXT:[[RETVAL_IMAGP:%.*]] = getelementptr inbounds { ppc_fp128, ppc_fp128 }, { ppc_fp128, ppc_fp128 }* [[RETVAL]], i32 0, i32 1
+// 64BITLE-NEXT:store ppc_fp128 [[TMP0]], ppc_fp128* [[RETVAL_REALP]], align 16
+// 64BITLE-NEXT:store ppc_fp128 [[TMP1]], ppc_fp128* [[RETVAL_IMAGP]], align 16
+// 64BITLE-NEXT:[[TMP2:%.*]] = load { ppc_fp128, ppc_fp128 }, { ppc_fp128, ppc_fp128 }* [[RETVAL]], align 16
+// 64BITLE-NEXT:ret { ppc_fp128, ppc_fp128 } [[TMP2]]
+//
+// 64BITAIX-LABEL: @test_xl_cmplxl(
+// 64BITAIX-NEXT:  entry:
+// 64BITAIX-NEXT:[[RETVAL:%.*]] = alloca { double, double }, align 4
+// 64BITAIX-NEXT:[[LDA_ADDR:%.*]] = alloca double, align 8
+// 64BITAIX-NEXT:[[LDB_ADDR:%.*]] = alloca double, align 8
+// 64BITAIX-NEXT:store double [[LDA:%.*]], double* [[LDA_ADDR]], align 8
+// 64BITAIX-NEXT:store double [[LDB:%.*]], double* [[LDB_ADDR]], align 8
+// 64BITAIX-NEXT:[[TMP0:%.*]] = load double, double* [[LDA_ADDR]], align 8
+// 64BITAIX-NEXT:[[TMP1:%.*]] = load double, double* [[LDB_ADDR]], align 8
+// 64BITAIX-NEXT:[[RETVAL_REALP:%.*]] = getelementptr inbounds { double, double }, { double, double }* [[RETVAL]], i32 0, i32 0
+// 64BITAIX-NEXT:[[RETVAL_IMAGP:%.*]] = getelementptr inbounds { double, double }, { double, double }* [[RETVAL]], i32 0, i32 1
+// 64BITAIX-NEXT:store double [[TMP0]], double* [[RETVAL_REALP]], align 4
+// 64BITAIX-NEXT:store double [[TMP1]], double* [[RETVAL_IMAGP]], align 4
+// 64BITAIX-NEXT:[[TMP2:%.*]] = load { double, double }, { double, double }* [[RETVAL]], align 4
+// 64BITAIX-NEXT:ret { double, double } [[TMP2]]
+//
+// 32BIT-LABEL: @test_xl_cmplxl(
+// 32BIT-NEXT:  entry:
+// 32BIT-NEXT:[[LDA_ADDR:%.*]] = alloca ppc_fp128, align 16
+// 32BIT-NEXT:[[LDB_ADDR:%.*]] = alloca ppc_fp128, align 16
+// 32BIT-NEXT:store ppc_fp128 [[LDA:%.*]], ppc_fp128* [[LDA_ADDR]], align 16
+// 32BIT-NEXT:store ppc_fp128 [[LDB:%.*]], ppc_fp128* [[LDB_ADDR]], align 16
+// 32BIT-NEXT:[[TMP0:%.*]] = load ppc_fp128, ppc_fp128* [[LDA_ADDR]], align 16
+// 32BIT-NEXT:[[TMP1:%.*]] = load ppc_fp128, ppc_fp128* [[LDB_ADDR]], align 16
+// 32BIT-NEXT:[[AGG_RESULT_REALP:%.*]] = getelementptr inbounds { ppc_fp128, ppc_fp128 }, { ppc_fp128, ppc_fp128 }* [[AGG_RESULT:%.*]], i32 0, i32 0
+//

[PATCH] D107138: [PowerPC] Implement cmplxl builtins

2021-08-09 Thread Albion Fung via Phabricator via cfe-commits

Conanap updated this revision to Diff 365289.
Conanap marked 3 inline comments as done.
Conanap added a comment.

Merged the test case into the existing cmplx test


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D107138/new/

https://reviews.llvm.org/D107138

Files:
  clang/lib/Basic/Targets/PPC.cpp
  clang/test/CodeGen/builtins-ppc-xlcompat-cmplx.c

Index: clang/test/CodeGen/builtins-ppc-xlcompat-cmplx.c
===
--- clang/test/CodeGen/builtins-ppc-xlcompat-cmplx.c
+++ clang/test/CodeGen/builtins-ppc-xlcompat-cmplx.c
@@ -1,5 +1,5 @@
-// REQUIRES: powerpc-registered-target
 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// REQUIRES: powerpc-registered-target
 // RUN: %clang_cc1 -triple powerpc64-unknown-unknown \
 // RUN:-emit-llvm %s -o -  -target-cpu pwr7 | FileCheck %s --check-prefix=64BIT
 // RUN: %clang_cc1 -triple powerpc64le-unknown-unknown \
@@ -226,3 +226,115 @@
 float _Complex testcmplxf(float real, float imag) {
   return __cmplxf(real, imag);
 }
+
+// 64BIT-LABEL: @test_xl_cmplxl(
+// 64BIT-NEXT:  entry:
+// 64BIT-NEXT:[[RETVAL:%.*]] = alloca { ppc_fp128, ppc_fp128 }, align 16
+// 64BIT-NEXT:[[LDA_ADDR:%.*]] = alloca ppc_fp128, align 16
+// 64BIT-NEXT:[[LDB_ADDR:%.*]] = alloca ppc_fp128, align 16
+// 64BIT-NEXT:store ppc_fp128 [[LDA:%.*]], ppc_fp128* [[LDA_ADDR]], align 16
+// 64BIT-NEXT:store ppc_fp128 [[LDB:%.*]], ppc_fp128* [[LDB_ADDR]], align 16
+// 64BIT-NEXT:[[TMP0:%.*]] = load ppc_fp128, ppc_fp128* [[LDA_ADDR]], align 16
+// 64BIT-NEXT:[[TMP1:%.*]] = load ppc_fp128, ppc_fp128* [[LDB_ADDR]], align 16
+// 64BIT-NEXT:[[RETVAL_REALP:%.*]] = getelementptr inbounds { ppc_fp128, ppc_fp128 }, { ppc_fp128, ppc_fp128 }* [[RETVAL]], i32 0, i32 0
+// 64BIT-NEXT:[[RETVAL_IMAGP:%.*]] = getelementptr inbounds { ppc_fp128, ppc_fp128 }, { ppc_fp128, ppc_fp128 }* [[RETVAL]], i32 0, i32 1
+// 64BIT-NEXT:store ppc_fp128 [[TMP0]], ppc_fp128* [[RETVAL_REALP]], align 16
+// 64BIT-NEXT:store ppc_fp128 [[TMP1]], ppc_fp128* [[RETVAL_IMAGP]], align 16
+// 64BIT-NEXT:[[TMP2:%.*]] = load { ppc_fp128, ppc_fp128 }, { ppc_fp128, ppc_fp128 }* [[RETVAL]], align 16
+// 64BIT-NEXT:ret { ppc_fp128, ppc_fp128 } [[TMP2]]
+//
+// 64BITLE-LABEL: @test_xl_cmplxl(
+// 64BITLE-NEXT:  entry:
+// 64BITLE-NEXT:[[RETVAL:%.*]] = alloca { ppc_fp128, ppc_fp128 }, align 16
+// 64BITLE-NEXT:[[LDA_ADDR:%.*]] = alloca ppc_fp128, align 16
+// 64BITLE-NEXT:[[LDB_ADDR:%.*]] = alloca ppc_fp128, align 16
+// 64BITLE-NEXT:store ppc_fp128 [[LDA:%.*]], ppc_fp128* [[LDA_ADDR]], align 16
+// 64BITLE-NEXT:store ppc_fp128 [[LDB:%.*]], ppc_fp128* [[LDB_ADDR]], align 16
+// 64BITLE-NEXT:[[TMP0:%.*]] = load ppc_fp128, ppc_fp128* [[LDA_ADDR]], align 16
+// 64BITLE-NEXT:[[TMP1:%.*]] = load ppc_fp128, ppc_fp128* [[LDB_ADDR]], align 16
+// 64BITLE-NEXT:[[RETVAL_REALP:%.*]] = getelementptr inbounds { ppc_fp128, ppc_fp128 }, { ppc_fp128, ppc_fp128 }* [[RETVAL]], i32 0, i32 0
+// 64BITLE-NEXT:[[RETVAL_IMAGP:%.*]] = getelementptr inbounds { ppc_fp128, ppc_fp128 }, { ppc_fp128, ppc_fp128 }* [[RETVAL]], i32 0, i32 1
+// 64BITLE-NEXT:store ppc_fp128 [[TMP0]], ppc_fp128* [[RETVAL_REALP]], align 16
+// 64BITLE-NEXT:store ppc_fp128 [[TMP1]], ppc_fp128* [[RETVAL_IMAGP]], align 16
+// 64BITLE-NEXT:[[TMP2:%.*]] = load { ppc_fp128, ppc_fp128 }, { ppc_fp128, ppc_fp128 }* [[RETVAL]], align 16
+// 64BITLE-NEXT:ret { ppc_fp128, ppc_fp128 } [[TMP2]]
+//
+// 64BITAIX-LABEL: @test_xl_cmplxl(
+// 64BITAIX-NEXT:  entry:
+// 64BITAIX-NEXT:[[RETVAL:%.*]] = alloca { double, double }, align 4
+// 64BITAIX-NEXT:[[LDA_ADDR:%.*]] = alloca double, align 8
+// 64BITAIX-NEXT:[[LDB_ADDR:%.*]] = alloca double, align 8
+// 64BITAIX-NEXT:store double [[LDA:%.*]], double* [[LDA_ADDR]], align 8
+// 64BITAIX-NEXT:store double [[LDB:%.*]], double* [[LDB_ADDR]], align 8
+// 64BITAIX-NEXT:[[TMP0:%.*]] = load double, double* [[LDA_ADDR]], align 8
+// 64BITAIX-NEXT:[[TMP1:%.*]] = load double, double* [[LDB_ADDR]], align 8
+// 64BITAIX-NEXT:[[RETVAL_REALP:%.*]] = getelementptr inbounds { double, double }, { double, double }* [[RETVAL]], i32 0, i32 0
+// 64BITAIX-NEXT:[[RETVAL_IMAGP:%.*]] = getelementptr inbounds { double, double }, { double, double }* [[RETVAL]], i32 0, i32 1
+// 64BITAIX-NEXT:store double [[TMP0]], double* [[RETVAL_REALP]], align 4
+// 64BITAIX-NEXT:store double [[TMP1]], double* [[RETVAL_IMAGP]], align 4
+// 64BITAIX-NEXT:[[TMP2:%.*]] = load { double, double }, { double, double }* [[RETVAL]], align 4
+// 64BITAIX-NEXT:ret { double, double } [[TMP2]]
+//
+// 32BIT-LABEL: @test_xl_cmplxl(
+// 32BIT-NEXT:  entry:
+// 32BIT-NEXT:[[LDA_ADDR:%.*]] = alloca ppc_fp128, align 16
+// 32BIT-NEXT:[[LDB_ADDR:%.*]] = alloca ppc_fp128, align 16
+// 32BIT-NEXT:store ppc_fp128 [[LDA:%.*]],

[PATCH] D107138: [PowerPC] Implement cmplxl builtins

2021-08-04 Thread Albion Fung via Phabricator via cfe-commits

Conanap marked an inline comment as done.
Conanap added inline comments.



Comment at: clang/test/CodeGen/builtins-ppc-xlcompat-complex.c:1
+// RUN: %clang_cc1 -O2 -triple powerpc64-unknown-unknown \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s

NeHuang wrote:
> NeHuang wrote:
> > `// REQUIRES: powerpc-registered-target`
> Question: why do we need `-O2` for this builtin?
> 
it's not required, but removes a lot of the extra load and stores that make the 
test cases longer unnecessarily. I can change it to O1 if preferred.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D107138/new/

https://reviews.llvm.org/D107138

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[PATCH] D107138: [PowerPC] Implement cmplxl builtins

2021-08-04 Thread Albion Fung via Phabricator via cfe-commits

Conanap updated this revision to Diff 364223.
Conanap marked 6 inline comments as done.
Conanap added a comment.

Removed backend tests, removed some uneeded definitions,
updated frontend test with regex for variable names.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D107138/new/

https://reviews.llvm.org/D107138

Files:
  clang/lib/Basic/Targets/PPC.cpp
  clang/test/CodeGen/builtins-ppc-xlcompat-complex.c


Index: clang/test/CodeGen/builtins-ppc-xlcompat-complex.c
===
--- /dev/null
+++ clang/test/CodeGen/builtins-ppc-xlcompat-complex.c
@@ -0,0 +1,30 @@
+// REQUIRES: powerpc-registered-target
+// RUN: %clang_cc1 -O2 -triple powerpc64-unknown-unknown \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s
+// RUN: %clang_cc1 -O2 -triple powerpc64le-unknown-unknown \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr8 | FileCheck %s
+// RUN: %clang_cc1 -O2 -triple powerpc-unknown-aix \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr7 | \
+// RUN:   FileCheck %s --check-prefix=CHECK-AIX
+// RUN: %clang_cc1 -O2 -triple powerpc64-unknown-aix \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s \
+// RUN:   --check-prefix=CHECK-AIX
+
+extern long double lda, ldb;
+
+long double _Complex test_xl_cmplxl() {
+  // CHECK-LABEL: test_xl_cmplxl
+  // CHECK: %0 = load ppc_fp128, ppc_fp128* @lda
+  // CHECK-NEXT: %1 = load ppc_fp128, ppc_fp128* @ldb
+  // CHECK-NEXT: [[VAR1:%.*]] = insertvalue { ppc_fp128, ppc_fp128 } undef, 
ppc_fp128 %0, 0
+  // CHECK-NEXT: [[VAR2:%.*]] = insertvalue { ppc_fp128, ppc_fp128 } [[VAR1]], 
ppc_fp128 %1, 1
+  // CHECK-NEXT: ret { ppc_fp128, ppc_fp128 } [[VAR2]]
+
+  // CHECK-AIX-LABEL: test_xl_cmplxl
+  // CHECK-AIX: %0 = load double, double* @lda
+  // CHECK-AIX-NEXT: %1 = load double, double* @ldb
+  // CHECK-AIX-NEXT: [[VAR3:%.*]] = insertvalue { double, double } undef, 
double %0, 0
+  // CHECK-AIX-NEXT: [[VAR4:%.*]] = insertvalue { double, double } [[VAR3]], 
double %1, 1
+  // CHECK-AIX-NEXT: ret { double, double } [[VAR4]]
+  return __cmplxl(lda, ldb);
+}
Index: clang/lib/Basic/Targets/PPC.cpp
===
--- clang/lib/Basic/Targets/PPC.cpp
+++ clang/lib/Basic/Targets/PPC.cpp
@@ -235,6 +235,7 @@
   Builder.defineMacro("__frsqrtes", "__builtin_ppc_frsqrtes");
   Builder.defineMacro("__fsqrt", "__builtin_ppc_fsqrt");
   Builder.defineMacro("__fsqrts", "__builtin_ppc_fsqrts");
+  Builder.defineMacro("__cmplxl", "__builtin_complex");
 }
 
 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific


Index: clang/test/CodeGen/builtins-ppc-xlcompat-complex.c
===
--- /dev/null
+++ clang/test/CodeGen/builtins-ppc-xlcompat-complex.c
@@ -0,0 +1,30 @@
+// REQUIRES: powerpc-registered-target
+// RUN: %clang_cc1 -O2 -triple powerpc64-unknown-unknown \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s
+// RUN: %clang_cc1 -O2 -triple powerpc64le-unknown-unknown \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr8 | FileCheck %s
+// RUN: %clang_cc1 -O2 -triple powerpc-unknown-aix \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr7 | \
+// RUN:   FileCheck %s --check-prefix=CHECK-AIX
+// RUN: %clang_cc1 -O2 -triple powerpc64-unknown-aix \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s \
+// RUN:   --check-prefix=CHECK-AIX
+
+extern long double lda, ldb;
+
+long double _Complex test_xl_cmplxl() {
+  // CHECK-LABEL: test_xl_cmplxl
+  // CHECK: %0 = load ppc_fp128, ppc_fp128* @lda
+  // CHECK-NEXT: %1 = load ppc_fp128, ppc_fp128* @ldb
+  // CHECK-NEXT: [[VAR1:%.*]] = insertvalue { ppc_fp128, ppc_fp128 } undef, ppc_fp128 %0, 0
+  // CHECK-NEXT: [[VAR2:%.*]] = insertvalue { ppc_fp128, ppc_fp128 } [[VAR1]], ppc_fp128 %1, 1
+  // CHECK-NEXT: ret { ppc_fp128, ppc_fp128 } [[VAR2]]
+
+  // CHECK-AIX-LABEL: test_xl_cmplxl
+  // CHECK-AIX: %0 = load double, double* @lda
+  // CHECK-AIX-NEXT: %1 = load double, double* @ldb
+  // CHECK-AIX-NEXT: [[VAR3:%.*]] = insertvalue { double, double } undef, double %0, 0
+  // CHECK-AIX-NEXT: [[VAR4:%.*]] = insertvalue { double, double } [[VAR3]], double %1, 1
+  // CHECK-AIX-NEXT: ret { double, double } [[VAR4]]
+  return __cmplxl(lda, ldb);
+}
Index: clang/lib/Basic/Targets/PPC.cpp
===
--- clang/lib/Basic/Targets/PPC.cpp
+++ clang/lib/Basic/Targets/PPC.cpp
@@ -235,6 +235,7 @@
   Builder.defineMacro("__frsqrtes", "__builtin_ppc_frsqrtes");
   Builder.defineMacro("__fsqrt", "__builtin_ppc_fsqrt");
   Builder.defineMacro("__fsqrts", "__builtin_ppc_fsqrts");
+  Builder.defineMacro("__cmplxl", "__builtin_complex");
 }
 
 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific
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[PATCH] D107138: [PowerPC] Implement cmplxl builtins

2021-07-30 Thread Albion Fung via Phabricator via cfe-commits

Conanap created this revision.
Herald added subscribers: shchenz, kbarton, nemanjai.
Conanap requested review of this revision.
Herald added projects: clang, LLVM.
Herald added subscribers: llvm-commits, cfe-commits.

This patch implements the builtins for cmplxl by utilising
__builtin_complex. This builtin is implemented to match XL
functionality.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D107138

Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/lib/Basic/Targets/PPC.cpp
  clang/test/CodeGen/builtins-ppc-xlcompat-complex.c
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-complex-32bit-only.ll
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-complex.ll

Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-complex.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-complex.ll
@@ -0,0 +1,41 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN:   -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN:   -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-AIX64
+
+@lda = external local_unnamed_addr global ppc_fp128, align 16
+@ldb = external local_unnamed_addr global ppc_fp128, align 16
+
+define { ppc_fp128, ppc_fp128 } @test_long_double_complex() {
+; CHECK-LABEL: test_long_double_complex:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:addis 3, 2, .LC0@toc@ha
+; CHECK-NEXT:addis 4, 2, .LC1@toc@ha
+; CHECK-NEXT:ld 3, .LC0@toc@l(3)
+; CHECK-NEXT:ld 4, .LC1@toc@l(4)
+; CHECK-NEXT:lfd 1, 0(3)
+; CHECK-NEXT:lfd 2, 8(3)
+; CHECK-NEXT:lfd 3, 0(4)
+; CHECK-NEXT:lfd 4, 8(4)
+; CHECK-NEXT:blr
+;
+; CHECK-AIX64-LABEL: test_long_double_complex:
+; CHECK-AIX64:   # %bb.0: # %entry
+; CHECK-AIX64-NEXT:ld 3, L..C0(2) # @lda
+; CHECK-AIX64-NEXT:ld 4, L..C1(2) # @ldb
+; CHECK-AIX64-NEXT:lfd 1, 0(3)
+; CHECK-AIX64-NEXT:lfd 2, 8(3)
+; CHECK-AIX64-NEXT:lfd 3, 0(4)
+; CHECK-AIX64-NEXT:lfd 4, 8(4)
+; CHECK-AIX64-NEXT:blr
+entry:
+  %0 = load ppc_fp128, ppc_fp128* @lda, align 16
+  %1 = load ppc_fp128, ppc_fp128* @ldb, align 16
+  %.fca.0.insert = insertvalue { ppc_fp128, ppc_fp128 } undef, ppc_fp128 %0, 0
+  %.fca.1.insert = insertvalue { ppc_fp128, ppc_fp128 } %.fca.0.insert, ppc_fp128 %1, 1
+  ret { ppc_fp128, ppc_fp128 } %.fca.1.insert
+}
+
Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-complex-32bit-only.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-complex-32bit-only.ll
@@ -0,0 +1,22 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
+; RUN:   -mcpu=pwr8 < %s | FileCheck %s
+
+@lda = external local_unnamed_addr global double, align 16
+@ldb = external local_unnamed_addr global double, align 16
+
+define { double, double } @test_long_double_complex() {
+; CHECK-LABEL: test_long_double_complex:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:lwz 3, L..C0(2) # @lda
+; CHECK-NEXT:lwz 4, L..C1(2) # @ldb
+; CHECK-NEXT:lfd 1, 0(3)
+; CHECK-NEXT:lfd 2, 0(4)
+; CHECK-NEXT:blr
+entry:
+  %0 = load double, double* @lda, align 16
+  %1 = load double, double* @ldb, align 16
+  %.fca.0.insert = insertvalue { double, double } undef, double %0, 0
+  %.fca.1.insert = insertvalue { double, double } %.fca.0.insert, double %1, 1
+  ret { double, double } %.fca.1.insert
+}
Index: clang/test/CodeGen/builtins-ppc-xlcompat-complex.c
===
--- /dev/null
+++ clang/test/CodeGen/builtins-ppc-xlcompat-complex.c
@@ -0,0 +1,46 @@
+// RUN: %clang_cc1 -O2 -triple powerpc64-unknown-unknown \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s
+// RUN: %clang_cc1 -O2 -triple powerpc64le-unknown-unknown \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr8 | FileCheck %s
+// RUN: %clang_cc1 -O2 -triple powerpc-unknown-aix \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr7 | \
+// RUN:   FileCheck %s --check-prefix=CHECK-AIX
+// RUN: %clang_cc1 -O2 -triple powerpc64-unknown-aix \
+// RUN:   -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s \
+// RUN:   --check-prefix=CHECK-AIX
+
+extern long double lda, ldb;
+
+long double _Complex test_cmplxl() {
+  // CHECK-LABEL: test_cmplxl
+  // CHECK: %0 = load ppc_fp128, ppc_fp128* @lda
+  // CHECK-NEXT: %1 = load ppc_fp128, ppc_fp128* @ldb
+  // CHECK-NEXT: %.fca.0.insert = insertvalue { ppc_fp128, ppc_fp128 } undef, ppc_fp128 %0, 0
+  // CHECK-NEXT: %.fca.1.insert = insertvalue { ppc_fp128, ppc_fp128 } %.fca.0.insert, ppc_fp128 %1, 1
+  // CHECK-NEXT: ret { ppc_fp128, ppc_fp128 }

[PATCH] D106817: [PowerPC] Changed sema checking range for tdw td builtin

2021-07-26 Thread Albion Fung via Phabricator via cfe-commits

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG18526b0d661f: [PowerPC] Changed sema checking range for tdw 
td builtin (authored by Conanap).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D106817/new/

https://reviews.llvm.org/D106817

Files:
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/builtins-ppc-xlcompat-error.c


Index: clang/test/CodeGen/builtins-ppc-xlcompat-error.c
===
--- clang/test/CodeGen/builtins-ppc-xlcompat-error.c
+++ clang/test/CodeGen/builtins-ppc-xlcompat-error.c
@@ -17,9 +17,11 @@
 
 void test_trap(void) {
 #ifdef __PPC64__
-  __tdw(lla, llb, 50); //expected-error {{argument value 50 is outside the 
valid range [0, 31]}}
+  __tdw(lla, llb, 50); //expected-error {{argument value 50 is outside the 
valid range [1, 31]}}
+  __tdw(lla, llb, 0); //expected-error {{argument value 0 is outside the valid 
range [1, 31]}}
 #endif
-  __tw(ia, ib, 50); //expected-error {{argument value 50 is outside the valid 
range [0, 31]}}
+  __tw(ia, ib, 50); //expected-error {{argument value 50 is outside the valid 
range [1, 31]}}
+  __tw(ia, ib, 0); //expected-error {{argument value 0 is outside the valid 
range [1, 31]}}
 }
 
 void test_builtin_ppc_rldimi() {
Index: clang/lib/Sema/SemaChecking.cpp
===
--- clang/lib/Sema/SemaChecking.cpp
+++ clang/lib/Sema/SemaChecking.cpp
@@ -3395,7 +3395,7 @@
  return SemaBuiltinConstantArgRange(TheCall, 3, 0, 7);
   case PPC::BI__builtin_ppc_tw:
   case PPC::BI__builtin_ppc_tdw:
-return SemaBuiltinConstantArgRange(TheCall, 2, 0, 31);
+return SemaBuiltinConstantArgRange(TheCall, 2, 1, 31);
   case PPC::BI__builtin_ppc_cmpeqb:
   case PPC::BI__builtin_ppc_setb:
   case PPC::BI__builtin_ppc_maddhd:


Index: clang/test/CodeGen/builtins-ppc-xlcompat-error.c
===
--- clang/test/CodeGen/builtins-ppc-xlcompat-error.c
+++ clang/test/CodeGen/builtins-ppc-xlcompat-error.c
@@ -17,9 +17,11 @@
 
 void test_trap(void) {
 #ifdef __PPC64__
-  __tdw(lla, llb, 50); //expected-error {{argument value 50 is outside the valid range [0, 31]}}
+  __tdw(lla, llb, 50); //expected-error {{argument value 50 is outside the valid range [1, 31]}}
+  __tdw(lla, llb, 0); //expected-error {{argument value 0 is outside the valid range [1, 31]}}
 #endif
-  __tw(ia, ib, 50); //expected-error {{argument value 50 is outside the valid range [0, 31]}}
+  __tw(ia, ib, 50); //expected-error {{argument value 50 is outside the valid range [1, 31]}}
+  __tw(ia, ib, 0); //expected-error {{argument value 0 is outside the valid range [1, 31]}}
 }
 
 void test_builtin_ppc_rldimi() {
Index: clang/lib/Sema/SemaChecking.cpp
===
--- clang/lib/Sema/SemaChecking.cpp
+++ clang/lib/Sema/SemaChecking.cpp
@@ -3395,7 +3395,7 @@
  return SemaBuiltinConstantArgRange(TheCall, 3, 0, 7);
   case PPC::BI__builtin_ppc_tw:
   case PPC::BI__builtin_ppc_tdw:
-return SemaBuiltinConstantArgRange(TheCall, 2, 0, 31);
+return SemaBuiltinConstantArgRange(TheCall, 2, 1, 31);
   case PPC::BI__builtin_ppc_cmpeqb:
   case PPC::BI__builtin_ppc_setb:
   case PPC::BI__builtin_ppc_maddhd:
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[PATCH] D106817: [PowerPC] Changed sema checking range for tdw td builtin

2021-07-26 Thread Albion Fung via Phabricator via cfe-commits

Conanap updated this revision to Diff 361754.
Conanap added a comment.
Herald added a subscriber: kbarton.

Updated test cases


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D106817/new/

https://reviews.llvm.org/D106817

Files:
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/builtins-ppc-xlcompat-error.c


Index: clang/test/CodeGen/builtins-ppc-xlcompat-error.c
===
--- clang/test/CodeGen/builtins-ppc-xlcompat-error.c
+++ clang/test/CodeGen/builtins-ppc-xlcompat-error.c
@@ -17,9 +17,11 @@
 
 void test_trap(void) {
 #ifdef __PPC64__
-  __tdw(lla, llb, 50); //expected-error {{argument value 50 is outside the 
valid range [0, 31]}}
+  __tdw(lla, llb, 50); //expected-error {{argument value 50 is outside the 
valid range [1, 31]}}
+  __tdw(lla, llb, 0); //expected-error {{argument value 0 is outside the valid 
range [1, 31]}}
 #endif
-  __tw(ia, ib, 50); //expected-error {{argument value 50 is outside the valid 
range [0, 31]}}
+  __tw(ia, ib, 50); //expected-error {{argument value 50 is outside the valid 
range [1, 31]}}
+  __tw(ia, ib, 0); //expected-error {{argument value 0 is outside the valid 
range [1, 31]}}
 }
 
 void test_builtin_ppc_rldimi() {
Index: clang/lib/Sema/SemaChecking.cpp
===
--- clang/lib/Sema/SemaChecking.cpp
+++ clang/lib/Sema/SemaChecking.cpp
@@ -3395,7 +3395,7 @@
  return SemaBuiltinConstantArgRange(TheCall, 3, 0, 7);
   case PPC::BI__builtin_ppc_tw:
   case PPC::BI__builtin_ppc_tdw:
-return SemaBuiltinConstantArgRange(TheCall, 2, 0, 31);
+return SemaBuiltinConstantArgRange(TheCall, 2, 1, 31);
   case PPC::BI__builtin_ppc_cmpeqb:
   case PPC::BI__builtin_ppc_setb:
   case PPC::BI__builtin_ppc_maddhd:


Index: clang/test/CodeGen/builtins-ppc-xlcompat-error.c
===
--- clang/test/CodeGen/builtins-ppc-xlcompat-error.c
+++ clang/test/CodeGen/builtins-ppc-xlcompat-error.c
@@ -17,9 +17,11 @@
 
 void test_trap(void) {
 #ifdef __PPC64__
-  __tdw(lla, llb, 50); //expected-error {{argument value 50 is outside the valid range [0, 31]}}
+  __tdw(lla, llb, 50); //expected-error {{argument value 50 is outside the valid range [1, 31]}}
+  __tdw(lla, llb, 0); //expected-error {{argument value 0 is outside the valid range [1, 31]}}
 #endif
-  __tw(ia, ib, 50); //expected-error {{argument value 50 is outside the valid range [0, 31]}}
+  __tw(ia, ib, 50); //expected-error {{argument value 50 is outside the valid range [1, 31]}}
+  __tw(ia, ib, 0); //expected-error {{argument value 0 is outside the valid range [1, 31]}}
 }
 
 void test_builtin_ppc_rldimi() {
Index: clang/lib/Sema/SemaChecking.cpp
===
--- clang/lib/Sema/SemaChecking.cpp
+++ clang/lib/Sema/SemaChecking.cpp
@@ -3395,7 +3395,7 @@
  return SemaBuiltinConstantArgRange(TheCall, 3, 0, 7);
   case PPC::BI__builtin_ppc_tw:
   case PPC::BI__builtin_ppc_tdw:
-return SemaBuiltinConstantArgRange(TheCall, 2, 0, 31);
+return SemaBuiltinConstantArgRange(TheCall, 2, 1, 31);
   case PPC::BI__builtin_ppc_cmpeqb:
   case PPC::BI__builtin_ppc_setb:
   case PPC::BI__builtin_ppc_maddhd:
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[PATCH] D106817: [PowerPC] Changed sema checking range for tdw td builtin

2021-07-26 Thread Albion Fung via Phabricator via cfe-commits

Conanap created this revision.
Herald added subscribers: steven.zhang, shchenz, nemanjai.
Conanap requested review of this revision.
Herald added a project: clang.
Herald added a subscriber: cfe-commits.

To match xlc behaviour and definition in the PowerPC ISA3.1,
it is a better idea to have the compiler produce an error when a
0 is passed to the builtin. This patch changes the accepted range
from 0 to 31 to 1 to 31.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D106817

Files:
  clang/lib/Sema/SemaChecking.cpp


Index: clang/lib/Sema/SemaChecking.cpp
===
--- clang/lib/Sema/SemaChecking.cpp
+++ clang/lib/Sema/SemaChecking.cpp
@@ -3395,7 +3395,7 @@
  return SemaBuiltinConstantArgRange(TheCall, 3, 0, 7);
   case PPC::BI__builtin_ppc_tw:
   case PPC::BI__builtin_ppc_tdw:
-return SemaBuiltinConstantArgRange(TheCall, 2, 0, 31);
+return SemaBuiltinConstantArgRange(TheCall, 2, 1, 31);
   case PPC::BI__builtin_ppc_cmpeqb:
   case PPC::BI__builtin_ppc_setb:
   case PPC::BI__builtin_ppc_maddhd:


Index: clang/lib/Sema/SemaChecking.cpp
===
--- clang/lib/Sema/SemaChecking.cpp
+++ clang/lib/Sema/SemaChecking.cpp
@@ -3395,7 +3395,7 @@
  return SemaBuiltinConstantArgRange(TheCall, 3, 0, 7);
   case PPC::BI__builtin_ppc_tw:
   case PPC::BI__builtin_ppc_tdw:
-return SemaBuiltinConstantArgRange(TheCall, 2, 0, 31);
+return SemaBuiltinConstantArgRange(TheCall, 2, 1, 31);
   case PPC::BI__builtin_ppc_cmpeqb:
   case PPC::BI__builtin_ppc_setb:
   case PPC::BI__builtin_ppc_maddhd:
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[PATCH] D106757: [PowerPC] Implement partial vector ld/st builtins for XL compatibility

2021-07-25 Thread Albion Fung via Phabricator via cfe-commits

Conanap accepted this revision.
Conanap added a comment.
This revision is now accepted and ready to land.

Thanks for answering the Qs. LGTM.


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[PATCH] D106757: [PowerPC] Implement partial vector ld/st builtins for XL compatibility

2021-07-24 Thread Albion Fung via Phabricator via cfe-commits

Conanap added a comment.

do we need an IR -> ASM test case as well?


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[PATCH] D106757: [PowerPC] Implement partial vector ld/st builtins for XL compatibility

2021-07-24 Thread Albion Fung via Phabricator via cfe-commits

Conanap added inline comments.



Comment at: clang/lib/Headers/altivec.h:3151
+#else
+#define __vec_ldrmb __builtin_vsx_ldrmb
+#define __vec_strmb __builtin_vsx_strmb

I believe the preference is to have this defined in 
`clang/lib/Basic/Targets/PPC.cpp` under `defineXLCompatMacros`


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[PATCH] D106484: [PowerPC] Add PowerPC "__stbcx" builtin and intrinsic for XL compatibility

2021-07-22 Thread Albion Fung via Phabricator via cfe-commits

Conanap added inline comments.



Comment at: clang/lib/Sema/SemaChecking.cpp:3437
   case PPC::BI__builtin_ppc_icbt:
+  case PPC::BI__builtin_ppc_stbcx:
 return SemaFeatureCheck(*this, TheCall, "isa-v207-instructions",

would prefer if this joined the list of `sthcx`, `lharx` and `lbarx` right 
below this case


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[PATCH] D105946: [PowerPC] Store, load, move from and to registers related builtins

2021-07-20 Thread Albion Fung via Phabricator via cfe-commits

Conanap added a comment.

issue should be fixed now; pushed with this: 
https://reviews.llvm.org/D106130#change-PZi4uueeCg9i
(I just had to move the test files into the `PowerPC` folder).

Will continue to monitor


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[PATCH] D106130: [PowerPC] Implemented mtmsr, mfspr, mtspr Builtins

2021-07-20 Thread Albion Fung via Phabricator via cfe-commits

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG2fd1520247de: [PowerPC] Implemented mtmsr, mfspr, mtspr 
Builtins (authored by Conanap).

Changed prior to commit:
  https://reviews.llvm.org/D106130?vs=359424=360304#toc

Repository:
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Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/lib/Basic/Targets/PPC.cpp
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/builtins-ppc-xlcompat-error.c
  clang/test/CodeGen/builtins-ppc-xlcompat-move-tofrom-regs.c
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/Target/PowerPC/PPCInstr64Bit.td
  llvm/lib/Target/PowerPC/PPCInstrInfo.td
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-mfspr-mtspr-64bit-only.ll
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-mfspr-mtspr-aix32.ll
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-move-tofrom-regs.ll

Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-move-tofrom-regs.ll
===
--- llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-move-tofrom-regs.ll
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-move-tofrom-regs.ll
@@ -3,13 +3,16 @@
 ; RUN:   -mcpu=pwr8 < %s | FileCheck %s
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
 ; RUN:   -mcpu=pwr7 < %s | FileCheck %s
-; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
-; RUN:   -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-32BIT
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
 ; RUN:   -mcpu=pwr7 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
+; RUN:   -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-32BIT
 
 declare i32 @llvm.ppc.mftbu()
 declare i32 @llvm.ppc.mfmsr()
+declare void @llvm.ppc.mtmsr(i32)
+
+@ula = external local_unnamed_addr global i64, align 8
 
 define dso_local zeroext i32 @test_mftbu() {
 ; CHECK-LABEL: test_mftbu:
@@ -44,3 +47,21 @@
   %conv = zext i32 %0 to i64
   ret i64 %conv
 }
+
+define dso_local void @test_mtmsr() {
+; CHECK-LABEL: test_mtmsr:
+; CHECK:mtmsr 3
+; CHECK-NEXT:blr
+;
+; CHECK-32BIT-LABEL: test_mtmsr:
+; CHECK-32BIT:   # %bb.0: # %entry
+; CHECK-32BIT-NEXT:lwz 3, L..C0(2) # @ula
+; CHECK-32BIT-NEXT:lwz 3, 4(3)
+; CHECK-32BIT-NEXT:mtmsr 3, 0
+; CHECK-32BIT-NEXT:blr
+entry:
+  %0 = load i64, i64* @ula, align 8
+  %conv = trunc i64 %0 to i32
+  call void @llvm.ppc.mtmsr(i32 %conv)
+  ret void
+}
Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-mfspr-mtspr-aix32.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-mfspr-mtspr-aix32.ll
@@ -0,0 +1,123 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
+; RUN:   -mcpu=pwr7 < %s | FileCheck %s
+
+declare i32 @llvm.ppc.mfspr.i32(i32 immarg)
+declare void @llvm.ppc.mtspr.i32(i32 immarg, i32)
+
+@ula = external dso_local global i32, align 4
+
+define dso_local i32 @test_mfxer() {
+; CHECK-LABEL: test_mfxer:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:mfxer 3
+; CHECK-NEXT:blr
+entry:
+  %0 = call i32 @llvm.ppc.mfspr.i32(i32 1)
+  ret i32 %0
+}
+
+define dso_local i32 @test_mflr() {
+; CHECK-LABEL: test_mflr:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:mfspr 3, 8
+; CHECK-NEXT:blr
+entry:
+  %0 = call i32 @llvm.ppc.mfspr.i32(i32 8)
+  ret i32 %0
+}
+
+define dso_local i32 @test_mfctr() {
+; CHECK-LABEL: test_mfctr:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:mfspr 3, 9
+; CHECK-NEXT:blr
+entry:
+  %0 = call i32 @llvm.ppc.mfspr.i32(i32 9)
+  ret i32 %0
+}
+
+define dso_local i32 @test_mfppr() {
+; CHECK-LABEL: test_mfppr:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:mfspr 3, 896
+; CHECK-NEXT:blr
+entry:
+  %0 = call i32 @llvm.ppc.mfspr.i32(i32 896)
+  ret i32 %0
+}
+
+define dso_local i32 @test_mfppr32() {
+; CHECK-LABEL: test_mfppr32:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:mfspr 3, 898
+; CHECK-NEXT:blr
+entry:
+  %0 = call i32 @llvm.ppc.mfspr.i32(i32 898)
+  ret i32 %0
+}
+
+define dso_local void @test_mtxer() {
+; CHECK-LABEL: test_mtxer:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:lwz 3, L..C0(2) # @ula
+; CHECK-NEXT:lwz 3, 0(3)
+; CHECK-NEXT:mtxer 3
+; CHECK-NEXT:blr
+entry:
+  %0 = load i32, i32* @ula, align 8
+  tail call void @llvm.ppc.mtspr.i32(i32 1, i32 %0)
+  ret void
+}
+
+define dso_local void @test_mtlr() {
+; CHECK-LABEL: test_mtlr:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:lwz 3, L..C0(2) # @ula
+; CHECK-NEXT:lwz 3, 0(3)
+; CHECK-NEXT:mtspr 8, 3
+; CHECK-NEXT:blr
+entry:
+  %0 = load i32, i32* @ula, align 8
+  tail call void @llvm.ppc.mtspr.i32(i32 8, i32 %0)
+

[PATCH] D105946: [PowerPC] Store, load, move from and to registers related builtins

2021-07-20 Thread Albion Fung via Phabricator via cfe-commits

Conanap added a comment.

I'm aware of the getting target issue; the fix will be up soon.


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[PATCH] D105946: [PowerPC] Store, load, move from and to registers related builtins

2021-07-20 Thread Albion Fung via Phabricator via cfe-commits

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG3434ac9e3902: [PowerPC] Store, load, move from and to 
registers related builtins (authored by Conanap).

Changed prior to commit:
  https://reviews.llvm.org/D105946?vs=359945=360259#toc

Repository:
  rG LLVM Github Monorepo

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Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/lib/Basic/Targets/PPC.cpp
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond.c
  clang/test/CodeGen/builtins-ppc-xlcompat-move-tofrom-regs.c
  clang/test/CodeGen/builtins-ppc-xlcompat-prefetch.c
  clang/test/CodeGen/builtins-ppc-xlcompat-stfiw.c
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/Target/PowerPC/PPC.td
  llvm/lib/Target/PowerPC/PPCInstrInfo.td
  llvm/lib/Target/PowerPC/PPCInstrVSX.td
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-LoadReserve-StoreCond.ll
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-stfiw.ll
  llvm/test/CodeGen/builtins-ppc-xlcompat-move-tofrom-regs.ll
  llvm/test/CodeGen/builtins-ppc-xlcompat-prefetch.ll

Index: llvm/test/CodeGen/builtins-ppc-xlcompat-prefetch.ll
===
--- /dev/null
+++ llvm/test/CodeGen/builtins-ppc-xlcompat-prefetch.ll
@@ -0,0 +1,71 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN:   -mcpu=pwr7 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
+; RUN:   -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-AIX
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN:   -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-AIX64
+
+declare void @llvm.ppc.dcbtstt(i8*)
+declare void @llvm.ppc.dcbtt(i8*)
+
+@vpa = external local_unnamed_addr global i8*, align 8
+
+define dso_local void @test_dcbtstt() {
+; CHECK-LABEL: test_dcbtstt:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:addis 3, 2, .LC0@toc@ha
+; CHECK-NEXT:ld 3, .LC0@toc@l(3)
+; CHECK-NEXT:ld 3, 0(3)
+; CHECK-NEXT:dcbtstt 0, 3
+; CHECK-NEXT:blr
+;
+; CHECK-AIX-LABEL: test_dcbtstt:
+; CHECK-AIX:   # %bb.0: # %entry
+; CHECK-AIX-NEXT:lwz 3, L..C0(2) # @vpa
+; CHECK-AIX-NEXT:lwz 3, 0(3)
+; CHECK-AIX-NEXT:dcbtstt 0, 3
+; CHECK-AIX-NEXT:blr
+;
+; CHECK-AIX64-LABEL: test_dcbtstt:
+; CHECK-AIX64:   # %bb.0: # %entry
+; CHECK-AIX64-NEXT:ld 3, L..C0(2) # @vpa
+; CHECK-AIX64-NEXT:ld 3, 0(3)
+; CHECK-AIX64-NEXT:dcbtstt 0, 3
+; CHECK-AIX64-NEXT:blr
+entry:
+  %0 = load i8*, i8** @vpa, align 8
+  tail call void @llvm.ppc.dcbtstt(i8* %0)
+  ret void
+}
+
+
+define dso_local void @test_dcbtt() {
+; CHECK-LABEL: test_dcbtt:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:addis 3, 2, .LC0@toc@ha
+; CHECK-NEXT:ld 3, .LC0@toc@l(3)
+; CHECK-NEXT:ld 3, 0(3)
+; CHECK-NEXT:dcbtt 0, 3
+; CHECK-NEXT:blr
+;
+; CHECK-AIX-LABEL: test_dcbtt:
+; CHECK-AIX:   # %bb.0: # %entry
+; CHECK-AIX-NEXT:lwz 3, L..C0(2) # @vpa
+; CHECK-AIX-NEXT:lwz 3, 0(3)
+; CHECK-AIX-NEXT:dcbtt 0, 3
+; CHECK-AIX-NEXT:blr
+;
+; CHECK-AIX64-LABEL: test_dcbtt:
+; CHECK-AIX64:   # %bb.0: # %entry
+; CHECK-AIX64-NEXT:ld 3, L..C0(2) # @vpa
+; CHECK-AIX64-NEXT:ld 3, 0(3)
+; CHECK-AIX64-NEXT:dcbtt 0, 3
+; CHECK-AIX64-NEXT:blr
+entry:
+  %0 = load i8*, i8** @vpa, align 8
+  tail call void @llvm.ppc.dcbtt(i8* %0)
+  ret void
+}
Index: llvm/test/CodeGen/builtins-ppc-xlcompat-move-tofrom-regs.ll
===
--- /dev/null
+++ llvm/test/CodeGen/builtins-ppc-xlcompat-move-tofrom-regs.ll
@@ -0,0 +1,46 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN:   -mcpu=pwr7 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
+; RUN:   -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-32BIT
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN:   -mcpu=pwr7 < %s | FileCheck %s
+
+declare i32 @llvm.ppc.mftbu()
+declare i32 @llvm.ppc.mfmsr()
+
+define dso_local zeroext i32 @test_mftbu() {
+; CHECK-LABEL: test_mftbu:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:mftbu 3
+; CHECK-NEXT:clrldi 3, 3, 32
+; CHECK-NEXT:blr
+;
+; CHECK-32BIT-LABEL: test_mftbu:
+; CHECK-32BIT:   # %bb.0: # %entry
+; CHECK-32BIT-NEXT:mftbu 3
+; CHECK-32BIT-NEXT:blr
+entry:
+  %0 =

[PATCH] D105926: [PowerPC] Extra test case for LDARX

2021-07-20 Thread Albion Fung via Phabricator via cfe-commits

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG2a7711f33a04: [PowerPC] Extra test case for LDARX (authored 
by Conanap).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D105926/new/

https://reviews.llvm.org/D105926

Files:
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-check-ldarx-opt.ll


Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-check-ldarx-opt.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-check-ldarx-opt.ll
@@ -0,0 +1,88 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN:   -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN:   -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-AIX
+
+; Function Attrs: nounwind uwtable
+define dso_local signext i32 @main() local_unnamed_addr {
+; CHECK-LABEL: main:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:li 3, -1
+; CHECK-NEXT:li 4, 0
+; CHECK-NEXT:std 3, -8(1)
+; CHECK-NEXT:addi 3, 1, -8
+; CHECK-NEXT:.p2align 5
+; CHECK-NEXT:  .LBB0_1: # %do.body
+; CHECK-NEXT:#
+; CHECK-NEXT:#APP
+; CHECK-NEXT:ldarx 5, 0, 3
+; CHECK-NEXT:#NO_APP
+; CHECK-NEXT:stdcx. 4, 0, 3
+; CHECK-NEXT:mfocrf 5, 128
+; CHECK-NEXT:srwi 5, 5, 28
+; CHECK-NEXT:cmplwi 5, 0
+; CHECK-NEXT:beq 0, .LBB0_1
+; CHECK-NEXT:  # %bb.2: # %do.end
+; CHECK-NEXT:ld 3, -8(1)
+; CHECK-NEXT:li 4, 55
+; CHECK-NEXT:cmpldi 3, 0
+; CHECK-NEXT:li 3, 66
+; CHECK-NEXT:iseleq 3, 4, 3
+; CHECK-NEXT:blr
+;
+; CHECK-AIX-LABEL: main:
+; CHECK-AIX:   # %bb.0: # %entry
+; CHECK-AIX-NEXT:li 3, -1
+; CHECK-AIX-NEXT:li 4, 0
+; CHECK-AIX-NEXT:std 3, -8(1)
+; CHECK-AIX-NEXT:addi 3, 1, -8
+; CHECK-AIX-NEXT:.align 5
+; CHECK-AIX-NEXT:  L..BB0_1: # %do.body
+; CHECK-AIX-NEXT:#
+; CHECK-AIX-NEXT:#APP
+; CHECK-AIX-NEXT:ldarx 5, 0, 3
+; CHECK-AIX-NEXT:#NO_APP
+; CHECK-AIX-NEXT:stdcx. 4, 0, 3
+; CHECK-AIX-NEXT:mfocrf 5, 128
+; CHECK-AIX-NEXT:srwi 5, 5, 28
+; CHECK-AIX-NEXT:cmplwi 5, 0
+; CHECK-AIX-NEXT:beq 0, L..BB0_1
+; CHECK-AIX-NEXT:  # %bb.2: # %do.end
+; CHECK-AIX-NEXT:ld 3, -8(1)
+; CHECK-AIX-NEXT:li 4, 55
+; CHECK-AIX-NEXT:cmpldi 3, 0
+; CHECK-AIX-NEXT:li 3, 66
+; CHECK-AIX-NEXT:iseleq 3, 4, 3
+; CHECK-AIX-NEXT:blr
+entry:
+  %x64 = alloca i64, align 8
+  %0 = bitcast i64* %x64 to i8*
+  call void @llvm.lifetime.start.p0i8(i64 8, i8* nonnull %0)
+  store i64 -1, i64* %x64, align 8
+  br label %do.body
+
+do.body:  ; preds = %do.body, %entry
+  %1 = call i64 asm sideeffect "ldarx $0, ${1:y}", "=r,*Z,~{memory}"(i64* 
nonnull %x64)
+  %2 = call i32 @llvm.ppc.stdcx(i8* nonnull %0, i64 0)
+  %tobool.not = icmp eq i32 %2, 0
+  br i1 %tobool.not, label %do.body, label %do.end
+
+do.end:   ; preds = %do.body
+  %3 = load i64, i64* %x64, align 8
+  %cmp = icmp eq i64 %3, 0
+  %. = select i1 %cmp, i32 55, i32 66
+  call void @llvm.lifetime.end.p0i8(i64 8, i8* nonnull %0)
+  ret i32 %.
+}
+
+; Function Attrs: argmemonly mustprogress nofree nosync nounwind willreturn
+declare void @llvm.lifetime.start.p0i8(i64 immarg, i8* nocapture)
+
+; Function Attrs: nounwind writeonly
+declare i32 @llvm.ppc.stdcx(i8*, i64)
+
+; Function Attrs: argmemonly mustprogress nofree nosync nounwind willreturn
+declare void @llvm.lifetime.end.p0i8(i64 immarg, i8* nocapture)


Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-check-ldarx-opt.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-check-ldarx-opt.ll
@@ -0,0 +1,88 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN:   -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN:   -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-AIX
+
+; Function Attrs: nounwind uwtable
+define dso_local signext i32 @main() local_unnamed_addr {
+; CHECK-LABEL: main:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:li 3, -1
+; CHECK-NEXT:li 4, 0
+; CHECK-NEXT:std 3, -8(1)
+; CHECK-NEXT:addi 3, 1, -8
+; CHECK-NEXT:.p2align 5
+; CHECK-NEXT:  .LBB0_1: # %do.body
+; CHECK-NEXT:#
+; CHECK-NEXT:

[PATCH] D105926: [PowerPC] Extra test case for LDARX

2021-07-20 Thread Albion Fung via Phabricator via cfe-commits

Conanap updated this revision to Diff 360114.
Conanap added a comment.
Herald added a project: LLVM.
Herald added a subscriber: llvm-commits.

Moved to llvm/test/CodeGen/PowerPC


Repository:
  rG LLVM Github Monorepo

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Files:
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-check-ldarx-opt.ll


Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-check-ldarx-opt.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-check-ldarx-opt.ll
@@ -0,0 +1,88 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN:   -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN:   -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-AIX
+
+; Function Attrs: nounwind uwtable
+define dso_local signext i32 @main() local_unnamed_addr {
+; CHECK-LABEL: main:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:li 3, -1
+; CHECK-NEXT:li 4, 0
+; CHECK-NEXT:std 3, -8(1)
+; CHECK-NEXT:addi 3, 1, -8
+; CHECK-NEXT:.p2align 5
+; CHECK-NEXT:  .LBB0_1: # %do.body
+; CHECK-NEXT:#
+; CHECK-NEXT:#APP
+; CHECK-NEXT:ldarx 5, 0, 3
+; CHECK-NEXT:#NO_APP
+; CHECK-NEXT:stdcx. 4, 0, 3
+; CHECK-NEXT:mfocrf 5, 128
+; CHECK-NEXT:srwi 5, 5, 28
+; CHECK-NEXT:cmplwi 5, 0
+; CHECK-NEXT:beq 0, .LBB0_1
+; CHECK-NEXT:  # %bb.2: # %do.end
+; CHECK-NEXT:ld 3, -8(1)
+; CHECK-NEXT:li 4, 55
+; CHECK-NEXT:cmpldi 3, 0
+; CHECK-NEXT:li 3, 66
+; CHECK-NEXT:iseleq 3, 4, 3
+; CHECK-NEXT:blr
+;
+; CHECK-AIX-LABEL: main:
+; CHECK-AIX:   # %bb.0: # %entry
+; CHECK-AIX-NEXT:li 3, -1
+; CHECK-AIX-NEXT:li 4, 0
+; CHECK-AIX-NEXT:std 3, -8(1)
+; CHECK-AIX-NEXT:addi 3, 1, -8
+; CHECK-AIX-NEXT:.align 5
+; CHECK-AIX-NEXT:  L..BB0_1: # %do.body
+; CHECK-AIX-NEXT:#
+; CHECK-AIX-NEXT:#APP
+; CHECK-AIX-NEXT:ldarx 5, 0, 3
+; CHECK-AIX-NEXT:#NO_APP
+; CHECK-AIX-NEXT:stdcx. 4, 0, 3
+; CHECK-AIX-NEXT:mfocrf 5, 128
+; CHECK-AIX-NEXT:srwi 5, 5, 28
+; CHECK-AIX-NEXT:cmplwi 5, 0
+; CHECK-AIX-NEXT:beq 0, L..BB0_1
+; CHECK-AIX-NEXT:  # %bb.2: # %do.end
+; CHECK-AIX-NEXT:ld 3, -8(1)
+; CHECK-AIX-NEXT:li 4, 55
+; CHECK-AIX-NEXT:cmpldi 3, 0
+; CHECK-AIX-NEXT:li 3, 66
+; CHECK-AIX-NEXT:iseleq 3, 4, 3
+; CHECK-AIX-NEXT:blr
+entry:
+  %x64 = alloca i64, align 8
+  %0 = bitcast i64* %x64 to i8*
+  call void @llvm.lifetime.start.p0i8(i64 8, i8* nonnull %0)
+  store i64 -1, i64* %x64, align 8
+  br label %do.body
+
+do.body:  ; preds = %do.body, %entry
+  %1 = call i64 asm sideeffect "ldarx $0, ${1:y}", "=r,*Z,~{memory}"(i64* 
nonnull %x64)
+  %2 = call i32 @llvm.ppc.stdcx(i8* nonnull %0, i64 0)
+  %tobool.not = icmp eq i32 %2, 0
+  br i1 %tobool.not, label %do.body, label %do.end
+
+do.end:   ; preds = %do.body
+  %3 = load i64, i64* %x64, align 8
+  %cmp = icmp eq i64 %3, 0
+  %. = select i1 %cmp, i32 55, i32 66
+  call void @llvm.lifetime.end.p0i8(i64 8, i8* nonnull %0)
+  ret i32 %.
+}
+
+; Function Attrs: argmemonly mustprogress nofree nosync nounwind willreturn
+declare void @llvm.lifetime.start.p0i8(i64 immarg, i8* nocapture)
+
+; Function Attrs: nounwind writeonly
+declare i32 @llvm.ppc.stdcx(i8*, i64)
+
+; Function Attrs: argmemonly mustprogress nofree nosync nounwind willreturn
+declare void @llvm.lifetime.end.p0i8(i64 immarg, i8* nocapture)


Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-check-ldarx-opt.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-check-ldarx-opt.ll
@@ -0,0 +1,88 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN:   -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN:   -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-AIX
+
+; Function Attrs: nounwind uwtable
+define dso_local signext i32 @main() local_unnamed_addr {
+; CHECK-LABEL: main:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:li 3, -1
+; CHECK-NEXT:li 4, 0
+; CHECK-NEXT:std 3, -8(1)
+; CHECK-NEXT:addi 3, 1, -8
+; CHECK-NEXT:.p2align 5
+; CHECK-NEXT:  .LBB0_1: # %do.body
+; CHECK-NEXT:#
+; CHECK-NEXT:#APP
+; CHECK-NEXT:ldarx 5, 0, 3
+;

[PATCH] D105926: [PowerPC] Extra test case for LDARX

2021-07-19 Thread Albion Fung via Phabricator via cfe-commits

Conanap reopened this revision.
Conanap added a comment.
This revision is now accepted and ready to land.

Had to revert this as I'm seeing failures on buildbots not owned by us. The 
error is:

  llc: error: : error: unable to get target for 
'powerpc64le-unknown-linux-gnu', see --version and --triple.

Note that when testing on local machines I did not encounter this error, 
neither did PowerPC buildbots, so I'll need to look into it.


Repository:
  rG LLVM Github Monorepo

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[PATCH] D105926: [PowerPC] Extra test case for LDARX

2021-07-19 Thread Albion Fung via Phabricator via cfe-commits

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG1d3e77e7a842: [PowerPC] Extra test case for LDARX (authored 
by Conanap).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D105926/new/

https://reviews.llvm.org/D105926

Files:
  clang/test/CodeGen/builtins-ppc-xlcompat-check-ldarx-opt.ll


Index: clang/test/CodeGen/builtins-ppc-xlcompat-check-ldarx-opt.ll
===
--- /dev/null
+++ clang/test/CodeGen/builtins-ppc-xlcompat-check-ldarx-opt.ll
@@ -0,0 +1,88 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN:   -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN:   -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-AIX
+
+; Function Attrs: nounwind uwtable
+define dso_local signext i32 @main() local_unnamed_addr {
+; CHECK-LABEL: main:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:li 3, -1
+; CHECK-NEXT:li 4, 0
+; CHECK-NEXT:std 3, -8(1)
+; CHECK-NEXT:addi 3, 1, -8
+; CHECK-NEXT:.p2align 5
+; CHECK-NEXT:  .LBB0_1: # %do.body
+; CHECK-NEXT:#
+; CHECK-NEXT:#APP
+; CHECK-NEXT:ldarx 5, 0, 3
+; CHECK-NEXT:#NO_APP
+; CHECK-NEXT:stdcx. 4, 0, 3
+; CHECK-NEXT:mfocrf 5, 128
+; CHECK-NEXT:srwi 5, 5, 28
+; CHECK-NEXT:cmplwi 5, 0
+; CHECK-NEXT:beq 0, .LBB0_1
+; CHECK-NEXT:  # %bb.2: # %do.end
+; CHECK-NEXT:ld 3, -8(1)
+; CHECK-NEXT:li 4, 55
+; CHECK-NEXT:cmpldi 3, 0
+; CHECK-NEXT:li 3, 66
+; CHECK-NEXT:iseleq 3, 4, 3
+; CHECK-NEXT:blr
+;
+; CHECK-AIX-LABEL: main:
+; CHECK-AIX:   # %bb.0: # %entry
+; CHECK-AIX-NEXT:li 3, -1
+; CHECK-AIX-NEXT:li 4, 0
+; CHECK-AIX-NEXT:std 3, -8(1)
+; CHECK-AIX-NEXT:addi 3, 1, -8
+; CHECK-AIX-NEXT:.align 5
+; CHECK-AIX-NEXT:  L..BB0_1: # %do.body
+; CHECK-AIX-NEXT:#
+; CHECK-AIX-NEXT:#APP
+; CHECK-AIX-NEXT:ldarx 5, 0, 3
+; CHECK-AIX-NEXT:#NO_APP
+; CHECK-AIX-NEXT:stdcx. 4, 0, 3
+; CHECK-AIX-NEXT:mfocrf 5, 128
+; CHECK-AIX-NEXT:srwi 5, 5, 28
+; CHECK-AIX-NEXT:cmplwi 5, 0
+; CHECK-AIX-NEXT:beq 0, L..BB0_1
+; CHECK-AIX-NEXT:  # %bb.2: # %do.end
+; CHECK-AIX-NEXT:ld 3, -8(1)
+; CHECK-AIX-NEXT:li 4, 55
+; CHECK-AIX-NEXT:cmpldi 3, 0
+; CHECK-AIX-NEXT:li 3, 66
+; CHECK-AIX-NEXT:iseleq 3, 4, 3
+; CHECK-AIX-NEXT:blr
+entry:
+  %x64 = alloca i64, align 8
+  %0 = bitcast i64* %x64 to i8*
+  call void @llvm.lifetime.start.p0i8(i64 8, i8* nonnull %0)
+  store i64 -1, i64* %x64, align 8
+  br label %do.body
+
+do.body:  ; preds = %do.body, %entry
+  %1 = call i64 asm sideeffect "ldarx $0, ${1:y}", "=r,*Z,~{memory}"(i64* 
nonnull %x64)
+  %2 = call i32 @llvm.ppc.stdcx(i8* nonnull %0, i64 0)
+  %tobool.not = icmp eq i32 %2, 0
+  br i1 %tobool.not, label %do.body, label %do.end
+
+do.end:   ; preds = %do.body
+  %3 = load i64, i64* %x64, align 8
+  %cmp = icmp eq i64 %3, 0
+  %. = select i1 %cmp, i32 55, i32 66
+  call void @llvm.lifetime.end.p0i8(i64 8, i8* nonnull %0)
+  ret i32 %.
+}
+
+; Function Attrs: argmemonly mustprogress nofree nosync nounwind willreturn
+declare void @llvm.lifetime.start.p0i8(i64 immarg, i8* nocapture)
+
+; Function Attrs: nounwind writeonly
+declare i32 @llvm.ppc.stdcx(i8*, i64)
+
+; Function Attrs: argmemonly mustprogress nofree nosync nounwind willreturn
+declare void @llvm.lifetime.end.p0i8(i64 immarg, i8* nocapture)


Index: clang/test/CodeGen/builtins-ppc-xlcompat-check-ldarx-opt.ll
===
--- /dev/null
+++ clang/test/CodeGen/builtins-ppc-xlcompat-check-ldarx-opt.ll
@@ -0,0 +1,88 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN:   -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN:   -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-AIX
+
+; Function Attrs: nounwind uwtable
+define dso_local signext i32 @main() local_unnamed_addr {
+; CHECK-LABEL: main:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:li 3, -1
+; CHECK-NEXT:li 4, 0
+; CHECK-NEXT:std 3, -8(1)
+; CHECK-NEXT:addi 3, 1, -8
+; CHECK-NEXT:.p2align 5
+; CHECK-NEXT:  .LBB0_1: # %do.body
+; CHECK-NEXT:#
+; CHECK-NEXT:#APP
+; CHECK-NEXT:ldarx 5, 0, 3

[PATCH] D105946: [PowerPC] Store, load, move from and to registers related builtins

2021-07-19 Thread Albion Fung via Phabricator via cfe-commits

Conanap updated this revision to Diff 359945.
Conanap added a comment.

Fixed a typo


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D105946/new/

https://reviews.llvm.org/D105946

Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/lib/Basic/Targets/PPC.cpp
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond.c
  clang/test/CodeGen/builtins-ppc-xlcompat-move-tofrom-regs.c
  clang/test/CodeGen/builtins-ppc-xlcompat-prefetch.c
  clang/test/CodeGen/builtins-ppc-xlcompat-stfiw.c
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/Target/PowerPC/PPC.td
  llvm/lib/Target/PowerPC/PPCInstrInfo.td
  llvm/lib/Target/PowerPC/PPCInstrVSX.td
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-LoadReserve-StoreCond.ll
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-stfiw.ll
  llvm/test/CodeGen/builtins-ppc-xlcompat-move-tofrom-regs.ll
  llvm/test/CodeGen/builtins-ppc-xlcompat-prefetch.ll

Index: llvm/test/CodeGen/builtins-ppc-xlcompat-prefetch.ll
===
--- /dev/null
+++ llvm/test/CodeGen/builtins-ppc-xlcompat-prefetch.ll
@@ -0,0 +1,71 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN:   -mcpu=pwr7 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
+; RUN:   -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-AIX
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN:   -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-AIX64
+
+declare void @llvm.ppc.dcbtstt(i8*)
+declare void @llvm.ppc.dcbtt(i8*)
+
+@vpa = external local_unnamed_addr global i8*, align 8
+
+define dso_local void @test_dcbtstt() {
+; CHECK-LABEL: test_dcbtstt:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:addis 3, 2, .LC0@toc@ha
+; CHECK-NEXT:ld 3, .LC0@toc@l(3)
+; CHECK-NEXT:ld 3, 0(3)
+; CHECK-NEXT:dcbtstt 0, 3
+; CHECK-NEXT:blr
+;
+; CHECK-AIX-LABEL: test_dcbtstt:
+; CHECK-AIX:   # %bb.0: # %entry
+; CHECK-AIX-NEXT:lwz 3, L..C0(2) # @vpa
+; CHECK-AIX-NEXT:lwz 3, 0(3)
+; CHECK-AIX-NEXT:dcbtstt 0, 3
+; CHECK-AIX-NEXT:blr
+;
+; CHECK-AIX64-LABEL: test_dcbtstt:
+; CHECK-AIX64:   # %bb.0: # %entry
+; CHECK-AIX64-NEXT:ld 3, L..C0(2) # @vpa
+; CHECK-AIX64-NEXT:ld 3, 0(3)
+; CHECK-AIX64-NEXT:dcbtstt 0, 3
+; CHECK-AIX64-NEXT:blr
+entry:
+  %0 = load i8*, i8** @vpa, align 8
+  tail call void @llvm.ppc.dcbtstt(i8* %0)
+  ret void
+}
+
+
+define dso_local void @test_dcbtt() {
+; CHECK-LABEL: test_dcbtt:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:addis 3, 2, .LC0@toc@ha
+; CHECK-NEXT:ld 3, .LC0@toc@l(3)
+; CHECK-NEXT:ld 3, 0(3)
+; CHECK-NEXT:dcbtt 0, 3
+; CHECK-NEXT:blr
+;
+; CHECK-AIX-LABEL: test_dcbtt:
+; CHECK-AIX:   # %bb.0: # %entry
+; CHECK-AIX-NEXT:lwz 3, L..C0(2) # @vpa
+; CHECK-AIX-NEXT:lwz 3, 0(3)
+; CHECK-AIX-NEXT:dcbtt 0, 3
+; CHECK-AIX-NEXT:blr
+;
+; CHECK-AIX64-LABEL: test_dcbtt:
+; CHECK-AIX64:   # %bb.0: # %entry
+; CHECK-AIX64-NEXT:ld 3, L..C0(2) # @vpa
+; CHECK-AIX64-NEXT:ld 3, 0(3)
+; CHECK-AIX64-NEXT:dcbtt 0, 3
+; CHECK-AIX64-NEXT:blr
+entry:
+  %0 = load i8*, i8** @vpa, align 8
+  tail call void @llvm.ppc.dcbtt(i8* %0)
+  ret void
+}
Index: llvm/test/CodeGen/builtins-ppc-xlcompat-move-tofrom-regs.ll
===
--- /dev/null
+++ llvm/test/CodeGen/builtins-ppc-xlcompat-move-tofrom-regs.ll
@@ -0,0 +1,46 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN:   -mcpu=pwr7 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
+; RUN:   -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-32BIT
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN:   -mcpu=pwr7 < %s | FileCheck %s
+
+declare i32 @llvm.ppc.mftbu()
+declare i32 @llvm.ppc.mfmsr()
+
+define dso_local zeroext i32 @test_mftbu() {
+; CHECK-LABEL: test_mftbu:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:mftbu 3
+; CHECK-NEXT:clrldi 3, 3, 32
+; CHECK-NEXT:blr
+;
+; CHECK-32BIT-LABEL: test_mftbu:
+; CHECK-32BIT:   # %bb.0: # %entry
+; CHECK-32BIT-NEXT:mftbu 3
+; CHECK-32BIT-NEXT:blr
+entry:
+  %0 = tail call i32 @llvm.ppc.mftbu()
+  ret i32 %0
+}
+
+define dso_local i64 @test_mfmsr() {
+; CHECK-LABEL: test_mfmsr:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:mfmsr 3
+; CHECK-NEXT:clrldi 3, 3, 32
+; CHECK-NEXT:blr
+;
+;

[PATCH] D105946: [PowerPC] Store, load, move from and to registers related builtins

2021-07-19 Thread Albion Fung via Phabricator via cfe-commits

Conanap updated this revision to Diff 359850.
Conanap added a comment.

Changed flags for intrinsic of dcbtt and dcbtstt


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D105946/new/

https://reviews.llvm.org/D105946

Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/lib/Basic/Targets/PPC.cpp
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond.c
  clang/test/CodeGen/builtins-ppc-xlcompat-move-tofrom-regs.c
  clang/test/CodeGen/builtins-ppc-xlcompat-prefetch.c
  clang/test/CodeGen/builtins-ppc-xlcompat-stfiw.c
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/Target/PowerPC/PPC.td
  llvm/lib/Target/PowerPC/PPCInstrInfo.td
  llvm/lib/Target/PowerPC/PPCInstrVSX.td
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-LoadReserve-StoreCond.ll
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-stfiw.ll
  llvm/test/CodeGen/builtins-ppc-xlcompat-move-tofrom-regs.ll
  llvm/test/CodeGen/builtins-ppc-xlcompat-prefetch.ll

Index: llvm/test/CodeGen/builtins-ppc-xlcompat-prefetch.ll
===
--- /dev/null
+++ llvm/test/CodeGen/builtins-ppc-xlcompat-prefetch.ll
@@ -0,0 +1,71 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN:   -mcpu=pwr7 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
+; RUN:   -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-AIX
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN:   -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-AIX64
+
+declare void @llvm.ppc.dcbtstt(i8*)
+declare void @llvm.ppc.dcbtt(i8*)
+
+@vpa = external local_unnamed_addr global i8*, align 8
+
+define dso_local void @test_dcbtstt() {
+; CHECK-LABEL: test_dcbtstt:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:addis 3, 2, .LC0@toc@ha
+; CHECK-NEXT:ld 3, .LC0@toc@l(3)
+; CHECK-NEXT:ld 3, 0(3)
+; CHECK-NEXT:dcbtstt 0, 3
+; CHECK-NEXT:blr
+;
+; CHECK-AIX-LABEL: test_dcbtstt:
+; CHECK-AIX:   # %bb.0: # %entry
+; CHECK-AIX-NEXT:lwz 3, L..C0(2) # @vpa
+; CHECK-AIX-NEXT:lwz 3, 0(3)
+; CHECK-AIX-NEXT:dcbtstt 0, 3
+; CHECK-AIX-NEXT:blr
+;
+; CHECK-AIX64-LABEL: test_dcbtstt:
+; CHECK-AIX64:   # %bb.0: # %entry
+; CHECK-AIX64-NEXT:ld 3, L..C0(2) # @vpa
+; CHECK-AIX64-NEXT:ld 3, 0(3)
+; CHECK-AIX64-NEXT:dcbtstt 0, 3
+; CHECK-AIX64-NEXT:blr
+entry:
+  %0 = load i8*, i8** @vpa, align 8
+  tail call void @llvm.ppc.dcbtstt(i8* %0)
+  ret void
+}
+
+
+define dso_local void @test_dcbtt() {
+; CHECK-LABEL: test_dcbtt:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:addis 3, 2, .LC0@toc@ha
+; CHECK-NEXT:ld 3, .LC0@toc@l(3)
+; CHECK-NEXT:ld 3, 0(3)
+; CHECK-NEXT:dcbtt 0, 3
+; CHECK-NEXT:blr
+;
+; CHECK-AIX-LABEL: test_dcbtt:
+; CHECK-AIX:   # %bb.0: # %entry
+; CHECK-AIX-NEXT:lwz 3, L..C0(2) # @vpa
+; CHECK-AIX-NEXT:lwz 3, 0(3)
+; CHECK-AIX-NEXT:dcbtt 0, 3
+; CHECK-AIX-NEXT:blr
+;
+; CHECK-AIX64-LABEL: test_dcbtt:
+; CHECK-AIX64:   # %bb.0: # %entry
+; CHECK-AIX64-NEXT:ld 3, L..C0(2) # @vpa
+; CHECK-AIX64-NEXT:ld 3, 0(3)
+; CHECK-AIX64-NEXT:dcbtt 0, 3
+; CHECK-AIX64-NEXT:blr
+entry:
+  %0 = load i8*, i8** @vpa, align 8
+  tail call void @llvm.ppc.dcbtt(i8* %0)
+  ret void
+}
Index: llvm/test/CodeGen/builtins-ppc-xlcompat-move-tofrom-regs.ll
===
--- /dev/null
+++ llvm/test/CodeGen/builtins-ppc-xlcompat-move-tofrom-regs.ll
@@ -0,0 +1,46 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN:   -mcpu=pwr7 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
+; RUN:   -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-32BIT
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN:   -mcpu=pwr7 < %s | FileCheck %s
+
+declare i32 @llvm.ppc.mftbu()
+declare i32 @llvm.ppc.mfmsr()
+
+define dso_local zeroext i32 @test_mftbu() {
+; CHECK-LABEL: test_mftbu:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:mftbu 3
+; CHECK-NEXT:clrldi 3, 3, 32
+; CHECK-NEXT:blr
+;
+; CHECK-32BIT-LABEL: test_mftbu:
+; CHECK-32BIT:   # %bb.0: # %entry
+; CHECK-32BIT-NEXT:mftbu 3
+; CHECK-32BIT-NEXT:blr
+entry:
+  %0 = tail call i32 @llvm.ppc.mftbu()
+  ret i32 %0
+}
+
+define dso_local i64 @test_mfmsr() {
+; CHECK-LABEL: test_mfmsr:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:mfmsr 3
+; CHECK-NEXT:clrldi 3, 3, 32
+;

[PATCH] D105926: [PowerPC] Extra test case for LDARX

2021-07-19 Thread Albion Fung via Phabricator via cfe-commits

Conanap updated this revision to Diff 359681.
Conanap added a comment.

Removed metadata, -O3 to generate the test case


Repository:
  rG LLVM Github Monorepo

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Files:
  clang/test/CodeGen/builtins-ppc-xlcompat-check-ldarx-opt.ll


Index: clang/test/CodeGen/builtins-ppc-xlcompat-check-ldarx-opt.ll
===
--- /dev/null
+++ clang/test/CodeGen/builtins-ppc-xlcompat-check-ldarx-opt.ll
@@ -0,0 +1,88 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN:   -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN:   -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-AIX
+
+; Function Attrs: nounwind uwtable
+define dso_local signext i32 @main() local_unnamed_addr {
+; CHECK-LABEL: main:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:li 3, -1
+; CHECK-NEXT:li 4, 0
+; CHECK-NEXT:std 3, -8(1)
+; CHECK-NEXT:addi 3, 1, -8
+; CHECK-NEXT:.p2align 5
+; CHECK-NEXT:  .LBB0_1: # %do.body
+; CHECK-NEXT:#
+; CHECK-NEXT:#APP
+; CHECK-NEXT:ldarx 5, 0, 3
+; CHECK-NEXT:#NO_APP
+; CHECK-NEXT:stdcx. 4, 0, 3
+; CHECK-NEXT:mfocrf 5, 128
+; CHECK-NEXT:srwi 5, 5, 28
+; CHECK-NEXT:cmplwi 5, 0
+; CHECK-NEXT:beq 0, .LBB0_1
+; CHECK-NEXT:  # %bb.2: # %do.end
+; CHECK-NEXT:ld 3, -8(1)
+; CHECK-NEXT:li 4, 55
+; CHECK-NEXT:cmpldi 3, 0
+; CHECK-NEXT:li 3, 66
+; CHECK-NEXT:iseleq 3, 4, 3
+; CHECK-NEXT:blr
+;
+; CHECK-AIX-LABEL: main:
+; CHECK-AIX:   # %bb.0: # %entry
+; CHECK-AIX-NEXT:li 3, -1
+; CHECK-AIX-NEXT:li 4, 0
+; CHECK-AIX-NEXT:std 3, -8(1)
+; CHECK-AIX-NEXT:addi 3, 1, -8
+; CHECK-AIX-NEXT:.align 5
+; CHECK-AIX-NEXT:  L..BB0_1: # %do.body
+; CHECK-AIX-NEXT:#
+; CHECK-AIX-NEXT:#APP
+; CHECK-AIX-NEXT:ldarx 5, 0, 3
+; CHECK-AIX-NEXT:#NO_APP
+; CHECK-AIX-NEXT:stdcx. 4, 0, 3
+; CHECK-AIX-NEXT:mfocrf 5, 128
+; CHECK-AIX-NEXT:srwi 5, 5, 28
+; CHECK-AIX-NEXT:cmplwi 5, 0
+; CHECK-AIX-NEXT:beq 0, L..BB0_1
+; CHECK-AIX-NEXT:  # %bb.2: # %do.end
+; CHECK-AIX-NEXT:ld 3, -8(1)
+; CHECK-AIX-NEXT:li 4, 55
+; CHECK-AIX-NEXT:cmpldi 3, 0
+; CHECK-AIX-NEXT:li 3, 66
+; CHECK-AIX-NEXT:iseleq 3, 4, 3
+; CHECK-AIX-NEXT:blr
+entry:
+  %x64 = alloca i64, align 8
+  %0 = bitcast i64* %x64 to i8*
+  call void @llvm.lifetime.start.p0i8(i64 8, i8* nonnull %0)
+  store i64 -1, i64* %x64, align 8
+  br label %do.body
+
+do.body:  ; preds = %do.body, %entry
+  %1 = call i64 asm sideeffect "ldarx $0, ${1:y}", "=r,*Z,~{memory}"(i64* 
nonnull %x64)
+  %2 = call i32 @llvm.ppc.stdcx(i8* nonnull %0, i64 0)
+  %tobool.not = icmp eq i32 %2, 0
+  br i1 %tobool.not, label %do.body, label %do.end
+
+do.end:   ; preds = %do.body
+  %3 = load i64, i64* %x64, align 8
+  %cmp = icmp eq i64 %3, 0
+  %. = select i1 %cmp, i32 55, i32 66
+  call void @llvm.lifetime.end.p0i8(i64 8, i8* nonnull %0)
+  ret i32 %.
+}
+
+; Function Attrs: argmemonly mustprogress nofree nosync nounwind willreturn
+declare void @llvm.lifetime.start.p0i8(i64 immarg, i8* nocapture)
+
+; Function Attrs: nounwind writeonly
+declare i32 @llvm.ppc.stdcx(i8*, i64)
+
+; Function Attrs: argmemonly mustprogress nofree nosync nounwind willreturn
+declare void @llvm.lifetime.end.p0i8(i64 immarg, i8* nocapture)


Index: clang/test/CodeGen/builtins-ppc-xlcompat-check-ldarx-opt.ll
===
--- /dev/null
+++ clang/test/CodeGen/builtins-ppc-xlcompat-check-ldarx-opt.ll
@@ -0,0 +1,88 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN:   -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN:   -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-AIX
+
+; Function Attrs: nounwind uwtable
+define dso_local signext i32 @main() local_unnamed_addr {
+; CHECK-LABEL: main:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:li 3, -1
+; CHECK-NEXT:li 4, 0
+; CHECK-NEXT:std 3, -8(1)
+; CHECK-NEXT:addi 3, 1, -8
+; CHECK-NEXT:.p2align 5
+; CHECK-NEXT:  .LBB0_1: # %do.body
+; CHECK-NEXT:#
+; CHECK-NEXT:#APP
+; CHECK-NEXT:ldarx 5, 0, 3
+; CHECK-NEXT:#NO_APP
+; CHECK-NEXT:stdcx. 4, 0, 3
+; CHECK-NEXT:mfocrf 5, 128
+;

[PATCH] D105926: [PowerPC] Extra test case for LDARX

2021-07-19 Thread Albion Fung via Phabricator via cfe-commits

Conanap added a comment.

In D105926#2885291 , @teemperor wrote:

> Sorry for raising an unrelated topic here, but I can't reach @Conanap 
> directly via the mail from the git commits: @Conanap could you please create 
> the git branches for your patches in your own Github fork instead of the main 
> LLVM repo? LLVM's policy is to have working branches in everyone's private 
> fork (even though I don't think we explicitly tell people that when they get 
> commit access). I'll go ahead and delete your created branches end of next 
> week, but let me know if I should wait a bit longer with that. Thanks!

Ah apologies, I'll do that. Sorry about that! I'll keep the rest of the 
branches on my personal repo; please feel free to delete these by the end of 
next week.


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[PATCH] D105946: [PowerPC] Store, load, move from and to registers related builtins

2021-07-16 Thread Albion Fung via Phabricator via cfe-commits

Conanap updated this revision to Diff 359516.
Conanap marked an inline comment as done.
Conanap added a comment.

Moved pattern to a more appropriate place, updated test cases


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
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Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/lib/Basic/Targets/PPC.cpp
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond.c
  clang/test/CodeGen/builtins-ppc-xlcompat-move-tofrom-regs.c
  clang/test/CodeGen/builtins-ppc-xlcompat-prefetch.c
  clang/test/CodeGen/builtins-ppc-xlcompat-stfiw.c
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/Target/PowerPC/PPC.td
  llvm/lib/Target/PowerPC/PPCInstrInfo.td
  llvm/lib/Target/PowerPC/PPCInstrVSX.td
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-LoadReserve-StoreCond.ll
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-stfiw.ll
  llvm/test/CodeGen/builtins-ppc-xlcompat-move-tofrom-regs.ll
  llvm/test/CodeGen/builtins-ppc-xlcompat-prefetch.ll

Index: llvm/test/CodeGen/builtins-ppc-xlcompat-prefetch.ll
===
--- /dev/null
+++ llvm/test/CodeGen/builtins-ppc-xlcompat-prefetch.ll
@@ -0,0 +1,71 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN:   -mcpu=pwr7 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
+; RUN:   -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-AIX
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN:   -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-AIX64
+
+declare void @llvm.ppc.dcbtstt(i8*)
+declare void @llvm.ppc.dcbtt(i8*)
+
+@vpa = external local_unnamed_addr global i8*, align 8
+
+define dso_local void @test_dcbtstt() {
+; CHECK-LABEL: test_dcbtstt:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:addis 3, 2, .LC0@toc@ha
+; CHECK-NEXT:ld 3, .LC0@toc@l(3)
+; CHECK-NEXT:ld 3, 0(3)
+; CHECK-NEXT:dcbtstt 0, 3
+; CHECK-NEXT:blr
+;
+; CHECK-AIX-LABEL: test_dcbtstt:
+; CHECK-AIX:   # %bb.0: # %entry
+; CHECK-AIX-NEXT:lwz 3, L..C0(2) # @vpa
+; CHECK-AIX-NEXT:lwz 3, 0(3)
+; CHECK-AIX-NEXT:dcbtstt 0, 3
+; CHECK-AIX-NEXT:blr
+;
+; CHECK-AIX64-LABEL: test_dcbtstt:
+; CHECK-AIX64:   # %bb.0: # %entry
+; CHECK-AIX64-NEXT:ld 3, L..C0(2) # @vpa
+; CHECK-AIX64-NEXT:ld 3, 0(3)
+; CHECK-AIX64-NEXT:dcbtstt 0, 3
+; CHECK-AIX64-NEXT:blr
+entry:
+  %0 = load i8*, i8** @vpa, align 8
+  tail call void @llvm.ppc.dcbtstt(i8* %0)
+  ret void
+}
+
+
+define dso_local void @test_dcbtt() {
+; CHECK-LABEL: test_dcbtt:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:addis 3, 2, .LC0@toc@ha
+; CHECK-NEXT:ld 3, .LC0@toc@l(3)
+; CHECK-NEXT:ld 3, 0(3)
+; CHECK-NEXT:dcbtt 0, 3
+; CHECK-NEXT:blr
+;
+; CHECK-AIX-LABEL: test_dcbtt:
+; CHECK-AIX:   # %bb.0: # %entry
+; CHECK-AIX-NEXT:lwz 3, L..C0(2) # @vpa
+; CHECK-AIX-NEXT:lwz 3, 0(3)
+; CHECK-AIX-NEXT:dcbtt 0, 3
+; CHECK-AIX-NEXT:blr
+;
+; CHECK-AIX64-LABEL: test_dcbtt:
+; CHECK-AIX64:   # %bb.0: # %entry
+; CHECK-AIX64-NEXT:ld 3, L..C0(2) # @vpa
+; CHECK-AIX64-NEXT:ld 3, 0(3)
+; CHECK-AIX64-NEXT:dcbtt 0, 3
+; CHECK-AIX64-NEXT:blr
+entry:
+  %0 = load i8*, i8** @vpa, align 8
+  tail call void @llvm.ppc.dcbtt(i8* %0)
+  ret void
+}
Index: llvm/test/CodeGen/builtins-ppc-xlcompat-move-tofrom-regs.ll
===
--- /dev/null
+++ llvm/test/CodeGen/builtins-ppc-xlcompat-move-tofrom-regs.ll
@@ -0,0 +1,46 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN:   -mcpu=pwr7 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
+; RUN:   -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-32BIT
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN:   -mcpu=pwr7 < %s | FileCheck %s
+
+declare i32 @llvm.ppc.mftbu()
+declare i32 @llvm.ppc.mfmsr()
+
+define dso_local zeroext i32 @test_mftbu() {
+; CHECK-LABEL: test_mftbu:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:mftbu 3
+; CHECK-NEXT:clrldi 3, 3, 32
+; CHECK-NEXT:blr
+;
+; CHECK-32BIT-LABEL: test_mftbu:
+; CHECK-32BIT:   # %bb.0: # %entry
+; CHECK-32BIT-NEXT:mftbu 3
+; CHECK-32BIT-NEXT:blr
+entry:
+  %0 = tail call i32 @llvm.ppc.mftbu()
+  ret i32 %0
+}
+
+define dso_local i64 @test_mfmsr() {
+; CHECK-LABEL: test_mfmsr:
+; CHECK:   # %bb.0: # %entry
+;

[PATCH] D105946: [PowerPC] Store, load, move from and to registers related builtins

2021-07-16 Thread Albion Fung via Phabricator via cfe-commits

Conanap marked 4 inline comments as done.
Conanap added a comment.

Addressed comments




Comment at: clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond.c:15
+  // CHECK-LABEL: @test_lwarx
   // CHECK: %0 = tail call i32 asm sideeffect "lwarx $0, ${1:y}", 
"=r,*Z,~{memory}"(i32* %a)
   return __lwarx(a);

lei wrote:
> where is the check for `CHECK-NON-PWR8-ERR:`?
`lwarx` and `stwcx` are both available before power8, so the check is not 
needed.


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[PATCH] D105946: [PowerPC] Store, load, move from and to registers related builtins

2021-07-16 Thread Albion Fung via Phabricator via cfe-commits

Conanap updated this revision to Diff 359433.
Conanap marked an inline comment as done.
Conanap added a comment.

Updated test cases


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D105946/new/

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Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/lib/Basic/Targets/PPC.cpp
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond.c
  clang/test/CodeGen/builtins-ppc-xlcompat-move-tofrom-regs.c
  clang/test/CodeGen/builtins-ppc-xlcompat-prefetch.c
  clang/test/CodeGen/builtins-ppc-xlcompat-stfiw.c
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/Target/PowerPC/PPC.td
  llvm/lib/Target/PowerPC/PPCInstrInfo.td
  llvm/lib/Target/PowerPC/PPCInstrVSX.td
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-LoadReserve-StoreCond.ll
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-stfiw.ll
  llvm/test/CodeGen/builtins-ppc-xlcompat-move-tofrom-regs.ll
  llvm/test/CodeGen/builtins-ppc-xlcompat-prefetch.ll

Index: llvm/test/CodeGen/builtins-ppc-xlcompat-prefetch.ll
===
--- /dev/null
+++ llvm/test/CodeGen/builtins-ppc-xlcompat-prefetch.ll
@@ -0,0 +1,71 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN:   -mcpu=pwr7 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
+; RUN:   -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-AIX
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN:   -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-AIX64
+
+declare void @llvm.ppc.dcbtstt(i8*)
+declare void @llvm.ppc.dcbtt(i8*)
+
+@vpa = external local_unnamed_addr global i8*, align 8
+
+define dso_local void @test_dcbtstt() {
+; CHECK-LABEL: test_dcbtstt:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:addis 3, 2, .LC0@toc@ha
+; CHECK-NEXT:ld 3, .LC0@toc@l(3)
+; CHECK-NEXT:ld 3, 0(3)
+; CHECK-NEXT:dcbtstt 0, 3
+; CHECK-NEXT:blr
+;
+; CHECK-AIX-LABEL: test_dcbtstt:
+; CHECK-AIX:   # %bb.0: # %entry
+; CHECK-AIX-NEXT:lwz 3, L..C0(2) # @vpa
+; CHECK-AIX-NEXT:lwz 3, 0(3)
+; CHECK-AIX-NEXT:dcbtstt 0, 3
+; CHECK-AIX-NEXT:blr
+;
+; CHECK-AIX64-LABEL: test_dcbtstt:
+; CHECK-AIX64:   # %bb.0: # %entry
+; CHECK-AIX64-NEXT:ld 3, L..C0(2) # @vpa
+; CHECK-AIX64-NEXT:ld 3, 0(3)
+; CHECK-AIX64-NEXT:dcbtstt 0, 3
+; CHECK-AIX64-NEXT:blr
+entry:
+  %0 = load i8*, i8** @vpa, align 8
+  tail call void @llvm.ppc.dcbtstt(i8* %0)
+  ret void
+}
+
+
+define dso_local void @test_dcbtt() {
+; CHECK-LABEL: test_dcbtt:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:addis 3, 2, .LC0@toc@ha
+; CHECK-NEXT:ld 3, .LC0@toc@l(3)
+; CHECK-NEXT:ld 3, 0(3)
+; CHECK-NEXT:dcbtt 0, 3
+; CHECK-NEXT:blr
+;
+; CHECK-AIX-LABEL: test_dcbtt:
+; CHECK-AIX:   # %bb.0: # %entry
+; CHECK-AIX-NEXT:lwz 3, L..C0(2) # @vpa
+; CHECK-AIX-NEXT:lwz 3, 0(3)
+; CHECK-AIX-NEXT:dcbtt 0, 3
+; CHECK-AIX-NEXT:blr
+;
+; CHECK-AIX64-LABEL: test_dcbtt:
+; CHECK-AIX64:   # %bb.0: # %entry
+; CHECK-AIX64-NEXT:ld 3, L..C0(2) # @vpa
+; CHECK-AIX64-NEXT:ld 3, 0(3)
+; CHECK-AIX64-NEXT:dcbtt 0, 3
+; CHECK-AIX64-NEXT:blr
+entry:
+  %0 = load i8*, i8** @vpa, align 8
+  tail call void @llvm.ppc.dcbtt(i8* %0)
+  ret void
+}
Index: llvm/test/CodeGen/builtins-ppc-xlcompat-move-tofrom-regs.ll
===
--- /dev/null
+++ llvm/test/CodeGen/builtins-ppc-xlcompat-move-tofrom-regs.ll
@@ -0,0 +1,46 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN:   -mcpu=pwr7 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
+; RUN:   -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-32BIT
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN:   -mcpu=pwr7 < %s | FileCheck %s
+
+declare i32 @llvm.ppc.mftbu()
+declare i32 @llvm.ppc.mfmsr()
+
+define dso_local zeroext i32 @test_mftbu() {
+; CHECK-LABEL: test_mftbu:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:mftbu 3
+; CHECK-NEXT:clrldi 3, 3, 32
+; CHECK-NEXT:blr
+;
+; CHECK-32BIT-LABEL: test_mftbu:
+; CHECK-32BIT:   # %bb.0: # %entry
+; CHECK-32BIT-NEXT:mftbu 3
+; CHECK-32BIT-NEXT:blr
+entry:
+  %0 = tail call i32 @llvm.ppc.mftbu()
+  ret i32 %0
+}
+
+define dso_local i64 @test_mfmsr() {
+; CHECK-LABEL: test_mfmsr:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:mfmsr 3
+; CHECK-NEXT:clrldi 3,

[PATCH] D106130: [PowerPC] Implemented mtmsr, mfspr, mtspr Builtins

2021-07-16 Thread Albion Fung via Phabricator via cfe-commits

Conanap updated this revision to Diff 359424.
Conanap added a comment.

added an error test


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D106130/new/

https://reviews.llvm.org/D106130

Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/lib/Basic/Targets/PPC.cpp
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/builtins-ppc-xlcompat-error.c
  clang/test/CodeGen/builtins-ppc-xlcompat-move-tofrom-regs.c
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/Target/PowerPC/PPCInstr64Bit.td
  llvm/lib/Target/PowerPC/PPCInstrInfo.td
  llvm/test/CodeGen/builtins-ppc-xlcompat-mfspr-mtspr-64bit-only.ll
  llvm/test/CodeGen/builtins-ppc-xlcompat-mfspr-mtspr-aix32.ll
  llvm/test/CodeGen/builtins-ppc-xlcompat-move-tofrom-regs.ll

Index: llvm/test/CodeGen/builtins-ppc-xlcompat-move-tofrom-regs.ll
===
--- llvm/test/CodeGen/builtins-ppc-xlcompat-move-tofrom-regs.ll
+++ llvm/test/CodeGen/builtins-ppc-xlcompat-move-tofrom-regs.ll
@@ -1,15 +1,20 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; NOTE: Had to manually modify the last test case (mtmsr) to allow the
+; NOTE: common check of mtmsr instead of 4 different check prefixes
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
 ; RUN:   -mcpu=pwr8 < %s | FileCheck %s
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
 ; RUN:   -mcpu=pwr7 < %s | FileCheck %s
-; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
-; RUN:   -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-AIX
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
 ; RUN:   -mcpu=pwr7 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
+; RUN:   -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-32BIT
 
 declare i32 @llvm.ppc.mftbu()
 declare i32 @llvm.ppc.mfmsr()
+declare void @llvm.ppc.mtmsr(i32)
+
+@ula = external local_unnamed_addr global i64, align 8
 
 define dso_local zeroext i32 @test_mftbu() {
 ; CHECK-LABEL: test_mftbu:
@@ -18,10 +23,10 @@
 ; CHECK-NEXT:clrldi 3, 3, 32
 ; CHECK-NEXT:blr
 ;
-; CHECK-AIX-LABEL: test_mftbu:
-; CHECK-AIX:   # %bb.0: # %entry
-; CHECK-AIX-NEXT:mftbu 3
-; CHECK-AIX-NEXT:blr
+; CHECK-32BIT-LABEL: test_mftbu:
+; CHECK-32BIT:   # %bb.0: # %entry
+; CHECK-32BIT-NEXT:mftbu 3
+; CHECK-32BIT-NEXT:blr
 entry:
   %0 = tail call i32 @llvm.ppc.mftbu()
   ret i32 %0
@@ -34,13 +39,31 @@
 ; CHECK-NEXT:clrldi 3, 3, 32
 ; CHECK-NEXT:blr
 ;
-; CHECK-AIX-LABEL: test_mfmsr:
-; CHECK-AIX:   # %bb.0: # %entry
-; CHECK-AIX-NEXT:mfmsr 4
-; CHECK-AIX-NEXT:li 3, 0
-; CHECK-AIX-NEXT:blr
+; CHECK-32BIT-LABEL: test_mfmsr:
+; CHECK-32BIT:   # %bb.0: # %entry
+; CHECK-32BIT-NEXT:mfmsr 4
+; CHECK-32BIT-NEXT:li 3, 0
+; CHECK-32BIT-NEXT:blr
 entry:
   %0 = tail call i32 @llvm.ppc.mfmsr()
   %conv = zext i32 %0 to i64
   ret i64 %conv
 }
+
+define dso_local void @test_mtmsr() {
+; CHECK-LABEL: test_mtmsr:
+; CHECK:mtmsr 3
+; CHECK-NEXT:blr
+;
+; CHECK-32BIT-LABEL: test_mtmsr:
+; CHECK-32BIT:   # %bb.0: # %entry
+; CHECK-32BIT-NEXT:lwz 3, L..C0(2) # @ula
+; CHECK-32BIT-NEXT:lwz 3, 4(3)
+; CHECK-32BIT-NEXT:mtmsr 3, 0
+; CHECK-32BIT-NEXT:blr
+entry:
+  %0 = load i64, i64* @ula, align 8
+  %conv = trunc i64 %0 to i32
+  call void @llvm.ppc.mtmsr(i32 %conv)
+  ret void
+}
Index: llvm/test/CodeGen/builtins-ppc-xlcompat-mfspr-mtspr-aix32.ll
===
--- /dev/null
+++ llvm/test/CodeGen/builtins-ppc-xlcompat-mfspr-mtspr-aix32.ll
@@ -0,0 +1,123 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
+; RUN:   -mcpu=pwr7 < %s | FileCheck %s
+
+declare i32 @llvm.ppc.mfspr.i32(i32 immarg)
+declare void @llvm.ppc.mtspr.i32(i32 immarg, i32)
+
+@ula = external dso_local global i32, align 4
+
+define dso_local i32 @test_mfxer() {
+; CHECK-LABEL: test_mfxer:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:mfxer 3
+; CHECK-NEXT:blr
+entry:
+  %0 = call i32 @llvm.ppc.mfspr.i32(i32 1)
+  ret i32 %0
+}
+
+define dso_local i32 @test_mflr() {
+; CHECK-LABEL: test_mflr:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:mfspr 3, 8
+; CHECK-NEXT:blr
+entry:
+  %0 = call i32 @llvm.ppc.mfspr.i32(i32 8)
+  ret i32 %0
+}
+
+define dso_local i32 @test_mfctr() {
+; CHECK-LABEL: test_mfctr:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:mfspr 3, 9
+; CHECK-NEXT:blr
+entry:
+  %0 = call i32 @llvm.ppc.mfspr.i32(i32 9)
+  ret i32 %0
+}
+
+define dso_local i32 @test_mfppr() {
+; CHECK-LABEL: test_mfppr:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:mfspr 3, 896
+; CHECK-NEXT:blr
+entry:
+  %0 = call i32 @llvm.ppc.mfspr.i32(i32 896)
+  ret i32 %0
+}
+
+define dso_local i32 @test_mfppr32() {
+;

[PATCH] D106130: [PowerPC] Implemented mtmsr, mfspr, mtspr Builtins

2021-07-16 Thread Albion Fung via Phabricator via cfe-commits

Conanap added inline comments.



Comment at: clang/lib/CodeGen/CGBuiltin.cpp:15586
+  case PPC::BI__builtin_ppc_mfspr: {
+llvm::Type *RetType = CGM.getDataLayout().getTypeSizeInBits(VoidPtrTy) == 
32
+  ? Int32Ty

nemanjai wrote:
> Is this the formatting that `clang-format` produces? Seems surprising it 
> would format it that way.
I ran `git clang-format HEAD^` and it didn't change it, so seems like it was 
happy with this.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D106130/new/

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[PATCH] D106130: [PowerPC] Implemented mtmsr, mfspr, mtspr Builtins

2021-07-16 Thread Albion Fung via Phabricator via cfe-commits

Conanap updated this revision to Diff 359400.
Conanap marked 4 inline comments as done.
Conanap added a comment.

Changed `i32` to `timm` for patterns, some nits


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D106130/new/

https://reviews.llvm.org/D106130

Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/lib/Basic/Targets/PPC.cpp
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/builtins-ppc-xlcompat-move-tofrom-regs.c
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/Target/PowerPC/PPCInstr64Bit.td
  llvm/lib/Target/PowerPC/PPCInstrInfo.td
  llvm/test/CodeGen/builtins-ppc-xlcompat-mfspr-mtspr-64bit-only.ll
  llvm/test/CodeGen/builtins-ppc-xlcompat-mfspr-mtspr-aix32.ll
  llvm/test/CodeGen/builtins-ppc-xlcompat-move-tofrom-regs.ll

Index: llvm/test/CodeGen/builtins-ppc-xlcompat-move-tofrom-regs.ll
===
--- llvm/test/CodeGen/builtins-ppc-xlcompat-move-tofrom-regs.ll
+++ llvm/test/CodeGen/builtins-ppc-xlcompat-move-tofrom-regs.ll
@@ -1,15 +1,20 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; NOTE: Had to manually modify the last test case (mtmsr) to allow the
+; NOTE: common check of mtmsr instead of 4 different check prefixes
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
 ; RUN:   -mcpu=pwr8 < %s | FileCheck %s
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
 ; RUN:   -mcpu=pwr7 < %s | FileCheck %s
-; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
-; RUN:   -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-AIX
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
 ; RUN:   -mcpu=pwr7 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
+; RUN:   -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-32BIT
 
 declare i32 @llvm.ppc.mftbu()
 declare i32 @llvm.ppc.mfmsr()
+declare void @llvm.ppc.mtmsr(i32)
+
+@ula = external local_unnamed_addr global i64, align 8
 
 define dso_local zeroext i32 @test_mftbu() {
 ; CHECK-LABEL: test_mftbu:
@@ -18,10 +23,10 @@
 ; CHECK-NEXT:clrldi 3, 3, 32
 ; CHECK-NEXT:blr
 ;
-; CHECK-AIX-LABEL: test_mftbu:
-; CHECK-AIX:   # %bb.0: # %entry
-; CHECK-AIX-NEXT:mftbu 3
-; CHECK-AIX-NEXT:blr
+; CHECK-32BIT-LABEL: test_mftbu:
+; CHECK-32BIT:   # %bb.0: # %entry
+; CHECK-32BIT-NEXT:mftbu 3
+; CHECK-32BIT-NEXT:blr
 entry:
   %0 = tail call i32 @llvm.ppc.mftbu()
   ret i32 %0
@@ -34,13 +39,31 @@
 ; CHECK-NEXT:clrldi 3, 3, 32
 ; CHECK-NEXT:blr
 ;
-; CHECK-AIX-LABEL: test_mfmsr:
-; CHECK-AIX:   # %bb.0: # %entry
-; CHECK-AIX-NEXT:mfmsr 4
-; CHECK-AIX-NEXT:li 3, 0
-; CHECK-AIX-NEXT:blr
+; CHECK-32BIT-LABEL: test_mfmsr:
+; CHECK-32BIT:   # %bb.0: # %entry
+; CHECK-32BIT-NEXT:mfmsr 4
+; CHECK-32BIT-NEXT:li 3, 0
+; CHECK-32BIT-NEXT:blr
 entry:
   %0 = tail call i32 @llvm.ppc.mfmsr()
   %conv = zext i32 %0 to i64
   ret i64 %conv
 }
+
+define dso_local void @test_mtmsr() {
+; CHECK-LABEL: test_mtmsr:
+; CHECK:mtmsr 3
+; CHECK-NEXT:blr
+;
+; CHECK-32BIT-LABEL: test_mtmsr:
+; CHECK-32BIT:   # %bb.0: # %entry
+; CHECK-32BIT-NEXT:lwz 3, L..C0(2) # @ula
+; CHECK-32BIT-NEXT:lwz 3, 4(3)
+; CHECK-32BIT-NEXT:mtmsr 3, 0
+; CHECK-32BIT-NEXT:blr
+entry:
+  %0 = load i64, i64* @ula, align 8
+  %conv = trunc i64 %0 to i32
+  call void @llvm.ppc.mtmsr(i32 %conv)
+  ret void
+}
Index: llvm/test/CodeGen/builtins-ppc-xlcompat-mfspr-mtspr-aix32.ll
===
--- /dev/null
+++ llvm/test/CodeGen/builtins-ppc-xlcompat-mfspr-mtspr-aix32.ll
@@ -0,0 +1,123 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
+; RUN:   -mcpu=pwr7 < %s | FileCheck %s
+
+declare i32 @llvm.ppc.mfspr.i32(i32 immarg)
+declare void @llvm.ppc.mtspr.i32(i32 immarg, i32)
+
+@ula = external dso_local global i32, align 4
+
+define dso_local i32 @test_mfxer() {
+; CHECK-LABEL: test_mfxer:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:mfxer 3
+; CHECK-NEXT:blr
+entry:
+  %0 = call i32 @llvm.ppc.mfspr.i32(i32 1)
+  ret i32 %0
+}
+
+define dso_local i32 @test_mflr() {
+; CHECK-LABEL: test_mflr:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:mfspr 3, 8
+; CHECK-NEXT:blr
+entry:
+  %0 = call i32 @llvm.ppc.mfspr.i32(i32 8)
+  ret i32 %0
+}
+
+define dso_local i32 @test_mfctr() {
+; CHECK-LABEL: test_mfctr:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:mfspr 3, 9
+; CHECK-NEXT:blr
+entry:
+  %0 = call i32 @llvm.ppc.mfspr.i32(i32 9)
+  ret i32 %0
+}
+
+define dso_local i32 @test_mfppr() {
+; CHECK-LABEL: test_mfppr:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:mfspr 3, 896
+; CHECK-NEXT:blr
+entry:
+  %0 = call i32 @llvm.ppc.mfspr.i32(i32 896)
+  ret i32 %0
+}
+
+define dso_local i32

[PATCH] D105946: [PowerPC] Store, load, move from and to registers related builtins

2021-07-16 Thread Albion Fung via Phabricator via cfe-commits

Conanap updated this revision to Diff 359380.
Conanap added a comment.

Updated a test case


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D105946/new/

https://reviews.llvm.org/D105946

Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/lib/Basic/Targets/PPC.cpp
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond.c
  clang/test/CodeGen/builtins-ppc-xlcompat-move-tofrom-regs.c
  clang/test/CodeGen/builtins-ppc-xlcompat-prefetch.c
  clang/test/CodeGen/builtins-ppc-xlcompat-stfiw.c
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/Target/PowerPC/PPC.td
  llvm/lib/Target/PowerPC/PPCInstrInfo.td
  llvm/lib/Target/PowerPC/PPCInstrVSX.td
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-LoadReserve-StoreCond.ll
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-stfiw.ll
  llvm/test/CodeGen/builtins-ppc-xlcompat-move-tofrom-regs.ll
  llvm/test/CodeGen/builtins-ppc-xlcompat-prefetch.ll

Index: llvm/test/CodeGen/builtins-ppc-xlcompat-prefetch.ll
===
--- /dev/null
+++ llvm/test/CodeGen/builtins-ppc-xlcompat-prefetch.ll
@@ -0,0 +1,71 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN:   -mcpu=pwr7 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
+; RUN:   -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-AIX
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN:   -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-AIX64
+
+declare void @llvm.ppc.dcbtstt(i8*)
+declare void @llvm.ppc.dcbtt(i8*)
+
+@vpa = external local_unnamed_addr global i8*, align 8
+
+define dso_local void @test_dcbtstt() {
+; CHECK-LABEL: test_dcbtstt:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:addis 3, 2, .LC0@toc@ha
+; CHECK-NEXT:ld 3, .LC0@toc@l(3)
+; CHECK-NEXT:ld 3, 0(3)
+; CHECK-NEXT:dcbtstt 0, 3
+; CHECK-NEXT:blr
+;
+; CHECK-AIX-LABEL: test_dcbtstt:
+; CHECK-AIX:   # %bb.0: # %entry
+; CHECK-AIX-NEXT:lwz 3, L..C0(2) # @vpa
+; CHECK-AIX-NEXT:lwz 3, 0(3)
+; CHECK-AIX-NEXT:dcbtstt 0, 3
+; CHECK-AIX-NEXT:blr
+;
+; CHECK-AIX64-LABEL: test_dcbtstt:
+; CHECK-AIX64:   # %bb.0: # %entry
+; CHECK-AIX64-NEXT:ld 3, L..C0(2) # @vpa
+; CHECK-AIX64-NEXT:ld 3, 0(3)
+; CHECK-AIX64-NEXT:dcbtstt 0, 3
+; CHECK-AIX64-NEXT:blr
+entry:
+  %0 = load i8*, i8** @vpa, align 8
+  tail call void @llvm.ppc.dcbtstt(i8* %0)
+  ret void
+}
+
+
+define dso_local void @test_dcbtt() {
+; CHECK-LABEL: test_dcbtt:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:addis 3, 2, .LC0@toc@ha
+; CHECK-NEXT:ld 3, .LC0@toc@l(3)
+; CHECK-NEXT:ld 3, 0(3)
+; CHECK-NEXT:dcbtt 0, 3
+; CHECK-NEXT:blr
+;
+; CHECK-AIX-LABEL: test_dcbtt:
+; CHECK-AIX:   # %bb.0: # %entry
+; CHECK-AIX-NEXT:lwz 3, L..C0(2) # @vpa
+; CHECK-AIX-NEXT:lwz 3, 0(3)
+; CHECK-AIX-NEXT:dcbtt 0, 3
+; CHECK-AIX-NEXT:blr
+;
+; CHECK-AIX64-LABEL: test_dcbtt:
+; CHECK-AIX64:   # %bb.0: # %entry
+; CHECK-AIX64-NEXT:ld 3, L..C0(2) # @vpa
+; CHECK-AIX64-NEXT:ld 3, 0(3)
+; CHECK-AIX64-NEXT:dcbtt 0, 3
+; CHECK-AIX64-NEXT:blr
+entry:
+  %0 = load i8*, i8** @vpa, align 8
+  tail call void @llvm.ppc.dcbtt(i8* %0)
+  ret void
+}
Index: llvm/test/CodeGen/builtins-ppc-xlcompat-move-tofrom-regs.ll
===
--- /dev/null
+++ llvm/test/CodeGen/builtins-ppc-xlcompat-move-tofrom-regs.ll
@@ -0,0 +1,46 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN:   -mcpu=pwr7 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
+; RUN:   -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-32BIT
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN:   -mcpu=pwr7 < %s | FileCheck %s
+
+declare i32 @llvm.ppc.mftbu()
+declare i32 @llvm.ppc.mfmsr()
+
+define dso_local zeroext i32 @test_mftbu() {
+; CHECK-LABEL: test_mftbu:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:mftbu 3
+; CHECK-NEXT:clrldi 3, 3, 32
+; CHECK-NEXT:blr
+;
+; CHECK-32BIT-LABEL: test_mftbu:
+; CHECK-32BIT:   # %bb.0: # %entry
+; CHECK-32BIT-NEXT:mftbu 3
+; CHECK-32BIT-NEXT:blr
+entry:
+  %0 = tail call i32 @llvm.ppc.mftbu()
+  ret i32 %0
+}
+
+define dso_local i64 @test_mfmsr() {
+; CHECK-LABEL: test_mfmsr:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:mfmsr 3
+; CHECK-NEXT:clrldi 3, 3, 32
+; CHECK-NEXT:blr
+;
+;

[PATCH] D105946: [PowerPC] Store, load, move from and to registers related builtins

2021-07-16 Thread Albion Fung via Phabricator via cfe-commits

Conanap updated this revision to Diff 359322.
Conanap marked 5 inline comments as done.
Conanap added a comment.

Added non-vsx pattern for stfiw, extra testline for that pattern,
some nits


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D105946/new/

https://reviews.llvm.org/D105946

Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/lib/Basic/Targets/PPC.cpp
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond.c
  clang/test/CodeGen/builtins-ppc-xlcompat-move-tofrom-regs.c
  clang/test/CodeGen/builtins-ppc-xlcompat-prefetch.c
  clang/test/CodeGen/builtins-ppc-xlcompat-stfiw.c
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/Target/PowerPC/PPC.td
  llvm/lib/Target/PowerPC/PPCInstrInfo.td
  llvm/lib/Target/PowerPC/PPCInstrVSX.td
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-LoadReserve-StoreCond.ll
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-stfiw.ll
  llvm/test/CodeGen/builtins-ppc-xlcompat-move-tofrom-regs.ll
  llvm/test/CodeGen/builtins-ppc-xlcompat-prefetch.ll

Index: llvm/test/CodeGen/builtins-ppc-xlcompat-prefetch.ll
===
--- /dev/null
+++ llvm/test/CodeGen/builtins-ppc-xlcompat-prefetch.ll
@@ -0,0 +1,71 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN:   -mcpu=pwr7 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
+; RUN:   -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-AIX
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN:   -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-AIX64
+
+declare void @llvm.ppc.dcbtstt(i8*)
+declare void @llvm.ppc.dcbtt(i8*)
+
+@vpa = external local_unnamed_addr global i8*, align 8
+
+define dso_local void @test_dcbtstt() {
+; CHECK-LABEL: test_dcbtstt:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:addis 3, 2, .LC0@toc@ha
+; CHECK-NEXT:ld 3, .LC0@toc@l(3)
+; CHECK-NEXT:ld 3, 0(3)
+; CHECK-NEXT:dcbtstt 0, 3
+; CHECK-NEXT:blr
+;
+; CHECK-AIX-LABEL: test_dcbtstt:
+; CHECK-AIX:   # %bb.0: # %entry
+; CHECK-AIX-NEXT:lwz 3, L..C0(2) # @vpa
+; CHECK-AIX-NEXT:lwz 3, 0(3)
+; CHECK-AIX-NEXT:dcbtstt 0, 3
+; CHECK-AIX-NEXT:blr
+;
+; CHECK-AIX64-LABEL: test_dcbtstt:
+; CHECK-AIX64:   # %bb.0: # %entry
+; CHECK-AIX64-NEXT:ld 3, L..C0(2) # @vpa
+; CHECK-AIX64-NEXT:ld 3, 0(3)
+; CHECK-AIX64-NEXT:dcbtstt 0, 3
+; CHECK-AIX64-NEXT:blr
+entry:
+  %0 = load i8*, i8** @vpa, align 8
+  tail call void @llvm.ppc.dcbtstt(i8* %0)
+  ret void
+}
+
+
+define dso_local void @test_dcbtt() {
+; CHECK-LABEL: test_dcbtt:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:addis 3, 2, .LC0@toc@ha
+; CHECK-NEXT:ld 3, .LC0@toc@l(3)
+; CHECK-NEXT:ld 3, 0(3)
+; CHECK-NEXT:dcbtt 0, 3
+; CHECK-NEXT:blr
+;
+; CHECK-AIX-LABEL: test_dcbtt:
+; CHECK-AIX:   # %bb.0: # %entry
+; CHECK-AIX-NEXT:lwz 3, L..C0(2) # @vpa
+; CHECK-AIX-NEXT:lwz 3, 0(3)
+; CHECK-AIX-NEXT:dcbtt 0, 3
+; CHECK-AIX-NEXT:blr
+;
+; CHECK-AIX64-LABEL: test_dcbtt:
+; CHECK-AIX64:   # %bb.0: # %entry
+; CHECK-AIX64-NEXT:ld 3, L..C0(2) # @vpa
+; CHECK-AIX64-NEXT:ld 3, 0(3)
+; CHECK-AIX64-NEXT:dcbtt 0, 3
+; CHECK-AIX64-NEXT:blr
+entry:
+  %0 = load i8*, i8** @vpa, align 8
+  tail call void @llvm.ppc.dcbtt(i8* %0)
+  ret void
+}
Index: llvm/test/CodeGen/builtins-ppc-xlcompat-move-tofrom-regs.ll
===
--- /dev/null
+++ llvm/test/CodeGen/builtins-ppc-xlcompat-move-tofrom-regs.ll
@@ -0,0 +1,46 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN:   -mcpu=pwr7 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
+; RUN:   -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-32BIT
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN:   -mcpu=pwr7 < %s | FileCheck %s
+
+declare i32 @llvm.ppc.mftbu()
+declare i32 @llvm.ppc.mfmsr()
+
+define dso_local zeroext i32 @test_mftbu() {
+; CHECK-LABEL: test_mftbu:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:mftbu 3
+; CHECK-NEXT:clrldi 3, 3, 32
+; CHECK-NEXT:blr
+;
+; CHECK-32BIT-LABEL: test_mftbu:
+; CHECK-32BIT:   # %bb.0: # %entry
+; CHECK-32BIT-NEXT:mftbu 3
+; CHECK-32BIT-NEXT:blr
+entry:
+  %0 = tail call i32 @llvm.ppc.mftbu()
+  ret i32 %0
+}
+
+define dso_local i64 @test_mfmsr() {
+; CHECK-LABEL: test_mfmsr:
+; CHECK:   # %bb.0: #

[PATCH] D105946: [PowerPC] Store, load, move from and to registers related builtins

2021-07-16 Thread Albion Fung via Phabricator via cfe-commits

Conanap updated this revision to Diff 359259.
Conanap added a comment.

Updated lharx and lbarx to inline asm implementation, implemented stfiw.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D105946/new/

https://reviews.llvm.org/D105946

Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/lib/Basic/Targets/PPC.cpp
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond.c
  clang/test/CodeGen/builtins-ppc-xlcompat-move-tofrom-regs.c
  clang/test/CodeGen/builtins-ppc-xlcompat-prefetch.c
  clang/test/CodeGen/builtins-ppc-xlcompat-stfiw.c
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/Target/PowerPC/PPC.td
  llvm/lib/Target/PowerPC/PPCInstrInfo.td
  llvm/lib/Target/PowerPC/PPCInstrVSX.td
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-LoadReserve-StoreCond.ll
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-stfiw.ll
  llvm/test/CodeGen/builtins-ppc-xlcompat-move-tofrom-regs.ll
  llvm/test/CodeGen/builtins-ppc-xlcompat-prefetch.ll

Index: llvm/test/CodeGen/builtins-ppc-xlcompat-prefetch.ll
===
--- /dev/null
+++ llvm/test/CodeGen/builtins-ppc-xlcompat-prefetch.ll
@@ -0,0 +1,71 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN:   -mcpu=pwr7 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
+; RUN:   -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-AIX
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN:   -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-AIX64
+
+declare void @llvm.ppc.dcbtstt(i8*)
+declare void @llvm.ppc.dcbtt(i8*)
+
+@vpa = external local_unnamed_addr global i8*, align 8
+
+define dso_local void @test_dcbtstt() {
+; CHECK-LABEL: test_dcbtstt:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:addis 3, 2, .LC0@toc@ha
+; CHECK-NEXT:ld 3, .LC0@toc@l(3)
+; CHECK-NEXT:ld 3, 0(3)
+; CHECK-NEXT:dcbtstt 0, 3
+; CHECK-NEXT:blr
+;
+; CHECK-AIX-LABEL: test_dcbtstt:
+; CHECK-AIX:   # %bb.0: # %entry
+; CHECK-AIX-NEXT:lwz 3, L..C0(2) # @vpa
+; CHECK-AIX-NEXT:lwz 3, 0(3)
+; CHECK-AIX-NEXT:dcbtstt 0, 3
+; CHECK-AIX-NEXT:blr
+;
+; CHECK-AIX64-LABEL: test_dcbtstt:
+; CHECK-AIX64:   # %bb.0: # %entry
+; CHECK-AIX64-NEXT:ld 3, L..C0(2) # @vpa
+; CHECK-AIX64-NEXT:ld 3, 0(3)
+; CHECK-AIX64-NEXT:dcbtstt 0, 3
+; CHECK-AIX64-NEXT:blr
+entry:
+  %0 = load i8*, i8** @vpa, align 8
+  tail call void @llvm.ppc.dcbtstt(i8* %0)
+  ret void
+}
+
+
+define dso_local void @test_dcbtt() {
+; CHECK-LABEL: test_dcbtt:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:addis 3, 2, .LC0@toc@ha
+; CHECK-NEXT:ld 3, .LC0@toc@l(3)
+; CHECK-NEXT:ld 3, 0(3)
+; CHECK-NEXT:dcbtt 0, 3
+; CHECK-NEXT:blr
+;
+; CHECK-AIX-LABEL: test_dcbtt:
+; CHECK-AIX:   # %bb.0: # %entry
+; CHECK-AIX-NEXT:lwz 3, L..C0(2) # @vpa
+; CHECK-AIX-NEXT:lwz 3, 0(3)
+; CHECK-AIX-NEXT:dcbtt 0, 3
+; CHECK-AIX-NEXT:blr
+;
+; CHECK-AIX64-LABEL: test_dcbtt:
+; CHECK-AIX64:   # %bb.0: # %entry
+; CHECK-AIX64-NEXT:ld 3, L..C0(2) # @vpa
+; CHECK-AIX64-NEXT:ld 3, 0(3)
+; CHECK-AIX64-NEXT:dcbtt 0, 3
+; CHECK-AIX64-NEXT:blr
+entry:
+  %0 = load i8*, i8** @vpa, align 8
+  tail call void @llvm.ppc.dcbtt(i8* %0)
+  ret void
+}
Index: llvm/test/CodeGen/builtins-ppc-xlcompat-move-tofrom-regs.ll
===
--- /dev/null
+++ llvm/test/CodeGen/builtins-ppc-xlcompat-move-tofrom-regs.ll
@@ -0,0 +1,46 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN:   -mcpu=pwr7 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
+; RUN:   -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-32BIT
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN:   -mcpu=pwr7 < %s | FileCheck %s
+
+declare i32 @llvm.ppc.mftbu()
+declare i32 @llvm.ppc.mfmsr()
+
+define dso_local zeroext i32 @test_mftbu() {
+; CHECK-LABEL: test_mftbu:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:mftbu 3
+; CHECK-NEXT:clrldi 3, 3, 32
+; CHECK-NEXT:blr
+;
+; CHECK-32BIT-LABEL: test_mftbu:
+; CHECK-32BIT:   # %bb.0: # %entry
+; CHECK-32BIT-NEXT:mftbu 3
+; CHECK-32BIT-NEXT:blr
+entry:
+  %0 = tail call i32 @llvm.ppc.mftbu()
+  ret i32 %0
+}
+
+define dso_local i64 @test_mfmsr() {
+; CHECK-LABEL: test_mfmsr:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:mfmsr 3
+; CHECK-NEXT:

[PATCH] D106130: [PowerPC] Implemented mtmsr, mfspr, mtspr Builtins

2021-07-16 Thread Albion Fung via Phabricator via cfe-commits

Conanap updated this revision to Diff 359236.
Conanap added a comment.

Added sema checking


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D106130/new/

https://reviews.llvm.org/D106130

Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/lib/Basic/Targets/PPC.cpp
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/builtins-ppc-xlcompat-move-tofrom-regs.c
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/Target/PowerPC/PPCInstr64Bit.td
  llvm/lib/Target/PowerPC/PPCInstrInfo.td
  llvm/test/CodeGen/builtins-ppc-xlcompat-mfspr-mtspr-64bit-only.ll
  llvm/test/CodeGen/builtins-ppc-xlcompat-mfspr-mtspr-aix32.ll
  llvm/test/CodeGen/builtins-ppc-xlcompat-move-tofrom-regs.ll

Index: llvm/test/CodeGen/builtins-ppc-xlcompat-move-tofrom-regs.ll
===
--- llvm/test/CodeGen/builtins-ppc-xlcompat-move-tofrom-regs.ll
+++ llvm/test/CodeGen/builtins-ppc-xlcompat-move-tofrom-regs.ll
@@ -1,15 +1,20 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; NOTE: Had to manually modify the last test case (mtmsr) to allow the
+; NOTE: common check of mtmsr instead of 4 different check prefixes
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
 ; RUN:   -mcpu=pwr8 < %s | FileCheck %s
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
 ; RUN:   -mcpu=pwr7 < %s | FileCheck %s
-; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
-; RUN:   -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-AIX
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
 ; RUN:   -mcpu=pwr7 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
+; RUN:   -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-32BIT
 
 declare i32 @llvm.ppc.mftbu()
 declare i32 @llvm.ppc.mfmsr()
+declare void @llvm.ppc.mtmsr(i32)
+
+@ula = external local_unnamed_addr global i64, align 8
 
 define dso_local zeroext i32 @test_mftbu() {
 ; CHECK-LABEL: test_mftbu:
@@ -18,10 +23,10 @@
 ; CHECK-NEXT:clrldi 3, 3, 32
 ; CHECK-NEXT:blr
 ;
-; CHECK-AIX-LABEL: test_mftbu:
-; CHECK-AIX:   # %bb.0: # %entry
-; CHECK-AIX-NEXT:mftbu 3
-; CHECK-AIX-NEXT:blr
+; CHECK-32BIT-LABEL: test_mftbu:
+; CHECK-32BIT:   # %bb.0: # %entry
+; CHECK-32BIT-NEXT:mftbu 3
+; CHECK-32BIT-NEXT:blr
 entry:
   %0 = tail call i32 @llvm.ppc.mftbu()
   ret i32 %0
@@ -34,13 +39,31 @@
 ; CHECK-NEXT:clrldi 3, 3, 32
 ; CHECK-NEXT:blr
 ;
-; CHECK-AIX-LABEL: test_mfmsr:
-; CHECK-AIX:   # %bb.0: # %entry
-; CHECK-AIX-NEXT:mfmsr 4
-; CHECK-AIX-NEXT:li 3, 0
-; CHECK-AIX-NEXT:blr
+; CHECK-32BIT-LABEL: test_mfmsr:
+; CHECK-32BIT:   # %bb.0: # %entry
+; CHECK-32BIT-NEXT:mfmsr 4
+; CHECK-32BIT-NEXT:li 3, 0
+; CHECK-32BIT-NEXT:blr
 entry:
   %0 = tail call i32 @llvm.ppc.mfmsr()
   %conv = zext i32 %0 to i64
   ret i64 %conv
 }
+
+define dso_local void @test_mtmsr() {
+; CHECK-LABEL: test_mtmsr:
+; CHECK:mtmsr 3
+; CHECK-NEXT:blr
+;
+; CHECK-32BIT-LABEL: test_mtmsr:
+; CHECK-32BIT:   # %bb.0: # %entry
+; CHECK-32BIT-NEXT:lwz 3, L..C0(2) # @ula
+; CHECK-32BIT-NEXT:lwz 3, 4(3)
+; CHECK-32BIT-NEXT:mtmsr 3, 0
+; CHECK-32BIT-NEXT:blr
+entry:
+  %0 = load i64, i64* @ula, align 8
+  %conv = trunc i64 %0 to i32
+  call void @llvm.ppc.mtmsr(i32 %conv)
+  ret void
+}
Index: llvm/test/CodeGen/builtins-ppc-xlcompat-mfspr-mtspr-aix32.ll
===
--- /dev/null
+++ llvm/test/CodeGen/builtins-ppc-xlcompat-mfspr-mtspr-aix32.ll
@@ -0,0 +1,123 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
+; RUN:   -mcpu=pwr7 < %s | FileCheck %s
+
+declare i32 @llvm.ppc.mfspr.i32(i32 immarg)
+declare void @llvm.ppc.mtspr.i32(i32 immarg, i32)
+
+@ula = external dso_local global i32, align 4
+
+define dso_local i32 @test_mfxer() {
+; CHECK-LABEL: test_mfxer:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:mfxer 3
+; CHECK-NEXT:blr
+entry:
+  %0 = call i32 @llvm.ppc.mfspr.i32(i32 1)
+  ret i32 %0
+}
+
+define dso_local i32 @test_mflr() {
+; CHECK-LABEL: test_mflr:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:mfspr 3, 8
+; CHECK-NEXT:blr
+entry:
+  %0 = call i32 @llvm.ppc.mfspr.i32(i32 8)
+  ret i32 %0
+}
+
+define dso_local i32 @test_mfctr() {
+; CHECK-LABEL: test_mfctr:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:mfspr 3, 9
+; CHECK-NEXT:blr
+entry:
+  %0 = call i32 @llvm.ppc.mfspr.i32(i32 9)
+  ret i32 %0
+}
+
+define dso_local i32 @test_mfppr() {
+; CHECK-LABEL: test_mfppr:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:mfspr 3, 896
+; CHECK-NEXT:blr
+entry:
+  %0 = call i32 @llvm.ppc.mfspr.i32(i32 896)
+  ret i32 %0
+}
+
+define dso_local i32 @test_mfppr32() {
+; CHECK-LABEL: test_mfppr32:

[PATCH] D106130: [PowerPC] Implemented mtmsr, mfspr, mtspr Builtins

2021-07-16 Thread Albion Fung via Phabricator via cfe-commits

Conanap created this revision.
Herald added subscribers: steven.zhang, shchenz, kbarton, hiraditya, nemanjai.
Conanap requested review of this revision.
Herald added projects: clang, LLVM.
Herald added subscribers: llvm-commits, cfe-commits.

Implemented builtins for mtmsr, mfspr, mtspr on PowerPC;
the patch is intended for XL Compatibility.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D106130

Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/lib/Basic/Targets/PPC.cpp
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/builtins-ppc-xlcompat-move-tofrom-regs.c
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/Target/PowerPC/PPCInstr64Bit.td
  llvm/lib/Target/PowerPC/PPCInstrInfo.td
  llvm/test/CodeGen/builtins-ppc-xlcompat-mfspr-mtspr-64bit-only.ll
  llvm/test/CodeGen/builtins-ppc-xlcompat-mfspr-mtspr-aix32.ll
  llvm/test/CodeGen/builtins-ppc-xlcompat-move-tofrom-regs.ll

Index: llvm/test/CodeGen/builtins-ppc-xlcompat-move-tofrom-regs.ll
===
--- llvm/test/CodeGen/builtins-ppc-xlcompat-move-tofrom-regs.ll
+++ llvm/test/CodeGen/builtins-ppc-xlcompat-move-tofrom-regs.ll
@@ -1,15 +1,20 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; NOTE: Had to manually modify the last test case (mtmsr) to allow the
+; NOTE: common check of mtmsr instead of 4 different check prefixes
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
 ; RUN:   -mcpu=pwr8 < %s | FileCheck %s
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
 ; RUN:   -mcpu=pwr7 < %s | FileCheck %s
-; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
-; RUN:   -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-AIX
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
 ; RUN:   -mcpu=pwr7 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
+; RUN:   -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-32BIT
 
 declare i32 @llvm.ppc.mftbu()
 declare i32 @llvm.ppc.mfmsr()
+declare void @llvm.ppc.mtmsr(i32)
+
+@ula = external local_unnamed_addr global i64, align 8
 
 define dso_local zeroext i32 @test_mftbu() {
 ; CHECK-LABEL: test_mftbu:
@@ -18,10 +23,10 @@
 ; CHECK-NEXT:clrldi 3, 3, 32
 ; CHECK-NEXT:blr
 ;
-; CHECK-AIX-LABEL: test_mftbu:
-; CHECK-AIX:   # %bb.0: # %entry
-; CHECK-AIX-NEXT:mftbu 3
-; CHECK-AIX-NEXT:blr
+; CHECK-32BIT-LABEL: test_mftbu:
+; CHECK-32BIT:   # %bb.0: # %entry
+; CHECK-32BIT-NEXT:mftbu 3
+; CHECK-32BIT-NEXT:blr
 entry:
   %0 = tail call i32 @llvm.ppc.mftbu()
   ret i32 %0
@@ -34,13 +39,31 @@
 ; CHECK-NEXT:clrldi 3, 3, 32
 ; CHECK-NEXT:blr
 ;
-; CHECK-AIX-LABEL: test_mfmsr:
-; CHECK-AIX:   # %bb.0: # %entry
-; CHECK-AIX-NEXT:mfmsr 4
-; CHECK-AIX-NEXT:li 3, 0
-; CHECK-AIX-NEXT:blr
+; CHECK-32BIT-LABEL: test_mfmsr:
+; CHECK-32BIT:   # %bb.0: # %entry
+; CHECK-32BIT-NEXT:mfmsr 4
+; CHECK-32BIT-NEXT:li 3, 0
+; CHECK-32BIT-NEXT:blr
 entry:
   %0 = tail call i32 @llvm.ppc.mfmsr()
   %conv = zext i32 %0 to i64
   ret i64 %conv
 }
+
+define dso_local void @test_mtmsr() {
+; CHECK-LABEL: test_mtmsr:
+; CHECK:mtmsr 3
+; CHECK-NEXT:blr
+;
+; CHECK-32BIT-LABEL: test_mtmsr:
+; CHECK-32BIT:   # %bb.0: # %entry
+; CHECK-32BIT-NEXT:lwz 3, L..C0(2) # @ula
+; CHECK-32BIT-NEXT:lwz 3, 4(3)
+; CHECK-32BIT-NEXT:mtmsr 3, 0
+; CHECK-32BIT-NEXT:blr
+entry:
+  %0 = load i64, i64* @ula, align 8
+  %conv = trunc i64 %0 to i32
+  call void @llvm.ppc.mtmsr(i32 %conv)
+  ret void
+}
Index: llvm/test/CodeGen/builtins-ppc-xlcompat-mfspr-mtspr-aix32.ll
===
--- /dev/null
+++ llvm/test/CodeGen/builtins-ppc-xlcompat-mfspr-mtspr-aix32.ll
@@ -0,0 +1,123 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
+; RUN:   -mcpu=pwr7 < %s | FileCheck %s
+
+declare i32 @llvm.ppc.mfspr.i32(i32 immarg)
+declare void @llvm.ppc.mtspr.i32(i32 immarg, i32)
+
+@ula = external dso_local global i32, align 4
+
+define dso_local i32 @test_mfxer() {
+; CHECK-LABEL: test_mfxer:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:mfxer 3
+; CHECK-NEXT:blr
+entry:
+  %0 = call i32 @llvm.ppc.mfspr.i32(i32 1)
+  ret i32 %0
+}
+
+define dso_local i32 @test_mflr() {
+; CHECK-LABEL: test_mflr:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:mfspr 3, 8
+; CHECK-NEXT:blr
+entry:
+  %0 = call i32 @llvm.ppc.mfspr.i32(i32 8)
+  ret i32 %0
+}
+
+define dso_local i32 @test_mfctr() {
+; CHECK-LABEL: test_mfctr:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:mfspr 3, 9
+; CHECK-NEXT:blr
+entry:
+  %0 = call i32 @llvm.ppc.mfspr.i32(i32 9)
+  ret i32 %0
+}
+
+define dso_local i32 @test_mfppr() {
+; CHECK-LABEL: test_mfppr:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:mfspr 3, 896
+; CHECK-NEXT:

[PATCH] D105946: [PowerPC] Store, load, move from and to registers related builtins

2021-07-15 Thread Albion Fung via Phabricator via cfe-commits

Conanap updated this revision to Diff 359104.
Conanap added a comment.

Changed more xoaddr to ForceXForm


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D105946/new/

https://reviews.llvm.org/D105946

Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/lib/Basic/Targets/PPC.cpp
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond.c
  clang/test/CodeGen/builtins-ppc-xlcompat-move-tofrom-regs.c
  clang/test/CodeGen/builtins-ppc-xlcompat-prefetch.c
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/Target/PowerPC/PPC.td
  llvm/lib/Target/PowerPC/PPCInstrInfo.td
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-LoadReserve-StoreCond.ll
  llvm/test/CodeGen/builtins-ppc-xlcompat-move-tofrom-regs.ll
  llvm/test/CodeGen/builtins-ppc-xlcompat-prefetch.ll

Index: llvm/test/CodeGen/builtins-ppc-xlcompat-prefetch.ll
===
--- /dev/null
+++ llvm/test/CodeGen/builtins-ppc-xlcompat-prefetch.ll
@@ -0,0 +1,71 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN:   -mcpu=pwr7 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
+; RUN:   -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-AIX
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN:   -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-AIX64
+
+declare void @llvm.ppc.dcbtstt(i8*)
+declare void @llvm.ppc.dcbtt(i8*)
+
+@vpa = external local_unnamed_addr global i8*, align 8
+
+define dso_local void @test_dcbtstt() {
+; CHECK-LABEL: test_dcbtstt:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:addis 3, 2, .LC0@toc@ha
+; CHECK-NEXT:ld 3, .LC0@toc@l(3)
+; CHECK-NEXT:ld 3, 0(3)
+; CHECK-NEXT:dcbtstt 0, 3
+; CHECK-NEXT:blr
+;
+; CHECK-AIX-LABEL: test_dcbtstt:
+; CHECK-AIX:   # %bb.0: # %entry
+; CHECK-AIX-NEXT:lwz 3, L..C0(2) # @vpa
+; CHECK-AIX-NEXT:lwz 3, 0(3)
+; CHECK-AIX-NEXT:dcbtstt 0, 3
+; CHECK-AIX-NEXT:blr
+;
+; CHECK-AIX64-LABEL: test_dcbtstt:
+; CHECK-AIX64:   # %bb.0: # %entry
+; CHECK-AIX64-NEXT:ld 3, L..C0(2) # @vpa
+; CHECK-AIX64-NEXT:ld 3, 0(3)
+; CHECK-AIX64-NEXT:dcbtstt 0, 3
+; CHECK-AIX64-NEXT:blr
+entry:
+  %0 = load i8*, i8** @vpa, align 8
+  tail call void @llvm.ppc.dcbtstt(i8* %0)
+  ret void
+}
+
+
+define dso_local void @test_dcbtt() {
+; CHECK-LABEL: test_dcbtt:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:addis 3, 2, .LC0@toc@ha
+; CHECK-NEXT:ld 3, .LC0@toc@l(3)
+; CHECK-NEXT:ld 3, 0(3)
+; CHECK-NEXT:dcbtt 0, 3
+; CHECK-NEXT:blr
+;
+; CHECK-AIX-LABEL: test_dcbtt:
+; CHECK-AIX:   # %bb.0: # %entry
+; CHECK-AIX-NEXT:lwz 3, L..C0(2) # @vpa
+; CHECK-AIX-NEXT:lwz 3, 0(3)
+; CHECK-AIX-NEXT:dcbtt 0, 3
+; CHECK-AIX-NEXT:blr
+;
+; CHECK-AIX64-LABEL: test_dcbtt:
+; CHECK-AIX64:   # %bb.0: # %entry
+; CHECK-AIX64-NEXT:ld 3, L..C0(2) # @vpa
+; CHECK-AIX64-NEXT:ld 3, 0(3)
+; CHECK-AIX64-NEXT:dcbtt 0, 3
+; CHECK-AIX64-NEXT:blr
+entry:
+  %0 = load i8*, i8** @vpa, align 8
+  tail call void @llvm.ppc.dcbtt(i8* %0)
+  ret void
+}
Index: llvm/test/CodeGen/builtins-ppc-xlcompat-move-tofrom-regs.ll
===
--- /dev/null
+++ llvm/test/CodeGen/builtins-ppc-xlcompat-move-tofrom-regs.ll
@@ -0,0 +1,46 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN:   -mcpu=pwr7 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
+; RUN:   -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-32BIT
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN:   -mcpu=pwr7 < %s | FileCheck %s
+
+declare i32 @llvm.ppc.mftbu()
+declare i32 @llvm.ppc.mfmsr()
+
+define dso_local zeroext i32 @test_mftbu() {
+; CHECK-LABEL: test_mftbu:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:mftbu 3
+; CHECK-NEXT:clrldi 3, 3, 32
+; CHECK-NEXT:blr
+;
+; CHECK-32BIT-LABEL: test_mftbu:
+; CHECK-32BIT:   # %bb.0: # %entry
+; CHECK-32BIT-NEXT:mftbu 3
+; CHECK-32BIT-NEXT:blr
+entry:
+  %0 = tail call i32 @llvm.ppc.mftbu()
+  ret i32 %0
+}
+
+define dso_local i64 @test_mfmsr() {
+; CHECK-LABEL: test_mfmsr:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:mfmsr 3
+; CHECK-NEXT:clrldi 3, 3, 32
+; CHECK-NEXT:blr
+;
+; CHECK-32BIT-LABEL: test_mfmsr:
+; CHECK-32BIT:   # %bb.0: # %entry
+; CHECK-32BIT-NEXT:mfmsr 4
+; CHECK-32BIT-NEXT:li 3, 0
+;

[PATCH] D105946: [PowerPC] Store, load, move from and to registers related builtins

2021-07-15 Thread Albion Fung via Phabricator via cfe-commits

Conanap updated this revision to Diff 359097.
Conanap marked 2 inline comments as done.
Conanap added a comment.

Changed xoaddr, removed extws, changed check prefix


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D105946/new/

https://reviews.llvm.org/D105946

Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/lib/Basic/Targets/PPC.cpp
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond.c
  clang/test/CodeGen/builtins-ppc-xlcompat-move-tofrom-regs.c
  clang/test/CodeGen/builtins-ppc-xlcompat-prefetch.c
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/Target/PowerPC/PPC.td
  llvm/lib/Target/PowerPC/PPCInstrInfo.td
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-LoadReserve-StoreCond.ll
  llvm/test/CodeGen/builtins-ppc-xlcompat-move-tofrom-regs.ll
  llvm/test/CodeGen/builtins-ppc-xlcompat-prefetch.ll

Index: llvm/test/CodeGen/builtins-ppc-xlcompat-prefetch.ll
===
--- /dev/null
+++ llvm/test/CodeGen/builtins-ppc-xlcompat-prefetch.ll
@@ -0,0 +1,71 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN:   -mcpu=pwr7 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
+; RUN:   -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-AIX
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN:   -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-AIX64
+
+declare void @llvm.ppc.dcbtstt(i8*)
+declare void @llvm.ppc.dcbtt(i8*)
+
+@vpa = external local_unnamed_addr global i8*, align 8
+
+define dso_local void @test_dcbtstt() {
+; CHECK-LABEL: test_dcbtstt:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:addis 3, 2, .LC0@toc@ha
+; CHECK-NEXT:ld 3, .LC0@toc@l(3)
+; CHECK-NEXT:ld 3, 0(3)
+; CHECK-NEXT:dcbtstt 0, 3
+; CHECK-NEXT:blr
+;
+; CHECK-AIX-LABEL: test_dcbtstt:
+; CHECK-AIX:   # %bb.0: # %entry
+; CHECK-AIX-NEXT:lwz 3, L..C0(2) # @vpa
+; CHECK-AIX-NEXT:lwz 3, 0(3)
+; CHECK-AIX-NEXT:dcbtstt 0, 3
+; CHECK-AIX-NEXT:blr
+;
+; CHECK-AIX64-LABEL: test_dcbtstt:
+; CHECK-AIX64:   # %bb.0: # %entry
+; CHECK-AIX64-NEXT:ld 3, L..C0(2) # @vpa
+; CHECK-AIX64-NEXT:ld 3, 0(3)
+; CHECK-AIX64-NEXT:dcbtstt 0, 3
+; CHECK-AIX64-NEXT:blr
+entry:
+  %0 = load i8*, i8** @vpa, align 8
+  tail call void @llvm.ppc.dcbtstt(i8* %0)
+  ret void
+}
+
+
+define dso_local void @test_dcbtt() {
+; CHECK-LABEL: test_dcbtt:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:addis 3, 2, .LC0@toc@ha
+; CHECK-NEXT:ld 3, .LC0@toc@l(3)
+; CHECK-NEXT:ld 3, 0(3)
+; CHECK-NEXT:dcbtt 0, 3
+; CHECK-NEXT:blr
+;
+; CHECK-AIX-LABEL: test_dcbtt:
+; CHECK-AIX:   # %bb.0: # %entry
+; CHECK-AIX-NEXT:lwz 3, L..C0(2) # @vpa
+; CHECK-AIX-NEXT:lwz 3, 0(3)
+; CHECK-AIX-NEXT:dcbtt 0, 3
+; CHECK-AIX-NEXT:blr
+;
+; CHECK-AIX64-LABEL: test_dcbtt:
+; CHECK-AIX64:   # %bb.0: # %entry
+; CHECK-AIX64-NEXT:ld 3, L..C0(2) # @vpa
+; CHECK-AIX64-NEXT:ld 3, 0(3)
+; CHECK-AIX64-NEXT:dcbtt 0, 3
+; CHECK-AIX64-NEXT:blr
+entry:
+  %0 = load i8*, i8** @vpa, align 8
+  tail call void @llvm.ppc.dcbtt(i8* %0)
+  ret void
+}
Index: llvm/test/CodeGen/builtins-ppc-xlcompat-move-tofrom-regs.ll
===
--- /dev/null
+++ llvm/test/CodeGen/builtins-ppc-xlcompat-move-tofrom-regs.ll
@@ -0,0 +1,46 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN:   -mcpu=pwr7 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
+; RUN:   -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-32BIT
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN:   -mcpu=pwr7 < %s | FileCheck %s
+
+declare i32 @llvm.ppc.mftbu()
+declare i32 @llvm.ppc.mfmsr()
+
+define dso_local zeroext i32 @test_mftbu() {
+; CHECK-LABEL: test_mftbu:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:mftbu 3
+; CHECK-NEXT:clrldi 3, 3, 32
+; CHECK-NEXT:blr
+;
+; CHECK-32BIT-LABEL: test_mftbu:
+; CHECK-32BIT:   # %bb.0: # %entry
+; CHECK-32BIT-NEXT:mftbu 3
+; CHECK-32BIT-NEXT:blr
+entry:
+  %0 = tail call i32 @llvm.ppc.mftbu()
+  ret i32 %0
+}
+
+define dso_local i64 @test_mfmsr() {
+; CHECK-LABEL: test_mfmsr:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:mfmsr 3
+; CHECK-NEXT:clrldi 3, 3, 32
+; CHECK-NEXT:blr
+;
+; CHECK-32BIT-LABEL: test_mfmsr:
+; CHECK-32BIT:   # %bb.0: # %entry
+;

[PATCH] D105946: [PowerPC] Store, load, move from and to registers related builtins

2021-07-15 Thread Albion Fung via Phabricator via cfe-commits

Conanap updated this revision to Diff 359066.
Conanap added a comment.

Added more tests, corrected sema checking and intrinsic flag


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D105946/new/

https://reviews.llvm.org/D105946

Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/lib/Basic/Targets/PPC.cpp
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond.c
  clang/test/CodeGen/builtins-ppc-xlcompat-move-tofrom-regs.c
  clang/test/CodeGen/builtins-ppc-xlcompat-prefetch.c
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/Target/PowerPC/PPC.td
  llvm/lib/Target/PowerPC/PPCInstrInfo.td
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-LoadReserve-StoreCond.ll
  llvm/test/CodeGen/builtins-ppc-xlcompat-move-tofrom-regs.ll
  llvm/test/CodeGen/builtins-ppc-xlcompat-prefetch.ll

Index: llvm/test/CodeGen/builtins-ppc-xlcompat-prefetch.ll
===
--- /dev/null
+++ llvm/test/CodeGen/builtins-ppc-xlcompat-prefetch.ll
@@ -0,0 +1,71 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN:   -mcpu=pwr7 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
+; RUN:   -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-AIX
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN:   -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-AIX64
+
+declare void @llvm.ppc.dcbtstt(i8*)
+declare void @llvm.ppc.dcbtt(i8*)
+
+@vpa = external local_unnamed_addr global i8*, align 8
+
+define dso_local void @test_dcbtstt() {
+; CHECK-LABEL: test_dcbtstt:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:addis 3, 2, .LC0@toc@ha
+; CHECK-NEXT:ld 3, .LC0@toc@l(3)
+; CHECK-NEXT:ld 3, 0(3)
+; CHECK-NEXT:dcbtstt 0, 3
+; CHECK-NEXT:blr
+;
+; CHECK-AIX-LABEL: test_dcbtstt:
+; CHECK-AIX:   # %bb.0: # %entry
+; CHECK-AIX-NEXT:lwz 3, L..C0(2) # @vpa
+; CHECK-AIX-NEXT:lwz 3, 0(3)
+; CHECK-AIX-NEXT:dcbtstt 0, 3
+; CHECK-AIX-NEXT:blr
+;
+; CHECK-AIX64-LABEL: test_dcbtstt:
+; CHECK-AIX64:   # %bb.0: # %entry
+; CHECK-AIX64-NEXT:ld 3, L..C0(2) # @vpa
+; CHECK-AIX64-NEXT:ld 3, 0(3)
+; CHECK-AIX64-NEXT:dcbtstt 0, 3
+; CHECK-AIX64-NEXT:blr
+entry:
+  %0 = load i8*, i8** @vpa, align 8
+  tail call void @llvm.ppc.dcbtstt(i8* %0)
+  ret void
+}
+
+
+define dso_local void @test_dcbtt() {
+; CHECK-LABEL: test_dcbtt:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:addis 3, 2, .LC0@toc@ha
+; CHECK-NEXT:ld 3, .LC0@toc@l(3)
+; CHECK-NEXT:ld 3, 0(3)
+; CHECK-NEXT:dcbtt 0, 3
+; CHECK-NEXT:blr
+;
+; CHECK-AIX-LABEL: test_dcbtt:
+; CHECK-AIX:   # %bb.0: # %entry
+; CHECK-AIX-NEXT:lwz 3, L..C0(2) # @vpa
+; CHECK-AIX-NEXT:lwz 3, 0(3)
+; CHECK-AIX-NEXT:dcbtt 0, 3
+; CHECK-AIX-NEXT:blr
+;
+; CHECK-AIX64-LABEL: test_dcbtt:
+; CHECK-AIX64:   # %bb.0: # %entry
+; CHECK-AIX64-NEXT:ld 3, L..C0(2) # @vpa
+; CHECK-AIX64-NEXT:ld 3, 0(3)
+; CHECK-AIX64-NEXT:dcbtt 0, 3
+; CHECK-AIX64-NEXT:blr
+entry:
+  %0 = load i8*, i8** @vpa, align 8
+  tail call void @llvm.ppc.dcbtt(i8* %0)
+  ret void
+}
Index: llvm/test/CodeGen/builtins-ppc-xlcompat-move-tofrom-regs.ll
===
--- /dev/null
+++ llvm/test/CodeGen/builtins-ppc-xlcompat-move-tofrom-regs.ll
@@ -0,0 +1,46 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN:   -mcpu=pwr7 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
+; RUN:   -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-AIX
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN:   -mcpu=pwr7 < %s | FileCheck %s
+
+declare i32 @llvm.ppc.mftbu()
+declare i32 @llvm.ppc.mfmsr()
+
+define dso_local zeroext i32 @test_mftbu() {
+; CHECK-LABEL: test_mftbu:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:mftbu 3
+; CHECK-NEXT:clrldi 3, 3, 32
+; CHECK-NEXT:blr
+;
+; CHECK-AIX-LABEL: test_mftbu:
+; CHECK-AIX:   # %bb.0: # %entry
+; CHECK-AIX-NEXT:mftbu 3
+; CHECK-AIX-NEXT:blr
+entry:
+  %0 = tail call i32 @llvm.ppc.mftbu()
+  ret i32 %0
+}
+
+define dso_local i64 @test_mfmsr() {
+; CHECK-LABEL: test_mfmsr:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:mfmsr 3
+; CHECK-NEXT:clrldi 3, 3, 32
+; CHECK-NEXT:blr
+;
+; CHECK-AIX-LABEL: test_mfmsr:
+; CHECK-AIX:   # %bb.0: # %entry
+; CHECK-AIX-NEXT:mfmsr 4
+; CHECK-AIX-NEXT:li 3, 0

[PATCH] D105946: [PowerPC] Store, load, move from and to registers related builtins

2021-07-14 Thread Albion Fung via Phabricator via cfe-commits

Conanap updated this revision to Diff 358738.
Conanap marked an inline comment as done.
Conanap added a comment.

Added more sema checking, test case update


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D105946/new/

https://reviews.llvm.org/D105946

Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/lib/Basic/Targets/PPC.cpp
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond.c
  clang/test/CodeGen/builtins-ppc-xlcompat-move-tofrom-regs.c
  clang/test/CodeGen/builtins-ppc-xlcompat-prefetch.c
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/Target/PowerPC/PPC.td
  llvm/lib/Target/PowerPC/PPCInstrInfo.td
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-LoadReserve-StoreCond.ll
  llvm/test/CodeGen/builtins-ppc-xlcompat-move-tofrom-regs.ll
  llvm/test/CodeGen/builtins-ppc-xlcompat-prefetch.ll

Index: llvm/test/CodeGen/builtins-ppc-xlcompat-prefetch.ll
===
--- /dev/null
+++ llvm/test/CodeGen/builtins-ppc-xlcompat-prefetch.ll
@@ -0,0 +1,71 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN:   -mcpu=pwr7 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
+; RUN:   -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-AIX
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN:   -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-AIX64
+
+declare void @llvm.ppc.dcbtstt(i8*)
+declare void @llvm.ppc.dcbtt(i8*)
+
+@vpa = external local_unnamed_addr global i8*, align 8
+
+define dso_local void @test_dcbtstt() {
+; CHECK-LABEL: test_dcbtstt:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:addis 3, 2, .LC0@toc@ha
+; CHECK-NEXT:ld 3, .LC0@toc@l(3)
+; CHECK-NEXT:ld 3, 0(3)
+; CHECK-NEXT:dcbtstt 0, 3
+; CHECK-NEXT:blr
+;
+; CHECK-AIX-LABEL: test_dcbtstt:
+; CHECK-AIX:   # %bb.0: # %entry
+; CHECK-AIX-NEXT:lwz 3, L..C0(2) # @vpa
+; CHECK-AIX-NEXT:lwz 3, 0(3)
+; CHECK-AIX-NEXT:dcbtstt 0, 3
+; CHECK-AIX-NEXT:blr
+;
+; CHECK-AIX64-LABEL: test_dcbtstt:
+; CHECK-AIX64:   # %bb.0: # %entry
+; CHECK-AIX64-NEXT:ld 3, L..C0(2) # @vpa
+; CHECK-AIX64-NEXT:ld 3, 0(3)
+; CHECK-AIX64-NEXT:dcbtstt 0, 3
+; CHECK-AIX64-NEXT:blr
+entry:
+  %0 = load i8*, i8** @vpa, align 8
+  tail call void @llvm.ppc.dcbtstt(i8* %0)
+  ret void
+}
+
+
+define dso_local void @test_dcbtt() {
+; CHECK-LABEL: test_dcbtt:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:addis 3, 2, .LC0@toc@ha
+; CHECK-NEXT:ld 3, .LC0@toc@l(3)
+; CHECK-NEXT:ld 3, 0(3)
+; CHECK-NEXT:dcbtt 0, 3
+; CHECK-NEXT:blr
+;
+; CHECK-AIX-LABEL: test_dcbtt:
+; CHECK-AIX:   # %bb.0: # %entry
+; CHECK-AIX-NEXT:lwz 3, L..C0(2) # @vpa
+; CHECK-AIX-NEXT:lwz 3, 0(3)
+; CHECK-AIX-NEXT:dcbtt 0, 3
+; CHECK-AIX-NEXT:blr
+;
+; CHECK-AIX64-LABEL: test_dcbtt:
+; CHECK-AIX64:   # %bb.0: # %entry
+; CHECK-AIX64-NEXT:ld 3, L..C0(2) # @vpa
+; CHECK-AIX64-NEXT:ld 3, 0(3)
+; CHECK-AIX64-NEXT:dcbtt 0, 3
+; CHECK-AIX64-NEXT:blr
+entry:
+  %0 = load i8*, i8** @vpa, align 8
+  tail call void @llvm.ppc.dcbtt(i8* %0)
+  ret void
+}
Index: llvm/test/CodeGen/builtins-ppc-xlcompat-move-tofrom-regs.ll
===
--- /dev/null
+++ llvm/test/CodeGen/builtins-ppc-xlcompat-move-tofrom-regs.ll
@@ -0,0 +1,46 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN:   -mcpu=pwr7 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
+; RUN:   -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-AIX
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN:   -mcpu=pwr7 < %s | FileCheck %s
+
+declare i32 @llvm.ppc.mftbu()
+declare i32 @llvm.ppc.mfmsr()
+
+define dso_local zeroext i32 @test_mftbu() {
+; CHECK-LABEL: test_mftbu:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:mftbu 3
+; CHECK-NEXT:clrldi 3, 3, 32
+; CHECK-NEXT:blr
+;
+; CHECK-AIX-LABEL: test_mftbu:
+; CHECK-AIX:   # %bb.0: # %entry
+; CHECK-AIX-NEXT:mftbu 3
+; CHECK-AIX-NEXT:blr
+entry:
+  %0 = tail call i32 @llvm.ppc.mftbu()
+  ret i32 %0
+}
+
+define dso_local i64 @test_mfmsr() {
+; CHECK-LABEL: test_mfmsr:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:mfmsr 3
+; CHECK-NEXT:clrldi 3, 3, 32
+; CHECK-NEXT:blr
+;
+; CHECK-AIX-LABEL: test_mfmsr:
+; CHECK-AIX:   # %bb.0: # %entry
+; CHECK-AIX-NEXT:mfmsr 4
+;

[PATCH] D105754: [PowerPC] Fix L[D|W]ARX Implementation

2021-07-14 Thread Albion Fung via Phabricator via cfe-commits

This revision was automatically updated to reflect the committed changes.
Closed by commit rGf1aca5ac96eb: [PowerPC] Fix L[D|W]ARX Implementation 
(authored by Conanap).

Changed prior to commit:
  https://reviews.llvm.org/D105754?vs=358032=358289#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D105754/new/

https://reviews.llvm.org/D105754

Files:
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond-64bit-only.c
  clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond.c
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/Target/PowerPC/PPCInstr64Bit.td
  llvm/lib/Target/PowerPC/PPCInstrInfo.td
  
llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-LoadReserve-StoreCond-64bit-only.ll
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-LoadReserve-StoreCond.ll

Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-LoadReserve-StoreCond.ll
===
--- llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-LoadReserve-StoreCond.ll
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-LoadReserve-StoreCond.ll
@@ -12,18 +12,21 @@
 define dso_local signext i32 @test_lwarx(i32* readnone %a) {
 ; CHECK-64-LABEL: test_lwarx:
 ; CHECK-64:   # %bb.0: # %entry
+; CHECK-64-NEXT:#APP
 ; CHECK-64-NEXT:lwarx 3, 0, 3
+; CHECK-64-NEXT:#NO_APP
 ; CHECK-64-NEXT:extsw 3, 3
 ; CHECK-64-NEXT:blr
 ;
 ; CHECK-32-LABEL: test_lwarx:
 ; CHECK-32:   # %bb.0: # %entry
+; CHECK-32-NEXT:#APP
 ; CHECK-32-NEXT:lwarx 3, 0, 3
+; CHECK-32-NEXT:#NO_APP
 ; CHECK-32-NEXT:blr
 entry:
-  %0 = bitcast i32* %a to i8*
-  %1 = tail call i32 @llvm.ppc.lwarx(i8* %0)
-  ret i32 %1
+  %0 = call i32 asm sideeffect "lwarx $0, ${1:y}", "=r,*Z,~{memory}"(i32* %a)
+  ret i32 %0
 }
 
 declare i32 @llvm.ppc.stwcx(i8*, i32)
Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-LoadReserve-StoreCond-64bit-only.ll
===
--- llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-LoadReserve-StoreCond-64bit-only.ll
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-LoadReserve-StoreCond-64bit-only.ll
@@ -10,17 +10,18 @@
 define dso_local i64 @test_ldarx(i64* readnone %a) {
 ; CHECK-LABEL: test_ldarx:
 ; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:#APP
 ; CHECK-NEXT:ldarx 3, 0, 3
+; CHECK-NEXT:#NO_APP
 ; CHECK-NEXT:blr
 entry:
-  %0 = bitcast i64* %a to i8*
-  %1 = tail call i64 @llvm.ppc.ldarx(i8* %0)
-  ret i64 %1
+  %0 = call i64 asm sideeffect "ldarx $0, ${1:y}", "=r,*Z,~{memory}"(i64* %a)
+  ret i64 %0
 }
 
 declare i32 @llvm.ppc.stdcx(i8*, i64)
-define dso_local i64 @test(i64* %a, i64 %b) {
-; CHECK-LABEL: test:
+define dso_local i64 @test_stdcx(i64* %a, i64 %b) {
+; CHECK-LABEL: test_stdcx:
 ; CHECK:   # %bb.0: # %entry
 ; CHECK-NEXT:stdcx. 4, 0, 3
 ; CHECK-NEXT:mfocrf 3, 128
Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td
===
--- llvm/lib/Target/PowerPC/PPCInstrInfo.td
+++ llvm/lib/Target/PowerPC/PPCInstrInfo.td
@@ -5413,8 +5413,6 @@
 def : Pat<(i64 (bitreverse i64:$A)),
   (OR8 (RLDICR DWBytes7654.DWord, 32, 31), DWBytes3210.DWord)>;
 
-def : Pat<(int_ppc_lwarx ForceXForm:$dst),
-  (LWARX ForceXForm:$dst)>;
 def : Pat<(int_ppc_stwcx ForceXForm:$dst, gprc:$A),
   (STWCX gprc:$A, ForceXForm:$dst)>;
 def : Pat<(int_ppc_tw gprc:$A, gprc:$B, i32:$IMM),
Index: llvm/lib/Target/PowerPC/PPCInstr64Bit.td
===
--- llvm/lib/Target/PowerPC/PPCInstr64Bit.td
+++ llvm/lib/Target/PowerPC/PPCInstr64Bit.td
@@ -1723,8 +1723,6 @@
 
 def : Pat<(int_ppc_stdcx ForceXForm:$dst, g8rc:$A),
   (STDCX g8rc:$A, ForceXForm:$dst)>;
-def : Pat<(int_ppc_ldarx ForceXForm:$dst),
-  (LDARX ForceXForm:$dst)>;
 def : Pat<(int_ppc_tdw g8rc:$A, g8rc:$B, i32:$IMM),
   (TD $IMM, $A, $B)>;
 
Index: llvm/include/llvm/IR/IntrinsicsPowerPC.td
===
--- llvm/include/llvm/IR/IntrinsicsPowerPC.td
+++ llvm/include/llvm/IR/IntrinsicsPowerPC.td
@@ -1565,9 +1565,5 @@
   def int_ppc_stwcx : GCCBuiltin<"__builtin_ppc_stwcx">,
   Intrinsic<[llvm_i32_ty], [llvm_ptr_ty, llvm_i32_ty],
 [IntrWriteMem]>;
-  def int_ppc_lwarx : GCCBuiltin<"__builtin_ppc_lwarx">,
-  Intrinsic<[llvm_i32_ty], [llvm_ptr_ty], [IntrNoMem]>;
-  def int_ppc_ldarx : GCCBuiltin<"__builtin_ppc_ldarx">,
-  Intrinsic<[llvm_i64_ty], [llvm_ptr_ty], [IntrNoMem]>;
 }
 
Index: clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond.c
===
--- clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond.c
+++ clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond.c
@@ -1,22 +1,20 @@
-// RUN:

[PATCH] D105946: [PowerPC] Store, load, move from and to registers related builtins

2021-07-13 Thread Albion Fung via Phabricator via cfe-commits

Conanap created this revision.
Herald added subscribers: shchenz, kbarton, hiraditya, nemanjai.
Conanap requested review of this revision.
Herald added projects: clang, LLVM.
Herald added subscribers: llvm-commits, cfe-commits.

  This patch implements store, load, move from and to registers related

builtins. The patch aims to provide feature parady with xlC on AIX.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D105946

Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/lib/Basic/Targets/PPC.cpp
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond.c
  clang/test/CodeGen/builtins-ppc-xlcompat-move-tofrom-regs.c
  clang/test/CodeGen/builtins-ppc-xlcompat-prefetch.c
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/Target/PowerPC/PPC.td
  llvm/lib/Target/PowerPC/PPCInstrInfo.td
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-LoadReserve-StoreCond.ll
  llvm/test/CodeGen/builtins-ppc-xlcompat-move-tofrom-regs.ll
  llvm/test/CodeGen/builtins-ppc-xlcompat-prefetch.ll

Index: llvm/test/CodeGen/builtins-ppc-xlcompat-prefetch.ll
===
--- /dev/null
+++ llvm/test/CodeGen/builtins-ppc-xlcompat-prefetch.ll
@@ -0,0 +1,71 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN:   -mcpu=pwr7 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
+; RUN:   -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-AIX
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN:   -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-AIX64
+
+declare void @llvm.ppc.dcbtstt(i8*)
+declare void @llvm.ppc.dcbtt(i8*)
+
+@vpa = external local_unnamed_addr global i8*, align 8
+
+define dso_local void @test_dcbtstt() {
+; CHECK-LABEL: test_dcbtstt:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:addis 3, 2, .LC0@toc@ha
+; CHECK-NEXT:ld 3, .LC0@toc@l(3)
+; CHECK-NEXT:ld 3, 0(3)
+; CHECK-NEXT:dcbtstt 0, 3
+; CHECK-NEXT:blr
+;
+; CHECK-AIX-LABEL: test_dcbtstt:
+; CHECK-AIX:   # %bb.0: # %entry
+; CHECK-AIX-NEXT:lwz 3, L..C0(2) # @vpa
+; CHECK-AIX-NEXT:lwz 3, 0(3)
+; CHECK-AIX-NEXT:dcbtstt 0, 3
+; CHECK-AIX-NEXT:blr
+;
+; CHECK-AIX64-LABEL: test_dcbtstt:
+; CHECK-AIX64:   # %bb.0: # %entry
+; CHECK-AIX64-NEXT:ld 3, L..C0(2) # @vpa
+; CHECK-AIX64-NEXT:ld 3, 0(3)
+; CHECK-AIX64-NEXT:dcbtstt 0, 3
+; CHECK-AIX64-NEXT:blr
+entry:
+  %0 = load i8*, i8** @vpa, align 8
+  tail call void @llvm.ppc.dcbtstt(i8* %0)
+  ret void
+}
+
+
+define dso_local void @test_dcbtt() {
+; CHECK-LABEL: test_dcbtt:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:addis 3, 2, .LC0@toc@ha
+; CHECK-NEXT:ld 3, .LC0@toc@l(3)
+; CHECK-NEXT:ld 3, 0(3)
+; CHECK-NEXT:dcbtt 0, 3
+; CHECK-NEXT:blr
+;
+; CHECK-AIX-LABEL: test_dcbtt:
+; CHECK-AIX:   # %bb.0: # %entry
+; CHECK-AIX-NEXT:lwz 3, L..C0(2) # @vpa
+; CHECK-AIX-NEXT:lwz 3, 0(3)
+; CHECK-AIX-NEXT:dcbtt 0, 3
+; CHECK-AIX-NEXT:blr
+;
+; CHECK-AIX64-LABEL: test_dcbtt:
+; CHECK-AIX64:   # %bb.0: # %entry
+; CHECK-AIX64-NEXT:ld 3, L..C0(2) # @vpa
+; CHECK-AIX64-NEXT:ld 3, 0(3)
+; CHECK-AIX64-NEXT:dcbtt 0, 3
+; CHECK-AIX64-NEXT:blr
+entry:
+  %0 = load i8*, i8** @vpa, align 8
+  tail call void @llvm.ppc.dcbtt(i8* %0)
+  ret void
+}
Index: llvm/test/CodeGen/builtins-ppc-xlcompat-move-tofrom-regs.ll
===
--- /dev/null
+++ llvm/test/CodeGen/builtins-ppc-xlcompat-move-tofrom-regs.ll
@@ -0,0 +1,46 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN:   -mcpu=pwr7 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
+; RUN:   -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-AIX
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN:   -mcpu=pwr7 < %s | FileCheck %s
+
+declare i32 @llvm.ppc.mftbu()
+declare i32 @llvm.ppc.mfmsr()
+
+define dso_local zeroext i32 @test_mftbu() {
+; CHECK-LABEL: test_mftbu:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:mftbu 3
+; CHECK-NEXT:clrldi 3, 3, 32
+; CHECK-NEXT:blr
+;
+; CHECK-AIX-LABEL: test_mftbu:
+; CHECK-AIX:   # %bb.0: # %entry
+; CHECK-AIX-NEXT:mftbu 3
+; CHECK-AIX-NEXT:blr
+entry:
+  %0 = tail call i32 @llvm.ppc.mftbu()
+  ret i32 %0
+}
+
+define dso_local i64 @test_mfmsr() {
+; CHECK-LABEL: test_mfmsr:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:mfmsr 3
+; CHECK-NEXT:clrldi 3, 3, 32
+; CHECK-NEXT:

[PATCH] D105926: [PowerPC] Extra test case for LDARX

2021-07-13 Thread Albion Fung via Phabricator via cfe-commits

Conanap created this revision.
Herald added subscribers: shchenz, kbarton, nemanjai.
Conanap requested review of this revision.
Herald added a project: clang.
Herald added a subscriber: cfe-commits.

An extra test case added for the builtin __LDARX.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D105926

Files:
  clang/test/CodeGen/builtins-ppc-xlcompat-check-ldarx-opt.ll

Index: clang/test/CodeGen/builtins-ppc-xlcompat-check-ldarx-opt.ll
===
--- /dev/null
+++ clang/test/CodeGen/builtins-ppc-xlcompat-check-ldarx-opt.ll
@@ -0,0 +1,160 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN:   -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN:   -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-AIX
+
+; Function Attrs: noinline nounwind optnone uwtable
+define dso_local signext i32 @main() #0 {
+; CHECK-LABEL: main:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:li 3, 0
+; CHECK-NEXT:stw 3, -12(1)
+; CHECK-NEXT:li 3, -1
+; CHECK-NEXT:std 3, -32(1)
+; CHECK-NEXT:li 3, 0
+; CHECK-NEXT:std 3, -40(1)
+; CHECK-NEXT:  .LBB0_1: # %do.body
+; CHECK-NEXT:#
+; CHECK-NEXT:addi 3, 1, -32
+; CHECK-NEXT:#APP
+; CHECK-NEXT:ldarx 3, 0, 3
+; CHECK-NEXT:#NO_APP
+; CHECK-NEXT:std 3, -24(1)
+; CHECK-NEXT:addi 3, 1, -32
+; CHECK-NEXT:ld 4, -24(1)
+; CHECK-NEXT:ld 5, -40(1)
+; CHECK-NEXT:and 4, 4, 5
+; CHECK-NEXT:stdcx. 4, 0, 3
+; CHECK-NEXT:mfocrf 3, 128
+; CHECK-NEXT:srwi 3, 3, 28
+; CHECK-NEXT:stw 3, -44(1)
+; CHECK-NEXT:  # %bb.2: # %do.cond
+; CHECK-NEXT:#
+; CHECK-NEXT:lwz 3, -44(1)
+; CHECK-NEXT:cmplwi 3, 0
+; CHECK-NEXT:beq 0, .LBB0_1
+; CHECK-NEXT:b .LBB0_3
+; CHECK-NEXT:  .LBB0_3: # %do.end
+; CHECK-NEXT:ld 3, -32(1)
+; CHECK-NEXT:cmpdi 3, 0
+; CHECK-NEXT:bne 0, .LBB0_5
+; CHECK-NEXT:  # %bb.4: # %if.then
+; CHECK-NEXT:li 3, 55
+; CHECK-NEXT:stw 3, -12(1)
+; CHECK-NEXT:b .LBB0_6
+; CHECK-NEXT:  .LBB0_5: # %if.end
+; CHECK-NEXT:li 3, 66
+; CHECK-NEXT:stw 3, -12(1)
+; CHECK-NEXT:  .LBB0_6: # %return
+; CHECK-NEXT:lwa 3, -12(1)
+; CHECK-NEXT:blr
+;
+; CHECK-AIX-LABEL: main:
+; CHECK-AIX:   # %bb.0: # %entry
+; CHECK-AIX-NEXT:li 3, 0
+; CHECK-AIX-NEXT:stw 3, -12(1)
+; CHECK-AIX-NEXT:li 4, -1
+; CHECK-AIX-NEXT:std 4, -32(1)
+; CHECK-AIX-NEXT:std 3, -40(1)
+; CHECK-AIX-NEXT:b L..BB0_1
+; CHECK-AIX-NEXT:  L..BB0_1: # %do.body
+; CHECK-AIX-NEXT:#
+; CHECK-AIX-NEXT:addi 3, 1, -32
+; CHECK-AIX-NEXT:#APP
+; CHECK-AIX-NEXT:ldarx 4, 0, 3
+; CHECK-AIX-NEXT:#NO_APP
+; CHECK-AIX-NEXT:std 4, -24(1)
+; CHECK-AIX-NEXT:ld 4, -24(1)
+; CHECK-AIX-NEXT:ld 5, -40(1)
+; CHECK-AIX-NEXT:and 4, 4, 5
+; CHECK-AIX-NEXT:stdcx. 4, 0, 3
+; CHECK-AIX-NEXT:mfocrf 3, 128
+; CHECK-AIX-NEXT:srwi 3, 3, 28
+; CHECK-AIX-NEXT:stw 3, -44(1)
+; CHECK-AIX-NEXT:b L..BB0_2
+; CHECK-AIX-NEXT:  L..BB0_2: # %do.cond
+; CHECK-AIX-NEXT:#
+; CHECK-AIX-NEXT:lwz 3, -44(1)
+; CHECK-AIX-NEXT:cmplwi 3, 0
+; CHECK-AIX-NEXT:beq 0, L..BB0_1
+; CHECK-AIX-NEXT:b L..BB0_3
+; CHECK-AIX-NEXT:  L..BB0_3: # %do.end
+; CHECK-AIX-NEXT:ld 3, -32(1)
+; CHECK-AIX-NEXT:cmpldi 3, 0
+; CHECK-AIX-NEXT:bne 0, L..BB0_5
+; CHECK-AIX-NEXT:b L..BB0_4
+; CHECK-AIX-NEXT:  L..BB0_4: # %if.then
+; CHECK-AIX-NEXT:li 3, 55
+; CHECK-AIX-NEXT:stw 3, -12(1)
+; CHECK-AIX-NEXT:b L..BB0_6
+; CHECK-AIX-NEXT:  L..BB0_5: # %if.end
+; CHECK-AIX-NEXT:li 3, 66
+; CHECK-AIX-NEXT:stw 3, -12(1)
+; CHECK-AIX-NEXT:b L..BB0_6
+; CHECK-AIX-NEXT:  L..BB0_6: # %return
+; CHECK-AIX-NEXT:lwa 3, -12(1)
+; CHECK-AIX-NEXT:blr
+entry:
+  %retval = alloca i32, align 4
+  %x = alloca i64, align 8
+  %x64 = alloca i64, align 8
+  %andval = alloca i64, align 8
+  %k = alloca i32, align 4
+  store i32 0, i32* %retval, align 4
+  store i64 -1, i64* %x64, align 8
+  store i64 0, i64* %andval, align 8
+  br label %do.body
+
+do.body:  ; preds = %do.cond, %entry
+  %0 = call i64 asm sideeffect "ldarx $0, ${1:y}", "=r,*Z,~{memory}"(i64* %x64)
+  store i64 %0, i64* %x, align 8
+  %1 = bitcast i64* %x64 to i8*
+  %2 = load i64, i64* %x, align 8
+  %3 = load i64, i64* %andval, align 8
+  %and = and i64 %2, %3
+  %4 = call i32 @llvm.ppc.stdcx(i8* %1, i64 %and)
+  store i32 %4, i32* %k, align 4
+  br label %do.cond
+
+do.cond:  ; preds = %do.body
+  %5 = load i32, i32* %k, align 4
+  %tobool = icmp ne i32 %5, 0
+  %lnot = xor i1 %tobool, true
+  br i1 %lnot, label %do.body, label

[PATCH] D105754: [PowerPC] Fix L[D|W]ARX Implementation

2021-07-13 Thread Albion Fung via Phabricator via cfe-commits

Conanap updated this revision to Diff 358032.
Conanap added a comment.

Updated lwarx test case with modifier


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D105754/new/

https://reviews.llvm.org/D105754

Files:
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond-64bit-only.c
  clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond.c
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/Target/PowerPC/PPCInstr64Bit.td
  llvm/lib/Target/PowerPC/PPCInstrInfo.td
  
llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-LoadReserve-StoreCond-64bit-only.ll
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-LoadReserve-StoreCond.ll

Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-LoadReserve-StoreCond.ll
===
--- llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-LoadReserve-StoreCond.ll
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-LoadReserve-StoreCond.ll
@@ -12,18 +12,21 @@
 define dso_local signext i32 @test_lwarx(i32* readnone %a) {
 ; CHECK-64-LABEL: test_lwarx:
 ; CHECK-64:   # %bb.0: # %entry
+; CHECK-64-NEXT:#APP
 ; CHECK-64-NEXT:lwarx 3, 0, 3
+; CHECK-64-NEXT:#NO_APP
 ; CHECK-64-NEXT:extsw 3, 3
 ; CHECK-64-NEXT:blr
 ;
 ; CHECK-32-LABEL: test_lwarx:
 ; CHECK-32:   # %bb.0: # %entry
+; CHECK-32-NEXT:#APP
 ; CHECK-32-NEXT:lwarx 3, 0, 3
+; CHECK-32-NEXT:#NO_APP
 ; CHECK-32-NEXT:blr
 entry:
-  %0 = bitcast i32* %a to i8*
-  %1 = tail call i32 @llvm.ppc.lwarx(i8* %0)
-  ret i32 %1
+  %0 = call i32 asm sideeffect "lwarx $0, ${1:y}", "=r,*Z,~{memory}"(i32* %a)
+  ret i32 %0
 }
 
 declare i32 @llvm.ppc.stwcx(i8*, i32)
Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-LoadReserve-StoreCond-64bit-only.ll
===
--- llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-LoadReserve-StoreCond-64bit-only.ll
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-LoadReserve-StoreCond-64bit-only.ll
@@ -10,17 +10,18 @@
 define dso_local i64 @test_ldarx(i64* readnone %a) {
 ; CHECK-LABEL: test_ldarx:
 ; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:#APP
 ; CHECK-NEXT:ldarx 3, 0, 3
+; CHECK-NEXT:#NO_APP
 ; CHECK-NEXT:blr
 entry:
-  %0 = bitcast i64* %a to i8*
-  %1 = tail call i64 @llvm.ppc.ldarx(i8* %0)
-  ret i64 %1
+  %0 = call i64 asm sideeffect "ldarx $0, ${1:y}", "=r,*Z,~{memory}"(i64* %a)
+  ret i64 %0
 }
 
 declare i32 @llvm.ppc.stdcx(i8*, i64)
-define dso_local i64 @test(i64* %a, i64 %b) {
-; CHECK-LABEL: test:
+define dso_local i64 @test_stdcx(i64* %a, i64 %b) {
+; CHECK-LABEL: test_stdcx:
 ; CHECK:   # %bb.0: # %entry
 ; CHECK-NEXT:stdcx. 4, 0, 3
 ; CHECK-NEXT:mfocrf 3, 128
Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td
===
--- llvm/lib/Target/PowerPC/PPCInstrInfo.td
+++ llvm/lib/Target/PowerPC/PPCInstrInfo.td
@@ -5412,7 +5412,5 @@
 def : Pat<(i64 (bitreverse i64:$A)),
   (OR8 (RLDICR DWBytes7654.DWord, 32, 31), DWBytes3210.DWord)>;
 
-def : Pat<(int_ppc_lwarx ForceXForm:$dst),
-  (LWARX ForceXForm:$dst)>;
 def : Pat<(int_ppc_stwcx ForceXForm:$dst, gprc:$A),
   (STWCX gprc:$A, ForceXForm:$dst)>;
Index: llvm/lib/Target/PowerPC/PPCInstr64Bit.td
===
--- llvm/lib/Target/PowerPC/PPCInstr64Bit.td
+++ llvm/lib/Target/PowerPC/PPCInstr64Bit.td
@@ -1723,5 +1723,3 @@
 
 def : Pat<(int_ppc_stdcx ForceXForm:$dst, g8rc:$A),
   (STDCX g8rc:$A, ForceXForm:$dst)>;
-def : Pat<(int_ppc_ldarx ForceXForm:$dst),
-  (LDARX ForceXForm:$dst)>;
Index: llvm/include/llvm/IR/IntrinsicsPowerPC.td
===
--- llvm/include/llvm/IR/IntrinsicsPowerPC.td
+++ llvm/include/llvm/IR/IntrinsicsPowerPC.td
@@ -1529,9 +1529,5 @@
   def int_ppc_stwcx : GCCBuiltin<"__builtin_ppc_stwcx">,
   Intrinsic<[llvm_i32_ty], [llvm_ptr_ty, llvm_i32_ty],
 [IntrWriteMem]>;
-  def int_ppc_lwarx : GCCBuiltin<"__builtin_ppc_lwarx">,
-  Intrinsic<[llvm_i32_ty], [llvm_ptr_ty], [IntrNoMem]>;
-  def int_ppc_ldarx : GCCBuiltin<"__builtin_ppc_ldarx">,
-  Intrinsic<[llvm_i64_ty], [llvm_ptr_ty], [IntrNoMem]>;
 }
 
Index: clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond.c
===
--- clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond.c
+++ clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond.c
@@ -1,22 +1,20 @@
-// RUN: %clang_cc1 -triple=powerpc-unknown-aix -emit-llvm %s -o - | \
+// RUN: %clang_cc1 -O2 -triple=powerpc-unknown-aix -emit-llvm %s -o - | \
 // RUN: FileCheck %s
-// RUN: %clang_cc1 -triple=powerpc64-unknown-aix -emit-llvm %s -o - | \
+// RUN: %clang_cc1 -O2

[PATCH] D105754: [PowerPC] Fix L[D|W]ARX Implementation

2021-07-13 Thread Albion Fung via Phabricator via cfe-commits

Conanap updated this revision to Diff 358028.
Conanap added a comment.

Updated a test case


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D105754/new/

https://reviews.llvm.org/D105754

Files:
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond-64bit-only.c
  clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond.c
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/Target/PowerPC/PPCInstr64Bit.td
  llvm/lib/Target/PowerPC/PPCInstrInfo.td
  
llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-LoadReserve-StoreCond-64bit-only.ll
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-LoadReserve-StoreCond.ll

Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-LoadReserve-StoreCond.ll
===
--- llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-LoadReserve-StoreCond.ll
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-LoadReserve-StoreCond.ll
@@ -12,18 +12,21 @@
 define dso_local signext i32 @test_lwarx(i32* readnone %a) {
 ; CHECK-64-LABEL: test_lwarx:
 ; CHECK-64:   # %bb.0: # %entry
+; CHECK-64-NEXT:#APP
 ; CHECK-64-NEXT:lwarx 3, 0, 3
+; CHECK-64-NEXT:#NO_APP
 ; CHECK-64-NEXT:extsw 3, 3
 ; CHECK-64-NEXT:blr
 ;
 ; CHECK-32-LABEL: test_lwarx:
 ; CHECK-32:   # %bb.0: # %entry
+; CHECK-32-NEXT:#APP
 ; CHECK-32-NEXT:lwarx 3, 0, 3
+; CHECK-32-NEXT:#NO_APP
 ; CHECK-32-NEXT:blr
 entry:
-  %0 = bitcast i32* %a to i8*
-  %1 = tail call i32 @llvm.ppc.lwarx(i8* %0)
-  ret i32 %1
+  %0 = call i32 asm sideeffect "lwarx $0, $1", "=r,*Z,~{memory}"(i32* %a)
+  ret i32 %0
 }
 
 declare i32 @llvm.ppc.stwcx(i8*, i32)
Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-LoadReserve-StoreCond-64bit-only.ll
===
--- llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-LoadReserve-StoreCond-64bit-only.ll
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-LoadReserve-StoreCond-64bit-only.ll
@@ -10,17 +10,18 @@
 define dso_local i64 @test_ldarx(i64* readnone %a) {
 ; CHECK-LABEL: test_ldarx:
 ; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:#APP
 ; CHECK-NEXT:ldarx 3, 0, 3
+; CHECK-NEXT:#NO_APP
 ; CHECK-NEXT:blr
 entry:
-  %0 = bitcast i64* %a to i8*
-  %1 = tail call i64 @llvm.ppc.ldarx(i8* %0)
-  ret i64 %1
+  %0 = call i64 asm sideeffect "ldarx $0, ${1:y}", "=r,*Z,~{memory}"(i64* %a)
+  ret i64 %0
 }
 
 declare i32 @llvm.ppc.stdcx(i8*, i64)
-define dso_local i64 @test(i64* %a, i64 %b) {
-; CHECK-LABEL: test:
+define dso_local i64 @test_stdcx(i64* %a, i64 %b) {
+; CHECK-LABEL: test_stdcx:
 ; CHECK:   # %bb.0: # %entry
 ; CHECK-NEXT:stdcx. 4, 0, 3
 ; CHECK-NEXT:mfocrf 3, 128
Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td
===
--- llvm/lib/Target/PowerPC/PPCInstrInfo.td
+++ llvm/lib/Target/PowerPC/PPCInstrInfo.td
@@ -5412,7 +5412,5 @@
 def : Pat<(i64 (bitreverse i64:$A)),
   (OR8 (RLDICR DWBytes7654.DWord, 32, 31), DWBytes3210.DWord)>;
 
-def : Pat<(int_ppc_lwarx ForceXForm:$dst),
-  (LWARX ForceXForm:$dst)>;
 def : Pat<(int_ppc_stwcx ForceXForm:$dst, gprc:$A),
   (STWCX gprc:$A, ForceXForm:$dst)>;
Index: llvm/lib/Target/PowerPC/PPCInstr64Bit.td
===
--- llvm/lib/Target/PowerPC/PPCInstr64Bit.td
+++ llvm/lib/Target/PowerPC/PPCInstr64Bit.td
@@ -1723,5 +1723,3 @@
 
 def : Pat<(int_ppc_stdcx ForceXForm:$dst, g8rc:$A),
   (STDCX g8rc:$A, ForceXForm:$dst)>;
-def : Pat<(int_ppc_ldarx ForceXForm:$dst),
-  (LDARX ForceXForm:$dst)>;
Index: llvm/include/llvm/IR/IntrinsicsPowerPC.td
===
--- llvm/include/llvm/IR/IntrinsicsPowerPC.td
+++ llvm/include/llvm/IR/IntrinsicsPowerPC.td
@@ -1529,9 +1529,5 @@
   def int_ppc_stwcx : GCCBuiltin<"__builtin_ppc_stwcx">,
   Intrinsic<[llvm_i32_ty], [llvm_ptr_ty, llvm_i32_ty],
 [IntrWriteMem]>;
-  def int_ppc_lwarx : GCCBuiltin<"__builtin_ppc_lwarx">,
-  Intrinsic<[llvm_i32_ty], [llvm_ptr_ty], [IntrNoMem]>;
-  def int_ppc_ldarx : GCCBuiltin<"__builtin_ppc_ldarx">,
-  Intrinsic<[llvm_i64_ty], [llvm_ptr_ty], [IntrNoMem]>;
 }
 
Index: clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond.c
===
--- clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond.c
+++ clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond.c
@@ -1,22 +1,20 @@
-// RUN: %clang_cc1 -triple=powerpc-unknown-aix -emit-llvm %s -o - | \
+// RUN: %clang_cc1 -O2 -triple=powerpc-unknown-aix -emit-llvm %s -o - | \
 // RUN: FileCheck %s
-// RUN: %clang_cc1 -triple=powerpc64-unknown-aix -emit-llvm %s -o - | \
+// RUN: %clang_cc1 -O2 -triple=powerpc64-unknown-aix -emit-llvm %s

[PATCH] D105754: [PowerPC] Fix L[D|W]ARX Implementation

2021-07-13 Thread Albion Fung via Phabricator via cfe-commits

Conanap added inline comments.



Comment at: 
llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-LoadReserve-StoreCond-64bit-only.ll:18
 entry:
-  %0 = bitcast i64* %a to i8*
-  %1 = tail call i64 @llvm.ppc.ldarx(i8* %0)
-  ret i64 %1
+  %0 = call i64 asm sideeffect "ldarx $0, $1", "=r,*Z,~{memory}"(i64* %a)
+  ret i64 %0

nemanjai wrote:
> Conanap wrote:
> > nemanjai wrote:
> > > This is not the asm that the front end generates. Why would you generate 
> > > one thing in the front end and then test a different thing in the back 
> > > end?
> > I'm not quite sure what you mean by this; the IR output is taken from the 
> > `.c` test case above.
> I don't think that is the case.
> Above:
> `call i64 asm sideeffect "ldarx $0, ${1:y}", "=r,*Z,~{memory}"(i64* %a)`
> Here: 
> `call i64 asm sideeffect "ldarx $0, $1", "=r,*Z,~{memory}"(i64* %a)`
ah I see I missed the modifier.


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[PATCH] D105754: [PowerPC] Fix L[D|W]ARX Implementation

2021-07-13 Thread Albion Fung via Phabricator via cfe-commits

Conanap added inline comments.



Comment at: 
llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-LoadReserve-StoreCond-64bit-only.ll:18
 entry:
-  %0 = bitcast i64* %a to i8*
-  %1 = tail call i64 @llvm.ppc.ldarx(i8* %0)
-  ret i64 %1
+  %0 = call i64 asm sideeffect "ldarx $0, $1", "=r,*Z,~{memory}"(i64* %a)
+  ret i64 %0

nemanjai wrote:
> This is not the asm that the front end generates. Why would you generate one 
> thing in the front end and then test a different thing in the back end?
I'm not quite sure what you mean by this; the IR output is taken from the `.c` 
test case above.


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[PATCH] D103668: [PowerPC] Implement trap and conversion builtins for XL compatibility

2021-07-12 Thread Albion Fung via Phabricator via cfe-commits

This revision was automatically updated to reflect the committed changes.
Closed by commit rGef49d925e2a7: [PowerPC] Implement trap and conversion 
builtins for XL compatibility (authored by Conanap).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
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Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/lib/Basic/Targets/PPC.cpp
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/builtins-ppc-xlcompat-conversionfunc.c
  clang/test/CodeGen/builtins-ppc-xlcompat-error.c
  clang/test/CodeGen/builtins-ppc-xlcompat-trap-64bit-only.c
  clang/test/CodeGen/builtins-ppc-xlcompat-trap.c
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/Target/PowerPC/PPCInstr64Bit.td
  llvm/lib/Target/PowerPC/PPCInstrInfo.td
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-conversionfunc.ll
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap-64bit-only.ll
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap.ll

Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap.ll
@@ -0,0 +1,139 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN:   -mcpu=pwr7 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
+; RUN:   -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN:   -mcpu=pwr8 < %s | FileCheck %s
+
+; tw
+declare void @llvm.ppc.tw(i32 %a, i32 %b, i32 %c)
+define dso_local void @test__twlgt(i32 %a, i32 %b) {
+; CHECK-LABEL: test__twlgt:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:twlgt 3, 4
+; CHECK-NEXT:blr
+  call void @llvm.ppc.tw(i32 %a, i32 %b, i32 1)
+  ret void
+}
+
+define dso_local void @test__twllt(i32 %a, i32 %b) {
+; CHECK-LABEL: test__twllt:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:twllt 3, 4
+; CHECK-NEXT:blr
+  call void @llvm.ppc.tw(i32 %a, i32 %b, i32 2)
+  ret void
+}
+
+define dso_local void @test__tw3(i32 %a, i32 %b) {
+; CHECK-LABEL: test__tw3:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:tw 3, 3, 4
+; CHECK-NEXT:blr
+  call void @llvm.ppc.tw(i32 %a, i32 %b, i32 3)
+  ret void
+}
+
+define dso_local void @test__tweq(i32 %a, i32 %b) {
+; CHECK-LABEL: test__tweq:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:tweq 3, 4
+; CHECK-NEXT:blr
+  call void @llvm.ppc.tw(i32 %a, i32 %b, i32 4)
+  ret void
+}
+
+define dso_local void @test__twlge(i32 %a, i32 %b) {
+; CHECK-LABEL: test__twlge:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:tw 5, 3, 4
+; CHECK-NEXT:blr
+  call void @llvm.ppc.tw(i32 %a, i32 %b, i32 5)
+  ret void
+}
+
+define dso_local void @test__twlle(i32 %a, i32 %b) {
+; CHECK-LABEL: test__twlle:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:tw 6, 3, 4
+; CHECK-NEXT:blr
+  call void @llvm.ppc.tw(i32 %a, i32 %b, i32 6)
+  ret void
+}
+
+define dso_local void @test__twgt(i32 %a, i32 %b) {
+; CHECK-LABEL: test__twgt:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:twgt 3, 4
+; CHECK-NEXT:blr
+  call void @llvm.ppc.tw(i32 %a, i32 %b, i32 8)
+  ret void
+}
+
+define dso_local void @test__twge(i32 %a, i32 %b) {
+; CHECK-LABEL: test__twge:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:tw 12, 3, 4
+; CHECK-NEXT:blr
+  call void @llvm.ppc.tw(i32 %a, i32 %b, i32 12)
+  ret void
+}
+
+define dso_local void @test__twlt(i32 %a, i32 %b) {
+; CHECK-LABEL: test__twlt:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:twlt 3, 4
+; CHECK-NEXT:blr
+  call void @llvm.ppc.tw(i32 %a, i32 %b, i32 16)
+  ret void
+}
+
+define dso_local void @test__twle(i32 %a, i32 %b) {
+; CHECK-LABEL: test__twle:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:tw 20, 3, 4
+; CHECK-NEXT:blr
+  call void @llvm.ppc.tw(i32 %a, i32 %b, i32 20)
+  ret void
+}
+
+define dso_local void @test__twne24(i32 %a, i32 %b) {
+; CHECK-LABEL: test__twne24:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:twne 3, 4
+; CHECK-NEXT:blr
+  call void @llvm.ppc.tw(i32 %a, i32 %b, i32 24)
+  ret void
+}
+
+define dso_local void @test__twu(i32 %a, i32 %b) {
+; CHECK-LABEL: test__twu:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:twu 3, 4
+; CHECK-NEXT:blr
+  call void @llvm.ppc.tw(i32 %a, i32 %b, i32 31)
+  ret void
+}
+
+define dso_local void @test__tw_no_match(i32 %a, i32 %b) {
+; CHECK-LABEL: test__tw_no_match:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:tw 13, 3, 4
+; CHECK-NEXT:blr
+  call void @llvm.ppc.tw(i32 %a, i32 %b, i32 13)
+  ret void
+}
+
+; trap
+declare void @llvm.ppc.trap(i32 %a)
+define dso_local void @test__trap(i32 %a) {
+; CHECK-LABEL: test__trap:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:twnei 3, 0
+; CHECK-NEXT:blr
+  call void @llvm.ppc.trap(i32 %a)
+  ret void
+}
Index:

[PATCH] D105754: [PowerPC] Fix L[D|W]ARX Implementation

2021-07-12 Thread Albion Fung via Phabricator via cfe-commits

Conanap updated this revision to Diff 357833.
Conanap added a comment.

Removed unintended change


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D105754/new/

https://reviews.llvm.org/D105754

Files:
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond-64bit-only.c
  clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond.c
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/Target/PowerPC/PPCInstr64Bit.td
  llvm/lib/Target/PowerPC/PPCInstrInfo.td
  
llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-LoadReserve-StoreCond-64bit-only.ll
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-LoadReserve-StoreCond.ll

Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-LoadReserve-StoreCond.ll
===
--- llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-LoadReserve-StoreCond.ll
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-LoadReserve-StoreCond.ll
@@ -12,18 +12,21 @@
 define dso_local signext i32 @test_lwarx(i32* readnone %a) {
 ; CHECK-64-LABEL: test_lwarx:
 ; CHECK-64:   # %bb.0: # %entry
+; CHECK-64-NEXT:#APP
 ; CHECK-64-NEXT:lwarx 3, 0, 3
+; CHECK-64-NEXT:#NO_APP
 ; CHECK-64-NEXT:extsw 3, 3
 ; CHECK-64-NEXT:blr
 ;
 ; CHECK-32-LABEL: test_lwarx:
 ; CHECK-32:   # %bb.0: # %entry
+; CHECK-32-NEXT:#APP
 ; CHECK-32-NEXT:lwarx 3, 0, 3
+; CHECK-32-NEXT:#NO_APP
 ; CHECK-32-NEXT:blr
 entry:
-  %0 = bitcast i32* %a to i8*
-  %1 = tail call i32 @llvm.ppc.lwarx(i8* %0)
-  ret i32 %1
+  %0 = call i32 asm sideeffect "lwarx $0, $1", "=r,*Z,~{memory}"(i32* %a)
+  ret i32 %0
 }
 
 declare i32 @llvm.ppc.stwcx(i8*, i32)
Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-LoadReserve-StoreCond-64bit-only.ll
===
--- llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-LoadReserve-StoreCond-64bit-only.ll
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-LoadReserve-StoreCond-64bit-only.ll
@@ -10,17 +10,18 @@
 define dso_local i64 @test_ldarx(i64* readnone %a) {
 ; CHECK-LABEL: test_ldarx:
 ; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:#APP
 ; CHECK-NEXT:ldarx 3, 0, 3
+; CHECK-NEXT:#NO_APP
 ; CHECK-NEXT:blr
 entry:
-  %0 = bitcast i64* %a to i8*
-  %1 = tail call i64 @llvm.ppc.ldarx(i8* %0)
-  ret i64 %1
+  %0 = call i64 asm sideeffect "ldarx $0, $1", "=r,*Z,~{memory}"(i64* %a)
+  ret i64 %0
 }
 
 declare i32 @llvm.ppc.stdcx(i8*, i64)
-define dso_local i64 @test(i64* %a, i64 %b) {
-; CHECK-LABEL: test:
+define dso_local i64 @test_stdcx(i64* %a, i64 %b) {
+; CHECK-LABEL: test_stdcx:
 ; CHECK:   # %bb.0: # %entry
 ; CHECK-NEXT:stdcx. 4, 0, 3
 ; CHECK-NEXT:mfocrf 3, 128
Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td
===
--- llvm/lib/Target/PowerPC/PPCInstrInfo.td
+++ llvm/lib/Target/PowerPC/PPCInstrInfo.td
@@ -5412,7 +5412,5 @@
 def : Pat<(i64 (bitreverse i64:$A)),
   (OR8 (RLDICR DWBytes7654.DWord, 32, 31), DWBytes3210.DWord)>;
 
-def : Pat<(int_ppc_lwarx ForceXForm:$dst),
-  (LWARX ForceXForm:$dst)>;
 def : Pat<(int_ppc_stwcx ForceXForm:$dst, gprc:$A),
   (STWCX gprc:$A, ForceXForm:$dst)>;
Index: llvm/lib/Target/PowerPC/PPCInstr64Bit.td
===
--- llvm/lib/Target/PowerPC/PPCInstr64Bit.td
+++ llvm/lib/Target/PowerPC/PPCInstr64Bit.td
@@ -1723,5 +1723,3 @@
 
 def : Pat<(int_ppc_stdcx ForceXForm:$dst, g8rc:$A),
   (STDCX g8rc:$A, ForceXForm:$dst)>;
-def : Pat<(int_ppc_ldarx ForceXForm:$dst),
-  (LDARX ForceXForm:$dst)>;
Index: llvm/include/llvm/IR/IntrinsicsPowerPC.td
===
--- llvm/include/llvm/IR/IntrinsicsPowerPC.td
+++ llvm/include/llvm/IR/IntrinsicsPowerPC.td
@@ -1529,9 +1529,5 @@
   def int_ppc_stwcx : GCCBuiltin<"__builtin_ppc_stwcx">,
   Intrinsic<[llvm_i32_ty], [llvm_ptr_ty, llvm_i32_ty],
 [IntrWriteMem]>;
-  def int_ppc_lwarx : GCCBuiltin<"__builtin_ppc_lwarx">,
-  Intrinsic<[llvm_i32_ty], [llvm_ptr_ty], [IntrNoMem]>;
-  def int_ppc_ldarx : GCCBuiltin<"__builtin_ppc_ldarx">,
-  Intrinsic<[llvm_i64_ty], [llvm_ptr_ty], [IntrNoMem]>;
 }
 
Index: clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond.c
===
--- clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond.c
+++ clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond.c
@@ -1,22 +1,20 @@
-// RUN: %clang_cc1 -triple=powerpc-unknown-aix -emit-llvm %s -o - | \
+// RUN: %clang_cc1 -O2 -triple=powerpc-unknown-aix -emit-llvm %s -o - | \
 // RUN: FileCheck %s
-// RUN: %clang_cc1 -triple=powerpc64-unknown-aix -emit-llvm %s -o - | \
+// RUN: %clang_cc1 -O2 -triple=powerpc64-unknown-aix -emit-llvm

[PATCH] D105754: [PowerPC] Fix L[D|W]ARX Implementation

2021-07-12 Thread Albion Fung via Phabricator via cfe-commits

Conanap updated this revision to Diff 357832.
Conanap marked 6 inline comments as done.
Conanap added a comment.
Herald added subscribers: frasercrmck, luismarques, apazos, sameer.abuasal, 
s.egerton, Jim, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, 
edward-jones, zzheng, MaskRay, jrtc27, niosHD, sabuasal, simoncook, johnrusso, 
rbar, asb.

Moved implementation to a more appropriate function,
updated test cases.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D105754/new/

https://reviews.llvm.org/D105754

Files:
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vadd.c
  clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond-64bit-only.c
  clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond.c
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/Target/PowerPC/PPCInstr64Bit.td
  llvm/lib/Target/PowerPC/PPCInstrInfo.td
  
llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-LoadReserve-StoreCond-64bit-only.ll
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-LoadReserve-StoreCond.ll

Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-LoadReserve-StoreCond.ll
===
--- llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-LoadReserve-StoreCond.ll
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-LoadReserve-StoreCond.ll
@@ -12,18 +12,21 @@
 define dso_local signext i32 @test_lwarx(i32* readnone %a) {
 ; CHECK-64-LABEL: test_lwarx:
 ; CHECK-64:   # %bb.0: # %entry
+; CHECK-64-NEXT:#APP
 ; CHECK-64-NEXT:lwarx 3, 0, 3
+; CHECK-64-NEXT:#NO_APP
 ; CHECK-64-NEXT:extsw 3, 3
 ; CHECK-64-NEXT:blr
 ;
 ; CHECK-32-LABEL: test_lwarx:
 ; CHECK-32:   # %bb.0: # %entry
+; CHECK-32-NEXT:#APP
 ; CHECK-32-NEXT:lwarx 3, 0, 3
+; CHECK-32-NEXT:#NO_APP
 ; CHECK-32-NEXT:blr
 entry:
-  %0 = bitcast i32* %a to i8*
-  %1 = tail call i32 @llvm.ppc.lwarx(i8* %0)
-  ret i32 %1
+  %0 = call i32 asm sideeffect "lwarx $0, $1", "=r,*Z,~{memory}"(i32* %a)
+  ret i32 %0
 }
 
 declare i32 @llvm.ppc.stwcx(i8*, i32)
Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-LoadReserve-StoreCond-64bit-only.ll
===
--- llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-LoadReserve-StoreCond-64bit-only.ll
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-LoadReserve-StoreCond-64bit-only.ll
@@ -10,17 +10,18 @@
 define dso_local i64 @test_ldarx(i64* readnone %a) {
 ; CHECK-LABEL: test_ldarx:
 ; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:#APP
 ; CHECK-NEXT:ldarx 3, 0, 3
+; CHECK-NEXT:#NO_APP
 ; CHECK-NEXT:blr
 entry:
-  %0 = bitcast i64* %a to i8*
-  %1 = tail call i64 @llvm.ppc.ldarx(i8* %0)
-  ret i64 %1
+  %0 = call i64 asm sideeffect "ldarx $0, $1", "=r,*Z,~{memory}"(i64* %a)
+  ret i64 %0
 }
 
 declare i32 @llvm.ppc.stdcx(i8*, i64)
-define dso_local i64 @test(i64* %a, i64 %b) {
-; CHECK-LABEL: test:
+define dso_local i64 @test_stdcx(i64* %a, i64 %b) {
+; CHECK-LABEL: test_stdcx:
 ; CHECK:   # %bb.0: # %entry
 ; CHECK-NEXT:stdcx. 4, 0, 3
 ; CHECK-NEXT:mfocrf 3, 128
Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td
===
--- llvm/lib/Target/PowerPC/PPCInstrInfo.td
+++ llvm/lib/Target/PowerPC/PPCInstrInfo.td
@@ -5412,7 +5412,5 @@
 def : Pat<(i64 (bitreverse i64:$A)),
   (OR8 (RLDICR DWBytes7654.DWord, 32, 31), DWBytes3210.DWord)>;
 
-def : Pat<(int_ppc_lwarx ForceXForm:$dst),
-  (LWARX ForceXForm:$dst)>;
 def : Pat<(int_ppc_stwcx ForceXForm:$dst, gprc:$A),
   (STWCX gprc:$A, ForceXForm:$dst)>;
Index: llvm/lib/Target/PowerPC/PPCInstr64Bit.td
===
--- llvm/lib/Target/PowerPC/PPCInstr64Bit.td
+++ llvm/lib/Target/PowerPC/PPCInstr64Bit.td
@@ -1723,5 +1723,3 @@
 
 def : Pat<(int_ppc_stdcx ForceXForm:$dst, g8rc:$A),
   (STDCX g8rc:$A, ForceXForm:$dst)>;
-def : Pat<(int_ppc_ldarx ForceXForm:$dst),
-  (LDARX ForceXForm:$dst)>;
Index: llvm/include/llvm/IR/IntrinsicsPowerPC.td
===
--- llvm/include/llvm/IR/IntrinsicsPowerPC.td
+++ llvm/include/llvm/IR/IntrinsicsPowerPC.td
@@ -1529,9 +1529,5 @@
   def int_ppc_stwcx : GCCBuiltin<"__builtin_ppc_stwcx">,
   Intrinsic<[llvm_i32_ty], [llvm_ptr_ty, llvm_i32_ty],
 [IntrWriteMem]>;
-  def int_ppc_lwarx : GCCBuiltin<"__builtin_ppc_lwarx">,
-  Intrinsic<[llvm_i32_ty], [llvm_ptr_ty], [IntrNoMem]>;
-  def int_ppc_ldarx : GCCBuiltin<"__builtin_ppc_ldarx">,
-  Intrinsic<[llvm_i64_ty], [llvm_ptr_ty], [IntrNoMem]>;
 }
 
Index: clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond.c
===
--- clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond.c

[PATCH] D105754: [PowerPC] Fix L[D|W]ARX Implementation

2021-07-10 Thread Albion Fung via Phabricator via cfe-commits

Conanap added a comment.

looking at the failing test cases, for example 
`./clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vadd.c`, which are not 
test cases compiled for `PPC`, I'm seeing this following error:

  clang: /home/conanap/llvm/ccom/llvm-project/llvm/lib/IR/Instructions.cpp:494: 
void llvm::CallInst::init(llvm::FunctionType *, llvm::Value *, 
ArrayRef, ArrayRef, const llvm::Twine 
&): Assertion `(i >= FTy->getNumParams() || FTy->getParamType(i) == 
Args[i]->getType()) && "Calling a function with a bad signature!"' failed.

Debug prints show that it's entering the code block `emitLoadReserveIntrinsic` 
and `BuiltinID` evaluates to `clang::PPC::BI__builtin_ppc_lwarx`. The `FTy` 
dump shows `i32 (i32 *)`, which is correct... I'm not exactly sure what to make 
of this yet, just putting this update here.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D105754/new/

https://reviews.llvm.org/D105754

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[PATCH] D105754: [PowerPC] Fix L[D|W]ARX Implementation

2021-07-09 Thread Albion Fung via Phabricator via cfe-commits

Conanap updated this revision to Diff 357684.
Conanap added a comment.

Fixed more test cases


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D105754/new/

https://reviews.llvm.org/D105754

Files:
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond-64bit-only.c
  clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond.c
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/Target/PowerPC/PPCInstr64Bit.td
  llvm/lib/Target/PowerPC/PPCInstrInfo.td
  
llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-LoadReserve-StoreCond-64bit-only.ll
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-LoadReserve-StoreCond.ll

Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-LoadReserve-StoreCond.ll
===
--- llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-LoadReserve-StoreCond.ll
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-LoadReserve-StoreCond.ll
@@ -12,18 +12,21 @@
 define dso_local signext i32 @test_lwarx(i32* readnone %a) {
 ; CHECK-64-LABEL: test_lwarx:
 ; CHECK-64:   # %bb.0: # %entry
+; CHECK-64-NEXT:#APP
 ; CHECK-64-NEXT:lwarx 3, 0, 3
+; CHECK-64-NEXT:#NO_APP
 ; CHECK-64-NEXT:extsw 3, 3
 ; CHECK-64-NEXT:blr
 ;
 ; CHECK-32-LABEL: test_lwarx:
 ; CHECK-32:   # %bb.0: # %entry
+; CHECK-32-NEXT:#APP
 ; CHECK-32-NEXT:lwarx 3, 0, 3
+; CHECK-32-NEXT:#NO_APP
 ; CHECK-32-NEXT:blr
 entry:
-  %0 = bitcast i32* %a to i8*
-  %1 = tail call i32 @llvm.ppc.lwarx(i8* %0)
-  ret i32 %1
+  %0 = call i32 asm sideeffect "lwarx $0, $1", "=r,*Z,~{memory}"(i32* %a)
+  ret i32 %0
 }
 
 declare i32 @llvm.ppc.stwcx(i8*, i32)
Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-LoadReserve-StoreCond-64bit-only.ll
===
--- llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-LoadReserve-StoreCond-64bit-only.ll
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-LoadReserve-StoreCond-64bit-only.ll
@@ -10,17 +10,18 @@
 define dso_local i64 @test_ldarx(i64* readnone %a) {
 ; CHECK-LABEL: test_ldarx:
 ; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:#APP
 ; CHECK-NEXT:ldarx 3, 0, 3
+; CHECK-NEXT:#NO_APP
 ; CHECK-NEXT:blr
 entry:
-  %0 = bitcast i64* %a to i8*
-  %1 = tail call i64 @llvm.ppc.ldarx(i8* %0)
-  ret i64 %1
+  %0 = call i64 asm sideeffect "ldarx $0, $1", "=r,*Z,~{memory}"(i64* %a)
+  ret i64 %0
 }
 
 declare i32 @llvm.ppc.stdcx(i8*, i64)
-define dso_local i64 @test(i64* %a, i64 %b) {
-; CHECK-LABEL: test:
+define dso_local i64 @test_stdcx(i64* %a, i64 %b) {
+; CHECK-LABEL: test_stdcx:
 ; CHECK:   # %bb.0: # %entry
 ; CHECK-NEXT:stdcx. 4, 0, 3
 ; CHECK-NEXT:mfocrf 3, 128
Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td
===
--- llvm/lib/Target/PowerPC/PPCInstrInfo.td
+++ llvm/lib/Target/PowerPC/PPCInstrInfo.td
@@ -5412,7 +5412,5 @@
 def : Pat<(i64 (bitreverse i64:$A)),
   (OR8 (RLDICR DWBytes7654.DWord, 32, 31), DWBytes3210.DWord)>;
 
-def : Pat<(int_ppc_lwarx ForceXForm:$dst),
-  (LWARX ForceXForm:$dst)>;
 def : Pat<(int_ppc_stwcx ForceXForm:$dst, gprc:$A),
   (STWCX gprc:$A, ForceXForm:$dst)>;
Index: llvm/lib/Target/PowerPC/PPCInstr64Bit.td
===
--- llvm/lib/Target/PowerPC/PPCInstr64Bit.td
+++ llvm/lib/Target/PowerPC/PPCInstr64Bit.td
@@ -1723,5 +1723,3 @@
 
 def : Pat<(int_ppc_stdcx ForceXForm:$dst, g8rc:$A),
   (STDCX g8rc:$A, ForceXForm:$dst)>;
-def : Pat<(int_ppc_ldarx ForceXForm:$dst),
-  (LDARX ForceXForm:$dst)>;
Index: llvm/include/llvm/IR/IntrinsicsPowerPC.td
===
--- llvm/include/llvm/IR/IntrinsicsPowerPC.td
+++ llvm/include/llvm/IR/IntrinsicsPowerPC.td
@@ -1529,9 +1529,5 @@
   def int_ppc_stwcx : GCCBuiltin<"__builtin_ppc_stwcx">,
   Intrinsic<[llvm_i32_ty], [llvm_ptr_ty, llvm_i32_ty],
 [IntrWriteMem]>;
-  def int_ppc_lwarx : GCCBuiltin<"__builtin_ppc_lwarx">,
-  Intrinsic<[llvm_i32_ty], [llvm_ptr_ty], [IntrNoMem]>;
-  def int_ppc_ldarx : GCCBuiltin<"__builtin_ppc_ldarx">,
-  Intrinsic<[llvm_i64_ty], [llvm_ptr_ty], [IntrNoMem]>;
 }
 
Index: clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond.c
===
--- clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond.c
+++ clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond.c
@@ -9,8 +9,8 @@
 
 int test_lwarx(volatile int* a) {
   // CHECK: @test_lwarx
-  // CHECK: %1 = bitcast i32* %0 to i8*
-  // CHECK: %2 = call i32 @llvm.ppc.lwarx(i8* %1)
+  // CHECK: %0 = load i32*, i32** %a.addr, align
+  // CHECK: %1 = call i32 asm sideeffect "lwarx $0, ${1:y}", "=r,*Z,~{memory}"(i32* %0)
   return

[PATCH] D105754: [PowerPC] Fix L[D|W]ARX Implementation

2021-07-09 Thread Albion Fung via Phabricator via cfe-commits

Conanap updated this revision to Diff 357681.
Conanap added a comment.

Added modifier to $1


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D105754/new/

https://reviews.llvm.org/D105754

Files:
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond-64bit-only.c
  clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond.c
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/Target/PowerPC/PPCInstr64Bit.td
  llvm/lib/Target/PowerPC/PPCInstrInfo.td

Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td
===
--- llvm/lib/Target/PowerPC/PPCInstrInfo.td
+++ llvm/lib/Target/PowerPC/PPCInstrInfo.td
@@ -5412,7 +5412,5 @@
 def : Pat<(i64 (bitreverse i64:$A)),
   (OR8 (RLDICR DWBytes7654.DWord, 32, 31), DWBytes3210.DWord)>;
 
-def : Pat<(int_ppc_lwarx ForceXForm:$dst),
-  (LWARX ForceXForm:$dst)>;
 def : Pat<(int_ppc_stwcx ForceXForm:$dst, gprc:$A),
   (STWCX gprc:$A, ForceXForm:$dst)>;
Index: llvm/lib/Target/PowerPC/PPCInstr64Bit.td
===
--- llvm/lib/Target/PowerPC/PPCInstr64Bit.td
+++ llvm/lib/Target/PowerPC/PPCInstr64Bit.td
@@ -1723,5 +1723,3 @@
 
 def : Pat<(int_ppc_stdcx ForceXForm:$dst, g8rc:$A),
   (STDCX g8rc:$A, ForceXForm:$dst)>;
-def : Pat<(int_ppc_ldarx ForceXForm:$dst),
-  (LDARX ForceXForm:$dst)>;
Index: llvm/include/llvm/IR/IntrinsicsPowerPC.td
===
--- llvm/include/llvm/IR/IntrinsicsPowerPC.td
+++ llvm/include/llvm/IR/IntrinsicsPowerPC.td
@@ -1529,9 +1529,5 @@
   def int_ppc_stwcx : GCCBuiltin<"__builtin_ppc_stwcx">,
   Intrinsic<[llvm_i32_ty], [llvm_ptr_ty, llvm_i32_ty],
 [IntrWriteMem]>;
-  def int_ppc_lwarx : GCCBuiltin<"__builtin_ppc_lwarx">,
-  Intrinsic<[llvm_i32_ty], [llvm_ptr_ty], [IntrNoMem]>;
-  def int_ppc_ldarx : GCCBuiltin<"__builtin_ppc_ldarx">,
-  Intrinsic<[llvm_i64_ty], [llvm_ptr_ty], [IntrNoMem]>;
 }
 
Index: clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond.c
===
--- clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond.c
+++ clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond.c
@@ -9,8 +9,8 @@
 
 int test_lwarx(volatile int* a) {
   // CHECK: @test_lwarx
-  // CHECK: %1 = bitcast i32* %0 to i8*
-  // CHECK: %2 = call i32 @llvm.ppc.lwarx(i8* %1)
+  // CHECK: %0 = load i32*, i32** %a.addr, align
+  // CHECK: %1 = call i32 asm sideeffect "lwarx $0, $1", "=r,*Z,~{memory}"(i32* %0)
   return __lwarx(a);
 }
 int test_stwcx(volatile int* a, int val) {
Index: clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond-64bit-only.c
===
--- clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond-64bit-only.c
+++ clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond-64bit-only.c
@@ -10,8 +10,7 @@
 long test_ldarx(volatile long* a) {
   // CHECK64-LABEL: @test_ldarx
   // CHECK64: %0 = load i64*, i64** %a.addr, align 8
-  // CHECK64: %1 = bitcast i64* %0 to i8*
-  // CHECK64: %2 = call i64 @llvm.ppc.ldarx(i8* %1)
+  // CHECK64: %1 = call i64 asm sideeffect "ldarx $0, $1", "=r,*Z,~{memory}"(i64* %0)
   // CHECK32-ERROR: error: this builtin is only available on 64-bit targets
   return __ldarx(a);
 }
Index: clang/lib/CodeGen/CGBuiltin.cpp
===
--- clang/lib/CodeGen/CGBuiltin.cpp
+++ clang/lib/CodeGen/CGBuiltin.cpp
@@ -994,6 +994,44 @@
   ShiftedByte, llvm::ConstantInt::get(CGF.Int8Ty, 1), "bittest.res");
 }
 
+static llvm::Value *emitLoadReserveIntrinsic(CodeGenFunction ,
+ unsigned BuiltinID,
+ const CallExpr *E) {
+  Value *addr = CGF.EmitScalarExpr(E->getArg(0));
+
+  SmallString<64> Asm;
+  raw_svector_ostream AsmOS(Asm);
+  llvm::IntegerType *RetType = CGF.Int32Ty;
+
+  switch (BuiltinID) {
+  case clang::PPC::BI__builtin_ppc_ldarx:
+AsmOS << "ldarx ";
+RetType = CGF.Int64Ty;
+break;
+  case clang::PPC::BI__builtin_ppc_lwarx:
+AsmOS << "lwarx ";
+RetType = CGF.Int32Ty;
+break;
+  }
+
+  AsmOS << "$0, ${1:y}";
+
+  std::string Constraints = "=r,*Z,~{memory}";
+  std::string MachineClobbers = CGF.getTarget().getClobbers();
+  if (!MachineClobbers.empty()) {
+Constraints += ',';
+Constraints += MachineClobbers;
+  }
+
+  llvm::Type *IntPtrType = RetType->getPointerTo();
+  llvm::FunctionType *FTy =
+  llvm::FunctionType::get(RetType, {IntPtrType}, false);
+
+  llvm::InlineAsm *IA =
+  llvm::InlineAsm::get(FTy, Asm, Constraints, /*hasSideEffects=*/true);
+  return CGF.Builder.CreateCall(IA, {addr});
+}
+
 namespace {
 enum class

[PATCH] D105754: [PowerPC] Fix L[D|W]ARX Implementation

2021-07-09 Thread Albion Fung via Phabricator via cfe-commits

Conanap updated this revision to Diff 357680.
Conanap added a comment.

Update test cases


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D105754/new/

https://reviews.llvm.org/D105754

Files:
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond-64bit-only.c
  clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond.c
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/Target/PowerPC/PPCInstr64Bit.td
  llvm/lib/Target/PowerPC/PPCInstrInfo.td

Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td
===
--- llvm/lib/Target/PowerPC/PPCInstrInfo.td
+++ llvm/lib/Target/PowerPC/PPCInstrInfo.td
@@ -5412,7 +5412,5 @@
 def : Pat<(i64 (bitreverse i64:$A)),
   (OR8 (RLDICR DWBytes7654.DWord, 32, 31), DWBytes3210.DWord)>;
 
-def : Pat<(int_ppc_lwarx ForceXForm:$dst),
-  (LWARX ForceXForm:$dst)>;
 def : Pat<(int_ppc_stwcx ForceXForm:$dst, gprc:$A),
   (STWCX gprc:$A, ForceXForm:$dst)>;
Index: llvm/lib/Target/PowerPC/PPCInstr64Bit.td
===
--- llvm/lib/Target/PowerPC/PPCInstr64Bit.td
+++ llvm/lib/Target/PowerPC/PPCInstr64Bit.td
@@ -1723,5 +1723,3 @@
 
 def : Pat<(int_ppc_stdcx ForceXForm:$dst, g8rc:$A),
   (STDCX g8rc:$A, ForceXForm:$dst)>;
-def : Pat<(int_ppc_ldarx ForceXForm:$dst),
-  (LDARX ForceXForm:$dst)>;
Index: llvm/include/llvm/IR/IntrinsicsPowerPC.td
===
--- llvm/include/llvm/IR/IntrinsicsPowerPC.td
+++ llvm/include/llvm/IR/IntrinsicsPowerPC.td
@@ -1529,9 +1529,5 @@
   def int_ppc_stwcx : GCCBuiltin<"__builtin_ppc_stwcx">,
   Intrinsic<[llvm_i32_ty], [llvm_ptr_ty, llvm_i32_ty],
 [IntrWriteMem]>;
-  def int_ppc_lwarx : GCCBuiltin<"__builtin_ppc_lwarx">,
-  Intrinsic<[llvm_i32_ty], [llvm_ptr_ty], [IntrNoMem]>;
-  def int_ppc_ldarx : GCCBuiltin<"__builtin_ppc_ldarx">,
-  Intrinsic<[llvm_i64_ty], [llvm_ptr_ty], [IntrNoMem]>;
 }
 
Index: clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond.c
===
--- clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond.c
+++ clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond.c
@@ -9,8 +9,8 @@
 
 int test_lwarx(volatile int* a) {
   // CHECK: @test_lwarx
-  // CHECK: %1 = bitcast i32* %0 to i8*
-  // CHECK: %2 = call i32 @llvm.ppc.lwarx(i8* %1)
+  // CHECK: %0 = load i32*, i32** %a.addr, align
+  // CHECK: %1 = call i32 asm sideeffect "lwarx $0, $1", "=r,*Z,~{memory}"(i32* %0)
   return __lwarx(a);
 }
 int test_stwcx(volatile int* a, int val) {
Index: clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond-64bit-only.c
===
--- clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond-64bit-only.c
+++ clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond-64bit-only.c
@@ -10,8 +10,7 @@
 long test_ldarx(volatile long* a) {
   // CHECK64-LABEL: @test_ldarx
   // CHECK64: %0 = load i64*, i64** %a.addr, align 8
-  // CHECK64: %1 = bitcast i64* %0 to i8*
-  // CHECK64: %2 = call i64 @llvm.ppc.ldarx(i8* %1)
+  // CHECK64: %1 = call i64 asm sideeffect "ldarx $0, $1", "=r,*Z,~{memory}"(i64* %0)
   // CHECK32-ERROR: error: this builtin is only available on 64-bit targets
   return __ldarx(a);
 }
Index: clang/lib/CodeGen/CGBuiltin.cpp
===
--- clang/lib/CodeGen/CGBuiltin.cpp
+++ clang/lib/CodeGen/CGBuiltin.cpp
@@ -994,6 +994,44 @@
   ShiftedByte, llvm::ConstantInt::get(CGF.Int8Ty, 1), "bittest.res");
 }
 
+static llvm::Value *emitLoadReserveIntrinsic(CodeGenFunction ,
+ unsigned BuiltinID,
+ const CallExpr *E) {
+  Value *addr = CGF.EmitScalarExpr(E->getArg(0));
+
+  SmallString<64> Asm;
+  raw_svector_ostream AsmOS(Asm);
+  llvm::IntegerType *RetType = CGF.Int32Ty;
+
+  switch (BuiltinID) {
+  case clang::PPC::BI__builtin_ppc_ldarx:
+AsmOS << "ldarx ";
+RetType = CGF.Int64Ty;
+break;
+  case clang::PPC::BI__builtin_ppc_lwarx:
+AsmOS << "lwarx ";
+RetType = CGF.Int32Ty;
+break;
+  }
+
+  AsmOS << "$0, $1";
+
+  std::string Constraints = "=r,*Z,~{memory}";
+  std::string MachineClobbers = CGF.getTarget().getClobbers();
+  if (!MachineClobbers.empty()) {
+Constraints += ',';
+Constraints += MachineClobbers;
+  }
+
+  llvm::Type *IntPtrType = RetType->getPointerTo();
+  llvm::FunctionType *FTy =
+  llvm::FunctionType::get(RetType, {IntPtrType}, false);
+
+  llvm::InlineAsm *IA =
+  llvm::InlineAsm::get(FTy, Asm, Constraints, /*hasSideEffects=*/true);
+  return CGF.Builder.CreateCall(IA, {addr});
+}
+
 namespace {
 enum class

[PATCH] D105754: [PowerPC] Fix L[D|W]ARX Implementation

2021-07-09 Thread Albion Fung via Phabricator via cfe-commits

Conanap created this revision.
Herald added subscribers: shchenz, kbarton, hiraditya, nemanjai.
Conanap requested review of this revision.
Herald added projects: clang, LLVM.
Herald added subscribers: llvm-commits, cfe-commits.

LDARX and LWARX sometimes gets optimized out by the compiler
when it is critical to the correctness of the code. This inline asm generation
ensures that it preserved.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D105754

Files:
  clang/lib/CodeGen/CGBuiltin.cpp
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/Target/PowerPC/PPCInstr64Bit.td
  llvm/lib/Target/PowerPC/PPCInstrInfo.td


Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td
===
--- llvm/lib/Target/PowerPC/PPCInstrInfo.td
+++ llvm/lib/Target/PowerPC/PPCInstrInfo.td
@@ -5412,7 +5412,5 @@
 def : Pat<(i64 (bitreverse i64:$A)),
   (OR8 (RLDICR DWBytes7654.DWord, 32, 31), DWBytes3210.DWord)>;
 
-def : Pat<(int_ppc_lwarx ForceXForm:$dst),
-  (LWARX ForceXForm:$dst)>;
 def : Pat<(int_ppc_stwcx ForceXForm:$dst, gprc:$A),
   (STWCX gprc:$A, ForceXForm:$dst)>;
Index: llvm/lib/Target/PowerPC/PPCInstr64Bit.td
===
--- llvm/lib/Target/PowerPC/PPCInstr64Bit.td
+++ llvm/lib/Target/PowerPC/PPCInstr64Bit.td
@@ -1723,5 +1723,3 @@
 
 def : Pat<(int_ppc_stdcx ForceXForm:$dst, g8rc:$A),
   (STDCX g8rc:$A, ForceXForm:$dst)>;
-def : Pat<(int_ppc_ldarx ForceXForm:$dst),
-  (LDARX ForceXForm:$dst)>;
Index: llvm/include/llvm/IR/IntrinsicsPowerPC.td
===
--- llvm/include/llvm/IR/IntrinsicsPowerPC.td
+++ llvm/include/llvm/IR/IntrinsicsPowerPC.td
@@ -1529,9 +1529,5 @@
   def int_ppc_stwcx : GCCBuiltin<"__builtin_ppc_stwcx">,
   Intrinsic<[llvm_i32_ty], [llvm_ptr_ty, llvm_i32_ty],
 [IntrWriteMem]>;
-  def int_ppc_lwarx : GCCBuiltin<"__builtin_ppc_lwarx">,
-  Intrinsic<[llvm_i32_ty], [llvm_ptr_ty], [IntrNoMem]>;
-  def int_ppc_ldarx : GCCBuiltin<"__builtin_ppc_ldarx">,
-  Intrinsic<[llvm_i64_ty], [llvm_ptr_ty], [IntrNoMem]>;
 }
 
Index: clang/lib/CodeGen/CGBuiltin.cpp
===
--- clang/lib/CodeGen/CGBuiltin.cpp
+++ clang/lib/CodeGen/CGBuiltin.cpp
@@ -994,6 +994,44 @@
   ShiftedByte, llvm::ConstantInt::get(CGF.Int8Ty, 1), "bittest.res");
 }
 
+static llvm::Value *emitLoadReserveIntrinsic(CodeGenFunction ,
+ unsigned BuiltinID,
+ const CallExpr *E) {
+  Value *addr = CGF.EmitScalarExpr(E->getArg(0));
+
+  SmallString<64> Asm;
+  raw_svector_ostream AsmOS(Asm);
+  llvm::IntegerType *RetType = CGF.Int32Ty;
+
+  switch (BuiltinID) {
+  case clang::PPC::BI__builtin_ppc_ldarx:
+AsmOS << "ldarx ";
+RetType = CGF.Int64Ty;
+break;
+  case clang::PPC::BI__builtin_ppc_lwarx:
+AsmOS << "lwarx ";
+RetType = CGF.Int32Ty;
+break;
+  }
+
+  AsmOS << "$0, $1";
+
+  std::string Constraints = "=r,*Z,~{memory}";
+  std::string MachineClobbers = CGF.getTarget().getClobbers();
+  if (!MachineClobbers.empty()) {
+Constraints += ',';
+Constraints += MachineClobbers;
+  }
+
+  llvm::Type *IntPtrType = RetType->getPointerTo();
+  llvm::FunctionType *FTy =
+  llvm::FunctionType::get(RetType, {IntPtrType}, false);
+
+  llvm::InlineAsm *IA =
+  llvm::InlineAsm::get(FTy, Asm, Constraints, /*hasSideEffects=*/true);
+  return CGF.Builder.CreateCall(IA, {addr});
+}
+
 namespace {
 enum class MSVCSetJmpKind {
   _setjmpex,
@@ -5103,6 +5141,9 @@
  Str.getPointer(), Zeros);
 return RValue::get(Ptr);
   }
+  case clang::PPC::BI__builtin_ppc_ldarx:
+  case clang::PPC::BI__builtin_ppc_lwarx:
+return RValue::get(emitLoadReserveIntrinsic(*this, BuiltinID, E));
   }
 
   // If this is an alias for a lib function (e.g. __builtin_sin), emit


Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td
===
--- llvm/lib/Target/PowerPC/PPCInstrInfo.td
+++ llvm/lib/Target/PowerPC/PPCInstrInfo.td
@@ -5412,7 +5412,5 @@
 def : Pat<(i64 (bitreverse i64:$A)),
   (OR8 (RLDICR DWBytes7654.DWord, 32, 31), DWBytes3210.DWord)>;
 
-def : Pat<(int_ppc_lwarx ForceXForm:$dst),
-  (LWARX ForceXForm:$dst)>;
 def : Pat<(int_ppc_stwcx ForceXForm:$dst, gprc:$A),
   (STWCX gprc:$A, ForceXForm:$dst)>;
Index: llvm/lib/Target/PowerPC/PPCInstr64Bit.td
===
--- llvm/lib/Target/PowerPC/PPCInstr64Bit.td
+++ llvm/lib/Target/PowerPC/PPCInstr64Bit.td
@@ -1723,5 +1723,3 @@
 
 def : Pat<(int_ppc_stdcx ForceXForm:$dst, g8rc:$A),
   (STDCX g8rc:$A, ForceXForm:$dst)>;
-def : Pat<(int_ppc_ldarx ForceXForm:$dst),
-

[PATCH] D103668: [PowerPC] Implement trap and conversion builtins for XL compatibility

2021-07-08 Thread Albion Fung via Phabricator via cfe-commits

Conanap updated this revision to Diff 357334.
Conanap added a comment.

Removed TWNE pattern as well


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D103668/new/

https://reviews.llvm.org/D103668

Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/lib/Basic/Targets/PPC.cpp
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/builtins-ppc-xlcompat-conversionfunc.c
  clang/test/CodeGen/builtins-ppc-xlcompat-error.c
  clang/test/CodeGen/builtins-ppc-xlcompat-trap-64bit-only.c
  clang/test/CodeGen/builtins-ppc-xlcompat-trap.c
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/Target/PowerPC/PPCInstr64Bit.td
  llvm/lib/Target/PowerPC/PPCInstrInfo.td
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-conversionfunc.ll
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap-64bit-only.ll
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap.ll

Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap.ll
@@ -0,0 +1,139 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN:   -mcpu=pwr7 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
+; RUN:   -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN:   -mcpu=pwr8 < %s | FileCheck %s
+
+; tw
+declare void @llvm.ppc.tw(i32 %a, i32 %b, i32 %c)
+define dso_local void @test__twlgt(i32 %a, i32 %b) {
+; CHECK-LABEL: test__twlgt:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:twlgt 3, 4
+; CHECK-NEXT:blr
+  call void @llvm.ppc.tw(i32 %a, i32 %b, i32 1)
+  ret void
+}
+
+define dso_local void @test__twllt(i32 %a, i32 %b) {
+; CHECK-LABEL: test__twllt:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:twllt 3, 4
+; CHECK-NEXT:blr
+  call void @llvm.ppc.tw(i32 %a, i32 %b, i32 2)
+  ret void
+}
+
+define dso_local void @test__tw3(i32 %a, i32 %b) {
+; CHECK-LABEL: test__tw3:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:tw 3, 3, 4
+; CHECK-NEXT:blr
+  call void @llvm.ppc.tw(i32 %a, i32 %b, i32 3)
+  ret void
+}
+
+define dso_local void @test__tweq(i32 %a, i32 %b) {
+; CHECK-LABEL: test__tweq:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:tweq 3, 4
+; CHECK-NEXT:blr
+  call void @llvm.ppc.tw(i32 %a, i32 %b, i32 4)
+  ret void
+}
+
+define dso_local void @test__twlge(i32 %a, i32 %b) {
+; CHECK-LABEL: test__twlge:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:tw 5, 3, 4
+; CHECK-NEXT:blr
+  call void @llvm.ppc.tw(i32 %a, i32 %b, i32 5)
+  ret void
+}
+
+define dso_local void @test__twlle(i32 %a, i32 %b) {
+; CHECK-LABEL: test__twlle:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:tw 6, 3, 4
+; CHECK-NEXT:blr
+  call void @llvm.ppc.tw(i32 %a, i32 %b, i32 6)
+  ret void
+}
+
+define dso_local void @test__twgt(i32 %a, i32 %b) {
+; CHECK-LABEL: test__twgt:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:twgt 3, 4
+; CHECK-NEXT:blr
+  call void @llvm.ppc.tw(i32 %a, i32 %b, i32 8)
+  ret void
+}
+
+define dso_local void @test__twge(i32 %a, i32 %b) {
+; CHECK-LABEL: test__twge:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:tw 12, 3, 4
+; CHECK-NEXT:blr
+  call void @llvm.ppc.tw(i32 %a, i32 %b, i32 12)
+  ret void
+}
+
+define dso_local void @test__twlt(i32 %a, i32 %b) {
+; CHECK-LABEL: test__twlt:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:twlt 3, 4
+; CHECK-NEXT:blr
+  call void @llvm.ppc.tw(i32 %a, i32 %b, i32 16)
+  ret void
+}
+
+define dso_local void @test__twle(i32 %a, i32 %b) {
+; CHECK-LABEL: test__twle:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:tw 20, 3, 4
+; CHECK-NEXT:blr
+  call void @llvm.ppc.tw(i32 %a, i32 %b, i32 20)
+  ret void
+}
+
+define dso_local void @test__twne24(i32 %a, i32 %b) {
+; CHECK-LABEL: test__twne24:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:twne 3, 4
+; CHECK-NEXT:blr
+  call void @llvm.ppc.tw(i32 %a, i32 %b, i32 24)
+  ret void
+}
+
+define dso_local void @test__twu(i32 %a, i32 %b) {
+; CHECK-LABEL: test__twu:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:twu 3, 4
+; CHECK-NEXT:blr
+  call void @llvm.ppc.tw(i32 %a, i32 %b, i32 31)
+  ret void
+}
+
+define dso_local void @test__tw_no_match(i32 %a, i32 %b) {
+; CHECK-LABEL: test__tw_no_match:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:tw 13, 3, 4
+; CHECK-NEXT:blr
+  call void @llvm.ppc.tw(i32 %a, i32 %b, i32 13)
+  ret void
+}
+
+; trap
+declare void @llvm.ppc.trap(i32 %a)
+define dso_local void @test__trap(i32 %a) {
+; CHECK-LABEL: test__trap:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:twnei 3, 0
+; CHECK-NEXT:blr
+  call void @llvm.ppc.trap(i32 %a)
+  ret void
+}
Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap-64bit-only.ll

[PATCH] D103668: [PowerPC] Implement trap and conversion builtins for XL compatibility

2021-07-08 Thread Albion Fung via Phabricator via cfe-commits

Conanap marked an inline comment as done.
Conanap added inline comments.



Comment at: llvm/lib/Target/PowerPC/PPCInstr64Bit.td:1733
+// as XL produces a tweq , .
+def : Pat<(int_ppc_tdw g8rc:$A, g8rc:$B, 31),
+  (TD 4, $A, $B)>;

nemanjai wrote:
> This is supposed to be an unconditional trap and the produced sequence is not 
> that.
this one is quite weird... I see the output on `xlC` as `tdnei`:
`0b 04 00 00 tdnei   r4,0`

Also for the `tdne` pattern that I removed (`TD 3, ...`), `xlC` outputs the 
same encoding for `TD 3` and `TD 24`:  

```
Disassembly of section .text:

 <.yes>:
   0:   7f 03 20 88 tdner3,r4
   4:   4e 80 00 20 blr
   8:   00 00 00 00 .long 0x0
   c:   00 00 20 00 .long 0x2000
  10:   00 00 00 00 .long 0x0
  14:   00 00 00 08 .long 0x8
...
void yes(long long a, long long b) {
   return __tdw(a, b, 24);
}
```

and for 3:
```
Disassembly of section .text:

 <.yes>:
   0:   7f 03 20 88 tdner3,r4
   4:   4e 80 00 20 blr
   8:   00 00 00 00 .long 0x0
   c:   00 00 20 00 .long 0x2000
  10:   00 00 00 00 .long 0x0
  14:   00 00 00 08 .long 0x8
...
void yes(long long a, long long b) {
   return __tdw(a, b, 3);
}
```


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[PATCH] D103668: [PowerPC] Implement trap and conversion builtins for XL compatibility

2021-07-08 Thread Albion Fung via Phabricator via cfe-commits

Conanap updated this revision to Diff 357270.
Conanap added a comment.

Removed some incorrect patterns


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Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/lib/Basic/Targets/PPC.cpp
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/builtins-ppc-xlcompat-conversionfunc.c
  clang/test/CodeGen/builtins-ppc-xlcompat-error.c
  clang/test/CodeGen/builtins-ppc-xlcompat-trap-64bit-only.c
  clang/test/CodeGen/builtins-ppc-xlcompat-trap.c
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/Target/PowerPC/PPCInstr64Bit.td
  llvm/lib/Target/PowerPC/PPCInstrInfo.td
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-conversionfunc.ll
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap-64bit-only.ll
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap.ll

Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap.ll
@@ -0,0 +1,139 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN:   -mcpu=pwr7 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
+; RUN:   -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN:   -mcpu=pwr8 < %s | FileCheck %s
+
+; tw
+declare void @llvm.ppc.tw(i32 %a, i32 %b, i32 %c)
+define dso_local void @test__twlgt(i32 %a, i32 %b) {
+; CHECK-LABEL: test__twlgt:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:twlgt 3, 4
+; CHECK-NEXT:blr
+  call void @llvm.ppc.tw(i32 %a, i32 %b, i32 1)
+  ret void
+}
+
+define dso_local void @test__twllt(i32 %a, i32 %b) {
+; CHECK-LABEL: test__twllt:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:twllt 3, 4
+; CHECK-NEXT:blr
+  call void @llvm.ppc.tw(i32 %a, i32 %b, i32 2)
+  ret void
+}
+
+define dso_local void @test__twne3(i32 %a, i32 %b) {
+; CHECK-LABEL: test__twne3:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:twne 3, 4
+; CHECK-NEXT:blr
+  call void @llvm.ppc.tw(i32 %a, i32 %b, i32 3)
+  ret void
+}
+
+define dso_local void @test__tweq(i32 %a, i32 %b) {
+; CHECK-LABEL: test__tweq:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:tweq 3, 4
+; CHECK-NEXT:blr
+  call void @llvm.ppc.tw(i32 %a, i32 %b, i32 4)
+  ret void
+}
+
+define dso_local void @test__twlge(i32 %a, i32 %b) {
+; CHECK-LABEL: test__twlge:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:tw 5, 3, 4
+; CHECK-NEXT:blr
+  call void @llvm.ppc.tw(i32 %a, i32 %b, i32 5)
+  ret void
+}
+
+define dso_local void @test__twlle(i32 %a, i32 %b) {
+; CHECK-LABEL: test__twlle:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:tw 6, 3, 4
+; CHECK-NEXT:blr
+  call void @llvm.ppc.tw(i32 %a, i32 %b, i32 6)
+  ret void
+}
+
+define dso_local void @test__twgt(i32 %a, i32 %b) {
+; CHECK-LABEL: test__twgt:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:twgt 3, 4
+; CHECK-NEXT:blr
+  call void @llvm.ppc.tw(i32 %a, i32 %b, i32 8)
+  ret void
+}
+
+define dso_local void @test__twge(i32 %a, i32 %b) {
+; CHECK-LABEL: test__twge:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:tw 12, 3, 4
+; CHECK-NEXT:blr
+  call void @llvm.ppc.tw(i32 %a, i32 %b, i32 12)
+  ret void
+}
+
+define dso_local void @test__twlt(i32 %a, i32 %b) {
+; CHECK-LABEL: test__twlt:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:twlt 3, 4
+; CHECK-NEXT:blr
+  call void @llvm.ppc.tw(i32 %a, i32 %b, i32 16)
+  ret void
+}
+
+define dso_local void @test__twle(i32 %a, i32 %b) {
+; CHECK-LABEL: test__twle:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:tw 20, 3, 4
+; CHECK-NEXT:blr
+  call void @llvm.ppc.tw(i32 %a, i32 %b, i32 20)
+  ret void
+}
+
+define dso_local void @test__twne24(i32 %a, i32 %b) {
+; CHECK-LABEL: test__twne24:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:twne 3, 4
+; CHECK-NEXT:blr
+  call void @llvm.ppc.tw(i32 %a, i32 %b, i32 24)
+  ret void
+}
+
+define dso_local void @test__tweq31(i32 %a, i32 %b) {
+; CHECK-LABEL: test__tweq31:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:tweq 3, 4
+; CHECK-NEXT:blr
+  call void @llvm.ppc.tw(i32 %a, i32 %b, i32 31)
+  ret void
+}
+
+define dso_local void @test__tw_no_match(i32 %a, i32 %b) {
+; CHECK-LABEL: test__tw_no_match:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:tw 13, 3, 4
+; CHECK-NEXT:blr
+  call void @llvm.ppc.tw(i32 %a, i32 %b, i32 13)
+  ret void
+}
+
+; trap
+declare void @llvm.ppc.trap(i32 %a)
+define dso_local void @test__trap(i32 %a) {
+; CHECK-LABEL: test__trap:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:twnei 3, 0
+; CHECK-NEXT:blr
+  call void @llvm.ppc.trap(i32 %a)
+  ret void
+}
Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap-64bit-only.ll

[PATCH] D103668: [PowerPC] Implement trap and conversion builtins for XL compatibility

2021-07-08 Thread Albion Fung via Phabricator via cfe-commits

Conanap added inline comments.



Comment at: 
llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap-64bit-only.ll:41
+; CHECK:   # %bb.0:
+; CHECK-NEXT:td 5, 3, 4
+; CHECK-NEXT:blr

NeHuang wrote:
> seems the InstAlias defined for `td` and `tw` not working as expected 
> 
after discussion with Nemanja, we'll leave out the inst alias as that is a very 
low priority fix.


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[PATCH] D103668: [PowerPC] Implement trap and conversion builtins for XL compatibility

2021-07-07 Thread Albion Fung via Phabricator via cfe-commits

Conanap updated this revision to Diff 357127.
Conanap added a comment.

Removed inst aliases


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Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/lib/Basic/Targets/PPC.cpp
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/builtins-ppc-xlcompat-conversionfunc.c
  clang/test/CodeGen/builtins-ppc-xlcompat-error.c
  clang/test/CodeGen/builtins-ppc-xlcompat-trap-64bit-only.c
  clang/test/CodeGen/builtins-ppc-xlcompat-trap.c
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/Target/PowerPC/PPCInstr64Bit.td
  llvm/lib/Target/PowerPC/PPCInstrInfo.td
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-conversionfunc.ll
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap-64bit-only.ll
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap.ll

Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap.ll
@@ -0,0 +1,139 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN:   -mcpu=pwr7 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
+; RUN:   -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN:   -mcpu=pwr8 < %s | FileCheck %s
+
+; tw
+declare void @llvm.ppc.tw(i32 %a, i32 %b, i32 %c)
+define dso_local void @test__twlgt(i32 %a, i32 %b) {
+; CHECK-LABEL: test__twlgt:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:twlgt 3, 4
+; CHECK-NEXT:blr
+  call void @llvm.ppc.tw(i32 %a, i32 %b, i32 1)
+  ret void
+}
+
+define dso_local void @test__twllt(i32 %a, i32 %b) {
+; CHECK-LABEL: test__twllt:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:twllt 3, 4
+; CHECK-NEXT:blr
+  call void @llvm.ppc.tw(i32 %a, i32 %b, i32 2)
+  ret void
+}
+
+define dso_local void @test__twne3(i32 %a, i32 %b) {
+; CHECK-LABEL: test__twne3:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:twne 3, 4
+; CHECK-NEXT:blr
+  call void @llvm.ppc.tw(i32 %a, i32 %b, i32 3)
+  ret void
+}
+
+define dso_local void @test__tweq(i32 %a, i32 %b) {
+; CHECK-LABEL: test__tweq:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:tweq 3, 4
+; CHECK-NEXT:blr
+  call void @llvm.ppc.tw(i32 %a, i32 %b, i32 4)
+  ret void
+}
+
+define dso_local void @test__twlge(i32 %a, i32 %b) {
+; CHECK-LABEL: test__twlge:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:tw 5, 3, 4
+; CHECK-NEXT:blr
+  call void @llvm.ppc.tw(i32 %a, i32 %b, i32 5)
+  ret void
+}
+
+define dso_local void @test__twlle(i32 %a, i32 %b) {
+; CHECK-LABEL: test__twlle:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:tw 6, 3, 4
+; CHECK-NEXT:blr
+  call void @llvm.ppc.tw(i32 %a, i32 %b, i32 6)
+  ret void
+}
+
+define dso_local void @test__twgt(i32 %a, i32 %b) {
+; CHECK-LABEL: test__twgt:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:twgt 3, 4
+; CHECK-NEXT:blr
+  call void @llvm.ppc.tw(i32 %a, i32 %b, i32 8)
+  ret void
+}
+
+define dso_local void @test__twge(i32 %a, i32 %b) {
+; CHECK-LABEL: test__twge:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:tw 12, 3, 4
+; CHECK-NEXT:blr
+  call void @llvm.ppc.tw(i32 %a, i32 %b, i32 12)
+  ret void
+}
+
+define dso_local void @test__twlt(i32 %a, i32 %b) {
+; CHECK-LABEL: test__twlt:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:twlt 3, 4
+; CHECK-NEXT:blr
+  call void @llvm.ppc.tw(i32 %a, i32 %b, i32 16)
+  ret void
+}
+
+define dso_local void @test__twle(i32 %a, i32 %b) {
+; CHECK-LABEL: test__twle:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:tw 20, 3, 4
+; CHECK-NEXT:blr
+  call void @llvm.ppc.tw(i32 %a, i32 %b, i32 20)
+  ret void
+}
+
+define dso_local void @test__twne24(i32 %a, i32 %b) {
+; CHECK-LABEL: test__twne24:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:twne 3, 4
+; CHECK-NEXT:blr
+  call void @llvm.ppc.tw(i32 %a, i32 %b, i32 24)
+  ret void
+}
+
+define dso_local void @test__tweq31(i32 %a, i32 %b) {
+; CHECK-LABEL: test__tweq31:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:tweq 3, 4
+; CHECK-NEXT:blr
+  call void @llvm.ppc.tw(i32 %a, i32 %b, i32 31)
+  ret void
+}
+
+define dso_local void @test__tw_no_match(i32 %a, i32 %b) {
+; CHECK-LABEL: test__tw_no_match:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:tw 13, 3, 4
+; CHECK-NEXT:blr
+  call void @llvm.ppc.tw(i32 %a, i32 %b, i32 13)
+  ret void
+}
+
+; trap
+declare void @llvm.ppc.trap(i32 %a)
+define dso_local void @test__trap(i32 %a) {
+; CHECK-LABEL: test__trap:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:twnei 3, 0
+; CHECK-NEXT:blr
+  call void @llvm.ppc.trap(i32 %a)
+  ret void
+}
Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap-64bit-only.ll

[PATCH] D103668: [PowerPC] Implement trap and conversion builtins for XL compatibility

2021-07-07 Thread Albion Fung via Phabricator via cfe-commits

Conanap added inline comments.



Comment at: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap.ll:135
+; CHECK:   # %bb.0:
+; CHECK-NEXT:twnei 3, 0
+; CHECK-NEXT:blr

nemanjai wrote:
> Where are the aliases `twnei` and `tdnei` coming from? You don't seem to add 
> them.
it should be from the trap extend mnemonics


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[PATCH] D103668: [PowerPC] Implement trap and conversion builtins for XL compatibility

2021-07-07 Thread Albion Fung via Phabricator via cfe-commits

Conanap updated this revision to Diff 357052.
Conanap marked 6 inline comments as done.
Conanap added a comment.

Rebased and changed aix test cases to pwr 7


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Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/lib/Basic/Targets/PPC.cpp
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/builtins-ppc-xlcompat-conversionfunc.c
  clang/test/CodeGen/builtins-ppc-xlcompat-error.c
  clang/test/CodeGen/builtins-ppc-xlcompat-trap-64bit-only.c
  clang/test/CodeGen/builtins-ppc-xlcompat-trap.c
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/Target/PowerPC/PPCInstr64Bit.td
  llvm/lib/Target/PowerPC/PPCInstrInfo.td
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-conversionfunc.ll
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap-64bit-only.ll
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap.ll

Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap.ll
@@ -0,0 +1,139 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN:   -mcpu=pwr7 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
+; RUN:   -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN:   -mcpu=pwr8 < %s | FileCheck %s
+
+; tw
+declare void @llvm.ppc.tw(i32 %a, i32 %b, i32 %c)
+define dso_local void @test__twlgt(i32 %a, i32 %b) {
+; CHECK-LABEL: test__twlgt:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:twlgt 3, 4
+; CHECK-NEXT:blr
+  call void @llvm.ppc.tw(i32 %a, i32 %b, i32 1)
+  ret void
+}
+
+define dso_local void @test__twllt(i32 %a, i32 %b) {
+; CHECK-LABEL: test__twllt:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:twllt 3, 4
+; CHECK-NEXT:blr
+  call void @llvm.ppc.tw(i32 %a, i32 %b, i32 2)
+  ret void
+}
+
+define dso_local void @test__twne3(i32 %a, i32 %b) {
+; CHECK-LABEL: test__twne3:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:twne 3, 4
+; CHECK-NEXT:blr
+  call void @llvm.ppc.tw(i32 %a, i32 %b, i32 3)
+  ret void
+}
+
+define dso_local void @test__tweq(i32 %a, i32 %b) {
+; CHECK-LABEL: test__tweq:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:tweq 3, 4
+; CHECK-NEXT:blr
+  call void @llvm.ppc.tw(i32 %a, i32 %b, i32 4)
+  ret void
+}
+
+define dso_local void @test__twlge(i32 %a, i32 %b) {
+; CHECK-LABEL: test__twlge:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:tw 5, 3, 4
+; CHECK-NEXT:blr
+  call void @llvm.ppc.tw(i32 %a, i32 %b, i32 5)
+  ret void
+}
+
+define dso_local void @test__twlle(i32 %a, i32 %b) {
+; CHECK-LABEL: test__twlle:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:tw 6, 3, 4
+; CHECK-NEXT:blr
+  call void @llvm.ppc.tw(i32 %a, i32 %b, i32 6)
+  ret void
+}
+
+define dso_local void @test__twgt(i32 %a, i32 %b) {
+; CHECK-LABEL: test__twgt:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:twgt 3, 4
+; CHECK-NEXT:blr
+  call void @llvm.ppc.tw(i32 %a, i32 %b, i32 8)
+  ret void
+}
+
+define dso_local void @test__twge(i32 %a, i32 %b) {
+; CHECK-LABEL: test__twge:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:tw 12, 3, 4
+; CHECK-NEXT:blr
+  call void @llvm.ppc.tw(i32 %a, i32 %b, i32 12)
+  ret void
+}
+
+define dso_local void @test__twlt(i32 %a, i32 %b) {
+; CHECK-LABEL: test__twlt:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:twlt 3, 4
+; CHECK-NEXT:blr
+  call void @llvm.ppc.tw(i32 %a, i32 %b, i32 16)
+  ret void
+}
+
+define dso_local void @test__twle(i32 %a, i32 %b) {
+; CHECK-LABEL: test__twle:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:tw 20, 3, 4
+; CHECK-NEXT:blr
+  call void @llvm.ppc.tw(i32 %a, i32 %b, i32 20)
+  ret void
+}
+
+define dso_local void @test__twne24(i32 %a, i32 %b) {
+; CHECK-LABEL: test__twne24:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:twne 3, 4
+; CHECK-NEXT:blr
+  call void @llvm.ppc.tw(i32 %a, i32 %b, i32 24)
+  ret void
+}
+
+define dso_local void @test__tweq31(i32 %a, i32 %b) {
+; CHECK-LABEL: test__tweq31:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:tweq 3, 4
+; CHECK-NEXT:blr
+  call void @llvm.ppc.tw(i32 %a, i32 %b, i32 31)
+  ret void
+}
+
+define dso_local void @test__tw_no_match(i32 %a, i32 %b) {
+; CHECK-LABEL: test__tw_no_match:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:tw 13, 3, 4
+; CHECK-NEXT:blr
+  call void @llvm.ppc.tw(i32 %a, i32 %b, i32 13)
+  ret void
+}
+
+; trap
+declare void @llvm.ppc.trap(i32 %a)
+define dso_local void @test__trap(i32 %a) {
+; CHECK-LABEL: test__trap:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:twnei 3, 0
+; CHECK-NEXT:blr
+  call void @llvm.ppc.trap(i32 %a)
+  ret void
+}
Index:

[PATCH] D103668: [PowerPC] Implement trap and conversion builtins for XL compatibility

2021-07-07 Thread Albion Fung via Phabricator via cfe-commits

Conanap updated this revision to Diff 356988.
Conanap added a comment.

Moved inst alias for 64bit to the 64 bit file


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D103668/new/

https://reviews.llvm.org/D103668

Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/lib/Basic/Targets/PPC.cpp
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/builtins-ppc-xlcompat-conversionfunc.c
  clang/test/CodeGen/builtins-ppc-xlcompat-error.c
  clang/test/CodeGen/builtins-ppc-xlcompat-trap-64bit-only.c
  clang/test/CodeGen/builtins-ppc-xlcompat-trap.c
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/Target/PowerPC/PPCInstr64Bit.td
  llvm/lib/Target/PowerPC/PPCInstrInfo.td
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-conversionfunc.ll
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap-64bit-only.ll
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap.ll

Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap.ll
@@ -0,0 +1,139 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN:   -mcpu=pwr7 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
+; RUN:   -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN:   -mcpu=pwr8 < %s | FileCheck %s
+
+; tw
+declare void @llvm.ppc.tw(i32 %a, i32 %b, i32 %c)
+define dso_local void @test__twlgt(i32 %a, i32 %b) {
+; CHECK-LABEL: test__twlgt:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:twlgt 3, 4
+; CHECK-NEXT:blr
+  call void @llvm.ppc.tw(i32 %a, i32 %b, i32 1)
+  ret void
+}
+
+define dso_local void @test__twllt(i32 %a, i32 %b) {
+; CHECK-LABEL: test__twllt:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:twllt 3, 4
+; CHECK-NEXT:blr
+  call void @llvm.ppc.tw(i32 %a, i32 %b, i32 2)
+  ret void
+}
+
+define dso_local void @test__twne3(i32 %a, i32 %b) {
+; CHECK-LABEL: test__twne3:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:twne 3, 4
+; CHECK-NEXT:blr
+  call void @llvm.ppc.tw(i32 %a, i32 %b, i32 3)
+  ret void
+}
+
+define dso_local void @test__tweq(i32 %a, i32 %b) {
+; CHECK-LABEL: test__tweq:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:tweq 3, 4
+; CHECK-NEXT:blr
+  call void @llvm.ppc.tw(i32 %a, i32 %b, i32 4)
+  ret void
+}
+
+define dso_local void @test__twlge(i32 %a, i32 %b) {
+; CHECK-LABEL: test__twlge:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:tw 5, 3, 4
+; CHECK-NEXT:blr
+  call void @llvm.ppc.tw(i32 %a, i32 %b, i32 5)
+  ret void
+}
+
+define dso_local void @test__twlle(i32 %a, i32 %b) {
+; CHECK-LABEL: test__twlle:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:tw 6, 3, 4
+; CHECK-NEXT:blr
+  call void @llvm.ppc.tw(i32 %a, i32 %b, i32 6)
+  ret void
+}
+
+define dso_local void @test__twgt(i32 %a, i32 %b) {
+; CHECK-LABEL: test__twgt:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:twgt 3, 4
+; CHECK-NEXT:blr
+  call void @llvm.ppc.tw(i32 %a, i32 %b, i32 8)
+  ret void
+}
+
+define dso_local void @test__twge(i32 %a, i32 %b) {
+; CHECK-LABEL: test__twge:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:tw 12, 3, 4
+; CHECK-NEXT:blr
+  call void @llvm.ppc.tw(i32 %a, i32 %b, i32 12)
+  ret void
+}
+
+define dso_local void @test__twlt(i32 %a, i32 %b) {
+; CHECK-LABEL: test__twlt:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:twlt 3, 4
+; CHECK-NEXT:blr
+  call void @llvm.ppc.tw(i32 %a, i32 %b, i32 16)
+  ret void
+}
+
+define dso_local void @test__twle(i32 %a, i32 %b) {
+; CHECK-LABEL: test__twle:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:tw 20, 3, 4
+; CHECK-NEXT:blr
+  call void @llvm.ppc.tw(i32 %a, i32 %b, i32 20)
+  ret void
+}
+
+define dso_local void @test__twne24(i32 %a, i32 %b) {
+; CHECK-LABEL: test__twne24:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:twne 3, 4
+; CHECK-NEXT:blr
+  call void @llvm.ppc.tw(i32 %a, i32 %b, i32 24)
+  ret void
+}
+
+define dso_local void @test__tweq31(i32 %a, i32 %b) {
+; CHECK-LABEL: test__tweq31:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:tweq 3, 4
+; CHECK-NEXT:blr
+  call void @llvm.ppc.tw(i32 %a, i32 %b, i32 31)
+  ret void
+}
+
+define dso_local void @test__tw_no_match(i32 %a, i32 %b) {
+; CHECK-LABEL: test__tw_no_match:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:tw 13, 3, 4
+; CHECK-NEXT:blr
+  call void @llvm.ppc.tw(i32 %a, i32 %b, i32 13)
+  ret void
+}
+
+; trap
+declare void @llvm.ppc.trap(i32 %a)
+define dso_local void @test__trap(i32 %a) {
+; CHECK-LABEL: test__trap:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:twnei 3, 0
+; CHECK-NEXT:blr
+  call void @llvm.ppc.trap(i32 %a)
+  ret void
+}
Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap-64bit-only.ll

[PATCH] D103668: [PowerPC] Implement trap and conversion builtins for XL compatibility

2021-07-07 Thread Albion Fung via Phabricator via cfe-commits

Conanap added inline comments.



Comment at: clang/include/clang/Basic/BuiltinsPPC.def:50
 BUILTIN(__builtin_ppc_compare_and_swaplp, "iLiD*Li*Li", "")
+BUILTIN(__builtin_ppc_tdw, "vLLiLLiIi", "")
+BUILTIN(__builtin_ppc_tw, "viiIi", "")

NeHuang wrote:
> definition here not matching prototype in document 
> ```
> void __tdw ( long a, long b, unsigned int TO);
> ```
the document had been incorrect; the document is now updated to to `long long`.



Comment at: llvm/lib/Target/PowerPC/PPCInstrInfo.td:2233
 
+def : InstAlias<"tdlle $rA, $rB", (TD 6, g8rc:$rA, g8rc:$rB)>;
+def : InstAlias<"tdlge $rA, $rB", (TD 5, g8rc:$rA, g8rc:$rB)>;

amyk wrote:
> Are `tdne`, `tweq` supposed to be aliases that are intended to be added here, 
> too?
the compiler seem to already know `tdne` and `tweq` so I didn't add those.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D103668/new/

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[PATCH] D103668: [PowerPC] Implement trap and conversion builtins for XL compatibility

2021-07-07 Thread Albion Fung via Phabricator via cfe-commits

Conanap updated this revision to Diff 356985.
Conanap marked 15 inline comments as done.
Conanap added a comment.

Addressed comments, separated 64 bit C test cases.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D103668/new/

https://reviews.llvm.org/D103668

Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/lib/Basic/Targets/PPC.cpp
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/builtins-ppc-xlcompat-conversionfunc.c
  clang/test/CodeGen/builtins-ppc-xlcompat-error.c
  clang/test/CodeGen/builtins-ppc-xlcompat-trap-64bit-only.c
  clang/test/CodeGen/builtins-ppc-xlcompat-trap.c
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/Target/PowerPC/PPCInstr64Bit.td
  llvm/lib/Target/PowerPC/PPCInstrInfo.td
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-conversionfunc.ll
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap-64bit-only.ll
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap.ll

Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap.ll
@@ -0,0 +1,139 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN:   -mcpu=pwr7 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
+; RUN:   -mcpu=pwr8 < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN:   -mcpu=pwr8 < %s | FileCheck %s
+
+; tw
+declare void @llvm.ppc.tw(i32 %a, i32 %b, i32 %c)
+define dso_local void @test__twlgt(i32 %a, i32 %b) {
+; CHECK-LABEL: test__twlgt:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:twlgt 3, 4
+; CHECK-NEXT:blr
+  call void @llvm.ppc.tw(i32 %a, i32 %b, i32 1)
+  ret void
+}
+
+define dso_local void @test__twllt(i32 %a, i32 %b) {
+; CHECK-LABEL: test__twllt:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:twllt 3, 4
+; CHECK-NEXT:blr
+  call void @llvm.ppc.tw(i32 %a, i32 %b, i32 2)
+  ret void
+}
+
+define dso_local void @test__twne3(i32 %a, i32 %b) {
+; CHECK-LABEL: test__twne3:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:twne 3, 4
+; CHECK-NEXT:blr
+  call void @llvm.ppc.tw(i32 %a, i32 %b, i32 3)
+  ret void
+}
+
+define dso_local void @test__tweq(i32 %a, i32 %b) {
+; CHECK-LABEL: test__tweq:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:tweq 3, 4
+; CHECK-NEXT:blr
+  call void @llvm.ppc.tw(i32 %a, i32 %b, i32 4)
+  ret void
+}
+
+define dso_local void @test__twlge(i32 %a, i32 %b) {
+; CHECK-LABEL: test__twlge:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:tw 5, 3, 4
+; CHECK-NEXT:blr
+  call void @llvm.ppc.tw(i32 %a, i32 %b, i32 5)
+  ret void
+}
+
+define dso_local void @test__twlle(i32 %a, i32 %b) {
+; CHECK-LABEL: test__twlle:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:tw 6, 3, 4
+; CHECK-NEXT:blr
+  call void @llvm.ppc.tw(i32 %a, i32 %b, i32 6)
+  ret void
+}
+
+define dso_local void @test__twgt(i32 %a, i32 %b) {
+; CHECK-LABEL: test__twgt:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:twgt 3, 4
+; CHECK-NEXT:blr
+  call void @llvm.ppc.tw(i32 %a, i32 %b, i32 8)
+  ret void
+}
+
+define dso_local void @test__twge(i32 %a, i32 %b) {
+; CHECK-LABEL: test__twge:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:tw 12, 3, 4
+; CHECK-NEXT:blr
+  call void @llvm.ppc.tw(i32 %a, i32 %b, i32 12)
+  ret void
+}
+
+define dso_local void @test__twlt(i32 %a, i32 %b) {
+; CHECK-LABEL: test__twlt:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:twlt 3, 4
+; CHECK-NEXT:blr
+  call void @llvm.ppc.tw(i32 %a, i32 %b, i32 16)
+  ret void
+}
+
+define dso_local void @test__twle(i32 %a, i32 %b) {
+; CHECK-LABEL: test__twle:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:tw 20, 3, 4
+; CHECK-NEXT:blr
+  call void @llvm.ppc.tw(i32 %a, i32 %b, i32 20)
+  ret void
+}
+
+define dso_local void @test__twne24(i32 %a, i32 %b) {
+; CHECK-LABEL: test__twne24:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:twne 3, 4
+; CHECK-NEXT:blr
+  call void @llvm.ppc.tw(i32 %a, i32 %b, i32 24)
+  ret void
+}
+
+define dso_local void @test__tweq31(i32 %a, i32 %b) {
+; CHECK-LABEL: test__tweq31:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:tweq 3, 4
+; CHECK-NEXT:blr
+  call void @llvm.ppc.tw(i32 %a, i32 %b, i32 31)
+  ret void
+}
+
+define dso_local void @test__tw_no_match(i32 %a, i32 %b) {
+; CHECK-LABEL: test__tw_no_match:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:tw 13, 3, 4
+; CHECK-NEXT:blr
+  call void @llvm.ppc.tw(i32 %a, i32 %b, i32 13)
+  ret void
+}
+
+; trap
+declare void @llvm.ppc.trap(i32 %a)
+define dso_local void @test__trap(i32 %a) {
+; CHECK-LABEL: test__trap:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:twnei 3, 0
+; CHECK-NEXT:blr
+  call void @llvm.ppc.trap(i32 %a)
+  ret void
+}
Index:

[PATCH] D105236: [PowerPC] Implement Load and Reserve and Store Conditional Builtins

2021-07-05 Thread Albion Fung via Phabricator via cfe-commits

Conanap added a comment.

In D105236#2858909 , @thakis wrote:

> Looks like this breaks tests: http://45.33.8.238/linux/50465/step_7.txt
>
> Please take a look, and revert for now if it takes a while to fix.

Hi! I accidentally included a test case meant for a later patch; it's been 
removed in this patch here: https://reviews.llvm.org/D105454


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