[clang] 13d3cd3 - [PowerPC] Implement vector float and vector double version for vec_orc builtin
Author: Albion Fung
Date: 2021-10-06T02:47:42-05:00
New Revision: 13d3cd37e27889cb343d92313944d5dabfe2762b
URL:
https://github.com/llvm/llvm-project/commit/13d3cd37e27889cb343d92313944d5dabfe2762b
DIFF:
https://github.com/llvm/llvm-project/commit/13d3cd37e27889cb343d92313944d5dabfe2762b.diff
LOG: [PowerPC] Implement vector float and vector double version for vec_orc
builtin
The builtin for vec_orc has support for the following two signatures,
but currently the compiler marks it ambiguous:
vector float vec_orc(vector float, vector float)
vector double vec_orc(vector double, vector double)
This patch implements these two builtins.
Differential revision: https://reviews.llvm.org/D110858
Added:
Modified:
clang/lib/Headers/altivec.h
clang/test/CodeGen/builtins-ppc-p8vector.c
Removed:
diff --git a/clang/lib/Headers/altivec.h b/clang/lib/Headers/altivec.h
index 4e229a4bf510c..a6dfe2d14423a 100644
--- a/clang/lib/Headers/altivec.h
+++ b/clang/lib/Headers/altivec.h
@@ -7109,6 +7109,11 @@ vec_orc(vector float __a, vector bool int __b) {
return (vector float)((vector unsigned int)__a | ~__b);
}
+static __inline__ vector float __ATTRS_o_ai vec_orc(vector float __a,
+vector float __b) {
+ return (vector float)((vector unsigned int)__a | ~(vector unsigned int)__b);
+}
+
static __inline__ vector signed long long __ATTRS_o_ai
vec_orc(vector signed long long __a, vector signed long long __b) {
return __a | ~__b;
@@ -7153,6 +7158,12 @@ static __inline__ vector double __ATTRS_o_ai
vec_orc(vector bool long long __a, vector double __b) {
return (vector double)(__a | ~(vector unsigned long long)__b);
}
+
+static __inline__ vector double __ATTRS_o_ai vec_orc(vector double __a,
+ vector double __b) {
+ return (vector double)((vector bool long long)__a |
+ ~(vector unsigned long long)__b);
+}
#endif
/* vec_vor */
diff --git a/clang/test/CodeGen/builtins-ppc-p8vector.c
b/clang/test/CodeGen/builtins-ppc-p8vector.c
index 16a306cc82ed2..90e6de283cb15 100644
--- a/clang/test/CodeGen/builtins-ppc-p8vector.c
+++ b/clang/test/CodeGen/builtins-ppc-p8vector.c
@@ -35,7 +35,9 @@ vector signed __int128 vsx = { 1 };
vector unsigned __int128 vux = { 1 };
vector float vfa = { 1.e-4f, -132.23f, -22.1, 32.00f };
+vector float vfb = { 1.e-4f, -132.23f, -22.1, 32.00f };
vector double vda = { 1.e-11, -132.23e10 };
+vector double vdb = { 1.e-11, -132.23e10 };
int res_i;
double res_d;
@@ -1067,6 +1069,12 @@ void test1() {
// CHECK: [[T1:%.+]] = xor <4 x i32> {{%.+}},
// CHECK: or <4 x i32> {{%.+}}, [[T1]]
// CHECK-LE: [[T1:%.+]] = xor <4 x i32> {{%.+}},
+// CHECK-LE: or <4 x i32> {{%.+}}, [[T1]]
+
+ res_vf = vec_orc(vfa, vfb);
+// CHECK: [[T1:%.+]] = xor <4 x i32> {{%.+}},
+// CHECK: or <4 x i32> {{%.+}}, [[T1]]
+// CHECK-LE: [[T1:%.+]] = xor <4 x i32> {{%.+}},
// CHECK-LE: or <4 x i32> {{%.+}}, [[T1]]
res_vsll = vec_orc(vsll, vsll);
@@ -1121,6 +1129,12 @@ void test1() {
// CHECK: [[T1:%.+]] = xor <2 x i64> {{%.+}},
// CHECK: or <2 x i64> {{%.+}}, [[T1]]
// CHECK-LE: [[T1:%.+]] = xor <2 x i64> {{%.+}},
+// CHECK-LE: or <2 x i64> {{%.+}}, [[T1]]
+
+ res_vd = vec_orc(vda, vdb);
+// CHECK: [[T1:%.+]] = xor <2 x i64> {{%.+}},
+// CHECK: or <2 x i64> {{%.+}}, [[T1]]
+// CHECK-LE: [[T1:%.+]] = xor <2 x i64> {{%.+}},
// CHECK-LE: or <2 x i64> {{%.+}}, [[T1]]
/* vec_sub */
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[clang] 29bb877 - [PowerPC] Fix lharx and lbarx builtin signatures
Author: Albion Fung
Date: 2021-09-30T22:36:13-05:00
New Revision: 29bb877499ce328f8f4a5d61e9bae94e5f97f908
URL:
https://github.com/llvm/llvm-project/commit/29bb877499ce328f8f4a5d61e9bae94e5f97f908
DIFF:
https://github.com/llvm/llvm-project/commit/29bb877499ce328f8f4a5d61e9bae94e5f97f908.diff
LOG: [PowerPC] Fix lharx and lbarx builtin signatures
The signatures for the PowerPC builtins lharx and
lbarx are incorrect, and causes issues when used in a function
that requires the return of the builtin to be promoted.
This patch fixes these signatures.
Differential revision: https://reviews.llvm.org/D110273
Added:
Modified:
clang/include/clang/Basic/BuiltinsPPC.def
clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond.c
Removed:
diff --git a/clang/include/clang/Basic/BuiltinsPPC.def
b/clang/include/clang/Basic/BuiltinsPPC.def
index 26286c270905e..65f490a214bcb 100644
--- a/clang/include/clang/Basic/BuiltinsPPC.def
+++ b/clang/include/clang/Basic/BuiltinsPPC.def
@@ -74,8 +74,8 @@ BUILTIN(__builtin_ppc_fetch_and_swap, "UiUiD*Ui", "")
BUILTIN(__builtin_ppc_fetch_and_swaplp, "ULiULiD*ULi", "")
BUILTIN(__builtin_ppc_ldarx, "LiLiD*", "")
BUILTIN(__builtin_ppc_lwarx, "iiD*", "")
-BUILTIN(__builtin_ppc_lharx, "isD*", "")
-BUILTIN(__builtin_ppc_lbarx, "UiUcD*", "")
+BUILTIN(__builtin_ppc_lharx, "ssD*", "")
+BUILTIN(__builtin_ppc_lbarx, "ccD*", "")
BUILTIN(__builtin_ppc_stdcx, "iLiD*Li", "")
BUILTIN(__builtin_ppc_stwcx, "iiD*i", "")
BUILTIN(__builtin_ppc_sthcx, "isD*s", "")
diff --git a/clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond.c
b/clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond.c
index 7c898f523dc85..0362ae389ba06 100644
--- a/clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond.c
+++ b/clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond.c
@@ -24,7 +24,7 @@ short test_lharx(volatile short *a) {
return __lharx(a);
}
-char test_lbarx(volatile unsigned char *a) {
+char test_lbarx(volatile char *a) {
// CHECK-LABEL: @test_lbarx
// CHECK: %0 = tail call i8 asm sideeffect "lbarx $0, ${1:y}",
"=r,*Z,~{memory}"(i8* %a)
// CHECK-NON-PWR8-ERR: error: this builtin is only valid on POWER8 or later
CPUs
@@ -46,3 +46,18 @@ int test_sthcx(volatile short *a, short val) {
// CHECK-NON-PWR8-ERR: error: this builtin is only valid on POWER8 or later
CPUs
return __sthcx(a, val);
}
+
+// Extra test cases that previously caused error during usage.
+int test_lharx_intret(volatile short *a) {
+ // CHECK-LABEL: @test_lharx_intret
+ // CHECK: %0 = tail call i16 asm sideeffect "lharx $0, ${1:y}",
"=r,*Z,~{memory}"(i16* %a)
+ // CHECK-NON-PWR8-ERR: error: this builtin is only valid on POWER8 or later
CPUs
+ return __lharx(a);
+}
+
+int test_lbarx_intret(volatile char *a) {
+ // CHECK-LABEL: @test_lbarx_intret
+ // CHECK: %0 = tail call i8 asm sideeffect "lbarx $0, ${1:y}",
"=r,*Z,~{memory}"(i8* %a)
+ // CHECK-NON-PWR8-ERR: error: this builtin is only valid on POWER8 or later
CPUs
+ return __lbarx(a);
+}
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[clang] 840afbd - [PowerPC] SemaChecking for darn family of builtins
Author: Albion Fung
Date: 2021-09-23T23:38:59-05:00
New Revision: 840afbde48e90213028174fdba715e10aa39dd85
URL:
https://github.com/llvm/llvm-project/commit/840afbde48e90213028174fdba715e10aa39dd85
DIFF:
https://github.com/llvm/llvm-project/commit/840afbde48e90213028174fdba715e10aa39dd85.diff
LOG: [PowerPC] SemaChecking for darn family of builtins
The __darn family of builtins are only available on Pwr9,
and only __darn_32 is available on both 64 and 32 bit, while the rest
are only available on 64 bit. The patch adds sema checking
for these builtins and separate the __darn_32's 32 bit
test cases.
Differential revision: https://reviews.llvm.org/D110282
Added:
Modified:
clang/lib/Sema/SemaChecking.cpp
clang/test/CodeGen/builtins-ppc-xlcompat-darn.c
clang/test/CodeGen/builtins-ppc-xlcompat-error.c
clang/test/CodeGen/builtins-ppc.c
Removed:
diff --git a/clang/lib/Sema/SemaChecking.cpp b/clang/lib/Sema/SemaChecking.cpp
index 5cc968c133ce3..0310e10f93704 100644
--- a/clang/lib/Sema/SemaChecking.cpp
+++ b/clang/lib/Sema/SemaChecking.cpp
@@ -3295,6 +3295,8 @@ static bool isPPC_64Builtin(unsigned BuiltinID) {
case PPC::BI__builtin_ppc_insert_exp:
case PPC::BI__builtin_ppc_extract_sig:
case PPC::BI__builtin_ppc_addex:
+ case PPC::BI__builtin_darn:
+ case PPC::BI__builtin_darn_raw:
return true;
}
return false;
@@ -3478,6 +3480,11 @@ bool Sema::CheckPPCBuiltinFunctionCall(const TargetInfo
, unsigned BuiltinID,
case PPC::BI__builtin_altivec_vcntmbw:
case PPC::BI__builtin_altivec_vcntmbd:
return SemaBuiltinConstantArgRange(TheCall, 1, 0, 1);
+ case PPC::BI__builtin_darn:
+ case PPC::BI__builtin_darn_raw:
+ case PPC::BI__builtin_darn_32:
+return SemaFeatureCheck(*this, TheCall, "isa-v30-instructions",
+diag::err_ppc_builtin_only_on_arch, "9");
#define CUSTOM_BUILTIN(Name, Intr, Types, Acc) \
case PPC::BI__builtin_##Name: \
return SemaBuiltinPPCMMACall(TheCall, Types);
diff --git a/clang/test/CodeGen/builtins-ppc-xlcompat-darn.c
b/clang/test/CodeGen/builtins-ppc-xlcompat-darn.c
index edf0bf3b8557b..779a635e4d35b 100644
--- a/clang/test/CodeGen/builtins-ppc-xlcompat-darn.c
+++ b/clang/test/CodeGen/builtins-ppc-xlcompat-darn.c
@@ -1,10 +1,13 @@
// REQUIRES: powerpc-registered-target
// RUN: %clang_cc1 -triple powerpc64-unknown-unknown \
-// RUN:-emit-llvm %s -o - -target-cpu pwr9 | FileCheck %s
+// RUN:-emit-llvm %s -o - -target-cpu pwr9 | \
+// RUN:FileCheck %s --check-prefix=CHECK-64
// RUN: %clang_cc1 -triple powerpc64le-unknown-unknown \
-// RUN: -emit-llvm %s -o - -target-cpu pwr9 | FileCheck %s
+// RUN: -emit-llvm %s -o - -target-cpu pwr9 | \
+// RUN:FileCheck %s --check-prefix=CHECK-64
// RUN: %clang_cc1 -triple powerpc64-unknown-aix \
-// RUN:-emit-llvm %s -o - -target-cpu pwr9 | FileCheck %s
+// RUN:-emit-llvm %s -o - -target-cpu pwr9 | \
+// RUN:FileCheck %s --check-prefix=CHECK-64
// RUN: %clang_cc1 -triple powerpc-unknown-unknown \
// RUN:-emit-llvm %s -o - -target-cpu pwr9 | FileCheck %s
// RUN: %clang_cc1 -triple powerpcle-unknown-unknown \
@@ -15,21 +18,23 @@
// The darn class of builtins are Power 9 and up and only darn_32 works in
// 32 bit mode.
-// CHECK-LABEL: @testdarn(
-// CHECK: [[TMP0:%.*]] = call i64 @llvm.ppc.darn()
-// CHECK-NEXT:ret i64 [[TMP0]]
+#ifdef __PPC64__
+// CHECK-64-LABEL: @testdarn(
+// CHECK-64: [[TMP0:%.*]] = call i64 @llvm.ppc.darn()
+// CHECK-64-NEXT:ret i64 [[TMP0]]
//
long long testdarn(void) {
return __darn();
}
-// CHECK-LABEL: @testdarn_raw(
-// CHECK: [[TMP0:%.*]] = call i64 @llvm.ppc.darnraw()
-// CHECK-NEXT:ret i64 [[TMP0]]
+// CHECK-64-LABEL: @testdarn_raw(
+// CHECK-64: [[TMP0:%.*]] = call i64 @llvm.ppc.darnraw()
+// CHECK-64-NEXT:ret i64 [[TMP0]]
//
long long testdarn_raw(void) {
return __darn_raw();
}
+#endif
// CHECK-LABEL: @testdarn_32(
// CHECK: [[TMP0:%.*]] = call i32 @llvm.ppc.darn32()
diff --git a/clang/test/CodeGen/builtins-ppc-xlcompat-error.c
b/clang/test/CodeGen/builtins-ppc-xlcompat-error.c
index 28bf2e4df8d66..4d5ab184e9a79 100644
--- a/clang/test/CodeGen/builtins-ppc-xlcompat-error.c
+++ b/clang/test/CodeGen/builtins-ppc-xlcompat-error.c
@@ -96,6 +96,14 @@ long long testdivde(long long dividend, long long divisor) {
unsigned long long testdivdeu(unsigned long long dividend, unsigned long long
divisor) {
return __divdeu(dividend, divisor); //expected-error {{this builtin is only
available on 64-bit targets}}
}
+
+int test_darn() {
+ return __darn(); //expected-error {{this builtin is only available on 64-bit
targets}}
+}
+
+int test_darn_raw() {
+ return __darn_raw(); //expected-error {{this builtin is only available on
64-bit targets}}
+}
#endif
unsigned long test_mfspr(void) {
diff --git
[clang] b93359e - [PowerPC] Support for vector bool int128 on vector comparison builtins
Author: Albion Fung
Date: 2021-09-21T16:29:37-05:00
New Revision: b93359ea3fe59ea0c652f5e61ee68231e2fb60c4
URL:
https://github.com/llvm/llvm-project/commit/b93359ea3fe59ea0c652f5e61ee68231e2fb60c4
DIFF:
https://github.com/llvm/llvm-project/commit/b93359ea3fe59ea0c652f5e61ee68231e2fb60c4.diff
LOG: [PowerPC] Support for vector bool int128 on vector comparison builtins
This patch implements support for the type vector bool int128
for arguments on vector comparison builtins listed below,
which would otherwise crash due to ambiguity.
The following builtins are added:
vec_all_eq (vector bool __int128, vector bool __int128)
vec_all_ne (vector bool __int128, vector bool __int128)
vec_any_eq (vector bool __int128, vector bool __int128)
vec_any_ne (vector bool __int128, vector bool __int128)
vec_cmpne(vector bool __int128 a, vector bool __int128 b)
vec_cmpeq(vector bool __int128 a, vector bool __int128 b)
Differential revision: https://reviews.llvm.org/D110084
Added:
Modified:
clang/lib/Headers/altivec.h
clang/test/CodeGen/builtins-ppc-p10vector.c
Removed:
diff --git a/clang/lib/Headers/altivec.h b/clang/lib/Headers/altivec.h
index fa9100a2639db..239c93d5b115c 100644
--- a/clang/lib/Headers/altivec.h
+++ b/clang/lib/Headers/altivec.h
@@ -1810,6 +1810,11 @@ vec_cmpeq(vector unsigned __int128 __a, vector unsigned
__int128 __b) {
return (vector bool __int128)__builtin_altivec_vcmpequq(
(vector bool __int128)__a, (vector bool __int128)__b);
}
+
+static __inline__ vector bool __int128 __ATTRS_o_ai
+vec_cmpeq(vector bool __int128 __a, vector bool __int128 __b) {
+ return (vector bool __int128)__builtin_altivec_vcmpequq(__a, __b);
+}
#endif
#ifdef __POWER9_VECTOR__
@@ -1887,6 +1892,11 @@ vec_cmpne(vector signed __int128 __a, vector signed
__int128 __b) {
return (vector bool __int128) ~(__builtin_altivec_vcmpequq(
(vector bool __int128)__a, (vector bool __int128)__b));
}
+
+static __inline__ vector bool __int128 __ATTRS_o_ai
+vec_cmpne(vector bool __int128 __a, vector bool __int128 __b) {
+ return (vector bool __int128) ~(__builtin_altivec_vcmpequq(__a, __b));
+}
#endif
/* vec_cmpnez */
@@ -14870,6 +14880,11 @@ static __inline__ int __ATTRS_o_ai vec_all_eq(vector
unsigned __int128 __a,
vector unsigned __int128 __b) {
return __builtin_altivec_vcmpequq_p(__CR6_LT, __a, __b);
}
+
+static __inline__ int __ATTRS_o_ai vec_all_eq(vector bool __int128 __a,
+ vector bool __int128 __b) {
+ return __builtin_altivec_vcmpequq_p(__CR6_LT, __a, __b);
+}
#endif
/* vec_all_ge */
@@ -15815,6 +15830,11 @@ static __inline__ int __ATTRS_o_ai vec_all_ne(vector
unsigned __int128 __a,
vector unsigned __int128 __b) {
return __builtin_altivec_vcmpequq_p(__CR6_EQ, __a, __b);
}
+
+static __inline__ int __ATTRS_o_ai vec_all_ne(vector bool __int128 __a,
+ vector bool __int128 __b) {
+ return __builtin_altivec_vcmpequq_p(__CR6_EQ, __a, __b);
+}
#endif
/* vec_all_nge */
@@ -16104,6 +16124,11 @@ static __inline__ int __ATTRS_o_ai vec_any_eq(vector
unsigned __int128 __a,
vector unsigned __int128 __b) {
return __builtin_altivec_vcmpequq_p(__CR6_EQ_REV, __a, __b);
}
+
+static __inline__ int __ATTRS_o_ai vec_any_eq(vector bool __int128 __a,
+ vector bool __int128 __b) {
+ return __builtin_altivec_vcmpequq_p(__CR6_EQ_REV, __a, __b);
+}
#endif
/* vec_any_ge */
@@ -17079,6 +17104,11 @@ static __inline__ int __ATTRS_o_ai vec_any_ne(vector
unsigned __int128 __a,
vector unsigned __int128 __b) {
return __builtin_altivec_vcmpequq_p(__CR6_LT_REV, __a, __b);
}
+
+static __inline__ int __ATTRS_o_ai vec_any_ne(vector bool __int128 __a,
+ vector bool __int128 __b) {
+ return __builtin_altivec_vcmpequq_p(__CR6_LT_REV, __a, __b);
+}
#endif
/* vec_any_nge */
diff --git a/clang/test/CodeGen/builtins-ppc-p10vector.c
b/clang/test/CodeGen/builtins-ppc-p10vector.c
index f97b445509267..8816ae8028ebf 100644
--- a/clang/test/CodeGen/builtins-ppc-p10vector.c
+++ b/clang/test/CodeGen/builtins-ppc-p10vector.c
@@ -19,6 +19,7 @@ vector signed long long vslla, vsllb;
vector unsigned long long vulla, vullb, vullc;
vector signed __int128 vsi128a, vsi128b, vsi128c;
vector unsigned __int128 vui128a, vui128b, vui128c;
+vector bool __int128 vbi128a, vbi128b;
vector float vfa, vfb;
vector double vda, vdb;
float fa;
@@ -1637,6 +1638,13 @@ vector bool __int128 test_vec_cmpeq_u128(void) {
return vec_cmpeq(vui128a, vui128b);
}
+vector bool __int128 test_vec_cmpeq_bool_int128(void) {
+ // CHECK-LABEL: @test_vec_cmpeq_bool_int128(
+ //
[clang] 9d4faa8 - [PowerPC] Implement cmplxl builtins
Author: Albion Fung
Date: 2021-08-19T21:36:43-05:00
New Revision: 9d4faa8ac3e7f98b1ca09951d4d3a015aeedab38
URL:
https://github.com/llvm/llvm-project/commit/9d4faa8ac3e7f98b1ca09951d4d3a015aeedab38
DIFF:
https://github.com/llvm/llvm-project/commit/9d4faa8ac3e7f98b1ca09951d4d3a015aeedab38.diff
LOG: [PowerPC] Implement cmplxl builtins
This patch implements the builtins for cmplxl by utilising
__builtin_complex. This builtin is implemented to match XL
functionality.
Differential revision: https://reviews.llvm.org/D107138
Added:
Modified:
clang/lib/Basic/Targets/PPC.cpp
clang/test/CodeGen/builtins-ppc-xlcompat-cmplx.c
Removed:
diff --git a/clang/lib/Basic/Targets/PPC.cpp b/clang/lib/Basic/Targets/PPC.cpp
index c15d2df33f9f..c8afb71e7dfd 100644
--- a/clang/lib/Basic/Targets/PPC.cpp
+++ b/clang/lib/Basic/Targets/PPC.cpp
@@ -237,6 +237,7 @@ static void defineXLCompatMacros(MacroBuilder ) {
Builder.defineMacro("__fsqrt", "__builtin_ppc_fsqrt");
Builder.defineMacro("__fsqrts", "__builtin_ppc_fsqrts");
Builder.defineMacro("__addex", "__builtin_ppc_addex");
+ Builder.defineMacro("__cmplxl", "__builtin_complex");
}
/// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific
diff --git a/clang/test/CodeGen/builtins-ppc-xlcompat-cmplx.c
b/clang/test/CodeGen/builtins-ppc-xlcompat-cmplx.c
index f3274fe19c1f..5e1f6a60bc2c 100644
--- a/clang/test/CodeGen/builtins-ppc-xlcompat-cmplx.c
+++ b/clang/test/CodeGen/builtins-ppc-xlcompat-cmplx.c
@@ -226,3 +226,115 @@ double _Complex testcmplx(double real, double imag) {
float _Complex testcmplxf(float real, float imag) {
return __cmplxf(real, imag);
}
+
+// 64BIT-LABEL: @test_xl_cmplxl(
+// 64BIT-NEXT: entry:
+// 64BIT-NEXT:[[RETVAL:%.*]] = alloca { ppc_fp128, ppc_fp128 }, align 16
+// 64BIT-NEXT:[[LDA_ADDR:%.*]] = alloca ppc_fp128, align 16
+// 64BIT-NEXT:[[LDB_ADDR:%.*]] = alloca ppc_fp128, align 16
+// 64BIT-NEXT:store ppc_fp128 [[LDA:%.*]], ppc_fp128* [[LDA_ADDR]], align
16
+// 64BIT-NEXT:store ppc_fp128 [[LDB:%.*]], ppc_fp128* [[LDB_ADDR]], align
16
+// 64BIT-NEXT:[[TMP0:%.*]] = load ppc_fp128, ppc_fp128* [[LDA_ADDR]],
align 16
+// 64BIT-NEXT:[[TMP1:%.*]] = load ppc_fp128, ppc_fp128* [[LDB_ADDR]],
align 16
+// 64BIT-NEXT:[[RETVAL_REALP:%.*]] = getelementptr inbounds { ppc_fp128,
ppc_fp128 }, { ppc_fp128, ppc_fp128 }* [[RETVAL]], i32 0, i32 0
+// 64BIT-NEXT:[[RETVAL_IMAGP:%.*]] = getelementptr inbounds { ppc_fp128,
ppc_fp128 }, { ppc_fp128, ppc_fp128 }* [[RETVAL]], i32 0, i32 1
+// 64BIT-NEXT:store ppc_fp128 [[TMP0]], ppc_fp128* [[RETVAL_REALP]], align
16
+// 64BIT-NEXT:store ppc_fp128 [[TMP1]], ppc_fp128* [[RETVAL_IMAGP]], align
16
+// 64BIT-NEXT:[[TMP2:%.*]] = load { ppc_fp128, ppc_fp128 }, { ppc_fp128,
ppc_fp128 }* [[RETVAL]], align 16
+// 64BIT-NEXT:ret { ppc_fp128, ppc_fp128 } [[TMP2]]
+//
+// 64BITLE-LABEL: @test_xl_cmplxl(
+// 64BITLE-NEXT: entry:
+// 64BITLE-NEXT:[[RETVAL:%.*]] = alloca { ppc_fp128, ppc_fp128 }, align 16
+// 64BITLE-NEXT:[[LDA_ADDR:%.*]] = alloca ppc_fp128, align 16
+// 64BITLE-NEXT:[[LDB_ADDR:%.*]] = alloca ppc_fp128, align 16
+// 64BITLE-NEXT:store ppc_fp128 [[LDA:%.*]], ppc_fp128* [[LDA_ADDR]],
align 16
+// 64BITLE-NEXT:store ppc_fp128 [[LDB:%.*]], ppc_fp128* [[LDB_ADDR]],
align 16
+// 64BITLE-NEXT:[[TMP0:%.*]] = load ppc_fp128, ppc_fp128* [[LDA_ADDR]],
align 16
+// 64BITLE-NEXT:[[TMP1:%.*]] = load ppc_fp128, ppc_fp128* [[LDB_ADDR]],
align 16
+// 64BITLE-NEXT:[[RETVAL_REALP:%.*]] = getelementptr inbounds { ppc_fp128,
ppc_fp128 }, { ppc_fp128, ppc_fp128 }* [[RETVAL]], i32 0, i32 0
+// 64BITLE-NEXT:[[RETVAL_IMAGP:%.*]] = getelementptr inbounds { ppc_fp128,
ppc_fp128 }, { ppc_fp128, ppc_fp128 }* [[RETVAL]], i32 0, i32 1
+// 64BITLE-NEXT:store ppc_fp128 [[TMP0]], ppc_fp128* [[RETVAL_REALP]],
align 16
+// 64BITLE-NEXT:store ppc_fp128 [[TMP1]], ppc_fp128* [[RETVAL_IMAGP]],
align 16
+// 64BITLE-NEXT:[[TMP2:%.*]] = load { ppc_fp128, ppc_fp128 }, { ppc_fp128,
ppc_fp128 }* [[RETVAL]], align 16
+// 64BITLE-NEXT:ret { ppc_fp128, ppc_fp128 } [[TMP2]]
+//
+// 64BITAIX-LABEL: @test_xl_cmplxl(
+// 64BITAIX-NEXT: entry:
+// 64BITAIX-NEXT:[[RETVAL:%.*]] = alloca { double, double }, align 4
+// 64BITAIX-NEXT:[[LDA_ADDR:%.*]] = alloca double, align 8
+// 64BITAIX-NEXT:[[LDB_ADDR:%.*]] = alloca double, align 8
+// 64BITAIX-NEXT:store double [[LDA:%.*]], double* [[LDA_ADDR]], align 8
+// 64BITAIX-NEXT:store double [[LDB:%.*]], double* [[LDB_ADDR]], align 8
+// 64BITAIX-NEXT:[[TMP0:%.*]] = load double, double* [[LDA_ADDR]], align 8
+// 64BITAIX-NEXT:[[TMP1:%.*]] = load double, double* [[LDB_ADDR]], align 8
+// 64BITAIX-NEXT:[[RETVAL_REALP:%.*]] = getelementptr inbounds { double,
double }, { double, double }* [[RETVAL]], i32 0, i32 0
+// 64BITAIX-NEXT:
[clang] 18526b0 - [PowerPC] Changed sema checking range for tdw td builtin
Author: Albion Fung
Date: 2021-07-26T18:44:33-05:00
New Revision: 18526b0d661f28e79cb70bfd712cedf9e7085154
URL:
https://github.com/llvm/llvm-project/commit/18526b0d661f28e79cb70bfd712cedf9e7085154
DIFF:
https://github.com/llvm/llvm-project/commit/18526b0d661f28e79cb70bfd712cedf9e7085154.diff
LOG: [PowerPC] Changed sema checking range for tdw td builtin
To match xlc behaviour and definition in the PowerPC ISA3.1,
it is a better idea to have ibm-clang produce an error when a
0 is passed to the builtin, which will match xlc's behaviour.
This patch changes the accepted range from 0 to 31 to 1 to 31.
Differential revision: https://reviews.llvm.org/D106817
Added:
Modified:
clang/lib/Sema/SemaChecking.cpp
clang/test/CodeGen/builtins-ppc-xlcompat-error.c
Removed:
diff --git a/clang/lib/Sema/SemaChecking.cpp b/clang/lib/Sema/SemaChecking.cpp
index e00eef4c05dd..de75c10417e7 100644
--- a/clang/lib/Sema/SemaChecking.cpp
+++ b/clang/lib/Sema/SemaChecking.cpp
@@ -3395,7 +3395,7 @@ bool Sema::CheckPPCBuiltinFunctionCall(const TargetInfo
, unsigned BuiltinID,
return SemaBuiltinConstantArgRange(TheCall, 3, 0, 7);
case PPC::BI__builtin_ppc_tw:
case PPC::BI__builtin_ppc_tdw:
-return SemaBuiltinConstantArgRange(TheCall, 2, 0, 31);
+return SemaBuiltinConstantArgRange(TheCall, 2, 1, 31);
case PPC::BI__builtin_ppc_cmpeqb:
case PPC::BI__builtin_ppc_setb:
case PPC::BI__builtin_ppc_maddhd:
diff --git a/clang/test/CodeGen/builtins-ppc-xlcompat-error.c
b/clang/test/CodeGen/builtins-ppc-xlcompat-error.c
index 1f18134f3292..28bf2e4df8d6 100644
--- a/clang/test/CodeGen/builtins-ppc-xlcompat-error.c
+++ b/clang/test/CodeGen/builtins-ppc-xlcompat-error.c
@@ -17,9 +17,11 @@ extern unsigned long ula;
void test_trap(void) {
#ifdef __PPC64__
- __tdw(lla, llb, 50); //expected-error {{argument value 50 is outside the
valid range [0, 31]}}
+ __tdw(lla, llb, 50); //expected-error {{argument value 50 is outside the
valid range [1, 31]}}
+ __tdw(lla, llb, 0); //expected-error {{argument value 0 is outside the valid
range [1, 31]}}
#endif
- __tw(ia, ib, 50); //expected-error {{argument value 50 is outside the valid
range [0, 31]}}
+ __tw(ia, ib, 50); //expected-error {{argument value 50 is outside the valid
range [1, 31]}}
+ __tw(ia, ib, 0); //expected-error {{argument value 0 is outside the valid
range [1, 31]}}
}
void test_builtin_ppc_rldimi() {
___
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[clang] 2fd1520 - [PowerPC] Implemented mtmsr, mfspr, mtspr Builtins
Author: Albion Fung
Date: 2021-07-20T17:51:00-05:00
New Revision: 2fd1520247de6ba1679e7288e3678fb7f8ca2183
URL:
https://github.com/llvm/llvm-project/commit/2fd1520247de6ba1679e7288e3678fb7f8ca2183
DIFF:
https://github.com/llvm/llvm-project/commit/2fd1520247de6ba1679e7288e3678fb7f8ca2183.diff
LOG: [PowerPC] Implemented mtmsr, mfspr, mtspr Builtins
Implemented builtins for mtmsr, mfspr, mtspr on PowerPC;
the patch is intended for XL Compatibility.
Differential revision: https://reviews.llvm.org/D106130
Added:
llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-mfspr-mtspr-64bit-only.ll
llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-mfspr-mtspr-aix32.ll
Modified:
clang/include/clang/Basic/BuiltinsPPC.def
clang/lib/Basic/Targets/PPC.cpp
clang/lib/CodeGen/CGBuiltin.cpp
clang/test/CodeGen/builtins-ppc-xlcompat-error.c
clang/test/CodeGen/builtins-ppc-xlcompat-move-tofrom-regs.c
llvm/include/llvm/IR/IntrinsicsPowerPC.td
llvm/lib/Target/PowerPC/PPCInstr64Bit.td
llvm/lib/Target/PowerPC/PPCInstrInfo.td
llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-move-tofrom-regs.ll
Removed:
diff --git a/clang/include/clang/Basic/BuiltinsPPC.def
b/clang/include/clang/Basic/BuiltinsPPC.def
index 10743ac95a1f..7d46cb96a302 100644
--- a/clang/include/clang/Basic/BuiltinsPPC.def
+++ b/clang/include/clang/Basic/BuiltinsPPC.def
@@ -124,6 +124,9 @@ BUILTIN(__builtin_ppc_dcbtstt, "vv*", "")
BUILTIN(__builtin_ppc_dcbtt, "vv*", "")
BUILTIN(__builtin_ppc_mftbu, "Ui","")
BUILTIN(__builtin_ppc_mfmsr, "Ui", "")
+BUILTIN(__builtin_ppc_mfspr, "ULiIi", "")
+BUILTIN(__builtin_ppc_mtmsr, "vUi", "")
+BUILTIN(__builtin_ppc_mtspr, "vIiULi", "")
BUILTIN(__builtin_ppc_stfiw, "viC*d", "")
BUILTIN(__builtin_ppc_get_timebase, "ULLi", "n")
diff --git a/clang/lib/Basic/Targets/PPC.cpp b/clang/lib/Basic/Targets/PPC.cpp
index dd8e92e0c43b..a8dd6a3fb2ad 100644
--- a/clang/lib/Basic/Targets/PPC.cpp
+++ b/clang/lib/Basic/Targets/PPC.cpp
@@ -217,6 +217,9 @@ static void defineXLCompatMacros(MacroBuilder ) {
Builder.defineMacro("__dcbtt", "__builtin_ppc_dcbtt");
Builder.defineMacro("__mftbu", "__builtin_ppc_mftbu");
Builder.defineMacro("__mfmsr", "__builtin_ppc_mfmsr");
+ Builder.defineMacro("__mtmsr", "__builtin_ppc_mtmsr");
+ Builder.defineMacro("__mfspr", "__builtin_ppc_mfspr");
+ Builder.defineMacro("__mtspr", "__builtin_ppc_mtspr");
}
/// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific
diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
index 1551ddde282a..46316d0b295e 100644
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -15690,6 +15690,20 @@ Value *CodeGenFunction::EmitPPCBuiltinExpr(unsigned
BuiltinID,
case PPC::BI__builtin_ppc_lharx:
case PPC::BI__builtin_ppc_lbarx:
return emitPPCLoadReserveIntrinsic(*this, BuiltinID, E);
+ case PPC::BI__builtin_ppc_mfspr: {
+llvm::Type *RetType = CGM.getDataLayout().getTypeSizeInBits(VoidPtrTy) ==
32
+ ? Int32Ty
+ : Int64Ty;
+Function *F = CGM.getIntrinsic(Intrinsic::ppc_mfspr, RetType);
+return Builder.CreateCall(F, Ops);
+ }
+ case PPC::BI__builtin_ppc_mtspr: {
+llvm::Type *RetType = CGM.getDataLayout().getTypeSizeInBits(VoidPtrTy) ==
32
+ ? Int32Ty
+ : Int64Ty;
+Function *F = CGM.getIntrinsic(Intrinsic::ppc_mtspr, RetType);
+return Builder.CreateCall(F, Ops);
+ }
case PPC::BI__builtin_ppc_popcntb: {
Value *ArgValue = EmitScalarExpr(E->getArg(0));
llvm::Type *ArgType = ArgValue->getType();
diff --git a/clang/test/CodeGen/builtins-ppc-xlcompat-error.c
b/clang/test/CodeGen/builtins-ppc-xlcompat-error.c
index 1220576dafac..1f18134f3292 100644
--- a/clang/test/CodeGen/builtins-ppc-xlcompat-error.c
+++ b/clang/test/CodeGen/builtins-ppc-xlcompat-error.c
@@ -12,6 +12,8 @@ extern long long lla, llb;
extern int ia, ib;
extern unsigned int ui;
extern unsigned long long ull;
+extern const int cia;
+extern unsigned long ula;
void test_trap(void) {
#ifdef __PPC64__
@@ -93,3 +95,11 @@ unsigned long long testdivdeu(unsigned long long dividend,
unsigned long long di
return __divdeu(dividend, divisor); //expected-error {{this builtin is only
available on 64-bit targets}}
}
#endif
+
+unsigned long test_mfspr(void) {
+ return __mfspr(cia); //expected-error {{argument to '__builtin_ppc_mfspr'
must be a constant integer}}
+}
+
+void test_mtspr(void) {
+ __mtspr(cia, ula); //expected-error {{argument to '__builtin_ppc_mtspr'
must be a constant integer}}
+}
diff --git a/clang/test/CodeGen/builtins-ppc-xlcompat-move-tofrom-regs.c
b/clang/test/CodeGen/builtins-ppc-xlcompat-move-tofrom-regs.c
index c05b1ebe80cb..ea9a2215ccf1 100644
--- a/clang/test/CodeGen/builtins-ppc-xlcompat-move-tofrom-regs.c
+++
[clang] 3434ac9 - [PowerPC] Store, load, move from and to registers related builtins
Author: Albion Fung
Date: 2021-07-20T15:46:14-05:00
New Revision: 3434ac9e39026ae19870a3356d744649dc85777e
URL:
https://github.com/llvm/llvm-project/commit/3434ac9e39026ae19870a3356d744649dc85777e
DIFF:
https://github.com/llvm/llvm-project/commit/3434ac9e39026ae19870a3356d744649dc85777e.diff
LOG: [PowerPC] Store, load, move from and to registers related builtins
This patch implements store, load, move from and to registers related
builtins, as well as the builtin for stfiw. The patch aims to provide
feature parady with xlC on AIX.
Differential revision: https://reviews.llvm.org/D105946
Added:
clang/test/CodeGen/builtins-ppc-xlcompat-move-tofrom-regs.c
clang/test/CodeGen/builtins-ppc-xlcompat-prefetch.c
clang/test/CodeGen/builtins-ppc-xlcompat-stfiw.c
llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-stfiw.ll
llvm/test/CodeGen/builtins-ppc-xlcompat-move-tofrom-regs.ll
llvm/test/CodeGen/builtins-ppc-xlcompat-prefetch.ll
Modified:
clang/include/clang/Basic/BuiltinsPPC.def
clang/lib/Basic/Targets/PPC.cpp
clang/lib/CodeGen/CGBuiltin.cpp
clang/lib/Sema/SemaChecking.cpp
clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond.c
llvm/include/llvm/IR/IntrinsicsPowerPC.td
llvm/lib/Target/PowerPC/PPC.td
llvm/lib/Target/PowerPC/PPCInstrInfo.td
llvm/lib/Target/PowerPC/PPCInstrVSX.td
llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-LoadReserve-StoreCond.ll
Removed:
diff --git a/clang/include/clang/Basic/BuiltinsPPC.def
b/clang/include/clang/Basic/BuiltinsPPC.def
index 5f8bbf6adb87..10743ac95a1f 100644
--- a/clang/include/clang/Basic/BuiltinsPPC.def
+++ b/clang/include/clang/Basic/BuiltinsPPC.def
@@ -59,8 +59,11 @@ BUILTIN(__builtin_ppc_fetch_and_swap, "UiUiD*Ui", "")
BUILTIN(__builtin_ppc_fetch_and_swaplp, "ULiULiD*ULi", "")
BUILTIN(__builtin_ppc_ldarx, "LiLiD*", "")
BUILTIN(__builtin_ppc_lwarx, "iiD*", "")
+BUILTIN(__builtin_ppc_lharx, "isD*", "")
+BUILTIN(__builtin_ppc_lbarx, "UiUcD*", "")
BUILTIN(__builtin_ppc_stdcx, "iLiD*Li", "")
BUILTIN(__builtin_ppc_stwcx, "iiD*i", "")
+BUILTIN(__builtin_ppc_sthcx, "isD*s", "")
BUILTIN(__builtin_ppc_tdw, "vLLiLLiIUi", "")
BUILTIN(__builtin_ppc_tw, "viiIUi", "")
BUILTIN(__builtin_ppc_trap, "vi", "")
@@ -117,6 +120,11 @@ BUILTIN(__builtin_ppc_fnmsub, "", "")
BUILTIN(__builtin_ppc_fnmsubs, "", "")
BUILTIN(__builtin_ppc_fre, "dd", "")
BUILTIN(__builtin_ppc_fres, "ff", "")
+BUILTIN(__builtin_ppc_dcbtstt, "vv*", "")
+BUILTIN(__builtin_ppc_dcbtt, "vv*", "")
+BUILTIN(__builtin_ppc_mftbu, "Ui","")
+BUILTIN(__builtin_ppc_mfmsr, "Ui", "")
+BUILTIN(__builtin_ppc_stfiw, "viC*d", "")
BUILTIN(__builtin_ppc_get_timebase, "ULLi", "n")
diff --git a/clang/lib/Basic/Targets/PPC.cpp b/clang/lib/Basic/Targets/PPC.cpp
index f4e646a7417f..dd8e92e0c43b 100644
--- a/clang/lib/Basic/Targets/PPC.cpp
+++ b/clang/lib/Basic/Targets/PPC.cpp
@@ -118,8 +118,12 @@ static void defineXLCompatMacros(MacroBuilder ) {
Builder.defineMacro("__fetch_and_swaplp", "__builtin_ppc_fetch_and_swaplp");
Builder.defineMacro("__ldarx", "__builtin_ppc_ldarx");
Builder.defineMacro("__lwarx", "__builtin_ppc_lwarx");
+ Builder.defineMacro("__lharx", "__builtin_ppc_lharx");
+ Builder.defineMacro("__lbarx", "__builtin_ppc_lbarx");
+ Builder.defineMacro("__stfiw", "__builtin_ppc_stfiw");
Builder.defineMacro("__stdcx", "__builtin_ppc_stdcx");
Builder.defineMacro("__stwcx", "__builtin_ppc_stwcx");
+ Builder.defineMacro("__sthcx", "__builtin_ppc_sthcx");
Builder.defineMacro("__tdw", "__builtin_ppc_tdw");
Builder.defineMacro("__tw", "__builtin_ppc_tw");
Builder.defineMacro("__trap", "__builtin_ppc_trap");
@@ -209,6 +213,10 @@ static void defineXLCompatMacros(MacroBuilder ) {
Builder.defineMacro("__rdlam", "__builtin_ppc_rdlam");
Builder.defineMacro("__setflm", "__builtin_setflm");
Builder.defineMacro("__setrnd", "__builtin_setrnd");
+ Builder.defineMacro("__dcbtstt", "__builtin_ppc_dcbtstt");
+ Builder.defineMacro("__dcbtt", "__builtin_ppc_dcbtt");
+ Builder.defineMacro("__mftbu", "__builtin_ppc_mftbu");
+ Builder.defineMacro("__mfmsr", "__builtin_ppc_mfmsr");
}
/// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific
diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
index 2bc194e1c795..1551ddde282a 100644
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -1012,6 +1012,14 @@ static llvm::Value
*emitPPCLoadReserveIntrinsic(CodeGenFunction ,
AsmOS << "lwarx ";
RetType = CGF.Int32Ty;
break;
+ case clang::PPC::BI__builtin_ppc_lharx:
+AsmOS << "lharx ";
+RetType = CGF.Int16Ty;
+break;
+ case clang::PPC::BI__builtin_ppc_lbarx:
+AsmOS << "lbarx ";
+RetType = CGF.Int8Ty;
+break;
default:
llvm_unreachable("Expected only PowerPC load reserve intrinsics");
}
@@ -15562,6 +15570,13 @@
[clang] 0d4f63e - Revert "[PowerPC] Extra test case for LDARX"
Author: Albion Fung
Date: 2021-07-19T21:27:02-05:00
New Revision: 0d4f63e1b78f6e44f7e406737c2639e96427f1d6
URL:
https://github.com/llvm/llvm-project/commit/0d4f63e1b78f6e44f7e406737c2639e96427f1d6
DIFF:
https://github.com/llvm/llvm-project/commit/0d4f63e1b78f6e44f7e406737c2639e96427f1d6.diff
LOG: Revert "[PowerPC] Extra test case for LDARX"
This reverts commit 1d3e77e7a8421a9d2dd13e3ef499ea967ea8f85c as
some buildbots seem to be unable to obtain the target
powerpc64le-unknown-linux-gnu.
Added:
Modified:
Removed:
clang/test/CodeGen/builtins-ppc-xlcompat-check-ldarx-opt.ll
diff --git a/clang/test/CodeGen/builtins-ppc-xlcompat-check-ldarx-opt.ll
b/clang/test/CodeGen/builtins-ppc-xlcompat-check-ldarx-opt.ll
deleted file mode 100644
index ed9bee2003b7..
--- a/clang/test/CodeGen/builtins-ppc-xlcompat-check-ldarx-opt.ll
+++ /dev/null
@@ -1,88 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
-; RUN: -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK
-; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
-; RUN: -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK
-; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
-; RUN: -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-AIX
-
-; Function Attrs: nounwind uwtable
-define dso_local signext i32 @main() local_unnamed_addr {
-; CHECK-LABEL: main:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT:li 3, -1
-; CHECK-NEXT:li 4, 0
-; CHECK-NEXT:std 3, -8(1)
-; CHECK-NEXT:addi 3, 1, -8
-; CHECK-NEXT:.p2align 5
-; CHECK-NEXT: .LBB0_1: # %do.body
-; CHECK-NEXT:#
-; CHECK-NEXT:#APP
-; CHECK-NEXT:ldarx 5, 0, 3
-; CHECK-NEXT:#NO_APP
-; CHECK-NEXT:stdcx. 4, 0, 3
-; CHECK-NEXT:mfocrf 5, 128
-; CHECK-NEXT:srwi 5, 5, 28
-; CHECK-NEXT:cmplwi 5, 0
-; CHECK-NEXT:beq 0, .LBB0_1
-; CHECK-NEXT: # %bb.2: # %do.end
-; CHECK-NEXT:ld 3, -8(1)
-; CHECK-NEXT:li 4, 55
-; CHECK-NEXT:cmpldi 3, 0
-; CHECK-NEXT:li 3, 66
-; CHECK-NEXT:iseleq 3, 4, 3
-; CHECK-NEXT:blr
-;
-; CHECK-AIX-LABEL: main:
-; CHECK-AIX: # %bb.0: # %entry
-; CHECK-AIX-NEXT:li 3, -1
-; CHECK-AIX-NEXT:li 4, 0
-; CHECK-AIX-NEXT:std 3, -8(1)
-; CHECK-AIX-NEXT:addi 3, 1, -8
-; CHECK-AIX-NEXT:.align 5
-; CHECK-AIX-NEXT: L..BB0_1: # %do.body
-; CHECK-AIX-NEXT:#
-; CHECK-AIX-NEXT:#APP
-; CHECK-AIX-NEXT:ldarx 5, 0, 3
-; CHECK-AIX-NEXT:#NO_APP
-; CHECK-AIX-NEXT:stdcx. 4, 0, 3
-; CHECK-AIX-NEXT:mfocrf 5, 128
-; CHECK-AIX-NEXT:srwi 5, 5, 28
-; CHECK-AIX-NEXT:cmplwi 5, 0
-; CHECK-AIX-NEXT:beq 0, L..BB0_1
-; CHECK-AIX-NEXT: # %bb.2: # %do.end
-; CHECK-AIX-NEXT:ld 3, -8(1)
-; CHECK-AIX-NEXT:li 4, 55
-; CHECK-AIX-NEXT:cmpldi 3, 0
-; CHECK-AIX-NEXT:li 3, 66
-; CHECK-AIX-NEXT:iseleq 3, 4, 3
-; CHECK-AIX-NEXT:blr
-entry:
- %x64 = alloca i64, align 8
- %0 = bitcast i64* %x64 to i8*
- call void @llvm.lifetime.start.p0i8(i64 8, i8* nonnull %0)
- store i64 -1, i64* %x64, align 8
- br label %do.body
-
-do.body: ; preds = %do.body, %entry
- %1 = call i64 asm sideeffect "ldarx $0, ${1:y}", "=r,*Z,~{memory}"(i64*
nonnull %x64)
- %2 = call i32 @llvm.ppc.stdcx(i8* nonnull %0, i64 0)
- %tobool.not = icmp eq i32 %2, 0
- br i1 %tobool.not, label %do.body, label %do.end
-
-do.end: ; preds = %do.body
- %3 = load i64, i64* %x64, align 8
- %cmp = icmp eq i64 %3, 0
- %. = select i1 %cmp, i32 55, i32 66
- call void @llvm.lifetime.end.p0i8(i64 8, i8* nonnull %0)
- ret i32 %.
-}
-
-; Function Attrs: argmemonly mustprogress nofree nosync nounwind willreturn
-declare void @llvm.lifetime.start.p0i8(i64 immarg, i8* nocapture)
-
-; Function Attrs: nounwind writeonly
-declare i32 @llvm.ppc.stdcx(i8*, i64)
-
-; Function Attrs: argmemonly mustprogress nofree nosync nounwind willreturn
-declare void @llvm.lifetime.end.p0i8(i64 immarg, i8* nocapture)
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[clang] 1d3e77e - [PowerPC] Extra test case for LDARX
Author: Albion Fung
Date: 2021-07-19T20:03:45-05:00
New Revision: 1d3e77e7a8421a9d2dd13e3ef499ea967ea8f85c
URL:
https://github.com/llvm/llvm-project/commit/1d3e77e7a8421a9d2dd13e3ef499ea967ea8f85c
DIFF:
https://github.com/llvm/llvm-project/commit/1d3e77e7a8421a9d2dd13e3ef499ea967ea8f85c.diff
LOG: [PowerPC] Extra test case for LDARX
An extra test case added for the builtin __LDARX.
Differential revision: https://reviews.llvm.org/D105926
Added:
clang/test/CodeGen/builtins-ppc-xlcompat-check-ldarx-opt.ll
Modified:
Removed:
diff --git a/clang/test/CodeGen/builtins-ppc-xlcompat-check-ldarx-opt.ll
b/clang/test/CodeGen/builtins-ppc-xlcompat-check-ldarx-opt.ll
new file mode 100644
index ..ed9bee2003b7
--- /dev/null
+++ b/clang/test/CodeGen/builtins-ppc-xlcompat-check-ldarx-opt.ll
@@ -0,0 +1,88 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN: -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
+; RUN: -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
+; RUN: -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-AIX
+
+; Function Attrs: nounwind uwtable
+define dso_local signext i32 @main() local_unnamed_addr {
+; CHECK-LABEL: main:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT:li 3, -1
+; CHECK-NEXT:li 4, 0
+; CHECK-NEXT:std 3, -8(1)
+; CHECK-NEXT:addi 3, 1, -8
+; CHECK-NEXT:.p2align 5
+; CHECK-NEXT: .LBB0_1: # %do.body
+; CHECK-NEXT:#
+; CHECK-NEXT:#APP
+; CHECK-NEXT:ldarx 5, 0, 3
+; CHECK-NEXT:#NO_APP
+; CHECK-NEXT:stdcx. 4, 0, 3
+; CHECK-NEXT:mfocrf 5, 128
+; CHECK-NEXT:srwi 5, 5, 28
+; CHECK-NEXT:cmplwi 5, 0
+; CHECK-NEXT:beq 0, .LBB0_1
+; CHECK-NEXT: # %bb.2: # %do.end
+; CHECK-NEXT:ld 3, -8(1)
+; CHECK-NEXT:li 4, 55
+; CHECK-NEXT:cmpldi 3, 0
+; CHECK-NEXT:li 3, 66
+; CHECK-NEXT:iseleq 3, 4, 3
+; CHECK-NEXT:blr
+;
+; CHECK-AIX-LABEL: main:
+; CHECK-AIX: # %bb.0: # %entry
+; CHECK-AIX-NEXT:li 3, -1
+; CHECK-AIX-NEXT:li 4, 0
+; CHECK-AIX-NEXT:std 3, -8(1)
+; CHECK-AIX-NEXT:addi 3, 1, -8
+; CHECK-AIX-NEXT:.align 5
+; CHECK-AIX-NEXT: L..BB0_1: # %do.body
+; CHECK-AIX-NEXT:#
+; CHECK-AIX-NEXT:#APP
+; CHECK-AIX-NEXT:ldarx 5, 0, 3
+; CHECK-AIX-NEXT:#NO_APP
+; CHECK-AIX-NEXT:stdcx. 4, 0, 3
+; CHECK-AIX-NEXT:mfocrf 5, 128
+; CHECK-AIX-NEXT:srwi 5, 5, 28
+; CHECK-AIX-NEXT:cmplwi 5, 0
+; CHECK-AIX-NEXT:beq 0, L..BB0_1
+; CHECK-AIX-NEXT: # %bb.2: # %do.end
+; CHECK-AIX-NEXT:ld 3, -8(1)
+; CHECK-AIX-NEXT:li 4, 55
+; CHECK-AIX-NEXT:cmpldi 3, 0
+; CHECK-AIX-NEXT:li 3, 66
+; CHECK-AIX-NEXT:iseleq 3, 4, 3
+; CHECK-AIX-NEXT:blr
+entry:
+ %x64 = alloca i64, align 8
+ %0 = bitcast i64* %x64 to i8*
+ call void @llvm.lifetime.start.p0i8(i64 8, i8* nonnull %0)
+ store i64 -1, i64* %x64, align 8
+ br label %do.body
+
+do.body: ; preds = %do.body, %entry
+ %1 = call i64 asm sideeffect "ldarx $0, ${1:y}", "=r,*Z,~{memory}"(i64*
nonnull %x64)
+ %2 = call i32 @llvm.ppc.stdcx(i8* nonnull %0, i64 0)
+ %tobool.not = icmp eq i32 %2, 0
+ br i1 %tobool.not, label %do.body, label %do.end
+
+do.end: ; preds = %do.body
+ %3 = load i64, i64* %x64, align 8
+ %cmp = icmp eq i64 %3, 0
+ %. = select i1 %cmp, i32 55, i32 66
+ call void @llvm.lifetime.end.p0i8(i64 8, i8* nonnull %0)
+ ret i32 %.
+}
+
+; Function Attrs: argmemonly mustprogress nofree nosync nounwind willreturn
+declare void @llvm.lifetime.start.p0i8(i64 immarg, i8* nocapture)
+
+; Function Attrs: nounwind writeonly
+declare i32 @llvm.ppc.stdcx(i8*, i64)
+
+; Function Attrs: argmemonly mustprogress nofree nosync nounwind willreturn
+declare void @llvm.lifetime.end.p0i8(i64 immarg, i8* nocapture)
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[clang] f1aca5a - [PowerPC] Fix L[D|W]ARX Implementation
Author: Albion Fung
Date: 2021-07-13T11:02:07-05:00
New Revision: f1aca5ac96ebd0beadfa68a474c5947d3bc8c109
URL:
https://github.com/llvm/llvm-project/commit/f1aca5ac96ebd0beadfa68a474c5947d3bc8c109
DIFF:
https://github.com/llvm/llvm-project/commit/f1aca5ac96ebd0beadfa68a474c5947d3bc8c109.diff
LOG: [PowerPC] Fix L[D|W]ARX Implementation
LDARX and LWARX sometimes gets optimized out by the compiler
when it is critical to the correctness of the code. This inline asm generation
ensures that it preserved.
Differential Revision: https://reviews.llvm.org/D105754
Added:
Modified:
clang/lib/CodeGen/CGBuiltin.cpp
clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond-64bit-only.c
clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond.c
llvm/include/llvm/IR/IntrinsicsPowerPC.td
llvm/lib/Target/PowerPC/PPCInstr64Bit.td
llvm/lib/Target/PowerPC/PPCInstrInfo.td
llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-LoadReserve-StoreCond-64bit-only.ll
llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-LoadReserve-StoreCond.ll
Removed:
diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
index 355ed8ffbfea1..baa1436954183 100644
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -994,6 +994,46 @@ static llvm::Value *EmitBitTestIntrinsic(CodeGenFunction
,
ShiftedByte, llvm::ConstantInt::get(CGF.Int8Ty, 1), "bittest.res");
}
+static llvm::Value *emitPPCLoadReserveIntrinsic(CodeGenFunction ,
+unsigned BuiltinID,
+const CallExpr *E) {
+ Value *Addr = CGF.EmitScalarExpr(E->getArg(0));
+
+ SmallString<64> Asm;
+ raw_svector_ostream AsmOS(Asm);
+ llvm::IntegerType *RetType = CGF.Int32Ty;
+
+ switch (BuiltinID) {
+ case clang::PPC::BI__builtin_ppc_ldarx:
+AsmOS << "ldarx ";
+RetType = CGF.Int64Ty;
+break;
+ case clang::PPC::BI__builtin_ppc_lwarx:
+AsmOS << "lwarx ";
+RetType = CGF.Int32Ty;
+break;
+ default:
+llvm_unreachable("Expected only PowerPC load reserve intrinsics");
+ }
+
+ AsmOS << "$0, ${1:y}";
+
+ std::string Constraints = "=r,*Z,~{memory}";
+ std::string MachineClobbers = CGF.getTarget().getClobbers();
+ if (!MachineClobbers.empty()) {
+Constraints += ',';
+Constraints += MachineClobbers;
+ }
+
+ llvm::Type *IntPtrType = RetType->getPointerTo();
+ llvm::FunctionType *FTy =
+ llvm::FunctionType::get(RetType, {IntPtrType}, false);
+
+ llvm::InlineAsm *IA =
+ llvm::InlineAsm::get(FTy, Asm, Constraints, /*hasSideEffects=*/true);
+ return CGF.Builder.CreateCall(IA, {Addr});
+}
+
namespace {
enum class MSVCSetJmpKind {
_setjmpex,
@@ -15532,6 +15572,9 @@ Value *CodeGenFunction::EmitPPCBuiltinExpr(unsigned
BuiltinID,
return MakeBinaryAtomicValue(*this, AtomicRMWInst::Xchg, E,
llvm::AtomicOrdering::Monotonic);
}
+ case PPC::BI__builtin_ppc_ldarx:
+ case PPC::BI__builtin_ppc_lwarx:
+return emitPPCLoadReserveIntrinsic(*this, BuiltinID, E);
}
}
diff --git
a/clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond-64bit-only.c
b/clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond-64bit-only.c
index 80bb4de424a13..f0a8ff184311a 100644
--- a/clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond-64bit-only.c
+++ b/clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond-64bit-only.c
@@ -1,27 +1,23 @@
// RUN: not %clang_cc1 -triple=powerpc-unknown-aix -emit-llvm %s -o - 2>&1 |\
// RUN: FileCheck %s --check-prefix=CHECK32-ERROR
-// RUN: %clang_cc1 -triple=powerpc64-unknown-aix -emit-llvm %s -o - | \
+// RUN: %clang_cc1 -O2 -triple=powerpc64-unknown-aix -emit-llvm %s -o - | \
// RUN: FileCheck %s --check-prefix=CHECK64
-// RUN: %clang_cc1 -triple=powerpc64le-unknown-unknown -emit-llvm %s \
+// RUN: %clang_cc1 -O2 -triple=powerpc64le-unknown-unknown -emit-llvm %s \
// RUN: -o - | FileCheck %s --check-prefix=CHECK64
-// RUN: %clang_cc1 -triple=powerpc64-unknown-unknown -emit-llvm %s \
+// RUN: %clang_cc1 -O2 -triple=powerpc64-unknown-unknown -emit-llvm %s \
// RUN: -o - | FileCheck %s --check-prefix=CHECK64
long test_ldarx(volatile long* a) {
// CHECK64-LABEL: @test_ldarx
- // CHECK64: %0 = load i64*, i64** %a.addr, align 8
- // CHECK64: %1 = bitcast i64* %0 to i8*
- // CHECK64: %2 = call i64 @llvm.ppc.ldarx(i8* %1)
+ // CHECK64: %0 = tail call i64 asm sideeffect "ldarx $0, ${1:y}",
"=r,*Z,~{memory}"(i64* %a)
// CHECK32-ERROR: error: this builtin is only available on 64-bit targets
return __ldarx(a);
}
int test_stdcx(volatile long* addr, long val) {
// CHECK64-LABEL: @test_stdcx
- // CHECK64: %0 = load i64*, i64** %addr.addr, align 8
- // CHECK64: %1 = bitcast i64* %0 to i8*
- // CHECK64: %2 = load i64, i64* %val.addr, align 8
- // CHECK64: %3 = call
[clang] ef49d92 - [PowerPC] Implement trap and conversion builtins for XL compatibility
Author: Albion Fung
Date: 2021-07-12T11:04:17-05:00
New Revision: ef49d925e2a788248473b847a0e51835c6ca854f
URL:
https://github.com/llvm/llvm-project/commit/ef49d925e2a788248473b847a0e51835c6ca854f
DIFF:
https://github.com/llvm/llvm-project/commit/ef49d925e2a788248473b847a0e51835c6ca854f.diff
LOG: [PowerPC] Implement trap and conversion builtins for XL compatibility
This patch implements trap and FP to and from double conversions. The builtins
generate code that mirror what is generated from the XL compiler. Intrinsics
are named conventionally with builtin_ppc, but are aliased to provide the same
builtin names as the XL compiler.
Differential Revision: https://reviews.llvm.org/D103668
Added:
clang/test/CodeGen/builtins-ppc-xlcompat-conversionfunc.c
clang/test/CodeGen/builtins-ppc-xlcompat-error.c
clang/test/CodeGen/builtins-ppc-xlcompat-trap-64bit-only.c
clang/test/CodeGen/builtins-ppc-xlcompat-trap.c
llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-conversionfunc.ll
llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap-64bit-only.ll
llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap.ll
Modified:
clang/include/clang/Basic/BuiltinsPPC.def
clang/lib/Basic/Targets/PPC.cpp
clang/lib/Sema/SemaChecking.cpp
llvm/include/llvm/IR/IntrinsicsPowerPC.td
llvm/lib/Target/PowerPC/PPCInstr64Bit.td
llvm/lib/Target/PowerPC/PPCInstrInfo.td
Removed:
diff --git a/clang/include/clang/Basic/BuiltinsPPC.def
b/clang/include/clang/Basic/BuiltinsPPC.def
index baaf5db9d1453..6a72cc089df7e 100644
--- a/clang/include/clang/Basic/BuiltinsPPC.def
+++ b/clang/include/clang/Basic/BuiltinsPPC.def
@@ -59,6 +59,18 @@ BUILTIN(__builtin_ppc_ldarx, "LiLiD*", "")
BUILTIN(__builtin_ppc_lwarx, "iiD*", "")
BUILTIN(__builtin_ppc_stdcx, "iLiD*Li", "")
BUILTIN(__builtin_ppc_stwcx, "iiD*i", "")
+BUILTIN(__builtin_ppc_tdw, "vLLiLLiIUi", "")
+BUILTIN(__builtin_ppc_tw, "viiIUi", "")
+BUILTIN(__builtin_ppc_trap, "vi", "")
+BUILTIN(__builtin_ppc_trapd, "vLi", "")
+BUILTIN(__builtin_ppc_fcfid, "dd", "")
+BUILTIN(__builtin_ppc_fcfud, "dd", "")
+BUILTIN(__builtin_ppc_fctid, "dd", "")
+BUILTIN(__builtin_ppc_fctidz, "dd", "")
+BUILTIN(__builtin_ppc_fctiw, "dd", "")
+BUILTIN(__builtin_ppc_fctiwz, "dd", "")
+BUILTIN(__builtin_ppc_fctudz, "dd", "")
+BUILTIN(__builtin_ppc_fctuwz, "dd", "")
BUILTIN(__builtin_ppc_get_timebase, "ULLi", "n")
diff --git a/clang/lib/Basic/Targets/PPC.cpp b/clang/lib/Basic/Targets/PPC.cpp
index e3c77b2e4450b..b77b4a38bc46f 100644
--- a/clang/lib/Basic/Targets/PPC.cpp
+++ b/clang/lib/Basic/Targets/PPC.cpp
@@ -112,6 +112,18 @@ static void defineXLCompatMacros(MacroBuilder ) {
Builder.defineMacro("__lwarx", "__builtin_ppc_lwarx");
Builder.defineMacro("__stdcx", "__builtin_ppc_stdcx");
Builder.defineMacro("__stwcx", "__builtin_ppc_stwcx");
+ Builder.defineMacro("__tdw", "__builtin_ppc_tdw");
+ Builder.defineMacro("__tw", "__builtin_ppc_tw");
+ Builder.defineMacro("__trap", "__builtin_ppc_trap");
+ Builder.defineMacro("__trapd", "__builtin_ppc_trapd");
+ Builder.defineMacro("__fcfid", "__builtin_ppc_fcfid");
+ Builder.defineMacro("__fcfud", "__builtin_ppc_fcfud");
+ Builder.defineMacro("__fctid", "__builtin_ppc_fctid");
+ Builder.defineMacro("__fctidz", "__builtin_ppc_fctidz");
+ Builder.defineMacro("__fctiw", "__builtin_ppc_fctiw");
+ Builder.defineMacro("__fctiwz", "__builtin_ppc_fctiwz");
+ Builder.defineMacro("__fctudz", "__builtin_ppc_fctudz");
+ Builder.defineMacro("__fctuwz", "__builtin_ppc_fctuwz");
}
/// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific
diff --git a/clang/lib/Sema/SemaChecking.cpp b/clang/lib/Sema/SemaChecking.cpp
index 64d838d2cd74f..99621a226dea6 100644
--- a/clang/lib/Sema/SemaChecking.cpp
+++ b/clang/lib/Sema/SemaChecking.cpp
@@ -3267,6 +3267,8 @@ static bool isPPC_64Builtin(unsigned BuiltinID) {
case PPC::BI__builtin_bpermd:
case PPC::BI__builtin_ppc_ldarx:
case PPC::BI__builtin_ppc_stdcx:
+ case PPC::BI__builtin_ppc_tdw:
+ case PPC::BI__builtin_ppc_trapd:
return true;
}
return false;
@@ -3347,6 +3349,9 @@ bool Sema::CheckPPCBuiltinFunctionCall(const TargetInfo
, unsigned BuiltinID,
return SemaBuiltinConstantArgRange(TheCall, 2, 0, 7);
case PPC::BI__builtin_vsx_xxpermx:
return SemaBuiltinConstantArgRange(TheCall, 3, 0, 7);
+ case PPC::BI__builtin_ppc_tw:
+ case PPC::BI__builtin_ppc_tdw:
+return SemaBuiltinConstantArgRange(TheCall, 2, 0, 31);
#define CUSTOM_BUILTIN(Name, Intr, Types, Acc) \
case PPC::BI__builtin_##Name: \
return SemaBuiltinPPCMMACall(TheCall, Types);
diff --git a/clang/test/CodeGen/builtins-ppc-xlcompat-conversionfunc.c
b/clang/test/CodeGen/builtins-ppc-xlcompat-conversionfunc.c
new file mode 100644
index 0..babc16fcd3a7e
--- /dev/null
+++ b/clang/test/CodeGen/builtins-ppc-xlcompat-conversionfunc.c
@@ -0,0 +1,121 @@
+//
[clang] 203b48c - [PowerPC] Removed a test case meant for a later patch
Author: Albion Fung
Date: 2021-07-05T22:31:17-05:00
New Revision: 203b48c71a0db835bd0d6869311578dbd7cc8b71
URL:
https://github.com/llvm/llvm-project/commit/203b48c71a0db835bd0d6869311578dbd7cc8b71
DIFF:
https://github.com/llvm/llvm-project/commit/203b48c71a0db835bd0d6869311578dbd7cc8b71.diff
LOG: [PowerPC] Removed a test case meant for a later patch
A test case meant for a later patch was accidentally
included.
Original Patch: https://reviews.llvm.org/D105236
Differential revision: https://reviews.llvm.org/D105454
Added:
Modified:
Removed:
clang/test/CodeGen/builtins-ppc-xlcompat-error.c
diff --git a/clang/test/CodeGen/builtins-ppc-xlcompat-error.c
b/clang/test/CodeGen/builtins-ppc-xlcompat-error.c
deleted file mode 100644
index 01ac35ca64fd..
--- a/clang/test/CodeGen/builtins-ppc-xlcompat-error.c
+++ /dev/null
@@ -1,17 +0,0 @@
-// REQUIRES: powerpc-registered-target
-// RUN: %clang_cc1 -triple powerpc64-unknown-unknown -fsyntax-only \
-// RUN: -Wall -Werror -verify %s
-// RUN: %clang_cc1 -triple powerpc64le-unknown-unknown -fsyntax-only \
-// RUN: -Wall -Werror -verify %s
-// RUN: %clang_cc1 -triple powerpc64-unknown-aix -fsyntax-only \
-// RUN: -Wall -Werror -verify %s
-// RUN: %clang_cc1 -triple powerpc-unknown-aix -fsyntax-only \
-// RUN: -Wall -Werror -verify %s
-
-long long lla, llb;
-int ia, ib;
-
-void test_trap(void) {
- __tdw(lla, llb, 50); //expected-error {{argument value 50 is outside the
valid range [0, 31]}}
- __tw(ia, ib, 50); //expected-error {{argument value 50 is outside the valid
range [0, 31]}}
-}
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[clang] 7d10dd6 - [PowerPC] Implament Load and Reserve and Store Conditional Builtins
Author: Albion Fung
Date: 2021-07-05T21:35:41-05:00
New Revision: 7d10dd60ce126a6a0a29aa1f3948f596bd6e4fb0
URL:
https://github.com/llvm/llvm-project/commit/7d10dd60ce126a6a0a29aa1f3948f596bd6e4fb0
DIFF:
https://github.com/llvm/llvm-project/commit/7d10dd60ce126a6a0a29aa1f3948f596bd6e4fb0.diff
LOG: [PowerPC] Implament Load and Reserve and Store Conditional Builtins
This patch implaments the load and reserve and store conditional
builtins for the PowerPC target, in order to have feature parody with
xlC on AIX.
Differential revision: https://reviews.llvm.org/D105236
Added:
clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond-64bit-only.c
clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond.c
clang/test/CodeGen/builtins-ppc-xlcompat-error.c
llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-LoadReserve-StoreCond-64bit-only.ll
llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-LoadReserve-StoreCond.ll
Modified:
clang/include/clang/Basic/BuiltinsPPC.def
clang/lib/Basic/Targets/PPC.cpp
clang/lib/Sema/SemaChecking.cpp
llvm/include/llvm/IR/IntrinsicsPowerPC.td
llvm/lib/Target/PowerPC/PPCInstr64Bit.td
llvm/lib/Target/PowerPC/PPCInstrInfo.td
Removed:
diff --git a/clang/include/clang/Basic/BuiltinsPPC.def
b/clang/include/clang/Basic/BuiltinsPPC.def
index e07632d415109..baaf5db9d1453 100644
--- a/clang/include/clang/Basic/BuiltinsPPC.def
+++ b/clang/include/clang/Basic/BuiltinsPPC.def
@@ -55,6 +55,10 @@ BUILTIN(__builtin_ppc_fetch_and_or, "UiUiD*Ui", "")
BUILTIN(__builtin_ppc_fetch_and_orlp, "ULiULiD*ULi", "")
BUILTIN(__builtin_ppc_fetch_and_swap, "UiUiD*Ui", "")
BUILTIN(__builtin_ppc_fetch_and_swaplp, "ULiULiD*ULi", "")
+BUILTIN(__builtin_ppc_ldarx, "LiLiD*", "")
+BUILTIN(__builtin_ppc_lwarx, "iiD*", "")
+BUILTIN(__builtin_ppc_stdcx, "iLiD*Li", "")
+BUILTIN(__builtin_ppc_stwcx, "iiD*i", "")
BUILTIN(__builtin_ppc_get_timebase, "ULLi", "n")
diff --git a/clang/lib/Basic/Targets/PPC.cpp b/clang/lib/Basic/Targets/PPC.cpp
index d431dda970222..e3c77b2e4450b 100644
--- a/clang/lib/Basic/Targets/PPC.cpp
+++ b/clang/lib/Basic/Targets/PPC.cpp
@@ -108,6 +108,10 @@ static void defineXLCompatMacros(MacroBuilder ) {
Builder.defineMacro("__fetch_and_orlp", "__builtin_ppc_fetch_and_orlp");
Builder.defineMacro("__fetch_and_swap", "__builtin_ppc_fetch_and_swap");
Builder.defineMacro("__fetch_and_swaplp", "__builtin_ppc_fetch_and_swaplp");
+ Builder.defineMacro("__ldarx", "__builtin_ppc_ldarx");
+ Builder.defineMacro("__lwarx", "__builtin_ppc_lwarx");
+ Builder.defineMacro("__stdcx", "__builtin_ppc_stdcx");
+ Builder.defineMacro("__stwcx", "__builtin_ppc_stwcx");
}
/// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific
diff --git a/clang/lib/Sema/SemaChecking.cpp b/clang/lib/Sema/SemaChecking.cpp
index 4d04f3017a2ef..0c9d2010e3777 100644
--- a/clang/lib/Sema/SemaChecking.cpp
+++ b/clang/lib/Sema/SemaChecking.cpp
@@ -3265,6 +3265,8 @@ static bool isPPC_64Builtin(unsigned BuiltinID) {
case PPC::BI__builtin_divde:
case PPC::BI__builtin_divdeu:
case PPC::BI__builtin_bpermd:
+ case PPC::BI__builtin_ppc_ldarx:
+ case PPC::BI__builtin_ppc_stdcx:
return true;
}
return false;
diff --git
a/clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond-64bit-only.c
b/clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond-64bit-only.c
new file mode 100644
index 0..80bb4de424a13
--- /dev/null
+++ b/clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond-64bit-only.c
@@ -0,0 +1,27 @@
+// RUN: not %clang_cc1 -triple=powerpc-unknown-aix -emit-llvm %s -o - 2>&1 |\
+// RUN: FileCheck %s --check-prefix=CHECK32-ERROR
+// RUN: %clang_cc1 -triple=powerpc64-unknown-aix -emit-llvm %s -o - | \
+// RUN: FileCheck %s --check-prefix=CHECK64
+// RUN: %clang_cc1 -triple=powerpc64le-unknown-unknown -emit-llvm %s \
+// RUN: -o - | FileCheck %s --check-prefix=CHECK64
+// RUN: %clang_cc1 -triple=powerpc64-unknown-unknown -emit-llvm %s \
+// RUN: -o - | FileCheck %s --check-prefix=CHECK64
+
+long test_ldarx(volatile long* a) {
+ // CHECK64-LABEL: @test_ldarx
+ // CHECK64: %0 = load i64*, i64** %a.addr, align 8
+ // CHECK64: %1 = bitcast i64* %0 to i8*
+ // CHECK64: %2 = call i64 @llvm.ppc.ldarx(i8* %1)
+ // CHECK32-ERROR: error: this builtin is only available on 64-bit targets
+ return __ldarx(a);
+}
+
+int test_stdcx(volatile long* addr, long val) {
+ // CHECK64-LABEL: @test_stdcx
+ // CHECK64: %0 = load i64*, i64** %addr.addr, align 8
+ // CHECK64: %1 = bitcast i64* %0 to i8*
+ // CHECK64: %2 = load i64, i64* %val.addr, align 8
+ // CHECK64: %3 = call i32 @llvm.ppc.stdcx(i8* %1, i64 %2)
+ // CHECK32-ERROR: error: this builtin is only available on 64-bit targets
+ return __stdcx(addr, val);
+}
diff --git a/clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond.c
[clang] 994bb93 - [PowerPC] Moving defineXLCompatMacros() definition
Author: Quinn Pham
Date: 2021-06-15T14:25:43-05:00
New Revision: 994bb937f020a014c7039151169649a7076ca9b1
URL:
https://github.com/llvm/llvm-project/commit/994bb937f020a014c7039151169649a7076ca9b1
DIFF:
https://github.com/llvm/llvm-project/commit/994bb937f020a014c7039151169649a7076ca9b1.diff
LOG: [PowerPC] Moving defineXLCompatMacros() definition
Moving the definition of the defineXLCompatMacros function from
the header file clang/lib/Basic/Targets/PPC.h to the source file
clang/lib/Basic/Targets/PPC.cpp.
Differential revision: https://reviews.llvm.org/D104125
Added:
Modified:
clang/lib/Basic/Targets/PPC.cpp
clang/lib/Basic/Targets/PPC.h
Removed:
diff --git a/clang/lib/Basic/Targets/PPC.cpp b/clang/lib/Basic/Targets/PPC.cpp
index 9f5c615ba752..3dfc0c0751e4 100644
--- a/clang/lib/Basic/Targets/PPC.cpp
+++ b/clang/lib/Basic/Targets/PPC.cpp
@@ -81,6 +81,24 @@ bool
PPCTargetInfo::handleTargetFeatures(std::vector ,
return true;
}
+static void defineXLCompatMacros(MacroBuilder ) {
+ Builder.defineMacro("__popcntb", "__builtin_ppc_popcntb");
+ Builder.defineMacro("__eieio", "__builtin_ppc_eieio");
+ Builder.defineMacro("__iospace_eieio", "__builtin_ppc_iospace_eieio");
+ Builder.defineMacro("__isync", "__builtin_ppc_isync");
+ Builder.defineMacro("__lwsync", "__builtin_ppc_lwsync");
+ Builder.defineMacro("__iospace_lwsync", "__builtin_ppc_iospace_lwsync");
+ Builder.defineMacro("__sync", "__builtin_ppc_sync");
+ Builder.defineMacro("__iospace_sync", "__builtin_ppc_iospace_sync");
+ Builder.defineMacro("__dcbfl", "__builtin_ppc_dcbfl");
+ Builder.defineMacro("__dcbflp", "__builtin_ppc_dcbflp");
+ Builder.defineMacro("__dcbst", "__builtin_ppc_dcbst");
+ Builder.defineMacro("__dcbt", "__builtin_ppc_dcbt");
+ Builder.defineMacro("__dcbtst", "__builtin_ppc_dcbtst");
+ Builder.defineMacro("__dcbz", "__builtin_ppc_dcbz");
+ Builder.defineMacro("__icbt", "__builtin_ppc_icbt");
+}
+
/// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific
/// #defines that are not tied to a specific subtarget.
void PPCTargetInfo::getTargetDefines(const LangOptions ,
diff --git a/clang/lib/Basic/Targets/PPC.h b/clang/lib/Basic/Targets/PPC.h
index 2ceb0b0cbf1c..554f2174fee0 100644
--- a/clang/lib/Basic/Targets/PPC.h
+++ b/clang/lib/Basic/Targets/PPC.h
@@ -350,24 +350,6 @@ class LLVM_LIBRARY_VISIBILITY PPCTargetInfo : public
TargetInfo {
bool isSPRegName(StringRef RegName) const override {
return RegName.equals("r1") || RegName.equals("x1");
}
-
- void defineXLCompatMacros(MacroBuilder ) const {
-Builder.defineMacro("__popcntb", "__builtin_ppc_popcntb");
-Builder.defineMacro("__eieio", "__builtin_ppc_eieio");
-Builder.defineMacro("__iospace_eieio", "__builtin_ppc_iospace_eieio");
-Builder.defineMacro("__isync", "__builtin_ppc_isync");
-Builder.defineMacro("__lwsync", "__builtin_ppc_lwsync");
-Builder.defineMacro("__iospace_lwsync", "__builtin_ppc_iospace_lwsync");
-Builder.defineMacro("__sync", "__builtin_ppc_sync");
-Builder.defineMacro("__iospace_sync", "__builtin_ppc_iospace_sync");
-Builder.defineMacro("__dcbfl", "__builtin_ppc_dcbfl");
-Builder.defineMacro("__dcbflp", "__builtin_ppc_dcbflp");
-Builder.defineMacro("__dcbst", "__builtin_ppc_dcbst");
-Builder.defineMacro("__dcbt", "__builtin_ppc_dcbt");
-Builder.defineMacro("__dcbtst", "__builtin_ppc_dcbtst");
-Builder.defineMacro("__dcbz", "__builtin_ppc_dcbz");
-Builder.defineMacro("__icbt", "__builtin_ppc_icbt");
- }
};
class LLVM_LIBRARY_VISIBILITY PPC32TargetInfo : public PPCTargetInfo {
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[clang] 3b7104a - Fix a test case that should check whether or not it is passed into lld
Author: Albion Fung
Date: 2021-02-25T10:32:32-05:00
New Revision: 3b7104a2f2033d100aebb605c46fbe0495ea320b
URL:
https://github.com/llvm/llvm-project/commit/3b7104a2f2033d100aebb605c46fbe0495ea320b
DIFF:
https://github.com/llvm/llvm-project/commit/3b7104a2f2033d100aebb605c46fbe0495ea320b.diff
LOG: Fix a test case that should check whether or not it is passed into lld
This test case was causing a PowerPC buildbot to fail as it happened to
be named lld-multistage,
which matches with the original regex and therefore fails the check-not.
This should better represent the desired check.
Differential Revision: https://reviews.llvm.org/D97423
Added:
Modified:
clang/test/Driver/hip-sanitize-options.hip
Removed:
diff --git a/clang/test/Driver/hip-sanitize-options.hip
b/clang/test/Driver/hip-sanitize-options.hip
index 6c9a6cc31723..19b09868213d 100644
--- a/clang/test/Driver/hip-sanitize-options.hip
+++ b/clang/test/Driver/hip-sanitize-options.hip
@@ -26,15 +26,15 @@
// RUN: %s 2>&1 | FileCheck -check-prefixes=FAIL %s
// CHECK-NOT: {{"[^"]*clang[^"]*".* "-fcuda-is-device".* "-fsanitize=address"}}
-// CHECK-NOT: {{"[^"]*lld[^"]*".* ".*hip.bc"}}
+// CHECK-NOT: {{"[^"]*lld(\.exe){0,1}".* ".*hip.bc"}}
// CHECK: {{"[^"]*clang[^"]*".* "-triple" "x86_64-unknown-linux-gnu".*
"-fsanitize=address"}}
// NORDC: {{"[^"]*clang[^"]*".* "-fcuda-is-device".* "-fsanitize=address".*}}
"-o" "[[OUT:[^"]*.bc]]"
-// NORDC: {{"[^"]*lld[^"]*".*}} "[[OUT]]" {{".*asanrtl.bc" ".*hip.bc"}}
+// NORDC: {{"[^"]*lld(\.exe){0,1}".*}} "[[OUT]]" {{".*asanrtl.bc" ".*hip.bc"}}
// NORDC: {{"[^"]*clang[^"]*".* "-triple" "x86_64-unknown-linux-gnu".*
"-fsanitize=address"}}
// RDC: {{"[^"]*clang[^"]*".* "-triple" "x86_64-unknown-linux-gnu".*
"-fsanitize=address"}}
// RDC: {{"[^"]*clang[^"]*".* "-emit-llvm-bc".* "-fcuda-is-device".*
"-fsanitize=address".*}} "-o" "[[OUT:[^"]*.bc]]"
-// RDC: {{"[^"]*lld[^"]*".*}} "[[OUT]]" {{".*asanrtl.bc" ".*hip.bc"}}
+// RDC: {{"[^"]*lld(\.exe){0,1}".*}} "[[OUT]]" {{".*asanrtl.bc" ".*hip.bc"}}
// FAIL: AMDGPU address sanitizer runtime library (asanrtl) is not found.
Please install ROCm device library which supports address sanitizer
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[clang] c289297 - [PowerPC] Rename the vector pair intrinsics and builtins to replace the _mma_ prefix by _vsx_
Author: Baptiste Saleil Date: 2020-12-17T13:19:27-05:00 New Revision: c2892978e919bf66535729c70fba73c4c3224548 URL: https://github.com/llvm/llvm-project/commit/c2892978e919bf66535729c70fba73c4c3224548 DIFF: https://github.com/llvm/llvm-project/commit/c2892978e919bf66535729c70fba73c4c3224548.diff LOG: [PowerPC] Rename the vector pair intrinsics and builtins to replace the _mma_ prefix by _vsx_ On PPC, the vector pair instructions are independent from MMA. This patch renames the vector pair LLVM intrinsics and Clang builtins to replace the _mma_ prefix by _vsx_ in their names. We also move the vector pair type/intrinsic/builtin tests to their own files. Differential Revision: https://reviews.llvm.org/D91974 Added: clang/test/CodeGen/builtins-ppc-pair-mma.c clang/test/Sema/ppc-pair-mma-types.c clang/test/SemaCXX/ppc-pair-mma-types.cpp llvm/test/CodeGen/PowerPC/paired-vector-intrinsics.ll Modified: clang/include/clang/Basic/BuiltinsPPC.def clang/lib/CodeGen/CGBuiltin.cpp clang/lib/Sema/SemaChecking.cpp llvm/include/llvm/IR/IntrinsicsPowerPC.td llvm/lib/Target/PowerPC/PPCISelLowering.cpp llvm/lib/Target/PowerPC/PPCInstrPrefix.td llvm/lib/Target/PowerPC/PPCLoopInstrFormPrep.cpp llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp llvm/test/CodeGen/PowerPC/dform-pair-load-store.ll llvm/test/CodeGen/PowerPC/loop-p10-pair-prepare.ll llvm/test/CodeGen/PowerPC/mma-intrinsics.ll llvm/test/CodeGen/PowerPC/mma-outer-product.ll llvm/test/CodeGen/PowerPC/mma-phi-accs.ll llvm/test/CodeGen/PowerPC/more-dq-form-prepare.ll Removed: clang/test/CodeGen/builtins-ppc-mma.c clang/test/Sema/ppc-mma-types.c clang/test/SemaCXX/ppc-mma-types.cpp llvm/test/CodeGen/PowerPC/paired-vector-intrinsics-without-mma.ll diff --git a/clang/include/clang/Basic/BuiltinsPPC.def b/clang/include/clang/Basic/BuiltinsPPC.def index 8975d126b897..39c66f5daeb1 100644 --- a/clang/include/clang/Basic/BuiltinsPPC.def +++ b/clang/include/clang/Basic/BuiltinsPPC.def @@ -7,8 +7,9 @@ //===--===// // // This file defines the PowerPC-specific builtin function database. Users of -// this file must define the BUILTIN macro or the MMA_BUILTIN macro to make use -// of this information. +// this file must define the BUILTIN macro or the CUSTOM_BUILTIN macro to +// make use of this information. The latter is used for builtins requiring +// custom code generation and checking. // //===--===// @@ -18,9 +19,9 @@ // The format of this database matches clang/Basic/Builtins.def except for the // MMA builtins that are using their own format documented below. -#if defined(BUILTIN) && !defined(MMA_BUILTIN) -# define MMA_BUILTIN(ID, TYPES, ACCUMULATE) BUILTIN(__builtin_mma_##ID, "i.", "t") -#elif defined(MMA_BUILTIN) && !defined(BUILTIN) +#if defined(BUILTIN) && !defined(CUSTOM_BUILTIN) +# define CUSTOM_BUILTIN(ID, TYPES, ACCUMULATE) BUILTIN(__builtin_##ID, "i.", "t") +#elif defined(CUSTOM_BUILTIN) && !defined(BUILTIN) # define BUILTIN(ID, TYPES, ATTRS) #endif @@ -659,94 +660,94 @@ BUILTIN(__builtin_setflm, "dd", "") // Cache built-ins BUILTIN(__builtin_dcbf, "vvC*", "") -// MMA built-ins -// All MMA built-ins are declared here using the MMA_BUILTIN macro. Because -// these built-ins rely on target-dependent types and to avoid pervasive change, -// they are type checked manually in Sema using custom type descriptors. -// The first argument of the MMA_BUILTIN macro is the name of the built-in, the -// second argument specifies the type of the function (result value, then each -// argument) as follows: +// Built-ins requiring custom code generation. +// Because these built-ins rely on target-dependent types and to avoid pervasive +// change, they are type checked manually in Sema using custom type descriptors. +// The first argument of the CUSTOM_BUILTIN macro is the name of the built-in +// with its prefix, the second argument specifies the type of the function +// (result value, then each argument) as follows: // i -> Unsigned integer followed by the greatest possible value for that // argument or 0 if no constraint on the value. // (e.g. i15 for a 4-bits value) -// v -> void // V -> Vector type used with MMA builtins (vector unsigned char) -// W -> MMA vector type followed by the size of the vector type. +// W -> PPC Vector type followed by the size of the vector type. // (e.g. W512 for __vector_quad) +// any other descriptor -> Fall back to generic type descriptor decoding. // The 'C' suffix can be used as a suffix to specify the const type. // The '*' suffix can be used as a suffix to specify a pointer to a type. // The third argument is set to true if the builtin accumulates its result into //
[clang] 1af037f - [PowerPC] Correct cpsgn's behaviour on PowerPC to match that of the ABI
Author: Albion Fung
Date: 2020-11-05T15:35:14-05:00
New Revision: 1af037f643fc5499f83d92e5aec199950871d475
URL:
https://github.com/llvm/llvm-project/commit/1af037f643fc5499f83d92e5aec199950871d475
DIFF:
https://github.com/llvm/llvm-project/commit/1af037f643fc5499f83d92e5aec199950871d475.diff
LOG: [PowerPC] Correct cpsgn's behaviour on PowerPC to match that of the ABI
This patch fixes the reversed behaviour exhibited by cpsgn on PPC. It now
matches the ABI.
Differential Revision: https://reviews.llvm.org/D84962
Added:
Modified:
clang/lib/Headers/altivec.h
clang/test/CodeGen/builtins-ppc-vsx.c
Removed:
diff --git a/clang/lib/Headers/altivec.h b/clang/lib/Headers/altivec.h
index 2df420d640f1..24d600e95201 100644
--- a/clang/lib/Headers/altivec.h
+++ b/clang/lib/Headers/altivec.h
@@ -2996,12 +2996,12 @@ static __inline__ void __ATTRS_o_ai
vec_xst_len_r(vector unsigned char __a,
#ifdef __VSX__
static __inline__ vector float __ATTRS_o_ai vec_cpsgn(vector float __a,
vector float __b) {
- return __builtin_vsx_xvcpsgnsp(__a, __b);
+ return __builtin_vsx_xvcpsgnsp(__b, __a);
}
static __inline__ vector double __ATTRS_o_ai vec_cpsgn(vector double __a,
vector double __b) {
- return __builtin_vsx_xvcpsgndp(__a, __b);
+ return __builtin_vsx_xvcpsgndp(__b, __a);
}
#endif
diff --git a/clang/test/CodeGen/builtins-ppc-vsx.c
b/clang/test/CodeGen/builtins-ppc-vsx.c
index d99b0c1e8f41..18aa7d22fa3f 100644
--- a/clang/test/CodeGen/builtins-ppc-vsx.c
+++ b/clang/test/CodeGen/builtins-ppc-vsx.c
@@ -1850,3 +1850,47 @@ void testVectorInt128Pack(){
// CHECK-NEXT-LE: %{{[0-9]+}} = extractelement <2 x i64> %[[V1]], i32 0
}
+
+void test_vector_cpsgn_float(vector float a, vector float b) {
+// CHECK-LABEL: test_vector_cpsgn_float
+// CHECK-DAG: load{{.*}}%__a
+// CHECK-DAG: load{{.*}}%__b
+// CHECK-NOT: SEPARATOR
+// CHECK-DAG: [[RA:%[0-9]+]] = load <4 x float>, <4 x float>* %__a.addr
+// CHECK-DAG: [[RB:%[0-9]+]] = load <4 x float>, <4 x float>* %__b.addr
+// CHECK-NEXT: call <4 x float> @llvm.copysign.v4f32(<4 x float> [[RB]], <4 x
float> [[RA]])
+ vec_cpsgn(a, b);
+}
+
+void test_vector_cpsgn_double(vector double a, vector double b) {
+// CHECK-LABEL: test_vector_cpsgn_double
+// CHECK-DAG: load{{.*}}%__a
+// CHECK-DAG: load{{.*}}%__b
+// CHECK-NOT: SEPARATOR
+// CHECK-DAG: [[RA:%[0-9]+]] = load <2 x double>, <2 x double>* %__a.addr
+// CHECK-DAG: [[RB:%[0-9]+]] = load <2 x double>, <2 x double>* %__b.addr
+// CHECK-NEXT: call <2 x double> @llvm.copysign.v2f64(<2 x double> [[RB]], <2
x double> [[RA]])
+ vec_cpsgn(a, b);
+}
+
+void test_builtin_xvcpsgnsp(vector float a, vector float b) {
+// CHECK-LABEL: test_builtin_xvcpsgnsp
+// CHECK-DAG: load{{.*}}%a
+// CHECK-DAG: load{{.*}}%b
+// CHECK-NOT: SEPARATOR
+// CHECK-DAG: [[RA:%[0-9]+]] = load <4 x float>, <4 x float>* %a.addr
+// CHECK-DAG: [[RB:%[0-9]+]] = load <4 x float>, <4 x float>* %b.addr
+// CHECK-NEXT: call <4 x float> @llvm.copysign.v4f32(<4 x float> [[RA]], <4 x
float> [[RB]])
+ __builtin_vsx_xvcpsgnsp(a, b);
+}
+
+void test_builtin_xvcpsgndp(vector double a, vector double b) {
+// CHECK-LABEL: test_builtin_xvcpsgndp
+// CHECK-DAG: load{{.*}}%a
+// CHECK-DAG: load{{.*}}%b
+// CHECK-NOT: SEPARATOR
+// CHECK-DAG: [[RA:%[0-9]+]] = load <2 x double>, <2 x double>* %a.addr
+// CHECK-DAG: [[RB:%[0-9]+]] = load <2 x double>, <2 x double>* %b.addr
+// CHECK-NEXT: call <2 x double> @llvm.copysign.v2f64(<2 x double> [[RA]], <2
x double> [[RB]])
+ __builtin_vsx_xvcpsgndp(a, b);
+}
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[clang] d30155f - [PowerPC] Implementation of 128-bit Binary Vector Rotate builtins
Author: Albion Fung
Date: 2020-10-16T18:03:22-04:00
New Revision: d30155feaa9c4ddd09cb115fb30ea5810f63af9c
URL:
https://github.com/llvm/llvm-project/commit/d30155feaa9c4ddd09cb115fb30ea5810f63af9c
DIFF:
https://github.com/llvm/llvm-project/commit/d30155feaa9c4ddd09cb115fb30ea5810f63af9c.diff
LOG: [PowerPC] Implementation of 128-bit Binary Vector Rotate builtins
This patch implements 128-bit Binary Vector Rotate builtins for PowerPC10.
Differential Revision: https://reviews.llvm.org/D86819
Added:
llvm/test/CodeGen/PowerPC/p10-vector-rotate.ll
Modified:
clang/include/clang/Basic/BuiltinsPPC.def
clang/lib/Headers/altivec.h
clang/test/CodeGen/builtins-ppc-p10vector.c
llvm/include/llvm/IR/IntrinsicsPowerPC.td
llvm/lib/Target/PowerPC/PPCISelLowering.cpp
llvm/lib/Target/PowerPC/PPCInstrPrefix.td
Removed:
diff --git a/clang/include/clang/Basic/BuiltinsPPC.def
b/clang/include/clang/Basic/BuiltinsPPC.def
index 015411abc508..fe20c9418e8d 100644
--- a/clang/include/clang/Basic/BuiltinsPPC.def
+++ b/clang/include/clang/Basic/BuiltinsPPC.def
@@ -422,6 +422,10 @@ BUILTIN(__builtin_altivec_vextduwvrx, "V2ULLiV4UiV4UiUi",
"")
BUILTIN(__builtin_altivec_vextddvlx, "V2ULLiV2ULLiV2ULLiUi", "")
BUILTIN(__builtin_altivec_vextddvrx, "V2ULLiV2ULLiV2ULLiUi", "")
+// P10 Vector rotate built-ins.
+BUILTIN(__builtin_altivec_vrlqmi, "V1ULLLiV1ULLLiV1ULLLiV1ULLLi", "")
+BUILTIN(__builtin_altivec_vrlqnm, "V1ULLLiV1ULLLiV1ULLLi", "")
+
// VSX built-ins.
BUILTIN(__builtin_vsx_lxvd2x, "V2divC*", "")
diff --git a/clang/lib/Headers/altivec.h b/clang/lib/Headers/altivec.h
index 1d7bc201d330..2df420d640f1 100644
--- a/clang/lib/Headers/altivec.h
+++ b/clang/lib/Headers/altivec.h
@@ -7927,6 +7927,18 @@ vec_rl(vector unsigned long long __a, vector unsigned
long long __b) {
}
#endif
+#ifdef __POWER10_VECTOR__
+static __inline__ vector signed __int128 __ATTRS_o_ai
+vec_rl(vector signed __int128 __a, vector unsigned __int128 __b) {
+ return (__b << __a)|(__b >> ((__CHAR_BIT__ * sizeof(vector signed __int128))
- __a));
+}
+
+static __inline__ vector unsigned __int128 __ATTRS_o_ai
+vec_rl(vector unsigned __int128 __a, vector unsigned __int128 __b) {
+ return (__b << __a)|(__b >> ((__CHAR_BIT__ * sizeof(vector unsigned
__int128)) - __a));
+}
+#endif
+
/* vec_rlmi */
#ifdef __POWER9_VECTOR__
static __inline__ vector unsigned int __ATTRS_o_ai
@@ -7940,8 +7952,24 @@ vec_rlmi(vector unsigned long long __a, vector unsigned
long long __b,
vector unsigned long long __c) {
return __builtin_altivec_vrldmi(__a, __c, __b);
}
+#endif
+
+#ifdef __POWER10_VECTOR__
+static __inline__ vector unsigned __int128 __ATTRS_o_ai
+vec_rlmi(vector unsigned __int128 __a, vector unsigned __int128 __b,
+ vector unsigned __int128 __c) {
+ return __builtin_altivec_vrlqmi(__a, __c, __b);
+}
+
+static __inline__ vector signed __int128 __ATTRS_o_ai
+vec_rlmi(vector signed __int128 __a, vector signed __int128 __b,
+ vector signed __int128 __c) {
+ return __builtin_altivec_vrlqmi(__a, __c, __b);
+}
+#endif
/* vec_rlnm */
+#ifdef __POWER9_VECTOR__
static __inline__ vector unsigned int __ATTRS_o_ai
vec_rlnm(vector unsigned int __a, vector unsigned int __b,
vector unsigned int __c) {
@@ -7957,6 +7985,42 @@ vec_rlnm(vector unsigned long long __a, vector unsigned
long long __b,
}
#endif
+#ifdef __POWER10_VECTOR__
+static __inline__ vector unsigned __int128 __ATTRS_o_ai
+vec_rlnm(vector unsigned __int128 __a, vector unsigned __int128 __b,
+ vector unsigned __int128 __c) {
+ // Merge __b and __c using an appropriate shuffle.
+ vector unsigned char TmpB = (vector unsigned char)__b;
+ vector unsigned char TmpC = (vector unsigned char)__c;
+ vector unsigned char MaskAndShift =
+#ifdef __LITTLE_ENDIAN__
+ __builtin_shufflevector(TmpB, TmpC, -1, -1, -1, -1, -1, -1, -1, -1, 16,
0,
+ 1, -1, -1, -1, -1, -1);
+#else
+ __builtin_shufflevector(TmpB, TmpC, -1, -1, -1, -1, -1, 31, 30, 15, -1,
+ -1, -1, -1, -1, -1, -1, -1);
+#endif
+ return __builtin_altivec_vrlqnm(__a, (vector unsigned __int128)
MaskAndShift);
+}
+
+static __inline__ vector signed __int128 __ATTRS_o_ai
+vec_rlnm(vector signed __int128 __a, vector signed __int128 __b,
+ vector signed __int128 __c) {
+ // Merge __b and __c using an appropriate shuffle.
+ vector unsigned char TmpB = (vector unsigned char)__b;
+ vector unsigned char TmpC = (vector unsigned char)__c;
+ vector unsigned char MaskAndShift =
+#ifdef __LITTLE_ENDIAN__
+ __builtin_shufflevector(TmpB, TmpC, -1, -1, -1, -1, -1, -1, -1, -1, 16,
0,
+ 1, -1, -1, -1, -1, -1);
+#else
+ __builtin_shufflevector(TmpB, TmpC, -1, -1, -1, -1, -1, 31, 30, 15, -1,
+ -1, -1, -1, -1, -1, -1, -1);
+#endif
+ return
[clang] 88cdbea - [PowerPC] Implement Vector signed/unsigned __int128 overloads for the comparison builtins
Author: Albion Fung
Date: 2020-09-23T16:49:40-04:00
New Revision: 88cdbeab417cc716d1da2de2a508d24622f4a4bc
URL:
https://github.com/llvm/llvm-project/commit/88cdbeab417cc716d1da2de2a508d24622f4a4bc
DIFF:
https://github.com/llvm/llvm-project/commit/88cdbeab417cc716d1da2de2a508d24622f4a4bc.diff
LOG: [PowerPC] Implement Vector signed/unsigned __int128 overloads for the
comparison builtins
This patch implements Vector signed/unsigned __int128 overloads for the
comparison builtins.
Differential Revision: https://reviews.llvm.org/D87804
Added:
llvm/test/CodeGen/PowerPC/vec_cmpq.ll
Modified:
clang/include/clang/Basic/BuiltinsPPC.def
clang/lib/Headers/altivec.h
clang/test/CodeGen/builtins-ppc-p10vector.c
llvm/include/llvm/IR/IntrinsicsPowerPC.td
llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
llvm/lib/Target/PowerPC/PPCISelLowering.cpp
Removed:
diff --git a/clang/include/clang/Basic/BuiltinsPPC.def
b/clang/include/clang/Basic/BuiltinsPPC.def
index 5de3584a2755..e236ebdd7082 100644
--- a/clang/include/clang/Basic/BuiltinsPPC.def
+++ b/clang/include/clang/Basic/BuiltinsPPC.def
@@ -156,6 +156,11 @@ BUILTIN(__builtin_altivec_vcmpgtsd, "V2LLiV2LLiV2LLi", "")
BUILTIN(__builtin_altivec_vcmpgtud, "V2LLiV2ULLiV2ULLi", "")
BUILTIN(__builtin_altivec_vcmpgtfp, "V4iV4fV4f", "")
+// P10 Vector compare builtins.
+BUILTIN(__builtin_altivec_vcmpequq, "V1LLLiV1ULLLiV1ULLLi", "")
+BUILTIN(__builtin_altivec_vcmpgtsq, "V1LLLiV1SLLLiV1SLLLi", "")
+BUILTIN(__builtin_altivec_vcmpgtuq, "V1LLLiV1ULLLiV1ULLLi", "")
+
BUILTIN(__builtin_altivec_vmaxsb, "V16ScV16ScV16Sc", "")
BUILTIN(__builtin_altivec_vmaxub, "V16UcV16UcV16Uc", "")
BUILTIN(__builtin_altivec_vmaxsh, "V8SsV8SsV8Ss", "")
diff --git a/clang/lib/Headers/altivec.h b/clang/lib/Headers/altivec.h
index b07e45d3c5a5..d1fcde741a37 100644
--- a/clang/lib/Headers/altivec.h
+++ b/clang/lib/Headers/altivec.h
@@ -1709,6 +1709,20 @@ vec_cmpeq(vector double __a, vector double __b) {
}
#endif
+#ifdef __POWER10_VECTOR__
+static __inline__ vector bool __int128 __ATTRS_o_ai
+vec_cmpeq(vector signed __int128 __a, vector signed __int128 __b) {
+ return (vector bool __int128)__builtin_altivec_vcmpequq(
+ (vector bool __int128)__a, (vector bool __int128)__b);
+}
+
+static __inline__ vector bool __int128 __ATTRS_o_ai
+vec_cmpeq(vector unsigned __int128 __a, vector unsigned __int128 __b) {
+ return (vector bool __int128)__builtin_altivec_vcmpequq(
+ (vector bool __int128)__a, (vector bool __int128)__b);
+}
+#endif
+
#ifdef __POWER9_VECTOR__
/* vec_cmpne */
@@ -1772,6 +1786,20 @@ vec_cmpne(vector float __a, vector float __b) {
(vector int)__b);
}
+#ifdef __POWER10_VECTOR__
+static __inline__ vector bool __int128 __ATTRS_o_ai
+vec_cmpne(vector unsigned __int128 __a, vector unsigned __int128 __b) {
+ return (vector bool __int128) ~(__builtin_altivec_vcmpequq(
+ (vector bool __int128)__a, (vector bool __int128)__b));
+}
+
+static __inline__ vector bool __int128 __ATTRS_o_ai
+vec_cmpne(vector signed __int128 __a, vector signed __int128 __b) {
+ return (vector bool __int128) ~(__builtin_altivec_vcmpequq(
+ (vector bool __int128)__a, (vector bool __int128)__b));
+}
+#endif
+
/* vec_cmpnez */
static __inline__ vector bool char __ATTRS_o_ai
@@ -2018,6 +2046,20 @@ vec_cmpgt(vector double __a, vector double __b) {
}
#endif
+#ifdef __POWER10_VECTOR__
+static __inline__ vector bool __int128 __ATTRS_o_ai
+vec_cmpgt(vector signed __int128 __a, vector signed __int128 __b) {
+ return (vector bool __int128)__builtin_altivec_vcmpgtsq(
+ (vector bool __int128)__a, (vector bool __int128)__b);
+}
+
+static __inline__ vector bool __int128 __ATTRS_o_ai
+vec_cmpgt(vector unsigned __int128 __a, vector unsigned __int128 __b) {
+ return (vector bool __int128)__builtin_altivec_vcmpgtuq(
+ (vector bool __int128)__a, (vector bool __int128)__b);
+}
+#endif
+
/* vec_cmpge */
static __inline__ vector bool char __ATTRS_o_ai
@@ -2078,6 +2120,18 @@ vec_cmpge(vector unsigned long long __a, vector unsigned
long long __b) {
}
#endif
+#ifdef __POWER10_VECTOR__
+static __inline__ vector bool __int128 __ATTRS_o_ai
+vec_cmpge(vector signed __int128 __a, vector signed __int128 __b) {
+ return ~(vec_cmpgt(__b, __a));
+}
+
+static __inline__ vector bool __int128 __ATTRS_o_ai
+vec_cmpge(vector unsigned __int128 __a, vector unsigned __int128 __b) {
+ return ~(vec_cmpgt(__b, __a));
+}
+#endif
+
/* vec_vcmpgefp */
static __inline__ vector bool int __attribute__((__always_inline__))
@@ -2190,6 +2244,18 @@ vec_cmple(vector unsigned long long __a, vector unsigned
long long __b) {
}
#endif
+#ifdef __POWER10_VECTOR__
+static __inline__ vector bool __int128 __ATTRS_o_ai
+vec_cmple(vector signed __int128 __a, vector signed __int128 __b) {
+ return vec_cmpge(__b, __a);
+}
+
+static __inline__ vector
[clang] 2e7117f - [PowerPC] Implement the 128-bit vec_[all|any]_[eq | ne | lt | gt | le | ge] builtins in Clang/LLVM
Author: Amy Kwan
Date: 2020-09-23T16:49:40-04:00
New Revision: 2e7117f847708d2fd1ff2d2961c3439470532b80
URL:
https://github.com/llvm/llvm-project/commit/2e7117f847708d2fd1ff2d2961c3439470532b80
DIFF:
https://github.com/llvm/llvm-project/commit/2e7117f847708d2fd1ff2d2961c3439470532b80.diff
LOG: [PowerPC] Implement the 128-bit vec_[all|any]_[eq | ne | lt | gt | le |
ge] builtins in Clang/LLVM
This patch implements the vec_[all|any]_[eq | ne | lt | gt | le | ge] builtins
for vector signed/unsigned __int128.
Differential Revision: https://reviews.llvm.org/D87910
Added:
Modified:
clang/include/clang/Basic/BuiltinsPPC.def
clang/lib/CodeGen/CGExprScalar.cpp
clang/lib/Headers/altivec.h
clang/test/CodeGen/builtins-ppc-p10vector.c
llvm/include/llvm/IR/IntrinsicsPowerPC.td
llvm/lib/Target/PowerPC/PPCISelLowering.cpp
llvm/test/CodeGen/PowerPC/vec_cmpq.ll
Removed:
diff --git a/clang/include/clang/Basic/BuiltinsPPC.def
b/clang/include/clang/Basic/BuiltinsPPC.def
index e236ebdd7082..91c3f040cb48 100644
--- a/clang/include/clang/Basic/BuiltinsPPC.def
+++ b/clang/include/clang/Basic/BuiltinsPPC.def
@@ -160,6 +160,9 @@ BUILTIN(__builtin_altivec_vcmpgtfp, "V4iV4fV4f", "")
BUILTIN(__builtin_altivec_vcmpequq, "V1LLLiV1ULLLiV1ULLLi", "")
BUILTIN(__builtin_altivec_vcmpgtsq, "V1LLLiV1SLLLiV1SLLLi", "")
BUILTIN(__builtin_altivec_vcmpgtuq, "V1LLLiV1ULLLiV1ULLLi", "")
+BUILTIN(__builtin_altivec_vcmpequq_p, "iiV1ULLLiV1LLLi", "")
+BUILTIN(__builtin_altivec_vcmpgtsq_p, "iiV1SLLLiV1SLLLi", "")
+BUILTIN(__builtin_altivec_vcmpgtuq_p, "iiV1ULLLiV1ULLLi", "")
BUILTIN(__builtin_altivec_vmaxsb, "V16ScV16ScV16Sc", "")
BUILTIN(__builtin_altivec_vmaxub, "V16UcV16UcV16Uc", "")
diff --git a/clang/lib/CodeGen/CGExprScalar.cpp
b/clang/lib/CodeGen/CGExprScalar.cpp
index da24ff273602..cee2210e74c1 100644
--- a/clang/lib/CodeGen/CGExprScalar.cpp
+++ b/clang/lib/CodeGen/CGExprScalar.cpp
@@ -3882,6 +3882,12 @@ static llvm::Intrinsic::ID GetIntrinsic(IntrinsicType IT,
case BuiltinType::Double:
return (IT == VCMPEQ) ? llvm::Intrinsic::ppc_vsx_xvcmpeqdp_p :
llvm::Intrinsic::ppc_vsx_xvcmpgtdp_p;
+ case BuiltinType::UInt128:
+return (IT == VCMPEQ) ? llvm::Intrinsic::ppc_altivec_vcmpequq_p
+ : llvm::Intrinsic::ppc_altivec_vcmpgtuq_p;
+ case BuiltinType::Int128:
+return (IT == VCMPEQ) ? llvm::Intrinsic::ppc_altivec_vcmpequq_p
+ : llvm::Intrinsic::ppc_altivec_vcmpgtsq_p;
}
}
diff --git a/clang/lib/Headers/altivec.h b/clang/lib/Headers/altivec.h
index d1fcde741a37..03e82c8ae7e0 100644
--- a/clang/lib/Headers/altivec.h
+++ b/clang/lib/Headers/altivec.h
@@ -14186,6 +14186,18 @@ static __inline__ int __ATTRS_o_ai vec_all_eq(vector
double __a,
}
#endif
+#ifdef __POWER10_VECTOR__
+static __inline__ int __ATTRS_o_ai vec_all_eq(vector signed __int128 __a,
+ vector signed __int128 __b) {
+ return __builtin_altivec_vcmpequq_p(__CR6_LT, __a, __b);
+}
+
+static __inline__ int __ATTRS_o_ai vec_all_eq(vector unsigned __int128 __a,
+ vector unsigned __int128 __b) {
+ return __builtin_altivec_vcmpequq_p(__CR6_LT, __a, __b);
+}
+#endif
+
/* vec_all_ge */
static __inline__ int __ATTRS_o_ai vec_all_ge(vector signed char __a,
@@ -14357,6 +14369,18 @@ static __inline__ int __ATTRS_o_ai vec_all_ge(vector
double __a,
}
#endif
+#ifdef __POWER10_VECTOR__
+static __inline__ int __ATTRS_o_ai vec_all_ge(vector signed __int128 __a,
+ vector signed __int128 __b) {
+ return __builtin_altivec_vcmpgtsq_p(__CR6_EQ, __b, __a);
+}
+
+static __inline__ int __ATTRS_o_ai vec_all_ge(vector unsigned __int128 __a,
+ vector unsigned __int128 __b) {
+ return __builtin_altivec_vcmpgtuq_p(__CR6_EQ, __b, __a);
+}
+#endif
+
/* vec_all_gt */
static __inline__ int __ATTRS_o_ai vec_all_gt(vector signed char __a,
@@ -14528,6 +14552,18 @@ static __inline__ int __ATTRS_o_ai vec_all_gt(vector
double __a,
}
#endif
+#ifdef __POWER10_VECTOR__
+static __inline__ int __ATTRS_o_ai vec_all_gt(vector signed __int128 __a,
+ vector signed __int128 __b) {
+ return __builtin_altivec_vcmpgtsq_p(__CR6_LT, __a, __b);
+}
+
+static __inline__ int __ATTRS_o_ai vec_all_gt(vector unsigned __int128 __a,
+ vector unsigned __int128 __b) {
+ return __builtin_altivec_vcmpgtuq_p(__CR6_LT, __a, __b);
+}
+#endif
+
/* vec_all_in */
static __inline__ int __attribute__((__always_inline__))
@@ -14707,6 +14743,18 @@ static __inline__ int __ATTRS_o_ai vec_all_le(vector
double __a,
}
#endif
+#ifdef __POWER10_VECTOR__
+static __inline__ int __ATTRS_o_ai vec_all_le(vector signed __int128 __a,
+
[clang] d7eb917 - [PowerPC] Implementation of 128-bit Binary Vector Mod and Sign Extend builtins
Author: Albion Fung
Date: 2020-09-23T01:18:14-05:00
New Revision: d7eb917a7cb793f49e16841fc24826b988dd5c8f
URL:
https://github.com/llvm/llvm-project/commit/d7eb917a7cb793f49e16841fc24826b988dd5c8f
DIFF:
https://github.com/llvm/llvm-project/commit/d7eb917a7cb793f49e16841fc24826b988dd5c8f.diff
LOG: [PowerPC] Implementation of 128-bit Binary Vector Mod and Sign Extend
builtins
This patch implements 128-bit Binary Vector Mod and Sign Extend builtins for
PowerPC10.
Differential: https://reviews.llvm.org/D87394#inline-815858
Added:
llvm/test/CodeGen/PowerPC/p10-vector-sign-extend.ll
llvm/test/CodeGen/PowerPC/p9-vector-sign-extend.ll
Modified:
clang/include/clang/Basic/BuiltinsPPC.def
clang/lib/Headers/altivec.h
clang/test/CodeGen/builtins-ppc-p10vector.c
clang/test/CodeGen/builtins-ppc-p9vector.c
llvm/include/llvm/IR/IntrinsicsPowerPC.td
llvm/lib/Target/PowerPC/PPCISelLowering.cpp
llvm/lib/Target/PowerPC/PPCInstrAltivec.td
llvm/lib/Target/PowerPC/PPCInstrPrefix.td
llvm/test/CodeGen/PowerPC/p10-vector-modulo.ll
Removed:
diff --git a/clang/include/clang/Basic/BuiltinsPPC.def
b/clang/include/clang/Basic/BuiltinsPPC.def
index b571454cfc7a..5de3584a2755 100644
--- a/clang/include/clang/Basic/BuiltinsPPC.def
+++ b/clang/include/clang/Basic/BuiltinsPPC.def
@@ -303,6 +303,16 @@ BUILTIN(__builtin_altivec_vrldmi,
"V2ULLiV2ULLiV2ULLiV2ULLi", "")
BUILTIN(__builtin_altivec_vrlwnm, "V4UiV4UiV4Ui", "")
BUILTIN(__builtin_altivec_vrldnm, "V2ULLiV2ULLiV2ULLi", "")
+// P9 Vector extend sign builtins.
+BUILTIN(__builtin_altivec_vextsb2w, "V4SiV16Sc", "")
+BUILTIN(__builtin_altivec_vextsb2d, "V2SLLiV16Sc", "")
+BUILTIN(__builtin_altivec_vextsh2w, "V4SiV8Ss", "")
+BUILTIN(__builtin_altivec_vextsh2d, "V2SLLiV8Ss", "")
+BUILTIN(__builtin_altivec_vextsw2d, "V2SLLiV4Si", "")
+
+// P10 Vector extend sign builtins.
+BUILTIN(__builtin_altivec_vextsd2q, "V1SLLLiV2SLLi", "")
+
// P10 Vector Extract with Mask built-ins.
BUILTIN(__builtin_altivec_vextractbm, "UiV16Uc", "")
BUILTIN(__builtin_altivec_vextracthm, "UiV8Us", "")
diff --git a/clang/lib/Headers/altivec.h b/clang/lib/Headers/altivec.h
index 2c09e477bd3c..b07e45d3c5a5 100644
--- a/clang/lib/Headers/altivec.h
+++ b/clang/lib/Headers/altivec.h
@@ -3007,6 +3007,42 @@ static __inline__ vector double __ATTRS_o_ai
vec_cpsgn(vector double __a,
#define vec_vctuxs __builtin_altivec_vctuxs
+/* vec_signext */
+
+#ifdef __POWER9_VECTOR__
+static __inline__ vector signed int __ATTRS_o_ai
+vec_signexti(vector signed char __a) {
+ return __builtin_altivec_vextsb2w(__a);
+}
+
+static __inline__ vector signed int __ATTRS_o_ai
+vec_signexti(vector signed short __a) {
+ return __builtin_altivec_vextsh2w(__a);
+}
+
+static __inline__ vector signed long long __ATTRS_o_ai
+vec_signextll(vector signed char __a) {
+ return __builtin_altivec_vextsb2d(__a);
+}
+
+static __inline__ vector signed long long __ATTRS_o_ai
+vec_signextll(vector signed short __a) {
+ return __builtin_altivec_vextsh2d(__a);
+}
+
+static __inline__ vector signed long long __ATTRS_o_ai
+vec_signextll(vector signed int __a) {
+ return __builtin_altivec_vextsw2d(__a);
+}
+#endif
+
+#ifdef __POWER10_VECTOR__
+static __inline__ vector signed __int128 __ATTRS_o_ai
+vec_signextq(vector signed long long __a) {
+ return __builtin_altivec_vextsd2q(__a);
+}
+#endif
+
/* vec_signed */
static __inline__ vector signed int __ATTRS_o_ai
@@ -17269,6 +17305,16 @@ vec_mod(vector unsigned long long __a, vector unsigned
long long __b) {
return __a % __b;
}
+static __inline__ vector signed __int128 __ATTRS_o_ai
+vec_mod(vector signed __int128 __a, vector signed __int128 __b) {
+ return __a % __b;
+}
+
+static __inline__ vector unsigned __int128 __ATTRS_o_ai
+vec_mod(vector unsigned __int128 __a, vector unsigned __int128 __b) {
+ return __a % __b;
+}
+
/* vec_sldbi */
#define vec_sldb(__a, __b, __c) __builtin_altivec_vsldbi(__a, __b, (__c & 0x7))
diff --git a/clang/test/CodeGen/builtins-ppc-p10vector.c
b/clang/test/CodeGen/builtins-ppc-p10vector.c
index 89f49adf28e9..b6788d783a5d 100644
--- a/clang/test/CodeGen/builtins-ppc-p10vector.c
+++ b/clang/test/CodeGen/builtins-ppc-p10vector.c
@@ -1481,3 +1481,21 @@ vector unsigned __int128 test_vec_xl_zext_i64(void) {
// CHECK: ret <1 x i128>
return vec_xl_zext(llb, ullap);
}
+
+vector signed __int128 test_vec_signextq_s128(void) {
+// CHECK: @llvm.ppc.altivec.vextsd2q(<2 x i64>
+// CHECK-NEXT: ret <1 x i128>
+return vec_signextq(vslla);
+}
+
+vector unsigned __int128 test_vec_mod_u128(void) {
+// CHECK: urem <1 x i128>
+// CHECK-NEXT: ret <1 x i128>
+return vec_mod(vui128a, vui128b);
+}
+
+vector signed __int128 test_vec_mod_s128(void) {
+// CHECK: srem <1 x i128>
+// CHECK-NEXT: ret <1 x i128>
+return vec_mod(vsi128a, vsi128b);
+}
diff --git
[clang] 05aa997 - [PowerPC] Implement __int128 vector divide operations
Author: Albion Fung
Date: 2020-09-15T15:19:35-04:00
New Revision: 05aa997d511eed530305e2f3aa401584d0691186
URL:
https://github.com/llvm/llvm-project/commit/05aa997d511eed530305e2f3aa401584d0691186
DIFF:
https://github.com/llvm/llvm-project/commit/05aa997d511eed530305e2f3aa401584d0691186.diff
LOG: [PowerPC] Implement __int128 vector divide operations
This patch implements __int128 vector divide operations for ISA3.1.
Differential Revision: https://reviews.llvm.org/D85453
Added:
Modified:
clang/lib/Headers/altivec.h
clang/test/CodeGen/builtins-ppc-p10vector.c
llvm/lib/Target/PowerPC/PPCISelLowering.cpp
llvm/lib/Target/PowerPC/PPCInstrPrefix.td
llvm/test/CodeGen/PowerPC/p10-vector-divide.ll
Removed:
diff --git a/clang/lib/Headers/altivec.h b/clang/lib/Headers/altivec.h
index 22744adefbef..51fd3d21b5e1 100644
--- a/clang/lib/Headers/altivec.h
+++ b/clang/lib/Headers/altivec.h
@@ -3368,6 +3368,18 @@ vec_dive(vector unsigned long long __a, vector unsigned
long long __b) {
}
#endif
+#ifdef __POWER10_VECTOR__
+static __inline__ vector unsigned __int128 __ATTRS_o_ai
+vec_div(vector unsigned __int128 __a, vector unsigned __int128 __b) {
+ return __a / __b;
+}
+
+static __inline__ vector signed __int128 __ATTRS_o_ai
+vec_div(vector signed __int128 __a, vector signed __int128 __b) {
+ return __a / __b;
+}
+#endif __POWER10_VECTOR__
+
/* vec_dss */
#define vec_dss __builtin_altivec_dss
diff --git a/clang/test/CodeGen/builtins-ppc-p10vector.c
b/clang/test/CodeGen/builtins-ppc-p10vector.c
index ad63d646196c..12ec3a6ab8f3 100644
--- a/clang/test/CodeGen/builtins-ppc-p10vector.c
+++ b/clang/test/CodeGen/builtins-ppc-p10vector.c
@@ -17,6 +17,7 @@ vector signed int vsia, vsib;
vector unsigned int vuia, vuib, vuic;
vector signed long long vslla, vsllb;
vector unsigned long long vulla, vullb, vullc;
+vector signed __int128 vsi128a, vsi128b;
vector unsigned __int128 vui128a, vui128b, vui128c;
vector float vfa, vfb;
vector double vda, vdb;
@@ -69,6 +70,18 @@ vector unsigned long long test_vec_div_ull(void) {
return vec_div(vulla, vullb);
}
+vector unsigned __int128 test_vec_div_u128(void) {
+ // CHECK: udiv <1 x i128>
+ // CHECK-NEXT: ret <1 x i128>
+ return vec_div(vui128a, vui128b);
+}
+
+vector signed __int128 test_vec_div_s128(void) {
+ // CHECK: sdiv <1 x i128>
+ // CHECK-NEXT: ret <1 x i128>
+ return vec_div(vsi128a, vsi128b);
+}
+
vector signed int test_vec_dive_si(void) {
// CHECK: @llvm.ppc.altivec.vdivesw(<4 x i32> %{{.+}}, <4 x i32> %{{.+}})
// CHECK-NEXT: ret <4 x i32>
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
index 66711f69a645..3b0acfa76ec8 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -888,6 +888,8 @@ PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine
,
setOperationAction(ISD::SREM, MVT::v2i64, Legal);
setOperationAction(ISD::UREM, MVT::v4i32, Legal);
setOperationAction(ISD::SREM, MVT::v4i32, Legal);
+ setOperationAction(ISD::UDIV, MVT::v1i128, Legal);
+ setOperationAction(ISD::SDIV, MVT::v1i128, Legal);
}
setOperationAction(ISD::MUL, MVT::v8i16, Legal);
diff --git a/llvm/lib/Target/PowerPC/PPCInstrPrefix.td
b/llvm/lib/Target/PowerPC/PPCInstrPrefix.td
index 55872a493dd6..4e951114b90f 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrPrefix.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrPrefix.td
@@ -1285,9 +1285,11 @@ let Predicates = [IsISA3_1] in {
[(set v1i128:$vD, (int_ppc_altivec_vmsumcud
v2i64:$vA, v2i64:$vB, v1i128:$vC))]>;
def VDIVSQ : VXForm_1<267, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
-"vdivsq $vD, $vA, $vB", IIC_VecGeneral, []>;
+"vdivsq $vD, $vA, $vB", IIC_VecGeneral,
+[(set v1i128:$vD, (sdiv v1i128:$vA, v1i128:$vB))]>;
def VDIVUQ : VXForm_1<11, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
-"vdivuq $vD, $vA, $vB", IIC_VecGeneral, []>;
+"vdivuq $vD, $vA, $vB", IIC_VecGeneral,
+[(set v1i128:$vD, (udiv v1i128:$vA, v1i128:$vB))]>;
def VDIVESQ : VXForm_1<779, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
"vdivesq $vD, $vA, $vB", IIC_VecGeneral, []>;
def VDIVEUQ : VXForm_1<523, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
diff --git a/llvm/test/CodeGen/PowerPC/p10-vector-divide.ll
b/llvm/test/CodeGen/PowerPC/p10-vector-divide.ll
index dc21b4fb49ee..b5f36a78b2b2 100644
--- a/llvm/test/CodeGen/PowerPC/p10-vector-divide.ll
+++ b/llvm/test/CodeGen/PowerPC/p10-vector-divide.ll
@@ -76,6 +76,24 @@ entry:
ret <4 x i32> %div
}
+define <1 x i128> @test_vdivsq(<1 x i128> %x, <1 x i128> %y) nounwind readnone
{
+; CHECK-LABEL: test_vdivsq:
[clang] 5d1fe3f - [PowerPC] Implemented Vector Multiply Builtins
Author: Albion Fung
Date: 2020-09-02T14:16:21-05:00
New Revision: 5d1fe3f903b9f46b994956f3b214305be119c4e2
URL:
https://github.com/llvm/llvm-project/commit/5d1fe3f903b9f46b994956f3b214305be119c4e2
DIFF:
https://github.com/llvm/llvm-project/commit/5d1fe3f903b9f46b994956f3b214305be119c4e2.diff
LOG: [PowerPC] Implemented Vector Multiply Builtins
This patch implements the builtins for Vector Multiply Builtins (vmulxxd family
of instructions), and adds the appropriate test cases for these builtins. The
builtins utilize the vector multiply instructions itnroduced with ISA 3.1.
Differential Revision: https://reviews.llvm.org/D83955
Added:
Modified:
clang/include/clang/Basic/BuiltinsPPC.def
clang/lib/Headers/altivec.h
clang/test/CodeGen/builtins-ppc-p10vector.c
llvm/include/llvm/IR/IntrinsicsPowerPC.td
llvm/lib/Target/PowerPC/PPCInstrPrefix.td
llvm/test/CodeGen/PowerPC/p10-vector-multiply.ll
Removed:
diff --git a/clang/include/clang/Basic/BuiltinsPPC.def
b/clang/include/clang/Basic/BuiltinsPPC.def
index b9824588939b..57ef39980c9b 100644
--- a/clang/include/clang/Basic/BuiltinsPPC.def
+++ b/clang/include/clang/Basic/BuiltinsPPC.def
@@ -100,6 +100,11 @@ BUILTIN(__builtin_altivec_vmulouh, "V4UiV8UsV8Us", "")
BUILTIN(__builtin_altivec_vmulosh, "V4SiV8SsV8Ss", "")
BUILTIN(__builtin_altivec_vmulouw, "V2ULLiV4UiV4Ui", "")
BUILTIN(__builtin_altivec_vmulosw, "V2SLLiV4SiV4Si", "")
+BUILTIN(__builtin_altivec_vmuleud, "V1ULLLiV2ULLiV2ULLi", "")
+BUILTIN(__builtin_altivec_vmulesd, "V1SLLLiV2SLLiV2SLLi", "")
+BUILTIN(__builtin_altivec_vmuloud, "V1ULLLiV2ULLiV2ULLi", "")
+BUILTIN(__builtin_altivec_vmulosd, "V1SLLLiV2SLLiV2SLLi", "")
+BUILTIN(__builtin_altivec_vmsumcud, "V1ULLLiV2ULLiV2ULLiV1ULLLi", "")
BUILTIN(__builtin_altivec_vnmsubfp, "V4fV4fV4fV4f", "")
diff --git a/clang/lib/Headers/altivec.h b/clang/lib/Headers/altivec.h
index 927f25751664..47119d702683 100644
--- a/clang/lib/Headers/altivec.h
+++ b/clang/lib/Headers/altivec.h
@@ -5487,6 +5487,16 @@ vec_msum(vector unsigned short __a, vector unsigned
short __b,
return __builtin_altivec_vmsumuhm(__a, __b, __c);
}
+/* vec_msumc */
+
+#ifdef __POWER10_VECTOR__
+static __inline__ vector unsigned __int128 __ATTRS_o_ai
+vec_msumc(vector unsigned long long __a, vector unsigned long long __b,
+ vector unsigned __int128 __c) {
+ return __builtin_altivec_vmsumcud(__a, __b, __c);
+}
+#endif
+
/* vec_vmsummbm */
static __inline__ vector int __attribute__((__always_inline__))
@@ -5713,6 +5723,26 @@ vec_mule(vector unsigned int __a, vector unsigned int
__b) {
}
#endif
+#ifdef __POWER10_VECTOR__
+static __inline__ vector signed __int128 __ATTRS_o_ai
+vec_mule(vector signed long long __a, vector signed long long __b) {
+#ifdef __LITTLE_ENDIAN__
+ return __builtin_altivec_vmulosd(__a, __b);
+#else
+ return __builtin_altivec_vmulesd(__a, __b);
+#endif
+}
+
+static __inline__ vector unsigned __int128 __ATTRS_o_ai
+vec_mule(vector unsigned long long __a, vector unsigned long long __b) {
+#ifdef __LITTLE_ENDIAN__
+ return __builtin_altivec_vmuloud(__a, __b);
+#else
+ return __builtin_altivec_vmuleud(__a, __b);
+#endif
+}
+#endif
+
/* vec_vmulesb */
static __inline__ vector short __attribute__((__always_inline__))
@@ -5839,6 +5869,26 @@ vec_mulo(vector unsigned int __a, vector unsigned int
__b) {
}
#endif
+#ifdef __POWER10_VECTOR__
+static __inline__ vector signed __int128 __ATTRS_o_ai
+vec_mulo(vector signed long long __a, vector signed long long __b) {
+#ifdef __LITTLE_ENDIAN__
+ return __builtin_altivec_vmulesd(__a, __b);
+#else
+ return __builtin_altivec_vmulosd(__a, __b);
+#endif
+}
+
+static __inline__ vector unsigned __int128 __ATTRS_o_ai
+vec_mulo(vector unsigned long long __a, vector unsigned long long __b) {
+#ifdef __LITTLE_ENDIAN__
+ return __builtin_altivec_vmuleud(__a, __b);
+#else
+ return __builtin_altivec_vmuloud(__a, __b);
+#endif
+}
+#endif
+
/* vec_vmulosb */
static __inline__ vector short __attribute__((__always_inline__))
diff --git a/clang/test/CodeGen/builtins-ppc-p10vector.c
b/clang/test/CodeGen/builtins-ppc-p10vector.c
index 6fe6d9fdf72d..ac766e264b2d 100644
--- a/clang/test/CodeGen/builtins-ppc-p10vector.c
+++ b/clang/test/CodeGen/builtins-ppc-p10vector.c
@@ -928,6 +928,44 @@ int test_vec_test_lsbb_all_zeros(void) {
return vec_test_lsbb_all_zeros(vuca);
}
+vector unsigned __int128 test_vec_mule_u128(void) {
+ // CHECK-BE: @llvm.ppc.altivec.vmuleud(<2 x i64>
+ // CHECK-BE-NEXT: ret <1 x i128>
+ // CHECK-LE: @llvm.ppc.altivec.vmuloud(<2 x i64>
+ // CHECK-LE-NEXT: ret <1 x i128>
+ return vec_mule(vulla, vullb);
+}
+
+vector signed __int128 test_vec_mule_s128(void) {
+ // CHECK-BE: @llvm.ppc.altivec.vmulesd(<2 x i64>
+ // CHECK-BE-NEXT: ret <1 x i128>
+ // CHECK-LE: @llvm.ppc.altivec.vmulosd(<2 x i64>
+ // CHECK-LE-NEXT: ret <1 x i128>
+ return vec_mule(vslla,
[clang] 331dcc4 - [PowerPC] Implemented Vector Load with Zero and Signed Extend Builtins
Author: Albion Fung
Date: 2020-08-28T11:28:58-05:00
New Revision: 331dcc43eac28b8e659f928fd1f1ce7fd091e1e3
URL:
https://github.com/llvm/llvm-project/commit/331dcc43eac28b8e659f928fd1f1ce7fd091e1e3
DIFF:
https://github.com/llvm/llvm-project/commit/331dcc43eac28b8e659f928fd1f1ce7fd091e1e3.diff
LOG: [PowerPC] Implemented Vector Load with Zero and Signed Extend Builtins
This patch implements the builtins for Vector Load with Zero and Signed Extend
Builtins (lxvr_x for b, h, w, d), and adds the appropriate test cases for these
builtins. The builtins utilize the vector load instructions itnroduced with ISA
3.1.
Differential Revision: https://reviews.llvm.org/D82502#inline-797941
Added:
Modified:
clang/lib/Headers/altivec.h
clang/test/CodeGen/builtins-ppc-p10vector.c
llvm/lib/Target/PowerPC/PPCISelLowering.cpp
llvm/lib/Target/PowerPC/PPCISelLowering.h
llvm/lib/Target/PowerPC/PPCInstrPrefix.td
llvm/test/CodeGen/PowerPC/builtins-ppc-p10vsx.ll
Removed:
diff --git a/clang/lib/Headers/altivec.h b/clang/lib/Headers/altivec.h
index 6583b0f22a16..5bc0e23792d4 100644
--- a/clang/lib/Headers/altivec.h
+++ b/clang/lib/Headers/altivec.h
@@ -16557,6 +16557,54 @@ vec_xl_be(signed long long __offset, unsigned
__int128 *__ptr) {
#define vec_xl_be vec_xl
#endif
+#if defined(__POWER10_VECTOR__) && defined(__VSX__)
+
+/* vect_xl_sext */
+
+static __inline__ vector unsigned __int128 __ATTRS_o_ai
+vec_xl_sext(signed long long __offset, signed char *__pointer) {
+ return (vector unsigned __int128)*(__pointer + __offset);
+}
+
+static __inline__ vector unsigned __int128 __ATTRS_o_ai
+vec_xl_sext(signed long long __offset, signed short *__pointer) {
+ return (vector unsigned __int128)*(__pointer + __offset);
+}
+
+static __inline__ vector unsigned __int128 __ATTRS_o_ai
+vec_xl_sext(signed long long __offset, signed int *__pointer) {
+ return (vector unsigned __int128)*(__pointer + __offset);
+}
+
+static __inline__ vector unsigned __int128 __ATTRS_o_ai
+vec_xl_sext(signed long long __offset, signed long long *__pointer) {
+ return (vector unsigned __int128)*(__pointer + __offset);
+}
+
+/* vec_xl_zext */
+
+static __inline__ vector unsigned __int128 __ATTRS_o_ai
+vec_xl_zext(signed long long __offset, unsigned char *__pointer) {
+ return (vector unsigned __int128)*(__pointer + __offset);
+}
+
+static __inline__ vector unsigned __int128 __ATTRS_o_ai
+vec_xl_zext(signed long long __offset, unsigned short *__pointer) {
+ return (vector unsigned __int128)*(__pointer + __offset);
+}
+
+static __inline__ vector unsigned __int128 __ATTRS_o_ai
+vec_xl_zext(signed long long __offset, unsigned int *__pointer) {
+ return (vector unsigned __int128)*(__pointer + __offset);
+}
+
+static __inline__ vector unsigned __int128 __ATTRS_o_ai
+vec_xl_zext(signed long long __offset, unsigned long long *__pointer) {
+ return (vector unsigned __int128)*(__pointer + __offset);
+}
+
+#endif
+
/* vec_xst */
static inline __ATTRS_o_ai void vec_xst(vector signed char __vec,
diff --git a/clang/test/CodeGen/builtins-ppc-p10vector.c
b/clang/test/CodeGen/builtins-ppc-p10vector.c
index 16e468b62318..09477891bb06 100644
--- a/clang/test/CodeGen/builtins-ppc-p10vector.c
+++ b/clang/test/CodeGen/builtins-ppc-p10vector.c
@@ -20,10 +20,14 @@ vector unsigned long long vulla, vullb, vullc;
vector unsigned __int128 vui128a, vui128b, vui128c;
vector float vfa, vfb;
vector double vda, vdb;
-unsigned int uia, uib;
-unsigned char uca;
-unsigned short usa;
-unsigned long long ulla;
+signed int *iap;
+unsigned int uia, uib, *uiap;
+signed char *cap;
+unsigned char uca, *ucap;
+signed short *sap;
+unsigned short usa, *usap;
+signed long long *llap, llb;
+unsigned long long ulla, *ullap;
vector signed long long test_vec_mul_sll(void) {
// CHECK: mul <2 x i64>
@@ -911,3 +915,59 @@ int test_vec_test_lsbb_all_zeros(void) {
// CHECK-NEXT: ret i32
return vec_test_lsbb_all_zeros(vuca);
}
+
+vector signed __int128 test_vec_xl_sext_i8(void) {
+ // CHECK: load i8
+ // CHECK: sext i8
+ // CHECK: ret <1 x i128>
+ return vec_xl_sext(llb, cap);
+}
+
+vector signed __int128 test_vec_xl_sext_i16(void) {
+ // CHECK: load i16
+ // CHECK: sext i16
+ // CHECK: ret <1 x i128>
+ return vec_xl_sext(llb, sap);
+}
+
+vector signed __int128 test_vec_xl_sext_i32(void) {
+ // CHECK: load i32
+ // CHECK: sext i32
+ // CHECK: ret <1 x i128>
+ return vec_xl_sext(llb, iap);
+}
+
+vector signed __int128 test_vec_xl_sext_i64(void) {
+ // CHECK: load i64
+ // CHECK: sext i64
+ // CHECK: ret <1 x i128>
+ return vec_xl_sext(llb, llap);
+}
+
+vector unsigned __int128 test_vec_xl_zext_i8(void) {
+ // CHECK: load i8
+ // CHECK: zext i8
+ // CHECK: ret <1 x i128>
+ return vec_xl_zext(llb, ucap);
+}
+
+vector unsigned __int128 test_vec_xl_zext_i16(void) {
+ // CHECK: load i16
+ // CHECK: zext i16
+ // CHECK: ret <1 x i128>
+ return
[clang] 3136cbe - [PowerPC] Implement Vector Shift Builtins
Author: Albion Fung
Date: 2020-08-12T18:26:58-05:00
New Revision: 3136cbe29e74e19e6cb71c5ce71e4b92a63d03d8
URL:
https://github.com/llvm/llvm-project/commit/3136cbe29e74e19e6cb71c5ce71e4b92a63d03d8
DIFF:
https://github.com/llvm/llvm-project/commit/3136cbe29e74e19e6cb71c5ce71e4b92a63d03d8.diff
LOG: [PowerPC] Implement Vector Shift Builtins
This patch implements the builtins for the vector shifts (shl, srl, sra), and
adds the appropriate test cases for these builtins. The builtins utilize the
vector shift instructions introduced within ISA 3.1.
Differential Revision: https://reviews.llvm.org/D83338
Added:
llvm/test/CodeGen/PowerPC/p10-vector-shift.ll
Modified:
clang/lib/Headers/altivec.h
clang/test/CodeGen/builtins-ppc-p10vector.c
llvm/lib/Target/PowerPC/PPCISelLowering.cpp
llvm/lib/Target/PowerPC/PPCInstrPrefix.td
Removed:
diff --git a/clang/lib/Headers/altivec.h b/clang/lib/Headers/altivec.h
index d0a3b198351c..ac4182613cdd 100644
--- a/clang/lib/Headers/altivec.h
+++ b/clang/lib/Headers/altivec.h
@@ -17321,6 +17321,53 @@ vec_test_lsbb_all_zeros(vector unsigned char __a) {
return __builtin_vsx_xvtlsbb(__a, 0);
}
#endif /* __VSX__ */
+
+/* vs[l | r | ra] */
+
+static __inline__ vector unsigned __int128 __ATTRS_o_ai
+vec_sl(vector unsigned __int128 __a, vector unsigned __int128 __b) {
+ return __a << (__b % (vector unsigned __int128)(sizeof(unsigned __int128) *
+ __CHAR_BIT__));
+}
+
+static __inline__ vector signed __int128 __ATTRS_o_ai
+vec_sl(vector signed __int128 __a, vector unsigned __int128 __b) {
+ return __a << (__b % (vector unsigned __int128)(sizeof(unsigned __int128) *
+ __CHAR_BIT__));
+}
+
+static __inline__ vector unsigned __int128 __ATTRS_o_ai
+vec_sr(vector unsigned __int128 __a, vector unsigned __int128 __b) {
+ return __a >> (__b % (vector unsigned __int128)(sizeof(unsigned __int128) *
+ __CHAR_BIT__));
+}
+
+static __inline__ vector signed __int128 __ATTRS_o_ai
+vec_sr(vector signed __int128 __a, vector unsigned __int128 __b) {
+ return (
+ vector signed __int128)(((vector unsigned __int128)__a) >>
+ (__b %
+ (vector unsigned __int128)(sizeof(
+ unsigned
__int128) *
+ __CHAR_BIT__)));
+}
+
+static __inline__ vector unsigned __int128 __ATTRS_o_ai
+vec_sra(vector unsigned __int128 __a, vector unsigned __int128 __b) {
+ return (
+ vector unsigned __int128)(((vector signed __int128)__a) >>
+(__b %
+ (vector unsigned __int128)(sizeof(
+unsigned
__int128) *
+__CHAR_BIT__)));
+}
+
+static __inline__ vector signed __int128 __ATTRS_o_ai
+vec_sra(vector signed __int128 __a, vector unsigned __int128 __b) {
+ return __a >> (__b % (vector unsigned __int128)(sizeof(unsigned __int128) *
+ __CHAR_BIT__));
+}
+
#endif /* __POWER10_VECTOR__ */
#undef __ATTRS_o_ai
diff --git a/clang/test/CodeGen/builtins-ppc-p10vector.c
b/clang/test/CodeGen/builtins-ppc-p10vector.c
index 2279d9c57c86..a575f5a924c5 100644
--- a/clang/test/CodeGen/builtins-ppc-p10vector.c
+++ b/clang/test/CodeGen/builtins-ppc-p10vector.c
@@ -8,6 +8,7 @@
#include
+vector signed __int128 vi128a;
vector signed char vsca, vscb;
vector unsigned char vuca, vucb, vucc;
vector signed short vssa, vssb;
@@ -778,6 +779,49 @@ void test_vec_xst_trunc_ull(vector unsigned __int128 __a,
signed long long __b,
vec_xst_trunc(__a, __b, __c);
}
+vector unsigned __int128 test_vec_slq_unsigned (void) {
+ // CHECK-LABEL: test_vec_slq_unsigned
+ // CHECK: shl <1 x i128> %{{.+}}, %{{.+}}
+ // CHECK: ret <1 x i128> %{{.+}}
+ return vec_sl(vui128a, vui128b);
+}
+
+vector signed __int128 test_vec_slq_signed (void) {
+ // CHECK-LABEL: test_vec_slq_signed
+ // CHECK: shl <1 x i128> %{{.+}}, %{{.+}}
+ // CHECK: ret <1 x i128>
+ return vec_sl(vi128a, vui128a);
+}
+
+vector unsigned __int128 test_vec_srq_unsigned (void) {
+ // CHECK-LABEL: test_vec_srq_unsigned
+ // CHECK: lshr <1 x i128> %{{.+}}, %{{.+}}
+ // CHECK: ret <1 x i128>
+ return vec_sr(vui128a, vui128b);
+}
+
+vector signed __int128 test_vec_srq_signed (void) {
+ // CHECK-LABEL: test_vec_srq_signed
+ // CHECK: lshr <1 x i128> %{{.+}}, %{{.+}}
+ // CHECK: ret <1 x i128>
+ return vec_sr(vi128a, vui128a);
+}
+
+vector unsigned __int128 test_vec_sraq_unsigned (void) {
+ // CHECK-LABEL: test_vec_sraq_unsigned
+ // CHECK: ashr <1 x i128> %{{.+}}, %{{.+}}
+ // CHECK: ret <1 x i128>
+
[clang] ed66df6 - test commit
Author: Albion Fung Date: 2020-08-10T21:18:36-04:00 New Revision: ed66df6705a9dffc36fecc3468cc3ab430849182 URL: https://github.com/llvm/llvm-project/commit/ed66df6705a9dffc36fecc3468cc3ab430849182 DIFF: https://github.com/llvm/llvm-project/commit/ed66df6705a9dffc36fecc3468cc3ab430849182.diff LOG: test commit Added: Modified: clang/test/CodeGen/builtins-ppc-p10vector.c Removed: diff --git a/clang/test/CodeGen/builtins-ppc-p10vector.c b/clang/test/CodeGen/builtins-ppc-p10vector.c index 5bab616921b3..2279d9c57c86 100644 --- a/clang/test/CodeGen/builtins-ppc-p10vector.c +++ b/clang/test/CodeGen/builtins-ppc-p10vector.c @@ -2,7 +2,6 @@ // RUN: %clang_cc1 -target-feature +vsx \ // RUN: -target-cpu pwr10 -triple powerpc64-unknown-unknown -emit-llvm %s \ // RUN: -o - | FileCheck %s -check-prefixes=CHECK-BE,CHECK - // RUN: %clang_cc1 -target-feature +vsx \ // RUN: -target-cpu pwr10 -triple powerpc64le-unknown-unknown -emit-llvm %s \ // RUN: -o - | FileCheck %s -check-prefixes=CHECK-LE,CHECK ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
