[clang] [llvm] [RISCV] Bump Zaamo and Zalrsc to version 1.0 (PR #91556)
https://github.com/4vtomat closed https://github.com/llvm/llvm-project/pull/91556 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Bump Zaamo and Zalrsc to version 1.0 (PR #91556)
https://github.com/4vtomat updated
https://github.com/llvm/llvm-project/pull/91556
>From 062d7d5017b01fb3afbaffe1a34487cfe36288d2 Mon Sep 17 00:00:00 2001
From: Brandon Wu
Date: Wed, 8 May 2024 21:43:07 -0700
Subject: [PATCH 1/4] [RISCV] Bump Zaamo and Zalrsc to version 1.0
The ratified information can be found here:
https://wiki.riscv.org/display/HOME/Ratified+Extensions
---
.../test/Preprocessor/riscv-target-features.c | 20 +--
llvm/lib/Target/RISCV/RISCVFeatures.td| 8
llvm/test/CodeGen/RISCV/attributes.ll | 16 +++
llvm/test/MC/RISCV/rv32zaamo-invalid.s| 2 +-
llvm/test/MC/RISCV/rv32zaamo-valid.s | 12 +--
llvm/test/MC/RISCV/rv32zalrsc-invalid.s | 2 +-
llvm/test/MC/RISCV/rv32zalrsc-valid.s | 12 +--
llvm/test/MC/RISCV/rv64zaamo-invalid.s| 2 +-
llvm/test/MC/RISCV/rv64zaamo-valid.s | 8
llvm/test/MC/RISCV/rv64zalrsc-invalid.s | 2 +-
llvm/test/MC/RISCV/rv64zalrsc-valid.s | 8
.../TargetParser/RISCVISAInfoTest.cpp | 4 ++--
12 files changed, 48 insertions(+), 48 deletions(-)
diff --git a/clang/test/Preprocessor/riscv-target-features.c
b/clang/test/Preprocessor/riscv-target-features.c
index 913093bb51db6..ead9ac9b4063f 100644
--- a/clang/test/Preprocessor/riscv-target-features.c
+++ b/clang/test/Preprocessor/riscv-target-features.c
@@ -1554,13 +1554,13 @@
// CHECK-ZVKT-EXT: __riscv_zvkt 100{{$}}
// Experimental extensions
-// RUN: %clang --target=riscv32 -menable-experimental-extensions \
-// RUN: -march=rv32i_zaamo0p2 -E -dM %s \
+// RUN: %clang --target=riscv32 \
+// RUN: -march=rv32i_zaamo1p0 -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZAAMO-EXT %s
-// RUN: %clang --target=riscv64 -menable-experimental-extensions \
-// RUN: -march=rv64i_zaamo0p2 -E -dM %s \
+// RUN: %clang --target=riscv64 \
+// RUN: -march=rv64i_zaamo1p0 -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZAAMO-EXT %s
-// CHECK-ZAAMO-EXT: __riscv_zaamo 2000{{$}}
+// CHECK-ZAAMO-EXT: __riscv_zaamo 100{{$}}
// RUN: %clang --target=riscv32 -menable-experimental-extensions \
// RUN: -march=rv32ia_zabha1p0 -E -dM %s \
@@ -1578,13 +1578,13 @@
// RUN: -o - | FileCheck --check-prefix=CHECK-ZALASR-EXT %s
// CHECK-ZALASR-EXT: __riscv_zalasr 1000{{$}}
-// RUN: %clang --target=riscv32 -menable-experimental-extensions \
-// RUN: -march=rv32i_zalrsc0p2 -E -dM %s \
+// RUN: %clang --target=riscv32 \
+// RUN: -march=rv32i_zalrsc1p0 -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZALRSC-EXT %s
-// RUN: %clang --target=riscv64 -menable-experimental-extensions \
-// RUN: -march=rv64i_zalrsc0p2 -E -dM %s \
+// RUN: %clang --target=riscv64 \
+// RUN: -march=rv64i_zalrsc1p0 -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZALRSC-EXT %s
-// CHECK-ZALRSC-EXT: __riscv_zalrsc 2000{{$}}
+// CHECK-ZALRSC-EXT: __riscv_zalrsc 100{{$}}
// RUN: %clang --target=riscv32 -menable-experimental-extensions \
// RUN: -march=rv32izfbfmin1p0 -E -dM %s \
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td
b/llvm/lib/Target/RISCV/RISCVFeatures.td
index 89e1214f469da..b099496d18388 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -211,8 +211,8 @@ def FeatureStdExtZa128rs : RISCVExtension<"za128rs", 1, 0,
"'Za128rs' (Reservation Set Size of
at Most 128 Bytes)">;
def FeatureStdExtZaamo
-: RISCVExperimentalExtension<"zaamo", 0, 2,
- "'Zaamo' (Atomic Memory Operations)">;
+: RISCVExtension<"zaamo", 1, 0,
+ "'Zaamo' (Atomic Memory Operations)">;
def HasStdExtAOrZaamo
: Predicate<"Subtarget->hasStdExtA() || Subtarget->hasStdExtZaamo()">,
AssemblerPredicate<(any_of FeatureStdExtA, FeatureStdExtZaamo),
@@ -242,8 +242,8 @@ def HasStdExtZalasr :
Predicate<"Subtarget->hasStdExtZalasr()">,
"'Zalasr' (Load-Acquire and Store-Release
Instructions)">;
def FeatureStdExtZalrsc
-: RISCVExperimentalExtension<"zalrsc", 0, 2,
- "'Zalrsc' (Load-Reserved/Store-Conditional)">;
+: RISCVExtension<"zalrsc", 1, 0,
+ "'Zalrsc' (Load-Reserved/Store-Conditional)">;
def HasStdExtAOrZalrsc
: Predicate<"Subtarget->hasStdExtA() || Subtarget->hasStdExtZalrsc()">,
AssemblerPredicate<(any_of FeatureStdExtA, FeatureStdExtZalrsc),
diff --git a/llvm/test/CodeGen/RISCV/attributes.ll
b/llvm/test/CodeGen/RISCV/attributes.ll
index 8f49f6648ad28..9fdd842e5dd37 100644
--- a/llvm/test/CodeGen/RISCV/attributes.ll
+++ b/llvm/test/CodeGen/RISCV/attributes.ll
@@ -112,10 +112,10 @@
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zfbfmin %s -o - | FileCheck
--check-prefixes=CHECK,RV32ZFBFMIN %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zvfbfmin %s -o - | FileCheck
[clang] [llvm] [RISCV] Bump Zaamo and Zalrsc to version 1.0 (PR #91556)
https://github.com/4vtomat updated
https://github.com/llvm/llvm-project/pull/91556
>From 062d7d5017b01fb3afbaffe1a34487cfe36288d2 Mon Sep 17 00:00:00 2001
From: Brandon Wu
Date: Wed, 8 May 2024 21:43:07 -0700
Subject: [PATCH 1/3] [RISCV] Bump Zaamo and Zalrsc to version 1.0
The ratified information can be found here:
https://wiki.riscv.org/display/HOME/Ratified+Extensions
---
.../test/Preprocessor/riscv-target-features.c | 20 +--
llvm/lib/Target/RISCV/RISCVFeatures.td| 8
llvm/test/CodeGen/RISCV/attributes.ll | 16 +++
llvm/test/MC/RISCV/rv32zaamo-invalid.s| 2 +-
llvm/test/MC/RISCV/rv32zaamo-valid.s | 12 +--
llvm/test/MC/RISCV/rv32zalrsc-invalid.s | 2 +-
llvm/test/MC/RISCV/rv32zalrsc-valid.s | 12 +--
llvm/test/MC/RISCV/rv64zaamo-invalid.s| 2 +-
llvm/test/MC/RISCV/rv64zaamo-valid.s | 8
llvm/test/MC/RISCV/rv64zalrsc-invalid.s | 2 +-
llvm/test/MC/RISCV/rv64zalrsc-valid.s | 8
.../TargetParser/RISCVISAInfoTest.cpp | 4 ++--
12 files changed, 48 insertions(+), 48 deletions(-)
diff --git a/clang/test/Preprocessor/riscv-target-features.c
b/clang/test/Preprocessor/riscv-target-features.c
index 913093bb51db6..ead9ac9b4063f 100644
--- a/clang/test/Preprocessor/riscv-target-features.c
+++ b/clang/test/Preprocessor/riscv-target-features.c
@@ -1554,13 +1554,13 @@
// CHECK-ZVKT-EXT: __riscv_zvkt 100{{$}}
// Experimental extensions
-// RUN: %clang --target=riscv32 -menable-experimental-extensions \
-// RUN: -march=rv32i_zaamo0p2 -E -dM %s \
+// RUN: %clang --target=riscv32 \
+// RUN: -march=rv32i_zaamo1p0 -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZAAMO-EXT %s
-// RUN: %clang --target=riscv64 -menable-experimental-extensions \
-// RUN: -march=rv64i_zaamo0p2 -E -dM %s \
+// RUN: %clang --target=riscv64 \
+// RUN: -march=rv64i_zaamo1p0 -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZAAMO-EXT %s
-// CHECK-ZAAMO-EXT: __riscv_zaamo 2000{{$}}
+// CHECK-ZAAMO-EXT: __riscv_zaamo 100{{$}}
// RUN: %clang --target=riscv32 -menable-experimental-extensions \
// RUN: -march=rv32ia_zabha1p0 -E -dM %s \
@@ -1578,13 +1578,13 @@
// RUN: -o - | FileCheck --check-prefix=CHECK-ZALASR-EXT %s
// CHECK-ZALASR-EXT: __riscv_zalasr 1000{{$}}
-// RUN: %clang --target=riscv32 -menable-experimental-extensions \
-// RUN: -march=rv32i_zalrsc0p2 -E -dM %s \
+// RUN: %clang --target=riscv32 \
+// RUN: -march=rv32i_zalrsc1p0 -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZALRSC-EXT %s
-// RUN: %clang --target=riscv64 -menable-experimental-extensions \
-// RUN: -march=rv64i_zalrsc0p2 -E -dM %s \
+// RUN: %clang --target=riscv64 \
+// RUN: -march=rv64i_zalrsc1p0 -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZALRSC-EXT %s
-// CHECK-ZALRSC-EXT: __riscv_zalrsc 2000{{$}}
+// CHECK-ZALRSC-EXT: __riscv_zalrsc 100{{$}}
// RUN: %clang --target=riscv32 -menable-experimental-extensions \
// RUN: -march=rv32izfbfmin1p0 -E -dM %s \
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td
b/llvm/lib/Target/RISCV/RISCVFeatures.td
index 89e1214f469da..b099496d18388 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -211,8 +211,8 @@ def FeatureStdExtZa128rs : RISCVExtension<"za128rs", 1, 0,
"'Za128rs' (Reservation Set Size of
at Most 128 Bytes)">;
def FeatureStdExtZaamo
-: RISCVExperimentalExtension<"zaamo", 0, 2,
- "'Zaamo' (Atomic Memory Operations)">;
+: RISCVExtension<"zaamo", 1, 0,
+ "'Zaamo' (Atomic Memory Operations)">;
def HasStdExtAOrZaamo
: Predicate<"Subtarget->hasStdExtA() || Subtarget->hasStdExtZaamo()">,
AssemblerPredicate<(any_of FeatureStdExtA, FeatureStdExtZaamo),
@@ -242,8 +242,8 @@ def HasStdExtZalasr :
Predicate<"Subtarget->hasStdExtZalasr()">,
"'Zalasr' (Load-Acquire and Store-Release
Instructions)">;
def FeatureStdExtZalrsc
-: RISCVExperimentalExtension<"zalrsc", 0, 2,
- "'Zalrsc' (Load-Reserved/Store-Conditional)">;
+: RISCVExtension<"zalrsc", 1, 0,
+ "'Zalrsc' (Load-Reserved/Store-Conditional)">;
def HasStdExtAOrZalrsc
: Predicate<"Subtarget->hasStdExtA() || Subtarget->hasStdExtZalrsc()">,
AssemblerPredicate<(any_of FeatureStdExtA, FeatureStdExtZalrsc),
diff --git a/llvm/test/CodeGen/RISCV/attributes.ll
b/llvm/test/CodeGen/RISCV/attributes.ll
index 8f49f6648ad28..9fdd842e5dd37 100644
--- a/llvm/test/CodeGen/RISCV/attributes.ll
+++ b/llvm/test/CodeGen/RISCV/attributes.ll
@@ -112,10 +112,10 @@
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zfbfmin %s -o - | FileCheck
--check-prefixes=CHECK,RV32ZFBFMIN %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zvfbfmin %s -o - | FileCheck
[clang] [llvm] [RISCV] Bump Zaamo and Zalrsc to version 1.0 (PR #91556)
@@ -1554,13 +1554,13 @@
// CHECK-ZVKT-EXT: __riscv_zvkt 100{{$}}
// Experimental extensions
-// RUN: %clang --target=riscv32 -menable-experimental-extensions \
-// RUN: -march=rv32i_zaamo0p2 -E -dM %s \
+// RUN: %clang --target=riscv32 \
4vtomat wrote:
Oh, I see. Thanks for catching this!
https://github.com/llvm/llvm-project/pull/91556
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[clang] [RISCV] Remove unneeded multiply in RISCV CodeGenTypes (PR #92644)
https://github.com/4vtomat closed https://github.com/llvm/llvm-project/pull/92644 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [RISCV] Remove unneeded multiply in RISCV CodeGenTypes (PR #92644)
https://github.com/4vtomat created
https://github.com/llvm/llvm-project/pull/92644
The NumVectors other than 1 is handled by the code above.
>From 4dbcf6e577d5f1aea0cde72e3a5a7fd73620b2d9 Mon Sep 17 00:00:00 2001
From: Brandon Wu
Date: Sat, 18 May 2024 03:07:43 -0700
Subject: [PATCH] [RISCV] Remove unneeded multiply in RISCV CodeGenTypes
The NumVectors other than 1 is handled by the code above.
---
clang/lib/CodeGen/CodeGenTypes.cpp | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/clang/lib/CodeGen/CodeGenTypes.cpp
b/clang/lib/CodeGen/CodeGenTypes.cpp
index e8d75eda029e6..0a926e4ac27fe 100644
--- a/clang/lib/CodeGen/CodeGenTypes.cpp
+++ b/clang/lib/CodeGen/CodeGenTypes.cpp
@@ -523,8 +523,7 @@ llvm::Type *CodeGenTypes::ConvertType(QualType T) {
return llvm::StructType::get(getLLVMContext(), EltTys);
}
return llvm::ScalableVectorType::get(ConvertType(Info.ElementType),
- Info.EC.getKnownMinValue() *
- Info.NumVectors);
+ Info.EC.getKnownMinValue());
}
#define WASM_REF_TYPE(Name, MangledName, Id, SingletonId, AS)
\
case BuiltinType::Id: {
\
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[clang] [llvm] [RISCV] Bump Zaamo and Zalrsc to version 1.0 (PR #91556)
4vtomat wrote: > > > Need to update RISCVUsage.rst and ReleaseNotes.rst > > > > > > Is it going to be cherry-picked to release branch? > > No. We just try to update the ReleaseNotes proactively for LLVM 19. Got it! https://github.com/llvm/llvm-project/pull/91556 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Bump Zaamo and Zalrsc to version 1.0 (PR #91556)
https://github.com/4vtomat updated
https://github.com/llvm/llvm-project/pull/91556
>From 062d7d5017b01fb3afbaffe1a34487cfe36288d2 Mon Sep 17 00:00:00 2001
From: Brandon Wu
Date: Wed, 8 May 2024 21:43:07 -0700
Subject: [PATCH 1/2] [RISCV] Bump Zaamo and Zalrsc to version 1.0
The ratified information can be found here:
https://wiki.riscv.org/display/HOME/Ratified+Extensions
---
.../test/Preprocessor/riscv-target-features.c | 20 +--
llvm/lib/Target/RISCV/RISCVFeatures.td| 8
llvm/test/CodeGen/RISCV/attributes.ll | 16 +++
llvm/test/MC/RISCV/rv32zaamo-invalid.s| 2 +-
llvm/test/MC/RISCV/rv32zaamo-valid.s | 12 +--
llvm/test/MC/RISCV/rv32zalrsc-invalid.s | 2 +-
llvm/test/MC/RISCV/rv32zalrsc-valid.s | 12 +--
llvm/test/MC/RISCV/rv64zaamo-invalid.s| 2 +-
llvm/test/MC/RISCV/rv64zaamo-valid.s | 8
llvm/test/MC/RISCV/rv64zalrsc-invalid.s | 2 +-
llvm/test/MC/RISCV/rv64zalrsc-valid.s | 8
.../TargetParser/RISCVISAInfoTest.cpp | 4 ++--
12 files changed, 48 insertions(+), 48 deletions(-)
diff --git a/clang/test/Preprocessor/riscv-target-features.c
b/clang/test/Preprocessor/riscv-target-features.c
index 913093bb51db6..ead9ac9b4063f 100644
--- a/clang/test/Preprocessor/riscv-target-features.c
+++ b/clang/test/Preprocessor/riscv-target-features.c
@@ -1554,13 +1554,13 @@
// CHECK-ZVKT-EXT: __riscv_zvkt 100{{$}}
// Experimental extensions
-// RUN: %clang --target=riscv32 -menable-experimental-extensions \
-// RUN: -march=rv32i_zaamo0p2 -E -dM %s \
+// RUN: %clang --target=riscv32 \
+// RUN: -march=rv32i_zaamo1p0 -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZAAMO-EXT %s
-// RUN: %clang --target=riscv64 -menable-experimental-extensions \
-// RUN: -march=rv64i_zaamo0p2 -E -dM %s \
+// RUN: %clang --target=riscv64 \
+// RUN: -march=rv64i_zaamo1p0 -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZAAMO-EXT %s
-// CHECK-ZAAMO-EXT: __riscv_zaamo 2000{{$}}
+// CHECK-ZAAMO-EXT: __riscv_zaamo 100{{$}}
// RUN: %clang --target=riscv32 -menable-experimental-extensions \
// RUN: -march=rv32ia_zabha1p0 -E -dM %s \
@@ -1578,13 +1578,13 @@
// RUN: -o - | FileCheck --check-prefix=CHECK-ZALASR-EXT %s
// CHECK-ZALASR-EXT: __riscv_zalasr 1000{{$}}
-// RUN: %clang --target=riscv32 -menable-experimental-extensions \
-// RUN: -march=rv32i_zalrsc0p2 -E -dM %s \
+// RUN: %clang --target=riscv32 \
+// RUN: -march=rv32i_zalrsc1p0 -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZALRSC-EXT %s
-// RUN: %clang --target=riscv64 -menable-experimental-extensions \
-// RUN: -march=rv64i_zalrsc0p2 -E -dM %s \
+// RUN: %clang --target=riscv64 \
+// RUN: -march=rv64i_zalrsc1p0 -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZALRSC-EXT %s
-// CHECK-ZALRSC-EXT: __riscv_zalrsc 2000{{$}}
+// CHECK-ZALRSC-EXT: __riscv_zalrsc 100{{$}}
// RUN: %clang --target=riscv32 -menable-experimental-extensions \
// RUN: -march=rv32izfbfmin1p0 -E -dM %s \
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td
b/llvm/lib/Target/RISCV/RISCVFeatures.td
index 89e1214f469da..b099496d18388 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -211,8 +211,8 @@ def FeatureStdExtZa128rs : RISCVExtension<"za128rs", 1, 0,
"'Za128rs' (Reservation Set Size of
at Most 128 Bytes)">;
def FeatureStdExtZaamo
-: RISCVExperimentalExtension<"zaamo", 0, 2,
- "'Zaamo' (Atomic Memory Operations)">;
+: RISCVExtension<"zaamo", 1, 0,
+ "'Zaamo' (Atomic Memory Operations)">;
def HasStdExtAOrZaamo
: Predicate<"Subtarget->hasStdExtA() || Subtarget->hasStdExtZaamo()">,
AssemblerPredicate<(any_of FeatureStdExtA, FeatureStdExtZaamo),
@@ -242,8 +242,8 @@ def HasStdExtZalasr :
Predicate<"Subtarget->hasStdExtZalasr()">,
"'Zalasr' (Load-Acquire and Store-Release
Instructions)">;
def FeatureStdExtZalrsc
-: RISCVExperimentalExtension<"zalrsc", 0, 2,
- "'Zalrsc' (Load-Reserved/Store-Conditional)">;
+: RISCVExtension<"zalrsc", 1, 0,
+ "'Zalrsc' (Load-Reserved/Store-Conditional)">;
def HasStdExtAOrZalrsc
: Predicate<"Subtarget->hasStdExtA() || Subtarget->hasStdExtZalrsc()">,
AssemblerPredicate<(any_of FeatureStdExtA, FeatureStdExtZalrsc),
diff --git a/llvm/test/CodeGen/RISCV/attributes.ll
b/llvm/test/CodeGen/RISCV/attributes.ll
index 8f49f6648ad28..9fdd842e5dd37 100644
--- a/llvm/test/CodeGen/RISCV/attributes.ll
+++ b/llvm/test/CodeGen/RISCV/attributes.ll
@@ -112,10 +112,10 @@
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zfbfmin %s -o - | FileCheck
--check-prefixes=CHECK,RV32ZFBFMIN %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zvfbfmin %s -o - | FileCheck
[clang] [llvm] [RISCV] Bump Zaamo and Zalrsc to version 1.0 (PR #91556)
4vtomat wrote: > Need to update RISCVUsage.rst and ReleaseNotes.rst Is it going to be cherry-picked to release branch? https://github.com/llvm/llvm-project/pull/91556 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Bump Zaamo and Zalrsc to version 1.0 (PR #91556)
https://github.com/4vtomat created
https://github.com/llvm/llvm-project/pull/91556
The ratified information can be found here:
https://wiki.riscv.org/display/HOME/Ratified+Extensions
>From 062d7d5017b01fb3afbaffe1a34487cfe36288d2 Mon Sep 17 00:00:00 2001
From: Brandon Wu
Date: Wed, 8 May 2024 21:43:07 -0700
Subject: [PATCH] [RISCV] Bump Zaamo and Zalrsc to version 1.0
The ratified information can be found here:
https://wiki.riscv.org/display/HOME/Ratified+Extensions
---
.../test/Preprocessor/riscv-target-features.c | 20 +--
llvm/lib/Target/RISCV/RISCVFeatures.td| 8
llvm/test/CodeGen/RISCV/attributes.ll | 16 +++
llvm/test/MC/RISCV/rv32zaamo-invalid.s| 2 +-
llvm/test/MC/RISCV/rv32zaamo-valid.s | 12 +--
llvm/test/MC/RISCV/rv32zalrsc-invalid.s | 2 +-
llvm/test/MC/RISCV/rv32zalrsc-valid.s | 12 +--
llvm/test/MC/RISCV/rv64zaamo-invalid.s| 2 +-
llvm/test/MC/RISCV/rv64zaamo-valid.s | 8
llvm/test/MC/RISCV/rv64zalrsc-invalid.s | 2 +-
llvm/test/MC/RISCV/rv64zalrsc-valid.s | 8
.../TargetParser/RISCVISAInfoTest.cpp | 4 ++--
12 files changed, 48 insertions(+), 48 deletions(-)
diff --git a/clang/test/Preprocessor/riscv-target-features.c
b/clang/test/Preprocessor/riscv-target-features.c
index 913093bb51db6..ead9ac9b4063f 100644
--- a/clang/test/Preprocessor/riscv-target-features.c
+++ b/clang/test/Preprocessor/riscv-target-features.c
@@ -1554,13 +1554,13 @@
// CHECK-ZVKT-EXT: __riscv_zvkt 100{{$}}
// Experimental extensions
-// RUN: %clang --target=riscv32 -menable-experimental-extensions \
-// RUN: -march=rv32i_zaamo0p2 -E -dM %s \
+// RUN: %clang --target=riscv32 \
+// RUN: -march=rv32i_zaamo1p0 -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZAAMO-EXT %s
-// RUN: %clang --target=riscv64 -menable-experimental-extensions \
-// RUN: -march=rv64i_zaamo0p2 -E -dM %s \
+// RUN: %clang --target=riscv64 \
+// RUN: -march=rv64i_zaamo1p0 -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZAAMO-EXT %s
-// CHECK-ZAAMO-EXT: __riscv_zaamo 2000{{$}}
+// CHECK-ZAAMO-EXT: __riscv_zaamo 100{{$}}
// RUN: %clang --target=riscv32 -menable-experimental-extensions \
// RUN: -march=rv32ia_zabha1p0 -E -dM %s \
@@ -1578,13 +1578,13 @@
// RUN: -o - | FileCheck --check-prefix=CHECK-ZALASR-EXT %s
// CHECK-ZALASR-EXT: __riscv_zalasr 1000{{$}}
-// RUN: %clang --target=riscv32 -menable-experimental-extensions \
-// RUN: -march=rv32i_zalrsc0p2 -E -dM %s \
+// RUN: %clang --target=riscv32 \
+// RUN: -march=rv32i_zalrsc1p0 -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZALRSC-EXT %s
-// RUN: %clang --target=riscv64 -menable-experimental-extensions \
-// RUN: -march=rv64i_zalrsc0p2 -E -dM %s \
+// RUN: %clang --target=riscv64 \
+// RUN: -march=rv64i_zalrsc1p0 -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-ZALRSC-EXT %s
-// CHECK-ZALRSC-EXT: __riscv_zalrsc 2000{{$}}
+// CHECK-ZALRSC-EXT: __riscv_zalrsc 100{{$}}
// RUN: %clang --target=riscv32 -menable-experimental-extensions \
// RUN: -march=rv32izfbfmin1p0 -E -dM %s \
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td
b/llvm/lib/Target/RISCV/RISCVFeatures.td
index 89e1214f469da..b099496d18388 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -211,8 +211,8 @@ def FeatureStdExtZa128rs : RISCVExtension<"za128rs", 1, 0,
"'Za128rs' (Reservation Set Size of
at Most 128 Bytes)">;
def FeatureStdExtZaamo
-: RISCVExperimentalExtension<"zaamo", 0, 2,
- "'Zaamo' (Atomic Memory Operations)">;
+: RISCVExtension<"zaamo", 1, 0,
+ "'Zaamo' (Atomic Memory Operations)">;
def HasStdExtAOrZaamo
: Predicate<"Subtarget->hasStdExtA() || Subtarget->hasStdExtZaamo()">,
AssemblerPredicate<(any_of FeatureStdExtA, FeatureStdExtZaamo),
@@ -242,8 +242,8 @@ def HasStdExtZalasr :
Predicate<"Subtarget->hasStdExtZalasr()">,
"'Zalasr' (Load-Acquire and Store-Release
Instructions)">;
def FeatureStdExtZalrsc
-: RISCVExperimentalExtension<"zalrsc", 0, 2,
- "'Zalrsc' (Load-Reserved/Store-Conditional)">;
+: RISCVExtension<"zalrsc", 1, 0,
+ "'Zalrsc' (Load-Reserved/Store-Conditional)">;
def HasStdExtAOrZalrsc
: Predicate<"Subtarget->hasStdExtA() || Subtarget->hasStdExtZalrsc()">,
AssemblerPredicate<(any_of FeatureStdExtA, FeatureStdExtZalrsc),
diff --git a/llvm/test/CodeGen/RISCV/attributes.ll
b/llvm/test/CodeGen/RISCV/attributes.ll
index 8f49f6648ad28..9fdd842e5dd37 100644
--- a/llvm/test/CodeGen/RISCV/attributes.ll
+++ b/llvm/test/CodeGen/RISCV/attributes.ll
@@ -112,10 +112,10 @@
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zfbfmin %s -o - | FileCheck
[clang] [llvm] [RISCV] Make parseArchString only accept [a-z0-9_]. (PR #90879)
https://github.com/4vtomat approved this pull request. LGTM～ https://github.com/llvm/llvm-project/pull/90879 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [Clang][RISCV] Handle RVV tuple types correctly as InputOperand/OutputOperand for inline asm (PR #89883)
4vtomat wrote: Ping. https://github.com/llvm/llvm-project/pull/89883 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [clang][RISCV] Remove LMUL=8 scalar input for some vector crypto instructions (PR #89867)
https://github.com/4vtomat closed https://github.com/llvm/llvm-project/pull/89867 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [Clang][RISCV] Handle RVV tuple types correctly as InputOperand/OutputOperand for inline asm (PR #89883)
https://github.com/4vtomat edited https://github.com/llvm/llvm-project/pull/89883 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [Clang][RISCV] Handle RVV tuple types correctly as InputOperand/OutputOperand for inline asm (PR #89883)
https://github.com/4vtomat edited https://github.com/llvm/llvm-project/pull/89883 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [Clang][RISCV] Handle RVV tuple types correctly as OutputOperand for inline asm (PR #89883)
https://github.com/4vtomat updated
https://github.com/llvm/llvm-project/pull/89883
>From 671bebcb9ad76aa3b43dabada3ab7a75d6934d73 Mon Sep 17 00:00:00 2001
From: eopXD
Date: Thu, 21 Sep 2023 06:34:57 -0700
Subject: [PATCH 1/2] [Clang][RISCV] Handle RVV tuple types correctly as
InputOperand/OutputOperand for inline asm
The RVV tuple type maps to an aggregate type with homogeneous scalable
vectors. EmitAsmStmt does not handle this correctly and this commit
attempts to fix it.
Get pass validation check for homogeneous scalable vector types in
InlineAsm::verify.
Handle RVV tuple types correctly under CGStmt.cpp:EmitAsmStores, since
we can allow direct store for the tuple types.
A follow-up commit will deal with details when associated with
InputOperands.
Note: Input tuple type operands doesn't need another process since it
can be passed directly.
Co-authored-by: Brandon Wu
---
clang/lib/CodeGen/CGStmt.cpp | 40 ---
.../rvv-inline-asm.c | 29 ++
llvm/lib/IR/InlineAsm.cpp | 11 -
3 files changed, 63 insertions(+), 17 deletions(-)
create mode 100644
clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-inline-asm.c
diff --git a/clang/lib/CodeGen/CGStmt.cpp b/clang/lib/CodeGen/CGStmt.cpp
index 576fe2f7a2d46f..099faf419ba5cd 100644
--- a/clang/lib/CodeGen/CGStmt.cpp
+++ b/clang/lib/CodeGen/CGStmt.cpp
@@ -29,6 +29,7 @@
#include "llvm/ADT/SmallSet.h"
#include "llvm/ADT/StringExtras.h"
#include "llvm/IR/Assumptions.h"
+#include "llvm/IR/Constants.h"
#include "llvm/IR/DataLayout.h"
#include "llvm/IR/InlineAsm.h"
#include "llvm/IR/Intrinsics.h"
@@ -2487,22 +2488,28 @@ EmitAsmStores(CodeGenFunction , const AsmStmt ,
// ResultTypeRequiresCast elements correspond to the first
// ResultTypeRequiresCast.size() elements of RegResults.
if ((i < ResultTypeRequiresCast.size()) && ResultTypeRequiresCast[i]) {
- unsigned Size = CGF.getContext().getTypeSize(ResultRegQualTys[i]);
- Address A = Dest.getAddress(CGF).withElementType(ResultRegTypes[i]);
- if (CGF.getTargetHooks().isScalarizableAsmOperand(CGF, TruncTy)) {
-Builder.CreateStore(Tmp, A);
-continue;
- }
+ if (ResultRegQualTys[i]->isRVVSizelessBuiltinType() &&
+ Tmp->getType()->isStructTy()) {
+Address A = Dest.getAddress(CGF).withElementType(ResultRegTypes[i]);
+Dest = CGF.MakeAddrLValue(A, ResultRegQualTys[i]);
+ } else {
+unsigned Size = CGF.getContext().getTypeSize(ResultRegQualTys[i]);
+Address A = Dest.getAddress(CGF).withElementType(ResultRegTypes[i]);
+if (CGF.getTargetHooks().isScalarizableAsmOperand(CGF, TruncTy)) {
+ Builder.CreateStore(Tmp, A);
+ continue;
+}
- QualType Ty =
- CGF.getContext().getIntTypeForBitwidth(Size, /*Signed=*/false);
- if (Ty.isNull()) {
-const Expr *OutExpr = S.getOutputExpr(i);
-CGM.getDiags().Report(OutExpr->getExprLoc(),
- diag::err_store_value_to_reg);
-return;
+QualType Ty =
+CGF.getContext().getIntTypeForBitwidth(Size, /*Signed=*/false);
+if (Ty.isNull()) {
+ const Expr *OutExpr = S.getOutputExpr(i);
+ CGM.getDiags().Report(OutExpr->getExprLoc(),
+diag::err_store_value_to_reg);
+ return;
+}
+Dest = CGF.MakeAddrLValue(A, Ty);
}
- Dest = CGF.MakeAddrLValue(A, Ty);
}
CGF.EmitStoreThroughLValue(RValue::get(Tmp), Dest);
}
@@ -2648,7 +2655,10 @@ void CodeGenFunction::EmitAsmStmt(const AsmStmt ) {
ResultTruncRegTypes.push_back(Ty);
ResultTypeRequiresCast.push_back(RequiresCast);
- if (RequiresCast) {
+ // Allow RVV tuple type (aggregate of homogeneous scalable vector) to be
+ // pushed into return type of inline asm call.
+ if (RequiresCast &&
+ !(QTy->isRVVSizelessBuiltinType() && Ty->isStructTy())) {
unsigned Size = getContext().getTypeSize(QTy);
Ty = llvm::IntegerType::get(getLLVMContext(), Size);
}
diff --git
a/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-inline-asm.c
b/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-inline-asm.c
new file mode 100644
index 00..c5beb33d0ef8cd
--- /dev/null
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-inline-asm.c
@@ -0,0 +1,29 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
UTC_ARGS: --version 3
+#include
+
+// RUN: %clang_cc1 -triple riscv64 -target-feature +zve32x -disable-O0-optnone
\
+// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | FileCheck %s
+
+// CHECK-LABEL: define dso_local void @foo(
+// CHECK-SAME: ) #[[ATTR0:[0-9]+]] {
+// CHECK-NEXT: entry:
+// CHECK-NEXT:[[TMP0:%.*]] = call { ,
} asm "#NOP", "=^vr"() #[[ATTR1:[0-9]+]], !srcloc [[META6:![0-9]+]]
+// CHECK-NEXT:ret void
[clang] [llvm] [Clang][RISCV] Handle RVV tuple types correctly as OutputOperand for inline asm (PR #89883)
https://github.com/4vtomat edited https://github.com/llvm/llvm-project/pull/89883 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [Clang][RISCV] Handle RVV tuple types correctly as OutputOperand for inline asm (PR #89883)
https://github.com/4vtomat created
https://github.com/llvm/llvm-project/pull/89883
The RVV tuple type maps to an aggregate type with homogeneous scalable
vectors. EmitAsmStmt does not handle this correctly and this commit
attempts to fix it.
Get pass validation check for homogeneous scalable vector types in
InlineAsm::verify.
Handle RVV tuple types correctly under CGStmt.cpp:EmitAsmStores, since
we can allow direct store for the tuple types.
A follow-up commit will deal with details when associated with
InputOperands.
Co-authored-by: Brandon Wu
>From e12940b301f955fd72850ebb8a1621854f22c868 Mon Sep 17 00:00:00 2001
From: eopXD
Date: Thu, 21 Sep 2023 06:34:57 -0700
Subject: [PATCH] [Clang][RISCV] Handle RVV tuple types correctly as
OutputOperand for inline asm
The RVV tuple type maps to an aggregate type with homogeneous scalable
vectors. EmitAsmStmt does not handle this correctly and this commit
attempts to fix it.
Get pass validation check for homogeneous scalable vector types in
InlineAsm::verify.
Handle RVV tuple types correctly under CGStmt.cpp:EmitAsmStores, since
we can allow direct store for the tuple types.
A follow-up commit will deal with details when associated with
InputOperands.
Co-authored-by: Brandon Wu
---
clang/lib/CodeGen/CGStmt.cpp | 40 ---
.../rvv-inline-asm.c | 29 ++
llvm/lib/IR/InlineAsm.cpp | 11 -
3 files changed, 63 insertions(+), 17 deletions(-)
create mode 100644
clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-inline-asm.c
diff --git a/clang/lib/CodeGen/CGStmt.cpp b/clang/lib/CodeGen/CGStmt.cpp
index 576fe2f7a2d46f..099faf419ba5cd 100644
--- a/clang/lib/CodeGen/CGStmt.cpp
+++ b/clang/lib/CodeGen/CGStmt.cpp
@@ -29,6 +29,7 @@
#include "llvm/ADT/SmallSet.h"
#include "llvm/ADT/StringExtras.h"
#include "llvm/IR/Assumptions.h"
+#include "llvm/IR/Constants.h"
#include "llvm/IR/DataLayout.h"
#include "llvm/IR/InlineAsm.h"
#include "llvm/IR/Intrinsics.h"
@@ -2487,22 +2488,28 @@ EmitAsmStores(CodeGenFunction , const AsmStmt ,
// ResultTypeRequiresCast elements correspond to the first
// ResultTypeRequiresCast.size() elements of RegResults.
if ((i < ResultTypeRequiresCast.size()) && ResultTypeRequiresCast[i]) {
- unsigned Size = CGF.getContext().getTypeSize(ResultRegQualTys[i]);
- Address A = Dest.getAddress(CGF).withElementType(ResultRegTypes[i]);
- if (CGF.getTargetHooks().isScalarizableAsmOperand(CGF, TruncTy)) {
-Builder.CreateStore(Tmp, A);
-continue;
- }
+ if (ResultRegQualTys[i]->isRVVSizelessBuiltinType() &&
+ Tmp->getType()->isStructTy()) {
+Address A = Dest.getAddress(CGF).withElementType(ResultRegTypes[i]);
+Dest = CGF.MakeAddrLValue(A, ResultRegQualTys[i]);
+ } else {
+unsigned Size = CGF.getContext().getTypeSize(ResultRegQualTys[i]);
+Address A = Dest.getAddress(CGF).withElementType(ResultRegTypes[i]);
+if (CGF.getTargetHooks().isScalarizableAsmOperand(CGF, TruncTy)) {
+ Builder.CreateStore(Tmp, A);
+ continue;
+}
- QualType Ty =
- CGF.getContext().getIntTypeForBitwidth(Size, /*Signed=*/false);
- if (Ty.isNull()) {
-const Expr *OutExpr = S.getOutputExpr(i);
-CGM.getDiags().Report(OutExpr->getExprLoc(),
- diag::err_store_value_to_reg);
-return;
+QualType Ty =
+CGF.getContext().getIntTypeForBitwidth(Size, /*Signed=*/false);
+if (Ty.isNull()) {
+ const Expr *OutExpr = S.getOutputExpr(i);
+ CGM.getDiags().Report(OutExpr->getExprLoc(),
+diag::err_store_value_to_reg);
+ return;
+}
+Dest = CGF.MakeAddrLValue(A, Ty);
}
- Dest = CGF.MakeAddrLValue(A, Ty);
}
CGF.EmitStoreThroughLValue(RValue::get(Tmp), Dest);
}
@@ -2648,7 +2655,10 @@ void CodeGenFunction::EmitAsmStmt(const AsmStmt ) {
ResultTruncRegTypes.push_back(Ty);
ResultTypeRequiresCast.push_back(RequiresCast);
- if (RequiresCast) {
+ // Allow RVV tuple type (aggregate of homogeneous scalable vector) to be
+ // pushed into return type of inline asm call.
+ if (RequiresCast &&
+ !(QTy->isRVVSizelessBuiltinType() && Ty->isStructTy())) {
unsigned Size = getContext().getTypeSize(QTy);
Ty = llvm::IntegerType::get(getLLVMContext(), Size);
}
diff --git
a/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-inline-asm.c
b/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-inline-asm.c
new file mode 100644
index 00..c5beb33d0ef8cd
--- /dev/null
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-inline-asm.c
@@ -0,0 +1,29 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
UTC_ARGS: --version 3
+#include
+
+// RUN: %clang_cc1 -triple riscv64
[clang] [clang][RISCV] Remove LMUL=8 scalar input for some vector crypto instructions (PR #89867)
https://github.com/4vtomat updated
https://github.com/llvm/llvm-project/pull/89867
>From 4db9d00610f110a163a1b7d5b168461f6a91f4ed Mon Sep 17 00:00:00 2001
From: Brandon Wu
Date: Tue, 23 Apr 2024 20:42:33 -0700
Subject: [PATCH] [clang][RISCV] Remove LMUL=8 scalar input for some vector
crypto instructions
Since the requirement is EEW=32, it's impossible that EGW=128 needs LMUL=8.
---
clang/include/clang/Basic/riscv_vector.td | 3 +--
.../non-policy/non-overloaded/vaesdf.c | 10 --
.../non-policy/non-overloaded/vaesdm.c | 10 --
.../non-policy/non-overloaded/vaesef.c | 10 --
.../non-policy/non-overloaded/vaesem.c | 10 --
.../non-policy/non-overloaded/vaesz.c | 10 --
.../non-policy/non-overloaded/vsm4r.c | 10 --
.../non-policy/overloaded/vaesdf.c | 10 --
.../non-policy/overloaded/vaesdm.c | 10 --
.../non-policy/overloaded/vaesef.c | 10 --
.../non-policy/overloaded/vaesem.c | 10 --
.../non-policy/overloaded/vaesz.c | 10 --
.../non-policy/overloaded/vsm4r.c | 10 --
.../policy/non-overloaded/vaesdf.c | 10 --
.../policy/non-overloaded/vaesdm.c | 10 --
.../policy/non-overloaded/vaesef.c | 10 --
.../policy/non-overloaded/vaesem.c | 10 --
.../policy/non-overloaded/vaesz.c | 10 --
.../policy/non-overloaded/vsm4r.c | 10 --
.../policy/overloaded/vaesdf.c | 10 --
.../policy/overloaded/vaesdm.c | 10 --
.../policy/overloaded/vaesef.c | 10 --
.../policy/overloaded/vaesem.c | 10 --
.../policy/overloaded/vaesz.c | 10 --
.../policy/overloaded/vsm4r.c | 10 --
25 files changed, 1 insertion(+), 242 deletions(-)
diff --git a/clang/include/clang/Basic/riscv_vector.td
b/clang/include/clang/Basic/riscv_vector.td
index 98ae17ec22a047..cca4367751b92b 100644
--- a/clang/include/clang/Basic/riscv_vector.td
+++ b/clang/include/clang/Basic/riscv_vector.td
@@ -2601,8 +2601,7 @@ multiclass RVVOutBuiltinSetZvk {
if HasVS then {
foreach vs2_lmul = ["(SEFixedLog2LMUL:-1)", "(SEFixedLog2LMUL:0)",
-"(SEFixedLog2LMUL:1)", "(SEFixedLog2LMUL:2)",
-"(SEFixedLog2LMUL:3)"] in {
+"(SEFixedLog2LMUL:1)", "(SEFixedLog2LMUL:2)"] in {
defvar name = NAME # !if(!eq(NAME, "vaesz"), "", "_vs");
let OverloadedName = name, IRName = NAME # "_vs", Name = NAME # "_vs",
IntrinsicTypes = [-1, 1] in
diff --git
a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesdf.c
b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesdf.c
index 76a9ddc0d52946..3e37ac4b774997 100644
---
a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesdf.c
+++
b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesdf.c
@@ -206,13 +206,3 @@ vuint32m8_t test_vaesdf_vv_u32m8(vuint32m8_t vd,
vuint32m8_t vs2, size_t vl) {
return __riscv_vaesdf_vv_u32m8(vd, vs2, vl);
}
-// CHECK-RV64-LABEL: define dso_local
@test_vaesdf_vs_u32m8_u32m8
-// CHECK-RV64-SAME: ( [[VD:%.*]],
[[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT:[[TMP0:%.*]] = call
@llvm.riscv.vaesdf.vs.nxv16i32.nxv16i32.i64( [[VD]], [[VS2]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT:ret [[TMP0]]
-//
-vuint32m8_t test_vaesdf_vs_u32m8_u32m8(vuint32m8_t vd, vuint32m8_t vs2, size_t
vl) {
- return __riscv_vaesdf_vs_u32m8_u32m8(vd, vs2, vl);
-}
-
diff --git
a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesdm.c
b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesdm.c
index 468c3f18378d3c..c29c1e983fce67 100644
---
a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesdm.c
+++
b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesdm.c
@@ -206,13 +206,3 @@ vuint32m8_t test_vaesdm_vv_u32m8(vuint32m8_t vd,
vuint32m8_t vs2, size_t vl) {
return __riscv_vaesdm_vv_u32m8(vd, vs2, vl);
}
-// CHECK-RV64-LABEL: define dso_local
@test_vaesdm_vs_u32m8_u32m8
-// CHECK-RV64-SAME: ( [[VD:%.*]],
[[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT:[[TMP0:%.*]] = call
@llvm.riscv.vaesdm.vs.nxv16i32.nxv16i32.i64( [[VD]], [[VS2]], i64 [[VL]], i64 3)
-//
[clang] [clang][RISCV] Remove LMUL=8 scalar input for some vector crypto instructions (PR #89867)
https://github.com/4vtomat edited https://github.com/llvm/llvm-project/pull/89867 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [clang][RISCV] Remove LMUL=8 scalar input for some vector crypto instructions (PR #89867)
https://github.com/4vtomat created
https://github.com/llvm/llvm-project/pull/89867
Since the minimum requirement is EEW=32, it's impossible that EGW=128
needs LMUL=8.
>From 1ed74c3732194512da7eee2e16bc252269f0e6ef Mon Sep 17 00:00:00 2001
From: Brandon Wu
Date: Tue, 23 Apr 2024 20:42:33 -0700
Subject: [PATCH] [clang][RISCV] Remove LMUL=8 scalar input for some vector
crypto instructions
Since the minimum requirement is EEW=32, it's impossible that EGW=128
needs LMUL=8.
---
clang/include/clang/Basic/riscv_vector.td | 3 +--
.../non-policy/non-overloaded/vaesdf.c | 10 --
.../non-policy/non-overloaded/vaesdm.c | 10 --
.../non-policy/non-overloaded/vaesef.c | 10 --
.../non-policy/non-overloaded/vaesem.c | 10 --
.../non-policy/non-overloaded/vaesz.c | 10 --
.../non-policy/non-overloaded/vsm4r.c | 10 --
.../non-policy/overloaded/vaesdf.c | 10 --
.../non-policy/overloaded/vaesdm.c | 10 --
.../non-policy/overloaded/vaesef.c | 10 --
.../non-policy/overloaded/vaesem.c | 10 --
.../non-policy/overloaded/vaesz.c | 10 --
.../non-policy/overloaded/vsm4r.c | 10 --
.../policy/non-overloaded/vaesdf.c | 10 --
.../policy/non-overloaded/vaesdm.c | 10 --
.../policy/non-overloaded/vaesef.c | 10 --
.../policy/non-overloaded/vaesem.c | 10 --
.../policy/non-overloaded/vaesz.c | 10 --
.../policy/non-overloaded/vsm4r.c | 10 --
.../policy/overloaded/vaesdf.c | 10 --
.../policy/overloaded/vaesdm.c | 10 --
.../policy/overloaded/vaesef.c | 10 --
.../policy/overloaded/vaesem.c | 10 --
.../policy/overloaded/vaesz.c | 10 --
.../policy/overloaded/vsm4r.c | 10 --
25 files changed, 1 insertion(+), 242 deletions(-)
diff --git a/clang/include/clang/Basic/riscv_vector.td
b/clang/include/clang/Basic/riscv_vector.td
index 98ae17ec22a047..cca4367751b92b 100644
--- a/clang/include/clang/Basic/riscv_vector.td
+++ b/clang/include/clang/Basic/riscv_vector.td
@@ -2601,8 +2601,7 @@ multiclass RVVOutBuiltinSetZvk {
if HasVS then {
foreach vs2_lmul = ["(SEFixedLog2LMUL:-1)", "(SEFixedLog2LMUL:0)",
-"(SEFixedLog2LMUL:1)", "(SEFixedLog2LMUL:2)",
-"(SEFixedLog2LMUL:3)"] in {
+"(SEFixedLog2LMUL:1)", "(SEFixedLog2LMUL:2)"] in {
defvar name = NAME # !if(!eq(NAME, "vaesz"), "", "_vs");
let OverloadedName = name, IRName = NAME # "_vs", Name = NAME # "_vs",
IntrinsicTypes = [-1, 1] in
diff --git
a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesdf.c
b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesdf.c
index 76a9ddc0d52946..3e37ac4b774997 100644
---
a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesdf.c
+++
b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesdf.c
@@ -206,13 +206,3 @@ vuint32m8_t test_vaesdf_vv_u32m8(vuint32m8_t vd,
vuint32m8_t vs2, size_t vl) {
return __riscv_vaesdf_vv_u32m8(vd, vs2, vl);
}
-// CHECK-RV64-LABEL: define dso_local
@test_vaesdf_vs_u32m8_u32m8
-// CHECK-RV64-SAME: ( [[VD:%.*]],
[[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT:[[TMP0:%.*]] = call
@llvm.riscv.vaesdf.vs.nxv16i32.nxv16i32.i64( [[VD]], [[VS2]], i64 [[VL]], i64 3)
-// CHECK-RV64-NEXT:ret [[TMP0]]
-//
-vuint32m8_t test_vaesdf_vs_u32m8_u32m8(vuint32m8_t vd, vuint32m8_t vs2, size_t
vl) {
- return __riscv_vaesdf_vs_u32m8_u32m8(vd, vs2, vl);
-}
-
diff --git
a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesdm.c
b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesdm.c
index 468c3f18378d3c..c29c1e983fce67 100644
---
a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesdm.c
+++
b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesdm.c
@@ -206,13 +206,3 @@ vuint32m8_t test_vaesdm_vv_u32m8(vuint32m8_t vd,
vuint32m8_t vs2, size_t vl) {
return __riscv_vaesdm_vv_u32m8(vd, vs2, vl);
}
-// CHECK-RV64-LABEL: define dso_local
@test_vaesdm_vs_u32m8_u32m8
-// CHECK-RV64-SAME: ( [[VD:%.*]],
[[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
-// CHECK-RV64-NEXT: entry:
-// CHECK-RV64-NEXT:[[TMP0:%.*]] = call
[clang] [clang][RISCV] Support RVV bfloat16 C intrinsics (PR #89354)
https://github.com/4vtomat closed https://github.com/llvm/llvm-project/pull/89354 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [clang][RISCV] Support RVV bfloat16 C intrinsics (PR #89354)
4vtomat wrote: Oh, I forgot to remove them. Or do you think they should be moved to bfloat folder to make them consistent? https://github.com/llvm/llvm-project/pull/89354 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [clang][RISCV] Remove unneeded overloaded suffix for vcreate (PR #89241)
https://github.com/4vtomat closed https://github.com/llvm/llvm-project/pull/89241 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [clang][RISCV] Remove unneeded overloaded suffix for vcreate (PR #89241)
https://github.com/4vtomat created
https://github.com/llvm/llvm-project/pull/89241
Since `vcreate` doesn't support overload, we can remove it.
>From a29cda00de03552529b510eda427804f822278e6 Mon Sep 17 00:00:00 2001
From: Brandon Wu
Date: Thu, 18 Apr 2024 07:29:42 -0700
Subject: [PATCH] [clang][RISCV] Remove unneeded overloaded suffix for vcreate
Since `vcreate` doesn't support overload, we can remove it.
---
clang/include/clang/Basic/riscv_vector.td | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/clang/include/clang/Basic/riscv_vector.td
b/clang/include/clang/Basic/riscv_vector.td
index 87a18e8474ef50..76ed544f3b2bb1 100644
--- a/clang/include/clang/Basic/riscv_vector.td
+++ b/clang/include/clang/Basic/riscv_vector.td
@@ -357,13 +357,13 @@ multiclass RVVNonTupleVCreateBuiltin src_lmul_list> {
defvar src_s = FixedVString.S;
def vcreate # src_v # dst_v : RVVBuiltin;
+ "csilxfd">;
defvar src_uv = FixedVString.V;
defvar src_us = FixedVString.S;
def vcreate_u # src_uv # dst_uv : RVVBuiltin;
+ "csil">;
}
}
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[clang] [clang][RISCV] Enable RVV with function attribute __attribute__((target("arch=+v"))) (PR #83674)
https://github.com/4vtomat closed https://github.com/llvm/llvm-project/pull/83674 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [clang][RISCV] Enable RVV with function attribute __attribute__((target("arch=+v"))) (PR #83674)
4vtomat wrote: Rebase https://github.com/llvm/llvm-project/pull/83674 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [clang][RISCV] Enable RVV with function attribute __attribute__((target("arch=+v"))) (PR #83674)
https://github.com/4vtomat updated
https://github.com/llvm/llvm-project/pull/83674
>From 10ab0fa16e62e44b8d04b372f20b95018f065048 Mon Sep 17 00:00:00 2001
From: Brandon Wu
Date: Fri, 1 Mar 2024 09:52:35 -0800
Subject: [PATCH 1/3] [clang][RISCV] Enable RVV with function attribute
__attribute__((target("arch=+v")))
It is currently not possible to use "RVV type" and "RVV intrinsics" if
the "zve32x" is not enabled globally. However in some cases we may want
to use them only in some functions, for instance:
```
#include
__attribute__((target("+zve32x")))
vint32m1_t rvv_add(vint32m1_t v1, vint32m1_t v2, size_t vl) {
return __riscv_vadd(v1, v2, vl);
}
int other_add(int i1, int i2) {
return i1 + i2;
}
```
, it is supposed to be compilable even the vector is not specified, e.g.
`clang -target riscv64 -march=rv64gc -S test.c`.
---
clang/include/clang/Sema/Sema.h | 3 +-
clang/lib/Basic/Targets/RISCV.cpp | 3 +-
clang/lib/Sema/Sema.cpp | 7 +-
clang/lib/Sema/SemaChecking.cpp | 70 +++
clang/lib/Sema/SemaDecl.cpp | 9 ++-
.../RISCV/rvb-intrinsics/riscv32-zbb-error.c | 4 +-
.../RISCV/rvb-intrinsics/riscv64-zbkb-error.c | 12 ++--
.../rvv-intrinsics-handcrafted/rvv-error.c| 2 +-
clang/test/Sema/riscv-function-target-attr.c | 41 +++
clang/utils/TableGen/RISCVVEmitter.cpp| 4 --
10 files changed, 73 insertions(+), 82 deletions(-)
create mode 100644 clang/test/Sema/riscv-function-target-attr.c
diff --git a/clang/include/clang/Sema/Sema.h b/clang/include/clang/Sema/Sema.h
index 5ecd2f9eb2881f..3a1abd4c7892b8 100644
--- a/clang/include/clang/Sema/Sema.h
+++ b/clang/include/clang/Sema/Sema.h
@@ -2234,7 +2234,8 @@ class Sema final {
bool CheckRISCVLMUL(CallExpr *TheCall, unsigned ArgNum);
bool CheckRISCVBuiltinFunctionCall(const TargetInfo , unsigned BuiltinID,
CallExpr *TheCall);
- void checkRVVTypeSupport(QualType Ty, SourceLocation Loc, Decl *D);
+ void checkRVVTypeSupport(QualType Ty, SourceLocation Loc, Decl *D,
+ const llvm::StringMap );
bool CheckLoongArchBuiltinFunctionCall(const TargetInfo ,
unsigned BuiltinID, CallExpr
*TheCall);
bool CheckWebAssemblyBuiltinFunctionCall(const TargetInfo ,
diff --git a/clang/lib/Basic/Targets/RISCV.cpp
b/clang/lib/Basic/Targets/RISCV.cpp
index f3d705e1551fe2..d597309905b4cf 100644
--- a/clang/lib/Basic/Targets/RISCV.cpp
+++ b/clang/lib/Basic/Targets/RISCV.cpp
@@ -463,7 +463,8 @@ ParsedTargetAttr RISCVTargetInfo::parseTargetAttr(StringRef
Features) const {
Ret.Duplicate = "tune=";
Ret.Tune = AttrString;
-}
+} else if (Feature.starts_with("+"))
+ Ret.Features.push_back(Feature.str());
}
return Ret;
}
diff --git a/clang/lib/Sema/Sema.cpp b/clang/lib/Sema/Sema.cpp
index b55f433a8be76f..72393bea620526 100644
--- a/clang/lib/Sema/Sema.cpp
+++ b/clang/lib/Sema/Sema.cpp
@@ -2065,8 +2065,11 @@ void Sema::checkTypeSupport(QualType Ty, SourceLocation
Loc, ValueDecl *D) {
targetDiag(D->getLocation(), diag::note_defined_here, FD) << D;
}
-if (TI.hasRISCVVTypes() && Ty->isRVVSizelessBuiltinType())
- checkRVVTypeSupport(Ty, Loc, D);
+if (TI.hasRISCVVTypes() && Ty->isRVVSizelessBuiltinType() && FD) {
+ llvm::StringMap CallerFeatureMap;
+ Context.getFunctionFeatureMap(CallerFeatureMap, FD);
+ checkRVVTypeSupport(Ty, Loc, D, CallerFeatureMap);
+}
// Don't allow SVE types in functions without a SVE target.
if (Ty->isSVESizelessBuiltinType() && FD && FD->hasBody()) {
diff --git a/clang/lib/Sema/SemaChecking.cpp b/clang/lib/Sema/SemaChecking.cpp
index 08449581330934..447e73686b4f3f 100644
--- a/clang/lib/Sema/SemaChecking.cpp
+++ b/clang/lib/Sema/SemaChecking.cpp
@@ -5760,57 +5760,6 @@ static bool CheckInvalidVLENandLMUL(const TargetInfo
, CallExpr *TheCall,
bool Sema::CheckRISCVBuiltinFunctionCall(const TargetInfo ,
unsigned BuiltinID,
CallExpr *TheCall) {
- // CodeGenFunction can also detect this, but this gives a better error
- // message.
- bool FeatureMissing = false;
- SmallVector ReqFeatures;
- StringRef Features = Context.BuiltinInfo.getRequiredFeatures(BuiltinID);
- Features.split(ReqFeatures, ',', -1, false);
-
- // Check if each required feature is included
- for (StringRef F : ReqFeatures) {
-SmallVector ReqOpFeatures;
-F.split(ReqOpFeatures, '|');
-
-if (llvm::none_of(ReqOpFeatures,
- [](StringRef OF) { return TI.hasFeature(OF); })) {
- std::string FeatureStrs;
- bool IsExtension = true;
- for (StringRef OF : ReqOpFeatures) {
-// If the feature is 64bit, alter the string so it will print better in
-// the diagnostic.
-if (OF == "64bit") {
-
[clang] [llvm] [RISCV] RISCV vector calling convention (1/2) (PR #77560)
https://github.com/4vtomat edited https://github.com/llvm/llvm-project/pull/77560 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] RISCV vector calling convention (1/2) (PR #77560)
https://github.com/4vtomat closed https://github.com/llvm/llvm-project/pull/77560 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] RISCV vector calling convention (1/2) (PR #77560)
https://github.com/4vtomat updated
https://github.com/llvm/llvm-project/pull/77560
>From 08371002a08d8958cd23eecb5ff3c5f2f2661c0e Mon Sep 17 00:00:00 2001
From: 4vtomat
Date: Wed, 22 Mar 2023 22:58:35 -0700
Subject: [PATCH] [RISCV] RISCV vector calling convention (1/2)
This is the vector calling convention based on
https://github.com/riscv-non-isa/riscv-elf-psabi-doc,
the idea is to split between "scalar" callee-saved registers
and "vector" callee-saved registers. "scalar" ones remain the
original strategy, however, "vector" ones are handled together
with RVV objects.
The stack layout would be:
|--| <-- FP
| callee-allocated save|
| area for register varargs|
|--|
| callee-saved registers | <-- scalar callee-saved
|(scalar) |
|--|
| RVV alignment padding|
|--|
| callee-saved registers | <-- vector callee-saved
|(vector) |
|--|
| RVV objects |
|--|
| padding before RVV |
|--|
| scalar local variables |
|--| <-- BP
| variable size objects|
|--| <-- SP
Note: This patch doesn't contain "tuple" type, e.g. vint32m1x2.
It will be handled in
https://github.com/riscv-non-isa/riscv-elf-psabi-doc (2/2).
Differential Revision: https://reviews.llvm.org/D154576
---
clang/include/clang-c/Index.h | 1 +
clang/include/clang/Basic/Attr.td | 7 ++
clang/include/clang/Basic/AttrDocs.td | 11 +++
clang/include/clang/Basic/Specifiers.h| 43
clang/lib/AST/ItaniumMangle.cpp | 1 +
clang/lib/AST/Type.cpp| 4 +
clang/lib/AST/TypePrinter.cpp | 6 ++
clang/lib/Basic/Targets/RISCV.cpp | 11 +++
clang/lib/Basic/Targets/RISCV.h | 2 +
clang/lib/CodeGen/CGCall.cpp | 6 ++
clang/lib/CodeGen/CGDebugInfo.cpp | 2 +
clang/lib/Sema/SemaDeclAttr.cpp | 7 ++
clang/lib/Sema/SemaType.cpp | 5 +-
.../RISCV/riscv-vector-callingconv-llvm-ir.c | 34 +++
.../riscv-vector-callingconv-llvm-ir.cpp | 32 ++
.../CodeGen/RISCV/riscv-vector-callingconv.c | 17
.../RISCV/riscv-vector-callingconv.cpp| 35 +++
clang/tools/libclang/CXType.cpp | 1 +
llvm/include/llvm/AsmParser/LLToken.h | 1 +
llvm/include/llvm/BinaryFormat/Dwarf.def | 1 +
llvm/include/llvm/IR/CallingConv.h| 3 +
llvm/lib/AsmParser/LLLexer.cpp| 1 +
llvm/lib/AsmParser/LLParser.cpp | 4 +
llvm/lib/IR/AsmWriter.cpp | 3 +
llvm/lib/Target/RISCV/RISCVCallingConv.td | 13 +++
llvm/lib/Target/RISCV/RISCVFrameLowering.cpp | 97 +--
llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 1 +
llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp | 15 +++
.../CodeGen/RISCV/rvv/callee-saved-regs.ll| 95 ++
29 files changed, 409 insertions(+), 50 deletions(-)
create mode 100644 clang/test/CodeGen/RISCV/riscv-vector-callingconv-llvm-ir.c
create mode 100644
clang/test/CodeGen/RISCV/riscv-vector-callingconv-llvm-ir.cpp
create mode 100644 clang/test/CodeGen/RISCV/riscv-vector-callingconv.c
create mode 100644 clang/test/CodeGen/RISCV/riscv-vector-callingconv.cpp
create mode 100644 llvm/test/CodeGen/RISCV/rvv/callee-saved-regs.ll
diff --git a/clang/include/clang-c/Index.h b/clang/include/clang-c/Index.h
index 60db3cf0966c02..7a8bd985a91fc0 100644
--- a/clang/include/clang-c/Index.h
+++ b/clang/include/clang-c/Index.h
@@ -2991,6 +2991,7 @@ enum CXCallingConv {
CXCallingConv_AArch64SVEPCS = 18,
CXCallingConv_M68kRTD = 19,
CXCallingConv_PreserveNone = 20,
+ CXCallingConv_RISCVVectorCall = 21,
CXCallingConv_Invalid = 100,
CXCallingConv_Unexposed = 200
diff --git a/clang/include/clang/Basic/Attr.td
b/clang/include/clang/Basic/Attr.td
index 318d4e5ac5ba44..80e607525a0a37 100644
--- a/clang/include/clang/Basic/Attr.td
+++ b/clang/include/clang/Basic/Attr.td
@@ -3011,6 +3011,13 @@ def PreserveNone : DeclOrTypeAttr,
TargetSpecificAttr {
let Documentation = [PreserveNoneDocs];
}
+def RISCVVectorCC: DeclOrTypeAttr, TargetSpecificAttr {
+ let Spellings = [CXX11<"riscv", "vector_cc">,
+ C23<"riscv", "vector_cc">,
+ Clang<"riscv_vector_cc">];
+ let Documentation = [RISCVVectorCCDocs];
+}
+
def Target : InheritableAttr {
let Spellings = [GCC<"target">];
let Args = [StringArgument<"featuresStr">];
diff --git a/clang/include/clang/Basic/AttrDocs.td
b/clang/include/clang/Basic/AttrDocs.td
index 384aebbdf2e32a..3ea4d676b4f89d 100644
--- a/clang/include/clang/Basic/AttrDocs.td
+++ b/clang/include/clang/Basic/AttrDocs.td
@@ -5494,6 +5494,17 @@ for clang builtin
[clang] [llvm] [RISCV] RISCV vector calling convention (1/2) (PR #77560)
4vtomat wrote: Rebase and squash https://github.com/llvm/llvm-project/pull/77560 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [clang][RISCV] Enable RVV with function attribute __attribute__((target("arch=+v"))) (PR #83674)
@@ -8927,8 +8927,13 @@ void Sema::CheckVariableDeclarationType(VarDecl *NewVD) {
}
}
- if (T->isRVVSizelessBuiltinType())
-checkRVVTypeSupport(T, NewVD->getLocation(), cast(CurContext));
+ if (T->isRVVSizelessBuiltinType() && isa(CurContext)) {
+const FunctionDecl *FD = cast(CurContext);
+llvm::StringMap CallerFeatureMap;
+Context.getFunctionFeatureMap(CallerFeatureMap, FD);
4vtomat wrote:
@lukel97 Got it, thanks!
https://github.com/llvm/llvm-project/pull/83674
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[clang] [clang][RISCV] Enable RVV with function attribute __attribute__((target("arch=+v"))) (PR #83674)
@@ -8927,8 +8927,13 @@ void Sema::CheckVariableDeclarationType(VarDecl *NewVD) {
}
}
- if (T->isRVVSizelessBuiltinType())
-checkRVVTypeSupport(T, NewVD->getLocation(), cast(CurContext));
+ if (T->isRVVSizelessBuiltinType() && isa(CurContext)) {
+const FunctionDecl *FD = cast(CurContext);
+llvm::StringMap CallerFeatureMap;
+Context.getFunctionFeatureMap(CallerFeatureMap, FD);
4vtomat wrote:
> > But we don't have the FunctionDecl info in the
> > RISCVTargetInfo::initFeatureMap call.
>
> What about keeping this map in ASTContext instead?
I guess it might be a feasible solution, however the memory usage might
increase since it has to keep the map for each function during the lifetime of
the ASTContext.
@topperc Do you think we can do this? Or we can leave it in TODO until it
becomes a problem in some real cases.
https://github.com/llvm/llvm-project/pull/83674
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[clang] [clang][RISCV] Enable RVV with function attribute __attribute__((target("arch=+v"))) (PR #83674)
@@ -8927,8 +8927,13 @@ void Sema::CheckVariableDeclarationType(VarDecl *NewVD) {
}
}
- if (T->isRVVSizelessBuiltinType())
-checkRVVTypeSupport(T, NewVD->getLocation(), cast(CurContext));
+ if (T->isRVVSizelessBuiltinType() && isa(CurContext)) {
+const FunctionDecl *FD = cast(CurContext);
+llvm::StringMap CallerFeatureMap;
+Context.getFunctionFeatureMap(CallerFeatureMap, FD);
4vtomat wrote:
> @4vtomat if the MCPU has a feature but the function explicitly disables it
> then I think we want the `-`
Why don't we just remove it from feature map?
https://github.com/llvm/llvm-project/pull/83674
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[clang] [clang][RISCV] Enable RVV with function attribute __attribute__((target("arch=+v"))) (PR #83674)
@@ -8927,8 +8927,13 @@ void Sema::CheckVariableDeclarationType(VarDecl *NewVD) {
}
}
- if (T->isRVVSizelessBuiltinType())
-checkRVVTypeSupport(T, NewVD->getLocation(), cast(CurContext));
+ if (T->isRVVSizelessBuiltinType() && isa(CurContext)) {
+const FunctionDecl *FD = cast(CurContext);
+llvm::StringMap CallerFeatureMap;
+Context.getFunctionFeatureMap(CallerFeatureMap, FD);
4vtomat wrote:
@topperc I'm not sure why we also need "-" for features that are not enabled,
is there any use case?
https://github.com/llvm/llvm-project/pull/83674
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[clang] [clang][RISCV] Enable RVV with function attribute __attribute__((target("arch=+v"))) (PR #83674)
@@ -8927,8 +8927,13 @@ void Sema::CheckVariableDeclarationType(VarDecl *NewVD) {
}
}
- if (T->isRVVSizelessBuiltinType())
-checkRVVTypeSupport(T, NewVD->getLocation(), cast(CurContext));
+ if (T->isRVVSizelessBuiltinType() && isa(CurContext)) {
+const FunctionDecl *FD = cast(CurContext);
+llvm::StringMap CallerFeatureMap;
+Context.getFunctionFeatureMap(CallerFeatureMap, FD);
4vtomat wrote:
However, if we can do something like that, we can get about 5x speedup with my
rough measurement lol~
https://github.com/llvm/llvm-project/pull/83674
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[clang] [llvm] [RISCV] Support RISC-V Profiles in -march option (PR #76357)
@@ -854,6 +895,30 @@ RISCVISAInfo::parseArchString(StringRef Arch, bool
EnableExperimentalExtension,
"string must be lowercase");
}
+ bool IsProfile = Arch.starts_with("rvi") || Arch.starts_with("rva") ||
+ Arch.starts_with("rvb") || Arch.starts_with("rvm");
+ std::string NewArch;
4vtomat wrote:
`NewArch` might be assigned twice, I'm wondering whether we can pre-reserve a
chunk of memory beforehand to prevent 1 more memory allocation?
https://github.com/llvm/llvm-project/pull/76357
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[clang] [llvm] [RISCV] Support RISC-V Profiles in -march option (PR #76357)
@@ -854,6 +895,30 @@ RISCVISAInfo::parseArchString(StringRef Arch, bool
EnableExperimentalExtension,
"string must be lowercase");
}
+ bool IsProfile = Arch.starts_with("rvi") || Arch.starts_with("rva") ||
+ Arch.starts_with("rvb") || Arch.starts_with("rvm");
+ std::string NewArch;
+ if (IsProfile) {
+const auto *FoundProfile =
+llvm::find_if(SupportedProfiles, [&](const RISCVProfile ) {
+ return Arch.starts_with(Profile.Name);
+});
+
+if (FoundProfile == std::end(SupportedProfiles))
+ return createStringError(errc::invalid_argument, "unsupported profile");
+
+NewArch = FoundProfile->MArch;
+StringRef ArchWithoutProfile = Arch.substr(strlen(FoundProfile->Name));
+if (!ArchWithoutProfile.empty()) {
+ if (!ArchWithoutProfile.starts_with("_"))
+return createStringError(
+errc::invalid_argument,
+"additional extensions must be after separator '_'");
+ NewArch = NewArch + ArchWithoutProfile.str();
4vtomat wrote:
Maybe `NewArch += ArchWithoutProfile.str()` to reduce 1 redundant copy?
https://github.com/llvm/llvm-project/pull/76357
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[clang] [llvm] [RISCV] Support RISC-V Profiles in -march option (PR #76357)
@@ -36,6 +36,11 @@ struct RISCVSupportedExtension {
}
};
+struct RISCVProfile {
4vtomat wrote:
Very minor too, if you use std::pair, could you add the comments describing
what the fields represent?
https://github.com/llvm/llvm-project/pull/76357
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[clang] [clang][RISCV] Enable RVV with function attribute __attribute__((target("arch=+v"))) (PR #83674)
@@ -8927,8 +8927,13 @@ void Sema::CheckVariableDeclarationType(VarDecl *NewVD) {
}
}
- if (T->isRVVSizelessBuiltinType())
-checkRVVTypeSupport(T, NewVD->getLocation(), cast(CurContext));
+ if (T->isRVVSizelessBuiltinType() && isa(CurContext)) {
+const FunctionDecl *FD = cast(CurContext);
+llvm::StringMap CallerFeatureMap;
+Context.getFunctionFeatureMap(CallerFeatureMap, FD);
4vtomat wrote:
Mostly costed by `llvm::RISCVISAInfo::parseFeatures` in
`RISCVTargetInfo::initFeatureMap`.
https://github.com/llvm/llvm-project/pull/83674
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[clang] [clang][RISCV] Enable RVV with function attribute __attribute__((target("arch=+v"))) (PR #83674)
https://github.com/4vtomat edited https://github.com/llvm/llvm-project/pull/83674 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [clang][RISCV] Enable RVV with function attribute __attribute__((target("arch=+v"))) (PR #83674)
@@ -8927,8 +8927,13 @@ void Sema::CheckVariableDeclarationType(VarDecl *NewVD) {
}
}
- if (T->isRVVSizelessBuiltinType())
-checkRVVTypeSupport(T, NewVD->getLocation(), cast(CurContext));
+ if (T->isRVVSizelessBuiltinType() && isa(CurContext)) {
+const FunctionDecl *FD = cast(CurContext);
+llvm::StringMap CallerFeatureMap;
+Context.getFunctionFeatureMap(CallerFeatureMap, FD);
4vtomat wrote:
Yes, it does.
With 100k RVV type declarations,
This pr's compile time is approximately 8 times slower than original one.(0.56
seconds vs 0.07 seconds on the server)
https://github.com/llvm/llvm-project/pull/83674
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[clang] [llvm] [RISCV] RISCV vector calling convention (1/2) (PR #77560)
@@ -3439,6 +3439,8 @@ StringRef FunctionType::getNameForCallConv(CallingConv
CC) {
case CC_PreserveAll: return "preserve_all";
case CC_M68kRTD: return "m68k_rtd";
case CC_PreserveNone: return "preserve_none";
+ case CC_RISCVVectorCall:
4vtomat wrote:
Sure~
https://github.com/llvm/llvm-project/pull/77560
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[clang] [clang][RISCV] Enable RVV with function attribute __attribute__((target("arch=+v"))) (PR #83674)
4vtomat wrote: Rebase. https://github.com/llvm/llvm-project/pull/83674 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [clang][RISCV] Enable RVV with function attribute __attribute__((target("arch=+v"))) (PR #83674)
https://github.com/4vtomat updated
https://github.com/llvm/llvm-project/pull/83674
>From faab3d0d9163e99185fb6a2d3efd21549ed33e00 Mon Sep 17 00:00:00 2001
From: Brandon Wu
Date: Fri, 1 Mar 2024 09:52:35 -0800
Subject: [PATCH 1/3] [clang][RISCV] Enable RVV with function attribute
__attribute__((target("arch=+v")))
It is currently not possible to use "RVV type" and "RVV intrinsics" if
the "zve32x" is not enabled globally. However in some cases we may want
to use them only in some functions, for instance:
```
#include
__attribute__((target("+zve32x")))
vint32m1_t rvv_add(vint32m1_t v1, vint32m1_t v2, size_t vl) {
return __riscv_vadd(v1, v2, vl);
}
int other_add(int i1, int i2) {
return i1 + i2;
}
```
, it is supposed to be compilable even the vector is not specified, e.g.
`clang -target riscv64 -march=rv64gc -S test.c`.
---
clang/include/clang/Sema/Sema.h | 3 +-
clang/lib/Basic/Targets/RISCV.cpp | 3 +-
clang/lib/Sema/Sema.cpp | 7 +-
clang/lib/Sema/SemaChecking.cpp | 70 +++
clang/lib/Sema/SemaDecl.cpp | 9 ++-
.../RISCV/rvb-intrinsics/riscv32-zbb-error.c | 4 +-
.../RISCV/rvb-intrinsics/riscv64-zbkb-error.c | 12 ++--
.../rvv-intrinsics-handcrafted/rvv-error.c| 2 +-
clang/test/Sema/riscv-function-target-attr.c | 41 +++
clang/utils/TableGen/RISCVVEmitter.cpp| 4 --
10 files changed, 73 insertions(+), 82 deletions(-)
create mode 100644 clang/test/Sema/riscv-function-target-attr.c
diff --git a/clang/include/clang/Sema/Sema.h b/clang/include/clang/Sema/Sema.h
index 25c4c58ad4ae43..229ae7c1050cd6 100644
--- a/clang/include/clang/Sema/Sema.h
+++ b/clang/include/clang/Sema/Sema.h
@@ -14081,7 +14081,8 @@ class Sema final {
bool CheckRISCVLMUL(CallExpr *TheCall, unsigned ArgNum);
bool CheckRISCVBuiltinFunctionCall(const TargetInfo , unsigned BuiltinID,
CallExpr *TheCall);
- void checkRVVTypeSupport(QualType Ty, SourceLocation Loc, Decl *D);
+ void checkRVVTypeSupport(QualType Ty, SourceLocation Loc, Decl *D,
+ const llvm::StringMap );
bool CheckLoongArchBuiltinFunctionCall(const TargetInfo ,
unsigned BuiltinID, CallExpr
*TheCall);
bool CheckWebAssemblyBuiltinFunctionCall(const TargetInfo ,
diff --git a/clang/lib/Basic/Targets/RISCV.cpp
b/clang/lib/Basic/Targets/RISCV.cpp
index a6d4af2b88111a..6991caa21d23b4 100644
--- a/clang/lib/Basic/Targets/RISCV.cpp
+++ b/clang/lib/Basic/Targets/RISCV.cpp
@@ -463,7 +463,8 @@ ParsedTargetAttr RISCVTargetInfo::parseTargetAttr(StringRef
Features) const {
Ret.Duplicate = "tune=";
Ret.Tune = AttrString;
-}
+} else if (Feature.starts_with("+"))
+ Ret.Features.push_back(Feature.str());
}
return Ret;
}
diff --git a/clang/lib/Sema/Sema.cpp b/clang/lib/Sema/Sema.cpp
index cfb653e665ea03..41c7bfb25a7921 100644
--- a/clang/lib/Sema/Sema.cpp
+++ b/clang/lib/Sema/Sema.cpp
@@ -2077,8 +2077,11 @@ void Sema::checkTypeSupport(QualType Ty, SourceLocation
Loc, ValueDecl *D) {
targetDiag(D->getLocation(), diag::note_defined_here, FD) << D;
}
-if (TI.hasRISCVVTypes() && Ty->isRVVSizelessBuiltinType())
- checkRVVTypeSupport(Ty, Loc, D);
+if (TI.hasRISCVVTypes() && Ty->isRVVSizelessBuiltinType() && FD) {
+ llvm::StringMap CallerFeatureMap;
+ Context.getFunctionFeatureMap(CallerFeatureMap, FD);
+ checkRVVTypeSupport(Ty, Loc, D, CallerFeatureMap);
+}
// Don't allow SVE types in functions without a SVE target.
if (Ty->isSVESizelessBuiltinType() && FD && FD->hasBody()) {
diff --git a/clang/lib/Sema/SemaChecking.cpp b/clang/lib/Sema/SemaChecking.cpp
index 561764edd08100..2a6aceaefa9b19 100644
--- a/clang/lib/Sema/SemaChecking.cpp
+++ b/clang/lib/Sema/SemaChecking.cpp
@@ -5429,57 +5429,6 @@ static bool CheckInvalidVLENandLMUL(const TargetInfo
, CallExpr *TheCall,
bool Sema::CheckRISCVBuiltinFunctionCall(const TargetInfo ,
unsigned BuiltinID,
CallExpr *TheCall) {
- // CodeGenFunction can also detect this, but this gives a better error
- // message.
- bool FeatureMissing = false;
- SmallVector ReqFeatures;
- StringRef Features = Context.BuiltinInfo.getRequiredFeatures(BuiltinID);
- Features.split(ReqFeatures, ',', -1, false);
-
- // Check if each required feature is included
- for (StringRef F : ReqFeatures) {
-SmallVector ReqOpFeatures;
-F.split(ReqOpFeatures, '|');
-
-if (llvm::none_of(ReqOpFeatures,
- [](StringRef OF) { return TI.hasFeature(OF); })) {
- std::string FeatureStrs;
- bool IsExtension = true;
- for (StringRef OF : ReqOpFeatures) {
-// If the feature is 64bit, alter the string so it will print better in
-// the diagnostic.
-if (OF == "64bit") {
-
[clang] [llvm] [RISCV] Improve error message when the extension is not supported (PR #83989)
https://github.com/4vtomat closed https://github.com/llvm/llvm-project/pull/83989 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Improve error message when the extension is not supported (PR #83989)
4vtomat wrote: > perhaps the llvm libSupport prats of this change should be unit tested in > LLVM, rather than only tested indirectly in clang? Good point, thanks! I've added for unites. https://github.com/llvm/llvm-project/pull/83989 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Improve error message when the extension is not supported (PR #83989)
https://github.com/4vtomat updated
https://github.com/llvm/llvm-project/pull/83989
>From 764c861931fd8013df5b144c2d789614bc952126 Mon Sep 17 00:00:00 2001
From: Brandon Wu
Date: Tue, 5 Mar 2024 02:28:10 -0800
Subject: [PATCH 1/2] [RISCV] Improve error message when the extension is not
supported
If the "march" has some extension with version that is not supported, it
returns the error message like: "error: invalid arch name 'some_arch',
unsupported version number 2.0 for extension 'some_arch'", which is not
precise enough, it should return the message that only tells users "the
extension is not supported".
---
clang/test/Driver/riscv-arch.c| 4 ++--
llvm/lib/Support/RISCVISAInfo.cpp | 26 --
2 files changed, 18 insertions(+), 12 deletions(-)
diff --git a/clang/test/Driver/riscv-arch.c b/clang/test/Driver/riscv-arch.c
index c9e984e07cbea9..8399b4e97f86d5 100644
--- a/clang/test/Driver/riscv-arch.c
+++ b/clang/test/Driver/riscv-arch.c
@@ -306,7 +306,7 @@
// RUN: not %clang --target=riscv32-unknown-elf -march=rv32ist2p0 -### %s \
// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-SMINOR0 %s
// RV32-SMINOR0: error: invalid arch name 'rv32ist2p0',
-// RV32-SMINOR0: unsupported version number 2.0 for extension 'st'
+// RV32-SMINOR0: unsupported standard supervisor-level extension 'st'
// RUN: not %clang --target=riscv32-unknown-elf -march=rv32ixabc_ -### %s \
// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-XSEP %s
@@ -397,7 +397,7 @@
// RUN: not %clang --target=riscv32-unknown-elf -march=rv32izbb1p0zbs1p0
-menable-experimental-extensions -### %s \
// RUN: -fsyntax-only 2>&1 | FileCheck
-check-prefix=RV32-EXPERIMENTAL-ZBB-ZBS-UNDERSCORE %s
-// RV32-EXPERIMENTAL-ZBB-ZBS-UNDERSCORE: error: invalid arch name
'rv32izbb1p0zbs1p0', unsupported version number 1.0 for extension 'zbb1p0zbs'
+// RV32-EXPERIMENTAL-ZBB-ZBS-UNDERSCORE: error: invalid arch name
'rv32izbb1p0zbs1p0', unsupported standard user-level extension 'zbb1p0zbs'
// RUN: %clang --target=riscv32-unknown-elf -march=rv32izba1p0 -### %s \
// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-ZBA %s
diff --git a/llvm/lib/Support/RISCVISAInfo.cpp
b/llvm/lib/Support/RISCVISAInfo.cpp
index 54b4dcb22de8e0..6eec03fd6f7082 100644
--- a/llvm/lib/Support/RISCVISAInfo.cpp
+++ b/llvm/lib/Support/RISCVISAInfo.cpp
@@ -531,6 +531,17 @@ std::vector RISCVISAInfo::toFeatures(bool
AddAllExtensions,
return Features;
}
+static Error getStringErrorForInvalidExt(std::string_view ExtName) {
+ if (ExtName.size() == 1) {
+return createStringError(errc::invalid_argument,
+ "unsupported standard user-level extension '" +
+ ExtName + "'");
+ }
+ return createStringError(errc::invalid_argument,
+ "unsupported " + getExtensionTypeDesc(ExtName) +
+ " '" + ExtName + "'");
+}
+
// Extensions may have a version number, and may be separated by
// an underscore '_' e.g.: rv32i2_m2.
// Version number is divided into major and minor version numbers,
@@ -629,6 +640,9 @@ static Error getExtensionVersion(StringRef Ext, StringRef
In, unsigned ,
if (RISCVISAInfo::isSupportedExtension(Ext, Major, Minor))
return Error::success();
+ if (!RISCVISAInfo::isSupportedExtension(Ext))
+return getStringErrorForInvalidExt(Ext);
+
std::string Error = "unsupported version number " + std::string(MajorStr);
if (!MinorStr.empty())
Error += "." + MinorStr.str();
@@ -965,16 +979,8 @@ RISCVISAInfo::parseArchString(StringRef Arch, bool
EnableExperimentalExtension,
const std::string = SeenExtAndVers.first;
RISCVISAInfo::ExtensionVersion ExtVers = SeenExtAndVers.second;
-if (!RISCVISAInfo::isSupportedExtension(ExtName)) {
- if (ExtName.size() == 1) {
-return createStringError(errc::invalid_argument,
- "unsupported standard user-level extension '"
+
- ExtName + "'");
- }
- return createStringError(errc::invalid_argument,
- "unsupported " + getExtensionTypeDesc(ExtName) +
- " '" + ExtName + "'");
-}
+if (!RISCVISAInfo::isSupportedExtension(ExtName))
+ return getStringErrorForInvalidExt(ExtName);
ISAInfo->addExtension(ExtName, ExtVers);
}
>From 0eb84049821dc6f71c185215b16696508cd46261 Mon Sep 17 00:00:00 2001
From: Brandon Wu
Date: Tue, 5 Mar 2024 17:20:09 -0800
Subject: [PATCH 2/2] fixup! [RISCV] Improve error message when the extension
is not supported
---
llvm/unittests/Support/RISCVISAInfoTest.cpp | 15 +++
1 file changed, 15 insertions(+)
diff --git a/llvm/unittests/Support/RISCVISAInfoTest.cpp
b/llvm/unittests/Support/RISCVISAInfoTest.cpp
index 8a627eca05cb4b..82cf4c639b6160 100644
--- a/llvm/unittests/Support/RISCVISAInfoTest.cpp
+++
[clang] [clang][RISCV] Reorder sema check for RVV type (PR #83553)
https://github.com/4vtomat closed https://github.com/llvm/llvm-project/pull/83553 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] Improve error message when the extension is not supported (PR #83989)
https://github.com/4vtomat created
https://github.com/llvm/llvm-project/pull/83989
If the "march" has some extension with version that is not supported, it
returns the error message like: "error: invalid arch name 'some_arch',
unsupported version number 2.0 for extension 'some_arch'", which is not
precise enough, it should return the message that only tells users "the
extension is not supported".
>From 764c861931fd8013df5b144c2d789614bc952126 Mon Sep 17 00:00:00 2001
From: Brandon Wu
Date: Tue, 5 Mar 2024 02:28:10 -0800
Subject: [PATCH] [RISCV] Improve error message when the extension is not
supported
If the "march" has some extension with version that is not supported, it
returns the error message like: "error: invalid arch name 'some_arch',
unsupported version number 2.0 for extension 'some_arch'", which is not
precise enough, it should return the message that only tells users "the
extension is not supported".
---
clang/test/Driver/riscv-arch.c| 4 ++--
llvm/lib/Support/RISCVISAInfo.cpp | 26 --
2 files changed, 18 insertions(+), 12 deletions(-)
diff --git a/clang/test/Driver/riscv-arch.c b/clang/test/Driver/riscv-arch.c
index c9e984e07cbea9..8399b4e97f86d5 100644
--- a/clang/test/Driver/riscv-arch.c
+++ b/clang/test/Driver/riscv-arch.c
@@ -306,7 +306,7 @@
// RUN: not %clang --target=riscv32-unknown-elf -march=rv32ist2p0 -### %s \
// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-SMINOR0 %s
// RV32-SMINOR0: error: invalid arch name 'rv32ist2p0',
-// RV32-SMINOR0: unsupported version number 2.0 for extension 'st'
+// RV32-SMINOR0: unsupported standard supervisor-level extension 'st'
// RUN: not %clang --target=riscv32-unknown-elf -march=rv32ixabc_ -### %s \
// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-XSEP %s
@@ -397,7 +397,7 @@
// RUN: not %clang --target=riscv32-unknown-elf -march=rv32izbb1p0zbs1p0
-menable-experimental-extensions -### %s \
// RUN: -fsyntax-only 2>&1 | FileCheck
-check-prefix=RV32-EXPERIMENTAL-ZBB-ZBS-UNDERSCORE %s
-// RV32-EXPERIMENTAL-ZBB-ZBS-UNDERSCORE: error: invalid arch name
'rv32izbb1p0zbs1p0', unsupported version number 1.0 for extension 'zbb1p0zbs'
+// RV32-EXPERIMENTAL-ZBB-ZBS-UNDERSCORE: error: invalid arch name
'rv32izbb1p0zbs1p0', unsupported standard user-level extension 'zbb1p0zbs'
// RUN: %clang --target=riscv32-unknown-elf -march=rv32izba1p0 -### %s \
// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-ZBA %s
diff --git a/llvm/lib/Support/RISCVISAInfo.cpp
b/llvm/lib/Support/RISCVISAInfo.cpp
index 54b4dcb22de8e0..6eec03fd6f7082 100644
--- a/llvm/lib/Support/RISCVISAInfo.cpp
+++ b/llvm/lib/Support/RISCVISAInfo.cpp
@@ -531,6 +531,17 @@ std::vector RISCVISAInfo::toFeatures(bool
AddAllExtensions,
return Features;
}
+static Error getStringErrorForInvalidExt(std::string_view ExtName) {
+ if (ExtName.size() == 1) {
+return createStringError(errc::invalid_argument,
+ "unsupported standard user-level extension '" +
+ ExtName + "'");
+ }
+ return createStringError(errc::invalid_argument,
+ "unsupported " + getExtensionTypeDesc(ExtName) +
+ " '" + ExtName + "'");
+}
+
// Extensions may have a version number, and may be separated by
// an underscore '_' e.g.: rv32i2_m2.
// Version number is divided into major and minor version numbers,
@@ -629,6 +640,9 @@ static Error getExtensionVersion(StringRef Ext, StringRef
In, unsigned ,
if (RISCVISAInfo::isSupportedExtension(Ext, Major, Minor))
return Error::success();
+ if (!RISCVISAInfo::isSupportedExtension(Ext))
+return getStringErrorForInvalidExt(Ext);
+
std::string Error = "unsupported version number " + std::string(MajorStr);
if (!MinorStr.empty())
Error += "." + MinorStr.str();
@@ -965,16 +979,8 @@ RISCVISAInfo::parseArchString(StringRef Arch, bool
EnableExperimentalExtension,
const std::string = SeenExtAndVers.first;
RISCVISAInfo::ExtensionVersion ExtVers = SeenExtAndVers.second;
-if (!RISCVISAInfo::isSupportedExtension(ExtName)) {
- if (ExtName.size() == 1) {
-return createStringError(errc::invalid_argument,
- "unsupported standard user-level extension '"
+
- ExtName + "'");
- }
- return createStringError(errc::invalid_argument,
- "unsupported " + getExtensionTypeDesc(ExtName) +
- " '" + ExtName + "'");
-}
+if (!RISCVISAInfo::isSupportedExtension(ExtName))
+ return getStringErrorForInvalidExt(ExtName);
ISAInfo->addExtension(ExtName, ExtVers);
}
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[clang] [clang][RISCV] Enable RVV with function attribute __attribute__((target("arch=+v"))) (PR #83674)
4vtomat wrote: Move the test cases to existing files. https://github.com/llvm/llvm-project/pull/83674 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [clang][RISCV] Enable RVV with function attribute __attribute__((target("arch=+v"))) (PR #83674)
https://github.com/4vtomat updated
https://github.com/llvm/llvm-project/pull/83674
>From f14c54cb7c3c31e84a78ddf33b932c4c74e20365 Mon Sep 17 00:00:00 2001
From: Brandon Wu
Date: Fri, 1 Mar 2024 09:52:35 -0800
Subject: [PATCH 1/3] [clang][RISCV] Enable RVV with function attribute
__attribute__((target("arch=+v")))
It is currently not possible to use "RVV type" and "RVV intrinsics" if
the "zve32x" is not enabled globally. However in some cases we may want
to use them only in some functions, for instance:
```
#include
__attribute__((target("+zve32x")))
vint32m1_t rvv_add(vint32m1_t v1, vint32m1_t v2, size_t vl) {
return __riscv_vadd(v1, v2, vl);
}
int other_add(int i1, int i2) {
return i1 + i2;
}
```
, it is supposed to be compilable even the vector is not specified, e.g.
`clang -target riscv64 -march=rv64gc -S test.c`.
---
clang/include/clang/Sema/Sema.h | 3 +-
clang/lib/Basic/Targets/RISCV.cpp | 3 +-
clang/lib/Sema/Sema.cpp | 7 +-
clang/lib/Sema/SemaChecking.cpp | 70 +++
clang/lib/Sema/SemaDecl.cpp | 9 ++-
.../RISCV/rvb-intrinsics/riscv32-zbb-error.c | 4 +-
.../RISCV/rvb-intrinsics/riscv64-zbkb-error.c | 12 ++--
.../rvv-intrinsics-handcrafted/rvv-error.c| 2 +-
clang/test/Sema/riscv-function-target-attr.c | 41 +++
clang/utils/TableGen/RISCVVEmitter.cpp| 4 --
10 files changed, 73 insertions(+), 82 deletions(-)
create mode 100644 clang/test/Sema/riscv-function-target-attr.c
diff --git a/clang/include/clang/Sema/Sema.h b/clang/include/clang/Sema/Sema.h
index ef4b93fac95ce5..932b76c82af0ee 100644
--- a/clang/include/clang/Sema/Sema.h
+++ b/clang/include/clang/Sema/Sema.h
@@ -14067,7 +14067,8 @@ class Sema final {
bool CheckRISCVLMUL(CallExpr *TheCall, unsigned ArgNum);
bool CheckRISCVBuiltinFunctionCall(const TargetInfo , unsigned BuiltinID,
CallExpr *TheCall);
- void checkRVVTypeSupport(QualType Ty, SourceLocation Loc, Decl *D);
+ void checkRVVTypeSupport(QualType Ty, SourceLocation Loc, Decl *D,
+ const llvm::StringMap );
bool CheckLoongArchBuiltinFunctionCall(const TargetInfo ,
unsigned BuiltinID, CallExpr
*TheCall);
bool CheckWebAssemblyBuiltinFunctionCall(const TargetInfo ,
diff --git a/clang/lib/Basic/Targets/RISCV.cpp
b/clang/lib/Basic/Targets/RISCV.cpp
index a6d4af2b88111a..6991caa21d23b4 100644
--- a/clang/lib/Basic/Targets/RISCV.cpp
+++ b/clang/lib/Basic/Targets/RISCV.cpp
@@ -463,7 +463,8 @@ ParsedTargetAttr RISCVTargetInfo::parseTargetAttr(StringRef
Features) const {
Ret.Duplicate = "tune=";
Ret.Tune = AttrString;
-}
+} else if (Feature.starts_with("+"))
+ Ret.Features.push_back(Feature.str());
}
return Ret;
}
diff --git a/clang/lib/Sema/Sema.cpp b/clang/lib/Sema/Sema.cpp
index cfb653e665ea03..41c7bfb25a7921 100644
--- a/clang/lib/Sema/Sema.cpp
+++ b/clang/lib/Sema/Sema.cpp
@@ -2077,8 +2077,11 @@ void Sema::checkTypeSupport(QualType Ty, SourceLocation
Loc, ValueDecl *D) {
targetDiag(D->getLocation(), diag::note_defined_here, FD) << D;
}
-if (TI.hasRISCVVTypes() && Ty->isRVVSizelessBuiltinType())
- checkRVVTypeSupport(Ty, Loc, D);
+if (TI.hasRISCVVTypes() && Ty->isRVVSizelessBuiltinType() && FD) {
+ llvm::StringMap CallerFeatureMap;
+ Context.getFunctionFeatureMap(CallerFeatureMap, FD);
+ checkRVVTypeSupport(Ty, Loc, D, CallerFeatureMap);
+}
// Don't allow SVE types in functions without a SVE target.
if (Ty->isSVESizelessBuiltinType() && FD && FD->hasBody()) {
diff --git a/clang/lib/Sema/SemaChecking.cpp b/clang/lib/Sema/SemaChecking.cpp
index 0d4d57db01c93a..50afb56ae09eac 100644
--- a/clang/lib/Sema/SemaChecking.cpp
+++ b/clang/lib/Sema/SemaChecking.cpp
@@ -5415,57 +5415,6 @@ static bool CheckInvalidVLENandLMUL(const TargetInfo
, CallExpr *TheCall,
bool Sema::CheckRISCVBuiltinFunctionCall(const TargetInfo ,
unsigned BuiltinID,
CallExpr *TheCall) {
- // CodeGenFunction can also detect this, but this gives a better error
- // message.
- bool FeatureMissing = false;
- SmallVector ReqFeatures;
- StringRef Features = Context.BuiltinInfo.getRequiredFeatures(BuiltinID);
- Features.split(ReqFeatures, ',', -1, false);
-
- // Check if each required feature is included
- for (StringRef F : ReqFeatures) {
-SmallVector ReqOpFeatures;
-F.split(ReqOpFeatures, '|');
-
-if (llvm::none_of(ReqOpFeatures,
- [](StringRef OF) { return TI.hasFeature(OF); })) {
- std::string FeatureStrs;
- bool IsExtension = true;
- for (StringRef OF : ReqOpFeatures) {
-// If the feature is 64bit, alter the string so it will print better in
-// the diagnostic.
-if (OF == "64bit") {
-
[clang] [clang][RISCV] Enable RVV with function attribute __attribute__((target("arch=+v"))) (PR #83674)
@@ -463,7 +463,8 @@ ParsedTargetAttr RISCVTargetInfo::parseTargetAttr(StringRef
Features) const {
Ret.Duplicate = "tune=";
Ret.Tune = AttrString;
-}
+} else if (Feature.starts_with("+"))
4vtomat wrote:
Updated!
https://github.com/llvm/llvm-project/pull/83674
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[clang] [clang][RISCV] Enable RVV with function attribute __attribute__((target("arch=+v"))) (PR #83674)
@@ -0,0 +1,41 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -triple riscv64 -S -verify %s
+
+// REQUIRES: riscv-registered-target
+#include
+
+void test_builtin() {
+ __riscv_vsetvl_e8m8(1); // expected-error {{'__builtin_rvv_vsetvli' needs
target feature zve32x}}
+}
+
+__attribute__((target("+zve32x")))
4vtomat wrote:
Updated thanks!
https://github.com/llvm/llvm-project/pull/83674
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[clang] [clang][RISCV] Enable RVV with function attribute __attribute__((target("arch=+v"))) (PR #83674)
https://github.com/4vtomat edited https://github.com/llvm/llvm-project/pull/83674 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [clang][RISCV] Enable RVV with function attribute __attribute__((target("+attr"))) (PR #83674)
https://github.com/4vtomat edited https://github.com/llvm/llvm-project/pull/83674 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [clang][RISCV] Support function attribute __attribute__((target("+attr"))) (PR #83674)
https://github.com/4vtomat updated
https://github.com/llvm/llvm-project/pull/83674
>From f14c54cb7c3c31e84a78ddf33b932c4c74e20365 Mon Sep 17 00:00:00 2001
From: Brandon Wu
Date: Fri, 1 Mar 2024 09:52:35 -0800
Subject: [PATCH 1/2] [clang][RISCV] Enable RVV with function attribute
__attribute__((target("arch=+v")))
It is currently not possible to use "RVV type" and "RVV intrinsics" if
the "zve32x" is not enabled globally. However in some cases we may want
to use them only in some functions, for instance:
```
#include
__attribute__((target("+zve32x")))
vint32m1_t rvv_add(vint32m1_t v1, vint32m1_t v2, size_t vl) {
return __riscv_vadd(v1, v2, vl);
}
int other_add(int i1, int i2) {
return i1 + i2;
}
```
, it is supposed to be compilable even the vector is not specified, e.g.
`clang -target riscv64 -march=rv64gc -S test.c`.
---
clang/include/clang/Sema/Sema.h | 3 +-
clang/lib/Basic/Targets/RISCV.cpp | 3 +-
clang/lib/Sema/Sema.cpp | 7 +-
clang/lib/Sema/SemaChecking.cpp | 70 +++
clang/lib/Sema/SemaDecl.cpp | 9 ++-
.../RISCV/rvb-intrinsics/riscv32-zbb-error.c | 4 +-
.../RISCV/rvb-intrinsics/riscv64-zbkb-error.c | 12 ++--
.../rvv-intrinsics-handcrafted/rvv-error.c| 2 +-
clang/test/Sema/riscv-function-target-attr.c | 41 +++
clang/utils/TableGen/RISCVVEmitter.cpp| 4 --
10 files changed, 73 insertions(+), 82 deletions(-)
create mode 100644 clang/test/Sema/riscv-function-target-attr.c
diff --git a/clang/include/clang/Sema/Sema.h b/clang/include/clang/Sema/Sema.h
index ef4b93fac95ce5..932b76c82af0ee 100644
--- a/clang/include/clang/Sema/Sema.h
+++ b/clang/include/clang/Sema/Sema.h
@@ -14067,7 +14067,8 @@ class Sema final {
bool CheckRISCVLMUL(CallExpr *TheCall, unsigned ArgNum);
bool CheckRISCVBuiltinFunctionCall(const TargetInfo , unsigned BuiltinID,
CallExpr *TheCall);
- void checkRVVTypeSupport(QualType Ty, SourceLocation Loc, Decl *D);
+ void checkRVVTypeSupport(QualType Ty, SourceLocation Loc, Decl *D,
+ const llvm::StringMap );
bool CheckLoongArchBuiltinFunctionCall(const TargetInfo ,
unsigned BuiltinID, CallExpr
*TheCall);
bool CheckWebAssemblyBuiltinFunctionCall(const TargetInfo ,
diff --git a/clang/lib/Basic/Targets/RISCV.cpp
b/clang/lib/Basic/Targets/RISCV.cpp
index a6d4af2b88111a..6991caa21d23b4 100644
--- a/clang/lib/Basic/Targets/RISCV.cpp
+++ b/clang/lib/Basic/Targets/RISCV.cpp
@@ -463,7 +463,8 @@ ParsedTargetAttr RISCVTargetInfo::parseTargetAttr(StringRef
Features) const {
Ret.Duplicate = "tune=";
Ret.Tune = AttrString;
-}
+} else if (Feature.starts_with("+"))
+ Ret.Features.push_back(Feature.str());
}
return Ret;
}
diff --git a/clang/lib/Sema/Sema.cpp b/clang/lib/Sema/Sema.cpp
index cfb653e665ea03..41c7bfb25a7921 100644
--- a/clang/lib/Sema/Sema.cpp
+++ b/clang/lib/Sema/Sema.cpp
@@ -2077,8 +2077,11 @@ void Sema::checkTypeSupport(QualType Ty, SourceLocation
Loc, ValueDecl *D) {
targetDiag(D->getLocation(), diag::note_defined_here, FD) << D;
}
-if (TI.hasRISCVVTypes() && Ty->isRVVSizelessBuiltinType())
- checkRVVTypeSupport(Ty, Loc, D);
+if (TI.hasRISCVVTypes() && Ty->isRVVSizelessBuiltinType() && FD) {
+ llvm::StringMap CallerFeatureMap;
+ Context.getFunctionFeatureMap(CallerFeatureMap, FD);
+ checkRVVTypeSupport(Ty, Loc, D, CallerFeatureMap);
+}
// Don't allow SVE types in functions without a SVE target.
if (Ty->isSVESizelessBuiltinType() && FD && FD->hasBody()) {
diff --git a/clang/lib/Sema/SemaChecking.cpp b/clang/lib/Sema/SemaChecking.cpp
index 0d4d57db01c93a..50afb56ae09eac 100644
--- a/clang/lib/Sema/SemaChecking.cpp
+++ b/clang/lib/Sema/SemaChecking.cpp
@@ -5415,57 +5415,6 @@ static bool CheckInvalidVLENandLMUL(const TargetInfo
, CallExpr *TheCall,
bool Sema::CheckRISCVBuiltinFunctionCall(const TargetInfo ,
unsigned BuiltinID,
CallExpr *TheCall) {
- // CodeGenFunction can also detect this, but this gives a better error
- // message.
- bool FeatureMissing = false;
- SmallVector ReqFeatures;
- StringRef Features = Context.BuiltinInfo.getRequiredFeatures(BuiltinID);
- Features.split(ReqFeatures, ',', -1, false);
-
- // Check if each required feature is included
- for (StringRef F : ReqFeatures) {
-SmallVector ReqOpFeatures;
-F.split(ReqOpFeatures, '|');
-
-if (llvm::none_of(ReqOpFeatures,
- [](StringRef OF) { return TI.hasFeature(OF); })) {
- std::string FeatureStrs;
- bool IsExtension = true;
- for (StringRef OF : ReqOpFeatures) {
-// If the feature is 64bit, alter the string so it will print better in
-// the diagnostic.
-if (OF == "64bit") {
-
[clang] [llvm] [RISCV] RISCV vector calling convention (1/2) (PR #77560)
4vtomat wrote:
> I tried compiling it and then got two warnings.
>
> ```
> llvm-project/clang/lib/CodeGen/CGDebugInfo.cpp:1408:11: warning: enumeration
> value 'CC_RISCVVectorCall' not handled in switch [-Wswitch]
> 1408 | switch (CC) {
> | ^~
> 1 warning generated.
> [3629/3776] Building CXX object
> tools/clang/tools/libclang/CMakeFiles/libclang.dir/CXType.cpp.o
> llvm-project/clang/tools/libclang/CXType.cpp:662:13: warning: enumeration
> value 'CC_RISCVVectorCall' not handled in switch [-Wswitch]
> 662 | switch (FD->getCallConv()) {
> | ^
> 1 warning generated.
> ```
I forgot to add these cases for `CC_RISCVVectorCall` lol, thanks~
https://github.com/llvm/llvm-project/pull/77560
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[clang] [clang][RISCV] Support function attribute __attribute__((target("+attr"))) (PR #83674)
4vtomat wrote: Related request: https://github.com/riscv-non-isa/riscv-c-api-doc/issues/69 https://github.com/llvm/llvm-project/pull/83674 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [clang][RISCV] Support function attribute __attribute__((target("+attr"))) (PR #83674)
https://github.com/4vtomat created
https://github.com/llvm/llvm-project/pull/83674
It is currently not possible to use "RVV type" and "RVV intrinsics" if
the "zve32x" is not enabled globally. However in some cases we may want
to use them only in some functions, for instance:
```
#include
__attribute__((target("+zve32x")))
vint32m1_t rvv_add(vint32m1_t v1, vint32m1_t v2, size_t vl) {
return __riscv_vadd(v1, v2, vl);
}
int other_add(int i1, int i2) {
return i1 + i2;
}
```
, it is supposed to be compilable even the vector is not specified, e.g.
`clang -target riscv64 -march=rv64gc -S test.c`.
>From 51c523397008dd307bfbc190fd8966fbc4fa4331 Mon Sep 17 00:00:00 2001
From: Brandon Wu
Date: Fri, 1 Mar 2024 09:52:35 -0800
Subject: [PATCH] [clang][RISCV] Support function attribute
__attribute__((target("+attr")))
It is currently not possible to use "RVV type" and "RVV intrinsics" if
the "zve32x" is not enabled globally. However in some cases we may want
to use them only in some functions, for instance:
```
#include
__attribute__((target("+zve32x")))
vint32m1_t rvv_add(vint32m1_t v1, vint32m1_t v2, size_t vl) {
return __riscv_vadd(v1, v2, vl);
}
int other_add(int i1, int i2) {
return i1 + i2;
}
```
, it is supposed to be compilable even the vector is not specified, e.g.
`clang -target riscv64 -march=rv64gc -S test.c`.
---
clang/include/clang/Sema/Sema.h | 3 +-
clang/lib/Basic/Targets/RISCV.cpp | 3 +-
clang/lib/Sema/Sema.cpp | 7 +-
clang/lib/Sema/SemaChecking.cpp | 70 +++
clang/lib/Sema/SemaDecl.cpp | 9 ++-
.../RISCV/rvb-intrinsics/riscv32-zbb-error.c | 4 +-
.../RISCV/rvb-intrinsics/riscv64-zbkb-error.c | 12 ++--
.../rvv-intrinsics-handcrafted/rvv-error.c| 2 +-
clang/test/Sema/riscv-function-target-attr.c | 41 +++
clang/utils/TableGen/RISCVVEmitter.cpp| 4 --
10 files changed, 73 insertions(+), 82 deletions(-)
create mode 100644 clang/test/Sema/riscv-function-target-attr.c
diff --git a/clang/include/clang/Sema/Sema.h b/clang/include/clang/Sema/Sema.h
index ef4b93fac95ce5..932b76c82af0ee 100644
--- a/clang/include/clang/Sema/Sema.h
+++ b/clang/include/clang/Sema/Sema.h
@@ -14067,7 +14067,8 @@ class Sema final {
bool CheckRISCVLMUL(CallExpr *TheCall, unsigned ArgNum);
bool CheckRISCVBuiltinFunctionCall(const TargetInfo , unsigned BuiltinID,
CallExpr *TheCall);
- void checkRVVTypeSupport(QualType Ty, SourceLocation Loc, Decl *D);
+ void checkRVVTypeSupport(QualType Ty, SourceLocation Loc, Decl *D,
+ const llvm::StringMap );
bool CheckLoongArchBuiltinFunctionCall(const TargetInfo ,
unsigned BuiltinID, CallExpr
*TheCall);
bool CheckWebAssemblyBuiltinFunctionCall(const TargetInfo ,
diff --git a/clang/lib/Basic/Targets/RISCV.cpp
b/clang/lib/Basic/Targets/RISCV.cpp
index a6d4af2b88111a..6991caa21d23b4 100644
--- a/clang/lib/Basic/Targets/RISCV.cpp
+++ b/clang/lib/Basic/Targets/RISCV.cpp
@@ -463,7 +463,8 @@ ParsedTargetAttr RISCVTargetInfo::parseTargetAttr(StringRef
Features) const {
Ret.Duplicate = "tune=";
Ret.Tune = AttrString;
-}
+} else if (Feature.starts_with("+"))
+ Ret.Features.push_back(Feature.str());
}
return Ret;
}
diff --git a/clang/lib/Sema/Sema.cpp b/clang/lib/Sema/Sema.cpp
index cfb653e665ea03..41c7bfb25a7921 100644
--- a/clang/lib/Sema/Sema.cpp
+++ b/clang/lib/Sema/Sema.cpp
@@ -2077,8 +2077,11 @@ void Sema::checkTypeSupport(QualType Ty, SourceLocation
Loc, ValueDecl *D) {
targetDiag(D->getLocation(), diag::note_defined_here, FD) << D;
}
-if (TI.hasRISCVVTypes() && Ty->isRVVSizelessBuiltinType())
- checkRVVTypeSupport(Ty, Loc, D);
+if (TI.hasRISCVVTypes() && Ty->isRVVSizelessBuiltinType() && FD) {
+ llvm::StringMap CallerFeatureMap;
+ Context.getFunctionFeatureMap(CallerFeatureMap, FD);
+ checkRVVTypeSupport(Ty, Loc, D, CallerFeatureMap);
+}
// Don't allow SVE types in functions without a SVE target.
if (Ty->isSVESizelessBuiltinType() && FD && FD->hasBody()) {
diff --git a/clang/lib/Sema/SemaChecking.cpp b/clang/lib/Sema/SemaChecking.cpp
index 0d4d57db01c93a..50afb56ae09eac 100644
--- a/clang/lib/Sema/SemaChecking.cpp
+++ b/clang/lib/Sema/SemaChecking.cpp
@@ -5415,57 +5415,6 @@ static bool CheckInvalidVLENandLMUL(const TargetInfo
, CallExpr *TheCall,
bool Sema::CheckRISCVBuiltinFunctionCall(const TargetInfo ,
unsigned BuiltinID,
CallExpr *TheCall) {
- // CodeGenFunction can also detect this, but this gives a better error
- // message.
- bool FeatureMissing = false;
- SmallVector ReqFeatures;
- StringRef Features = Context.BuiltinInfo.getRequiredFeatures(BuiltinID);
- Features.split(ReqFeatures, ',', -1, false);
-
- // Check if each required
[clang] [clang][RISCV] Reorder sema check for RVV type (PR #83553)
4vtomat wrote: Maybe we can modify the current test case, it would get the error message "RISC-V type 'vfloat64m1_t' ... requires the 'zve64x' extension", but should be 'zve64d' instead. https://github.com/llvm/llvm-project/pull/83553 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [clang][RISCV] Reorder sema check for RVV type (PR #83553)
https://github.com/4vtomat updated
https://github.com/llvm/llvm-project/pull/83553
>From 8ad3a883d29155dc26c79abdd57ea0f72d046dfc Mon Sep 17 00:00:00 2001
From: Brandon Wu
Date: Fri, 1 Mar 2024 00:40:21 -0800
Subject: [PATCH 1/3] [clang][RISCV] Reorder sema check for RVV type
Currently using the command `clang -cc1 -triple riscv64` to compile the
code below:
```
#include
void foo() {
vfloat64m1_t f64m1;
}
```
would get the error message "RISC-V type 'vfloat64m1_t' ... requires the
'zve64x' extension"
which is supposed to be "RISC-V type 'vfloat64m1_t' ... requires the 'zve64d'
extension".
---
clang/lib/Sema/SemaChecking.cpp | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/clang/lib/Sema/SemaChecking.cpp b/clang/lib/Sema/SemaChecking.cpp
index 979b63884359fc..27ed6f2da05254 100644
--- a/clang/lib/Sema/SemaChecking.cpp
+++ b/clang/lib/Sema/SemaChecking.cpp
@@ -6332,9 +6332,12 @@ void Sema::checkRVVTypeSupport(QualType Ty,
SourceLocation Loc, Decl *D) {
unsigned EltSize = Context.getTypeSize(Info.ElementType);
unsigned MinElts = Info.EC.getKnownMinValue();
+ if (Info.ElementType->isSpecificBuiltinType(BuiltinType::Double) &&
+ !TI.hasFeature("zve64d"))
+Diag(Loc, diag::err_riscv_type_requires_extension, D) << Ty << "zve64d";
// (ELEN, LMUL) pairs of (8, mf8), (16, mf4), (32, mf2), (64, m1) requires at
// least zve64x
- if (((EltSize == 64 && Info.ElementType->isIntegerType()) || MinElts == 1) &&
+ else if (((EltSize == 64 && Info.ElementType->isIntegerType()) || MinElts ==
1) &&
!TI.hasFeature("zve64x"))
Diag(Loc, diag::err_riscv_type_requires_extension, D) << Ty << "zve64x";
else if (Info.ElementType->isFloat16Type() && !TI.hasFeature("zvfh") &&
@@ -6347,9 +6350,6 @@ void Sema::checkRVVTypeSupport(QualType Ty,
SourceLocation Loc, Decl *D) {
else if (Info.ElementType->isSpecificBuiltinType(BuiltinType::Float) &&
!TI.hasFeature("zve32f"))
Diag(Loc, diag::err_riscv_type_requires_extension, D) << Ty << "zve32f";
- else if (Info.ElementType->isSpecificBuiltinType(BuiltinType::Double) &&
- !TI.hasFeature("zve64d"))
-Diag(Loc, diag::err_riscv_type_requires_extension, D) << Ty << "zve64d";
// Given that caller already checked isRVVType() before calling this
function,
// if we don't have at least zve32x supported, then we need to emit error.
else if (!TI.hasFeature("zve32x"))
>From 779aebac10d2128d4507f74c2c929ab0924a80b6 Mon Sep 17 00:00:00 2001
From: Brandon Wu
Date: Fri, 1 Mar 2024 02:57:00 -0800
Subject: [PATCH 2/3] fixup! [clang][RISCV] Reorder sema check for RVV type
---
clang/lib/Sema/SemaChecking.cpp | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/clang/lib/Sema/SemaChecking.cpp b/clang/lib/Sema/SemaChecking.cpp
index 27ed6f2da05254..ae011806eec629 100644
--- a/clang/lib/Sema/SemaChecking.cpp
+++ b/clang/lib/Sema/SemaChecking.cpp
@@ -6333,12 +6333,13 @@ void Sema::checkRVVTypeSupport(QualType Ty,
SourceLocation Loc, Decl *D) {
unsigned MinElts = Info.EC.getKnownMinValue();
if (Info.ElementType->isSpecificBuiltinType(BuiltinType::Double) &&
- !TI.hasFeature("zve64d"))
+ !TI.hasFeature("zve64d"))
Diag(Loc, diag::err_riscv_type_requires_extension, D) << Ty << "zve64d";
// (ELEN, LMUL) pairs of (8, mf8), (16, mf4), (32, mf2), (64, m1) requires at
// least zve64x
- else if (((EltSize == 64 && Info.ElementType->isIntegerType()) || MinElts ==
1) &&
- !TI.hasFeature("zve64x"))
+ else if (((EltSize == 64 && Info.ElementType->isIntegerType()) ||
+MinElts == 1) &&
+ !TI.hasFeature("zve64x"))
Diag(Loc, diag::err_riscv_type_requires_extension, D) << Ty << "zve64x";
else if (Info.ElementType->isFloat16Type() && !TI.hasFeature("zvfh") &&
!TI.hasFeature("zvfhmin"))
>From ee33c7d12c307835b5f999eef9f3db6f0d0071f7 Mon Sep 17 00:00:00 2001
From: Brandon Wu
Date: Sat, 2 Mar 2024 02:58:12 -0800
Subject: [PATCH 3/3] fixup! [clang][RISCV] Reorder sema check for RVV type
---
clang/test/Sema/riscv-vector-float64-check.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/clang/test/Sema/riscv-vector-float64-check.c
b/clang/test/Sema/riscv-vector-float64-check.c
index ee7db32663959e..f21ae5c0c70405 100644
--- a/clang/test/Sema/riscv-vector-float64-check.c
+++ b/clang/test/Sema/riscv-vector-float64-check.c
@@ -1,5 +1,4 @@
-// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
-// RUN: -target-feature +zve64f -target-feature +zfh \
+// RUN: %clang_cc1 -triple riscv64 -target-feature +zve32x \
// RUN: -disable-O0-optnone -o - -fsyntax-only %s -verify
// REQUIRES: riscv-registered-target
#include
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[clang] [clang][RISCV] Reorder sema check for RVV type (PR #83553)
https://github.com/4vtomat updated
https://github.com/llvm/llvm-project/pull/83553
>From 8ad3a883d29155dc26c79abdd57ea0f72d046dfc Mon Sep 17 00:00:00 2001
From: Brandon Wu
Date: Fri, 1 Mar 2024 00:40:21 -0800
Subject: [PATCH 1/2] [clang][RISCV] Reorder sema check for RVV type
Currently using the command `clang -cc1 -triple riscv64` to compile the
code below:
```
#include
void foo() {
vfloat64m1_t f64m1;
}
```
would get the error message "RISC-V type 'vfloat64m1_t' ... requires the
'zve64x' extension"
which is supposed to be "RISC-V type 'vfloat64m1_t' ... requires the 'zve64d'
extension".
---
clang/lib/Sema/SemaChecking.cpp | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/clang/lib/Sema/SemaChecking.cpp b/clang/lib/Sema/SemaChecking.cpp
index 979b63884359fc..27ed6f2da05254 100644
--- a/clang/lib/Sema/SemaChecking.cpp
+++ b/clang/lib/Sema/SemaChecking.cpp
@@ -6332,9 +6332,12 @@ void Sema::checkRVVTypeSupport(QualType Ty,
SourceLocation Loc, Decl *D) {
unsigned EltSize = Context.getTypeSize(Info.ElementType);
unsigned MinElts = Info.EC.getKnownMinValue();
+ if (Info.ElementType->isSpecificBuiltinType(BuiltinType::Double) &&
+ !TI.hasFeature("zve64d"))
+Diag(Loc, diag::err_riscv_type_requires_extension, D) << Ty << "zve64d";
// (ELEN, LMUL) pairs of (8, mf8), (16, mf4), (32, mf2), (64, m1) requires at
// least zve64x
- if (((EltSize == 64 && Info.ElementType->isIntegerType()) || MinElts == 1) &&
+ else if (((EltSize == 64 && Info.ElementType->isIntegerType()) || MinElts ==
1) &&
!TI.hasFeature("zve64x"))
Diag(Loc, diag::err_riscv_type_requires_extension, D) << Ty << "zve64x";
else if (Info.ElementType->isFloat16Type() && !TI.hasFeature("zvfh") &&
@@ -6347,9 +6350,6 @@ void Sema::checkRVVTypeSupport(QualType Ty,
SourceLocation Loc, Decl *D) {
else if (Info.ElementType->isSpecificBuiltinType(BuiltinType::Float) &&
!TI.hasFeature("zve32f"))
Diag(Loc, diag::err_riscv_type_requires_extension, D) << Ty << "zve32f";
- else if (Info.ElementType->isSpecificBuiltinType(BuiltinType::Double) &&
- !TI.hasFeature("zve64d"))
-Diag(Loc, diag::err_riscv_type_requires_extension, D) << Ty << "zve64d";
// Given that caller already checked isRVVType() before calling this
function,
// if we don't have at least zve32x supported, then we need to emit error.
else if (!TI.hasFeature("zve32x"))
>From 779aebac10d2128d4507f74c2c929ab0924a80b6 Mon Sep 17 00:00:00 2001
From: Brandon Wu
Date: Fri, 1 Mar 2024 02:57:00 -0800
Subject: [PATCH 2/2] fixup! [clang][RISCV] Reorder sema check for RVV type
---
clang/lib/Sema/SemaChecking.cpp | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/clang/lib/Sema/SemaChecking.cpp b/clang/lib/Sema/SemaChecking.cpp
index 27ed6f2da05254..ae011806eec629 100644
--- a/clang/lib/Sema/SemaChecking.cpp
+++ b/clang/lib/Sema/SemaChecking.cpp
@@ -6333,12 +6333,13 @@ void Sema::checkRVVTypeSupport(QualType Ty,
SourceLocation Loc, Decl *D) {
unsigned MinElts = Info.EC.getKnownMinValue();
if (Info.ElementType->isSpecificBuiltinType(BuiltinType::Double) &&
- !TI.hasFeature("zve64d"))
+ !TI.hasFeature("zve64d"))
Diag(Loc, diag::err_riscv_type_requires_extension, D) << Ty << "zve64d";
// (ELEN, LMUL) pairs of (8, mf8), (16, mf4), (32, mf2), (64, m1) requires at
// least zve64x
- else if (((EltSize == 64 && Info.ElementType->isIntegerType()) || MinElts ==
1) &&
- !TI.hasFeature("zve64x"))
+ else if (((EltSize == 64 && Info.ElementType->isIntegerType()) ||
+MinElts == 1) &&
+ !TI.hasFeature("zve64x"))
Diag(Loc, diag::err_riscv_type_requires_extension, D) << Ty << "zve64x";
else if (Info.ElementType->isFloat16Type() && !TI.hasFeature("zvfh") &&
!TI.hasFeature("zvfhmin"))
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[clang] [clang][RISCV] Reorder sema check for RVV type (PR #83553)
https://github.com/4vtomat created
https://github.com/llvm/llvm-project/pull/83553
Currently using the command `clang -cc1 -triple riscv64` to compile the
code below:
```
#include
void foo() {
vfloat64m1_t f64m1;
}
```
would get the error message "RISC-V type 'vfloat64m1_t' ... requires the
'zve64x' extension"
which is supposed to be "RISC-V type 'vfloat64m1_t' ... requires the 'zve64d'
extension".
>From 8ad3a883d29155dc26c79abdd57ea0f72d046dfc Mon Sep 17 00:00:00 2001
From: Brandon Wu
Date: Fri, 1 Mar 2024 00:40:21 -0800
Subject: [PATCH] [clang][RISCV] Reorder sema check for RVV type
Currently using the command `clang -cc1 -triple riscv64` to compile the
code below:
```
#include
void foo() {
vfloat64m1_t f64m1;
}
```
would get the error message "RISC-V type 'vfloat64m1_t' ... requires the
'zve64x' extension"
which is supposed to be "RISC-V type 'vfloat64m1_t' ... requires the 'zve64d'
extension".
---
clang/lib/Sema/SemaChecking.cpp | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/clang/lib/Sema/SemaChecking.cpp b/clang/lib/Sema/SemaChecking.cpp
index 979b63884359fc..27ed6f2da05254 100644
--- a/clang/lib/Sema/SemaChecking.cpp
+++ b/clang/lib/Sema/SemaChecking.cpp
@@ -6332,9 +6332,12 @@ void Sema::checkRVVTypeSupport(QualType Ty,
SourceLocation Loc, Decl *D) {
unsigned EltSize = Context.getTypeSize(Info.ElementType);
unsigned MinElts = Info.EC.getKnownMinValue();
+ if (Info.ElementType->isSpecificBuiltinType(BuiltinType::Double) &&
+ !TI.hasFeature("zve64d"))
+Diag(Loc, diag::err_riscv_type_requires_extension, D) << Ty << "zve64d";
// (ELEN, LMUL) pairs of (8, mf8), (16, mf4), (32, mf2), (64, m1) requires at
// least zve64x
- if (((EltSize == 64 && Info.ElementType->isIntegerType()) || MinElts == 1) &&
+ else if (((EltSize == 64 && Info.ElementType->isIntegerType()) || MinElts ==
1) &&
!TI.hasFeature("zve64x"))
Diag(Loc, diag::err_riscv_type_requires_extension, D) << Ty << "zve64x";
else if (Info.ElementType->isFloat16Type() && !TI.hasFeature("zvfh") &&
@@ -6347,9 +6350,6 @@ void Sema::checkRVVTypeSupport(QualType Ty,
SourceLocation Loc, Decl *D) {
else if (Info.ElementType->isSpecificBuiltinType(BuiltinType::Float) &&
!TI.hasFeature("zve32f"))
Diag(Loc, diag::err_riscv_type_requires_extension, D) << Ty << "zve32f";
- else if (Info.ElementType->isSpecificBuiltinType(BuiltinType::Double) &&
- !TI.hasFeature("zve64d"))
-Diag(Loc, diag::err_riscv_type_requires_extension, D) << Ty << "zve64d";
// Given that caller already checked isRVVType() before calling this
function,
// if we don't have at least zve32x supported, then we need to emit error.
else if (!TI.hasFeature("zve32x"))
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[clang] [llvm] [RISCV] RISCV vector calling convention (1/2) (PR #77560)
4vtomat wrote: ping https://github.com/llvm/llvm-project/pull/77560 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] RISCV vector calling convention (1/2) (PR #77560)
4vtomat wrote: Rebase https://github.com/llvm/llvm-project/pull/77560 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RISCV] RISCV vector calling convention (1/2) (PR #77560)
4vtomat wrote: The latest fixup commit add [[riscv::riscv_vector]] supports for C23 and C++11. https://github.com/llvm/llvm-project/pull/77560 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [RISCV][clang] Add Zvfbfwma C intrinsics support (PR #79615)
https://github.com/4vtomat closed https://github.com/llvm/llvm-project/pull/79615 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [RISCV][clang] Add Zvfbfmin C intrinsics support (PR #79618)
https://github.com/4vtomat closed https://github.com/llvm/llvm-project/pull/79618 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [RISCV][clang] Add Zvfbfmin C intrinsics support (PR #79618)
@@ -1883,6 +1883,12 @@ let Log2LMUL = [-3, -2, -1, 0, 1, 2] in {
def vfncvt_rtz_x_f_w : RVVConvToNarrowingSignedBuiltin<"vfncvt_rtz_x">;
def vfncvt_rod_f_f_w : RVVConvBuiltin<"v", "vw", "xf", "vfncvt_rod_f">;
}
+
+// Zvfbfmin - Vector convert BF16 to FP32
+let Log2LMUL = [-2, -1, 0, 1, 2],
+OverloadedName = "vfwcvtbf16_f" in
+defm : RVVConvBuiltinSet<"vfwcvtbf16_f_f_v", "y", [["Fw", "Fwv"]]>;
4vtomat wrote:
Yes, we can just define like this~
https://github.com/llvm/llvm-project/pull/79618
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[clang] [RISCV][clang] Add Zvfbfmin C intrinsics support (PR #79618)
https://github.com/4vtomat deleted https://github.com/llvm/llvm-project/pull/79618 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [RISCV][clang] Add Zvfbfwma C intrinsics support (PR #79615)
@@ -1730,12 +1730,26 @@ let ManualCodegen = [{
defm vfwnmacc : RVVFloatingWidenTerBuiltinSetRoundingMode;
defm vfwmsac : RVVFloatingWidenTerBuiltinSetRoundingMode;
defm vfwnmsac : RVVFloatingWidenTerBuiltinSetRoundingMode;
+
+// Vector BF16 widening multiply-accumulate
+let Log2LMUL = [-2, -1, 0, 1, 2],
4vtomat wrote:
Yes, we do.
https://github.com/llvm/llvm-project/pull/79615
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[clang] [RISCV][clang] Add Zvfbfwma C intrinsics support (PR #79615)
@@ -0,0 +1,479 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \ +// RUN: -target-feature +zvfh -target-feature +experimental-zvfbfwma -disable-O0-optnone \ 4vtomat wrote: No, it doesn't, I just copied the test cases from [this](https://github.com/riscv-non-isa/rvv-intrinsic-doc/pull/293) lol. I will remove it though. https://github.com/llvm/llvm-project/pull/79615 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [RISCV][clang] Add Zvfbfmin C intrinsics support (PR #79618)
@@ -1883,6 +1883,12 @@ let Log2LMUL = [-3, -2, -1, 0, 1, 2] in {
def vfncvt_rtz_x_f_w : RVVConvToNarrowingSignedBuiltin<"vfncvt_rtz_x">;
def vfncvt_rod_f_f_w : RVVConvBuiltin<"v", "vw", "xf", "vfncvt_rod_f">;
}
+
+// Zvfbfmin - Vector convert BF16 to FP32
+let Log2LMUL = [-2, -1, 0, 1, 2],
+OverloadedName = "vfwcvtbf16_f" in
+defm : RVVConvBuiltinSet<"vfwcvtbf16_f_f_v", "y", [["Fw", "Fwv"]]>;
4vtomat wrote:
There are two same definitions in this scope, one has `HasFRMRoundModeOp` and
the other doesn't. If we define the name then it causes the redefinition error.
https://github.com/llvm/llvm-project/pull/79618
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[clang] [RISCV][clang] Optimize memory usage of intrinsic lookup table (PR #77487)
https://github.com/4vtomat closed https://github.com/llvm/llvm-project/pull/77487 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [RISCV][clang] Optimize memory usage of intrinsic lookup table (PR #77487)
https://github.com/4vtomat updated
https://github.com/llvm/llvm-project/pull/77487
>From d52f1e4652f7791413c61cfb075755a46fca8cfa Mon Sep 17 00:00:00 2001
From: Brandon Wu
Date: Sun, 7 Jan 2024 18:10:59 -0800
Subject: [PATCH 1/3] [RISCV][clang] Optimize memory usage of intrinsic lookup
table
This patch optimize:
1. Reduce string size of RVVIntrinsicDef.
2. Reduce the type size of the index of intrinsics.
I use valgrind --tool=massif to analyze a simple program:
```
#include
vint32m1_t test(vint32m1_t v1, vint32m1_t v2, size_t vl) {
return __riscv_vadd(v1, v2, vl);
}
```
and before optimization, the peak memory usage is 15.68MB,
after optimization, the peak memory usage is 13.69MB.
---
clang/include/clang/Support/RISCVVIntrinsicUtils.h | 6 --
clang/lib/Sema/SemaRISCVVectorLookup.cpp | 13 +++--
clang/lib/Support/RISCVVIntrinsicUtils.cpp | 5 -
3 files changed, 11 insertions(+), 13 deletions(-)
diff --git a/clang/include/clang/Support/RISCVVIntrinsicUtils.h
b/clang/include/clang/Support/RISCVVIntrinsicUtils.h
index 05a5e02e1390054..a0b70d1c4155039 100644
--- a/clang/include/clang/Support/RISCVVIntrinsicUtils.h
+++ b/clang/include/clang/Support/RISCVVIntrinsicUtils.h
@@ -416,8 +416,10 @@ class RVVIntrinsic {
RVVTypePtr getOutputType() const { return OutputType; }
const RVVTypes () const { return InputTypes; }
llvm::StringRef getBuiltinName() const { return BuiltinName; }
- llvm::StringRef getName() const { return Name; }
- llvm::StringRef getOverloadedName() const { return OverloadedName; }
+ llvm::StringRef getName() const { return "__riscv_" + Name; }
+ llvm::StringRef getOverloadedName() const {
+return "__riscv_" + OverloadedName;
+ }
bool hasMaskedOffOperand() const { return HasMaskedOffOperand; }
bool hasVL() const { return HasVL; }
bool hasPolicy() const { return Scheme != PolicyScheme::SchemeNone; }
diff --git a/clang/lib/Sema/SemaRISCVVectorLookup.cpp
b/clang/lib/Sema/SemaRISCVVectorLookup.cpp
index 00a5ea65f3f4e7d..0f8c3e99f0c84e9 100644
--- a/clang/lib/Sema/SemaRISCVVectorLookup.cpp
+++ b/clang/lib/Sema/SemaRISCVVectorLookup.cpp
@@ -43,7 +43,7 @@ struct RVVIntrinsicDef {
struct RVVOverloadIntrinsicDef {
// Indexes of RISCVIntrinsicManagerImpl::IntrinsicList.
- SmallVector Indexes;
+ SmallVector Indexes;
};
} // namespace
@@ -162,7 +162,7 @@ class RISCVIntrinsicManagerImpl : public
sema::RISCVIntrinsicManager {
// List of all RVV intrinsic.
std::vector IntrinsicList;
// Mapping function name to index of IntrinsicList.
- StringMap Intrinsics;
+ StringMap Intrinsics;
// Mapping function name to RVVOverloadIntrinsicDef.
StringMap OverloadIntrinsics;
@@ -379,14 +379,14 @@ void RISCVIntrinsicManagerImpl::InitRVVIntrinsic(
OverloadedName += "_" + OverloadedSuffixStr.str();
// clang built-in function name, e.g. __builtin_rvv_vadd.
- std::string BuiltinName = "__builtin_rvv_" + std::string(Record.Name);
+ std::string BuiltinName = std::string(Record.Name);
RVVIntrinsic::updateNamesAndPolicy(IsMasked, HasPolicy, Name, BuiltinName,
OverloadedName, PolicyAttrs,
Record.HasFRMRoundModeOp);
// Put into IntrinsicList.
- uint32_t Index = IntrinsicList.size();
+ uint16_t Index = IntrinsicList.size();
IntrinsicList.push_back({BuiltinName, Signature});
// Creating mapping to Intrinsics.
@@ -451,7 +451,8 @@ void
RISCVIntrinsicManagerImpl::CreateRVVIntrinsicDecl(LookupResult ,
RVVIntrinsicDecl->addAttr(OverloadableAttr::CreateImplicit(Context));
// Setup alias to __builtin_rvv_*
- IdentifierInfo = PP.getIdentifierTable().get(IDef.BuiltinName);
+ IdentifierInfo =
+ PP.getIdentifierTable().get("__builtin_rvv_" + IDef.BuiltinName);
RVVIntrinsicDecl->addAttr(
BuiltinAliasAttr::CreateImplicit(S.Context, ));
@@ -462,7 +463,7 @@ void
RISCVIntrinsicManagerImpl::CreateRVVIntrinsicDecl(LookupResult ,
bool RISCVIntrinsicManagerImpl::CreateIntrinsicIfFound(LookupResult ,
IdentifierInfo *II,
Preprocessor ) {
- StringRef Name = II->getName();
+ StringRef Name = II->getName().substr(8);
// Lookup the function name from the overload intrinsics first.
auto OvIItr = OverloadIntrinsics.find(Name);
diff --git a/clang/lib/Support/RISCVVIntrinsicUtils.cpp
b/clang/lib/Support/RISCVVIntrinsicUtils.cpp
index 2de977a3dc720bd..7d2a2d7e826f9cd 100644
--- a/clang/lib/Support/RISCVVIntrinsicUtils.cpp
+++ b/clang/lib/Support/RISCVVIntrinsicUtils.cpp
@@ -1150,11 +1150,6 @@ void RVVIntrinsic::updateNamesAndPolicy(
OverloadedName += suffix;
};
- // This follows the naming guideline under riscv-c-api-doc to add the
- // `__riscv_` suffix for all RVV intrinsics.
- Name = "__riscv_" + Name;
- OverloadedName = "__riscv_" + OverloadedName;
-
if (HasFRMRoundModeOp) {
[llvm] [clang] [RISCV][SiFive] Reduce intrinsics of SiFive VCIX extension (PR #79407)
https://github.com/4vtomat closed https://github.com/llvm/llvm-project/pull/79407 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [RISCV] Add missing dependency check for Zvkb (PR #79467)
https://github.com/4vtomat closed https://github.com/llvm/llvm-project/pull/79467 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [RISCV] Add missing dependency check for Zvkb (PR #79467)
https://github.com/4vtomat updated
https://github.com/llvm/llvm-project/pull/79467
>From 6f16a5b2807e1cab5edae90f92cf0145474f4f23 Mon Sep 17 00:00:00 2001
From: Brandon Wu
Date: Thu, 25 Jan 2024 08:13:31 -0800
Subject: [PATCH] [RISCV] Add missing dependency check for Zvkb
---
clang/test/Driver/riscv-toolchain-gcc-multilib-reuse.c | 2 +-
llvm/lib/Support/RISCVISAInfo.cpp | 4 ++--
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/clang/test/Driver/riscv-toolchain-gcc-multilib-reuse.c
b/clang/test/Driver/riscv-toolchain-gcc-multilib-reuse.c
index 1f8a5a8821edfad..ac70fb2631a590c 100644
--- a/clang/test/Driver/riscv-toolchain-gcc-multilib-reuse.c
+++ b/clang/test/Driver/riscv-toolchain-gcc-multilib-reuse.c
@@ -66,7 +66,7 @@
// RUN: -target riscv64-unknown-elf \
// RUN: --gcc-toolchain=%S/Inputs/multilib_riscv_elf_sdk \
// RUN: --print-multi-directory \
-// RUN: -march=rv32i_zvkb -mabi=ilp32 \
+// RUN: -march=rv32iv_zvkb -mabi=ilp32 \
// RUN: | FileCheck -check-prefix=GCC-MULTI-LIB-REUSE-RV32I_ZVKB-ILP32 %s
// GCC-MULTI-LIB-REUSE-RV32I_ZVKB-ILP32: rv32i/ilp32
// GCC-MULTI-LIB-REUSE-RV32I_ZVKB-ILP32-NOT: {{^.+$}}
diff --git a/llvm/lib/Support/RISCVISAInfo.cpp
b/llvm/lib/Support/RISCVISAInfo.cpp
index 32b4ff5de86f1ea..a359e6eefa8f1d1 100644
--- a/llvm/lib/Support/RISCVISAInfo.cpp
+++ b/llvm/lib/Support/RISCVISAInfo.cpp
@@ -976,8 +976,8 @@ Error RISCVISAInfo::checkDependency() {
errc::invalid_argument,
"'zvbc' requires 'v' or 'zve64*' extension to also be specified");
- if ((Exts.count("zvkg") || Exts.count("zvkned") || Exts.count("zvknha") ||
- Exts.count("zvksed") || Exts.count("zvksh")) &&
+ if ((Exts.count("zvkb") || Exts.count("zvkg") || Exts.count("zvkned") ||
+ Exts.count("zvknha") || Exts.count("zvksed") || Exts.count("zvksh")) &&
!HasVector)
return createStringError(
errc::invalid_argument,
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[clang] [llvm] [RISCV] Add missing dependency check for Zvkb (PR #79467)
https://github.com/4vtomat updated
https://github.com/llvm/llvm-project/pull/79467
>From d451e89a2bf650d3af638a2d22582135ad53cc27 Mon Sep 17 00:00:00 2001
From: Brandon Wu
Date: Thu, 25 Jan 2024 08:13:31 -0800
Subject: [PATCH] [RISCV] Add missing dependency check for Zvkb
---
clang/test/Driver/riscv-toolchain-gcc-multilib-reuse.c | 2 +-
llvm/lib/Support/RISCVISAInfo.cpp | 4 ++--
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/clang/test/Driver/riscv-toolchain-gcc-multilib-reuse.c
b/clang/test/Driver/riscv-toolchain-gcc-multilib-reuse.c
index 1f8a5a8821edfa..ac70fb2631a590 100644
--- a/clang/test/Driver/riscv-toolchain-gcc-multilib-reuse.c
+++ b/clang/test/Driver/riscv-toolchain-gcc-multilib-reuse.c
@@ -66,7 +66,7 @@
// RUN: -target riscv64-unknown-elf \
// RUN: --gcc-toolchain=%S/Inputs/multilib_riscv_elf_sdk \
// RUN: --print-multi-directory \
-// RUN: -march=rv32i_zvkb -mabi=ilp32 \
+// RUN: -march=rv32iv_zvkb -mabi=ilp32 \
// RUN: | FileCheck -check-prefix=GCC-MULTI-LIB-REUSE-RV32I_ZVKB-ILP32 %s
// GCC-MULTI-LIB-REUSE-RV32I_ZVKB-ILP32: rv32i/ilp32
// GCC-MULTI-LIB-REUSE-RV32I_ZVKB-ILP32-NOT: {{^.+$}}
diff --git a/llvm/lib/Support/RISCVISAInfo.cpp
b/llvm/lib/Support/RISCVISAInfo.cpp
index 32b4ff5de86f1e..a359e6eefa8f1d 100644
--- a/llvm/lib/Support/RISCVISAInfo.cpp
+++ b/llvm/lib/Support/RISCVISAInfo.cpp
@@ -976,8 +976,8 @@ Error RISCVISAInfo::checkDependency() {
errc::invalid_argument,
"'zvbc' requires 'v' or 'zve64*' extension to also be specified");
- if ((Exts.count("zvkg") || Exts.count("zvkned") || Exts.count("zvknha") ||
- Exts.count("zvksed") || Exts.count("zvksh")) &&
+ if ((Exts.count("zvkb") || Exts.count("zvkg") || Exts.count("zvkned") ||
+ Exts.count("zvknha") || Exts.count("zvksed") || Exts.count("zvksh")) &&
!HasVector)
return createStringError(
errc::invalid_argument,
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[clang] [RISCV][clang] Optimize memory usage of intrinsic lookup table (PR #77487)
https://github.com/4vtomat updated
https://github.com/llvm/llvm-project/pull/77487
>From 84ea759c43d8e9cb450d95d00fd802be622153a2 Mon Sep 17 00:00:00 2001
From: Brandon Wu
Date: Sun, 7 Jan 2024 18:10:59 -0800
Subject: [PATCH 1/3] [RISCV][clang] Optimize memory usage of intrinsic lookup
table
This patch optimize:
1. Reduce string size of RVVIntrinsicDef.
2. Reduce the type size of the index of intrinsics.
I use valgrind --tool=massif to analyze a simple program:
```
#include
vint32m1_t test(vint32m1_t v1, vint32m1_t v2, size_t vl) {
return __riscv_vadd(v1, v2, vl);
}
```
and before optimization, the peak memory usage is 15.68MB,
after optimization, the peak memory usage is 13.69MB.
---
clang/include/clang/Support/RISCVVIntrinsicUtils.h | 6 --
clang/lib/Sema/SemaRISCVVectorLookup.cpp | 13 +++--
clang/lib/Support/RISCVVIntrinsicUtils.cpp | 5 -
3 files changed, 11 insertions(+), 13 deletions(-)
diff --git a/clang/include/clang/Support/RISCVVIntrinsicUtils.h
b/clang/include/clang/Support/RISCVVIntrinsicUtils.h
index c525d3443331e0b..7e20f022c28b551 100644
--- a/clang/include/clang/Support/RISCVVIntrinsicUtils.h
+++ b/clang/include/clang/Support/RISCVVIntrinsicUtils.h
@@ -416,8 +416,10 @@ class RVVIntrinsic {
RVVTypePtr getOutputType() const { return OutputType; }
const RVVTypes () const { return InputTypes; }
llvm::StringRef getBuiltinName() const { return BuiltinName; }
- llvm::StringRef getName() const { return Name; }
- llvm::StringRef getOverloadedName() const { return OverloadedName; }
+ llvm::StringRef getName() const { return "__riscv_" + Name; }
+ llvm::StringRef getOverloadedName() const {
+return "__riscv_" + OverloadedName;
+ }
bool hasMaskedOffOperand() const { return HasMaskedOffOperand; }
bool hasVL() const { return HasVL; }
bool hasPolicy() const { return Scheme != PolicyScheme::SchemeNone; }
diff --git a/clang/lib/Sema/SemaRISCVVectorLookup.cpp
b/clang/lib/Sema/SemaRISCVVectorLookup.cpp
index 3ed3e6195441893..e9523871e9cd1fb 100644
--- a/clang/lib/Sema/SemaRISCVVectorLookup.cpp
+++ b/clang/lib/Sema/SemaRISCVVectorLookup.cpp
@@ -43,7 +43,7 @@ struct RVVIntrinsicDef {
struct RVVOverloadIntrinsicDef {
// Indexes of RISCVIntrinsicManagerImpl::IntrinsicList.
- SmallVector Indexes;
+ SmallVector Indexes;
};
} // namespace
@@ -162,7 +162,7 @@ class RISCVIntrinsicManagerImpl : public
sema::RISCVIntrinsicManager {
// List of all RVV intrinsic.
std::vector IntrinsicList;
// Mapping function name to index of IntrinsicList.
- StringMap Intrinsics;
+ StringMap Intrinsics;
// Mapping function name to RVVOverloadIntrinsicDef.
StringMap OverloadIntrinsics;
@@ -380,14 +380,14 @@ void RISCVIntrinsicManagerImpl::InitRVVIntrinsic(
OverloadedName += "_" + OverloadedSuffixStr.str();
// clang built-in function name, e.g. __builtin_rvv_vadd.
- std::string BuiltinName = "__builtin_rvv_" + std::string(Record.Name);
+ std::string BuiltinName = std::string(Record.Name);
RVVIntrinsic::updateNamesAndPolicy(IsMasked, HasPolicy, Name, BuiltinName,
OverloadedName, PolicyAttrs,
Record.HasFRMRoundModeOp);
// Put into IntrinsicList.
- uint32_t Index = IntrinsicList.size();
+ uint16_t Index = IntrinsicList.size();
IntrinsicList.push_back({BuiltinName, Signature});
// Creating mapping to Intrinsics.
@@ -452,7 +452,8 @@ void
RISCVIntrinsicManagerImpl::CreateRVVIntrinsicDecl(LookupResult ,
RVVIntrinsicDecl->addAttr(OverloadableAttr::CreateImplicit(Context));
// Setup alias to __builtin_rvv_*
- IdentifierInfo = PP.getIdentifierTable().get(IDef.BuiltinName);
+ IdentifierInfo =
+ PP.getIdentifierTable().get("__builtin_rvv_" + IDef.BuiltinName);
RVVIntrinsicDecl->addAttr(
BuiltinAliasAttr::CreateImplicit(S.Context, ));
@@ -463,7 +464,7 @@ void
RISCVIntrinsicManagerImpl::CreateRVVIntrinsicDecl(LookupResult ,
bool RISCVIntrinsicManagerImpl::CreateIntrinsicIfFound(LookupResult ,
IdentifierInfo *II,
Preprocessor ) {
- StringRef Name = II->getName();
+ StringRef Name = II->getName().substr(8);
// Lookup the function name from the overload intrinsics first.
auto OvIItr = OverloadIntrinsics.find(Name);
diff --git a/clang/lib/Support/RISCVVIntrinsicUtils.cpp
b/clang/lib/Support/RISCVVIntrinsicUtils.cpp
index 2de977a3dc720bd..7d2a2d7e826f9cd 100644
--- a/clang/lib/Support/RISCVVIntrinsicUtils.cpp
+++ b/clang/lib/Support/RISCVVIntrinsicUtils.cpp
@@ -1150,11 +1150,6 @@ void RVVIntrinsic::updateNamesAndPolicy(
OverloadedName += suffix;
};
- // This follows the naming guideline under riscv-c-api-doc to add the
- // `__riscv_` suffix for all RVV intrinsics.
- Name = "__riscv_" + Name;
- OverloadedName = "__riscv_" + OverloadedName;
-
if (HasFRMRoundModeOp) {
[clang] [RISCV][clang] Optimize memory usage of intrinsic lookup table (PR #77487)
@@ -464,7 +466,8 @@ void
RISCVIntrinsicManagerImpl::CreateRVVIntrinsicDecl(LookupResult ,
bool RISCVIntrinsicManagerImpl::CreateIntrinsicIfFound(LookupResult ,
IdentifierInfo *II,
Preprocessor ) {
- StringRef Name = II->getName().substr(8);
+ StringRef Name = II->getName();
+ Name.consume_front("__riscv_");
4vtomat wrote:
Sure~
https://github.com/llvm/llvm-project/pull/77487
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[clang] [llvm] [RISCV] Add missing dependency check for Zvkb (PR #79467)
https://github.com/4vtomat created
https://github.com/llvm/llvm-project/pull/79467
None
>From 61dd60b6172df5a73daa403d1fc5b5e39169df40 Mon Sep 17 00:00:00 2001
From: Brandon Wu
Date: Thu, 25 Jan 2024 08:13:31 -0800
Subject: [PATCH] [RISCV] Add missing dependency check for Zvkb
---
clang/test/Driver/riscv-toolchain-gcc-multilib-reuse.c | 2 +-
llvm/lib/Support/RISCVISAInfo.cpp | 4 ++--
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/clang/test/Driver/riscv-toolchain-gcc-multilib-reuse.c
b/clang/test/Driver/riscv-toolchain-gcc-multilib-reuse.c
index 1f8a5a8821edfa..ac70fb2631a590 100644
--- a/clang/test/Driver/riscv-toolchain-gcc-multilib-reuse.c
+++ b/clang/test/Driver/riscv-toolchain-gcc-multilib-reuse.c
@@ -66,7 +66,7 @@
// RUN: -target riscv64-unknown-elf \
// RUN: --gcc-toolchain=%S/Inputs/multilib_riscv_elf_sdk \
// RUN: --print-multi-directory \
-// RUN: -march=rv32i_zvkb -mabi=ilp32 \
+// RUN: -march=rv32iv_zvkb -mabi=ilp32 \
// RUN: | FileCheck -check-prefix=GCC-MULTI-LIB-REUSE-RV32I_ZVKB-ILP32 %s
// GCC-MULTI-LIB-REUSE-RV32I_ZVKB-ILP32: rv32i/ilp32
// GCC-MULTI-LIB-REUSE-RV32I_ZVKB-ILP32-NOT: {{^.+$}}
diff --git a/llvm/lib/Support/RISCVISAInfo.cpp
b/llvm/lib/Support/RISCVISAInfo.cpp
index 32b4ff5de86f1e..a359e6eefa8f1d 100644
--- a/llvm/lib/Support/RISCVISAInfo.cpp
+++ b/llvm/lib/Support/RISCVISAInfo.cpp
@@ -976,8 +976,8 @@ Error RISCVISAInfo::checkDependency() {
errc::invalid_argument,
"'zvbc' requires 'v' or 'zve64*' extension to also be specified");
- if ((Exts.count("zvkg") || Exts.count("zvkned") || Exts.count("zvknha") ||
- Exts.count("zvksed") || Exts.count("zvksh")) &&
+ if ((Exts.count("zvkb") || Exts.count("zvkg") || Exts.count("zvkned") ||
+ Exts.count("zvknha") || Exts.count("zvksed") || Exts.count("zvksh")) &&
!HasVector)
return createStringError(
errc::invalid_argument,
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[clang] [Clang][RISCV][RVV Intrinsic] Fix codegen redundant intrinsic names (PR #77889)
https://github.com/4vtomat approved this pull request. Thanks, LGTM~ https://github.com/llvm/llvm-project/pull/77889 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [RISCV][clang] Optimize memory usage of intrinsic lookup table (PR #77487)
@@ -380,14 +380,14 @@ void RISCVIntrinsicManagerImpl::InitRVVIntrinsic( OverloadedName += "_" + OverloadedSuffixStr.str(); // clang built-in function name, e.g. __builtin_rvv_vadd. - std::string BuiltinName = "__builtin_rvv_" + std::string(Record.Name); + std::string BuiltinName = std::string(Record.Name); RVVIntrinsic::updateNamesAndPolicy(IsMasked, HasPolicy, Name, BuiltinName, OverloadedName, PolicyAttrs, Record.HasFRMRoundModeOp); // Put into IntrinsicList. - uint32_t Index = IntrinsicList.size(); + uint16_t Index = IntrinsicList.size(); 4vtomat wrote: I've added an assertion for checking whether intrinsics overflow. https://github.com/llvm/llvm-project/pull/77487 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [RISCV][clang] Optimize memory usage of intrinsic lookup table (PR #77487)
https://github.com/4vtomat updated
https://github.com/llvm/llvm-project/pull/77487
>From 84ea759c43d8e9cb450d95d00fd802be622153a2 Mon Sep 17 00:00:00 2001
From: Brandon Wu
Date: Sun, 7 Jan 2024 18:10:59 -0800
Subject: [PATCH 1/2] [RISCV][clang] Optimize memory usage of intrinsic lookup
table
This patch optimize:
1. Reduce string size of RVVIntrinsicDef.
2. Reduce the type size of the index of intrinsics.
I use valgrind --tool=massif to analyze a simple program:
```
#include
vint32m1_t test(vint32m1_t v1, vint32m1_t v2, size_t vl) {
return __riscv_vadd(v1, v2, vl);
}
```
and before optimization, the peak memory usage is 15.68MB,
after optimization, the peak memory usage is 13.69MB.
---
clang/include/clang/Support/RISCVVIntrinsicUtils.h | 6 --
clang/lib/Sema/SemaRISCVVectorLookup.cpp | 13 +++--
clang/lib/Support/RISCVVIntrinsicUtils.cpp | 5 -
3 files changed, 11 insertions(+), 13 deletions(-)
diff --git a/clang/include/clang/Support/RISCVVIntrinsicUtils.h
b/clang/include/clang/Support/RISCVVIntrinsicUtils.h
index c525d3443331e0b..7e20f022c28b551 100644
--- a/clang/include/clang/Support/RISCVVIntrinsicUtils.h
+++ b/clang/include/clang/Support/RISCVVIntrinsicUtils.h
@@ -416,8 +416,10 @@ class RVVIntrinsic {
RVVTypePtr getOutputType() const { return OutputType; }
const RVVTypes () const { return InputTypes; }
llvm::StringRef getBuiltinName() const { return BuiltinName; }
- llvm::StringRef getName() const { return Name; }
- llvm::StringRef getOverloadedName() const { return OverloadedName; }
+ llvm::StringRef getName() const { return "__riscv_" + Name; }
+ llvm::StringRef getOverloadedName() const {
+return "__riscv_" + OverloadedName;
+ }
bool hasMaskedOffOperand() const { return HasMaskedOffOperand; }
bool hasVL() const { return HasVL; }
bool hasPolicy() const { return Scheme != PolicyScheme::SchemeNone; }
diff --git a/clang/lib/Sema/SemaRISCVVectorLookup.cpp
b/clang/lib/Sema/SemaRISCVVectorLookup.cpp
index 3ed3e6195441893..e9523871e9cd1fb 100644
--- a/clang/lib/Sema/SemaRISCVVectorLookup.cpp
+++ b/clang/lib/Sema/SemaRISCVVectorLookup.cpp
@@ -43,7 +43,7 @@ struct RVVIntrinsicDef {
struct RVVOverloadIntrinsicDef {
// Indexes of RISCVIntrinsicManagerImpl::IntrinsicList.
- SmallVector Indexes;
+ SmallVector Indexes;
};
} // namespace
@@ -162,7 +162,7 @@ class RISCVIntrinsicManagerImpl : public
sema::RISCVIntrinsicManager {
// List of all RVV intrinsic.
std::vector IntrinsicList;
// Mapping function name to index of IntrinsicList.
- StringMap Intrinsics;
+ StringMap Intrinsics;
// Mapping function name to RVVOverloadIntrinsicDef.
StringMap OverloadIntrinsics;
@@ -380,14 +380,14 @@ void RISCVIntrinsicManagerImpl::InitRVVIntrinsic(
OverloadedName += "_" + OverloadedSuffixStr.str();
// clang built-in function name, e.g. __builtin_rvv_vadd.
- std::string BuiltinName = "__builtin_rvv_" + std::string(Record.Name);
+ std::string BuiltinName = std::string(Record.Name);
RVVIntrinsic::updateNamesAndPolicy(IsMasked, HasPolicy, Name, BuiltinName,
OverloadedName, PolicyAttrs,
Record.HasFRMRoundModeOp);
// Put into IntrinsicList.
- uint32_t Index = IntrinsicList.size();
+ uint16_t Index = IntrinsicList.size();
IntrinsicList.push_back({BuiltinName, Signature});
// Creating mapping to Intrinsics.
@@ -452,7 +452,8 @@ void
RISCVIntrinsicManagerImpl::CreateRVVIntrinsicDecl(LookupResult ,
RVVIntrinsicDecl->addAttr(OverloadableAttr::CreateImplicit(Context));
// Setup alias to __builtin_rvv_*
- IdentifierInfo = PP.getIdentifierTable().get(IDef.BuiltinName);
+ IdentifierInfo =
+ PP.getIdentifierTable().get("__builtin_rvv_" + IDef.BuiltinName);
RVVIntrinsicDecl->addAttr(
BuiltinAliasAttr::CreateImplicit(S.Context, ));
@@ -463,7 +464,7 @@ void
RISCVIntrinsicManagerImpl::CreateRVVIntrinsicDecl(LookupResult ,
bool RISCVIntrinsicManagerImpl::CreateIntrinsicIfFound(LookupResult ,
IdentifierInfo *II,
Preprocessor ) {
- StringRef Name = II->getName();
+ StringRef Name = II->getName().substr(8);
// Lookup the function name from the overload intrinsics first.
auto OvIItr = OverloadIntrinsics.find(Name);
diff --git a/clang/lib/Support/RISCVVIntrinsicUtils.cpp
b/clang/lib/Support/RISCVVIntrinsicUtils.cpp
index 2de977a3dc720bd..7d2a2d7e826f9cd 100644
--- a/clang/lib/Support/RISCVVIntrinsicUtils.cpp
+++ b/clang/lib/Support/RISCVVIntrinsicUtils.cpp
@@ -1150,11 +1150,6 @@ void RVVIntrinsic::updateNamesAndPolicy(
OverloadedName += suffix;
};
- // This follows the naming guideline under riscv-c-api-doc to add the
- // `__riscv_` suffix for all RVV intrinsics.
- Name = "__riscv_" + Name;
- OverloadedName = "__riscv_" + OverloadedName;
-
if (HasFRMRoundModeOp) {
[clang] [llvm] [RISCV][SiFive] Reduce intrinsics of SiFive VCIX extension (PR #79407)
@@ -10,7 +10,8 @@ // CHECK-RV64-LABEL: @test_sf_vc_x_se_u64m1( // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT:call void @llvm.riscv.sf.vc.x.se.e64m1.i64.i64.i64(i64 3, i64 31, i64 31, i64 [[RS1:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT:[[CONV:%.*]] = trunc i64 [[RS1:%.*]] to i32 4vtomat wrote: I guess it's because I just use "i" for `sf_vc_x` in `riscv_sifive_vector.td`. Maybe I should also add ["c", "s", "l"] back~ https://github.com/llvm/llvm-project/pull/79407 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [Clang][RISCV][RVV Intrinsic] Fix codegen redundant intrinsic names (PR #77889)
4vtomat wrote: Since it only reduces about 160 of 54100 intrinsics generated, I have no opinion on this, just left the final decision to others~ But if this PR is finally decided to be merged, please add some comments around the code you added to explain, thanks! https://github.com/llvm/llvm-project/pull/77889 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [RISCV][clang] Optimize memory usage of intrinsic lookup table (PR #77487)
@@ -416,8 +416,10 @@ class RVVIntrinsic {
RVVTypePtr getOutputType() const { return OutputType; }
const RVVTypes () const { return InputTypes; }
llvm::StringRef getBuiltinName() const { return BuiltinName; }
- llvm::StringRef getName() const { return Name; }
- llvm::StringRef getOverloadedName() const { return OverloadedName; }
+ llvm::StringRef getName() const { return "__riscv_" + Name; }
4vtomat wrote:
I just can't find where is `getName` and `getOverloadedName`, I just comment
out this 2 member functions and run `ninja check-clang`, it passed.
Can we delete them?
https://github.com/llvm/llvm-project/pull/77487
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[clang] [RISCV][clang] Optimize memory usage of intrinsic lookup table (PR #77487)
https://github.com/4vtomat edited https://github.com/llvm/llvm-project/pull/77487 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [RISCV][clang] Optimize memory usage of intrinsic lookup table (PR #77487)
@@ -463,7 +464,7 @@ void
RISCVIntrinsicManagerImpl::CreateRVVIntrinsicDecl(LookupResult ,
bool RISCVIntrinsicManagerImpl::CreateIntrinsicIfFound(LookupResult ,
IdentifierInfo *II,
Preprocessor ) {
- StringRef Name = II->getName();
+ StringRef Name = II->getName().substr(8);
4vtomat wrote:
Yes, I think we should early return if `consume_front` return `false`.
https://github.com/llvm/llvm-project/pull/77487
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[clang] [RISCV][clang] Optimize memory usage of intrinsic lookup table (PR #77487)
@@ -416,8 +416,10 @@ class RVVIntrinsic {
RVVTypePtr getOutputType() const { return OutputType; }
const RVVTypes () const { return InputTypes; }
llvm::StringRef getBuiltinName() const { return BuiltinName; }
- llvm::StringRef getName() const { return Name; }
- llvm::StringRef getOverloadedName() const { return OverloadedName; }
+ llvm::StringRef getName() const { return "__riscv_" + Name; }
4vtomat wrote:
I mean, return the temporary string's raw data pointer(const char*).
https://github.com/llvm/llvm-project/pull/77487
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[clang] [RISCV][clang] Optimize memory usage of intrinsic lookup table (PR #77487)
@@ -416,8 +416,10 @@ class RVVIntrinsic {
RVVTypePtr getOutputType() const { return OutputType; }
const RVVTypes () const { return InputTypes; }
llvm::StringRef getBuiltinName() const { return BuiltinName; }
- llvm::StringRef getName() const { return Name; }
- llvm::StringRef getOverloadedName() const { return OverloadedName; }
+ llvm::StringRef getName() const { return "__riscv_" + Name; }
4vtomat wrote:
Do you think converting them to string literal is a good idea?
https://github.com/llvm/llvm-project/pull/77487
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[clang] [RISCV][clang] Optimize memory usage of intrinsic lookup table (PR #77487)
https://github.com/4vtomat deleted https://github.com/llvm/llvm-project/pull/77487 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [RISCV][clang] Optimize memory usage of intrinsic lookup table (PR #77487)
@@ -416,8 +416,10 @@ class RVVIntrinsic {
RVVTypePtr getOutputType() const { return OutputType; }
const RVVTypes () const { return InputTypes; }
llvm::StringRef getBuiltinName() const { return BuiltinName; }
- llvm::StringRef getName() const { return Name; }
- llvm::StringRef getOverloadedName() const { return OverloadedName; }
+ llvm::StringRef getName() const { return "__riscv_" + Name; }
4vtomat wrote:
Isn't it returning *this?
https://cplusplus.com/reference/string/string/operator+=/
https://github.com/llvm/llvm-project/pull/77487
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[clang] [RISCV][clang] Optimize memory usage of intrinsic lookup table (PR #77487)
@@ -463,7 +464,7 @@ void
RISCVIntrinsicManagerImpl::CreateRVVIntrinsicDecl(LookupResult ,
bool RISCVIntrinsicManagerImpl::CreateIntrinsicIfFound(LookupResult ,
IdentifierInfo *II,
Preprocessor ) {
- StringRef Name = II->getName();
+ StringRef Name = II->getName().substr(8);
4vtomat wrote:
Yes, if it doesn't match, it won't create the intrinsic.
https://github.com/llvm/llvm-project/pull/77487
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[clang] [RISCV][clang] Optimize memory usage of intrinsic lookup table (PR #77487)
@@ -380,14 +380,14 @@ void RISCVIntrinsicManagerImpl::InitRVVIntrinsic( OverloadedName += "_" + OverloadedSuffixStr.str(); // clang built-in function name, e.g. __builtin_rvv_vadd. - std::string BuiltinName = "__builtin_rvv_" + std::string(Record.Name); + std::string BuiltinName = std::string(Record.Name); RVVIntrinsic::updateNamesAndPolicy(IsMasked, HasPolicy, Name, BuiltinName, OverloadedName, PolicyAttrs, Record.HasFRMRoundModeOp); // Put into IntrinsicList. - uint32_t Index = IntrinsicList.size(); + uint16_t Index = IntrinsicList.size(); 4vtomat wrote: Currently we have 54848 RVV intrinsics. https://github.com/llvm/llvm-project/pull/77487 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [RISCV][clang] Optimize memory usage of intrinsic lookup table (PR #77487)
@@ -463,7 +464,7 @@ void
RISCVIntrinsicManagerImpl::CreateRVVIntrinsicDecl(LookupResult ,
bool RISCVIntrinsicManagerImpl::CreateIntrinsicIfFound(LookupResult ,
IdentifierInfo *II,
Preprocessor ) {
- StringRef Name = II->getName();
+ StringRef Name = II->getName().substr(8);
4vtomat wrote:
We can't add an assertion since other tokens go through this function too, or
can we filter out the token?
https://github.com/llvm/llvm-project/pull/77487
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[clang] [RISCV][clang] Optimize memory usage of intrinsic lookup table (PR #77487)
@@ -416,8 +416,10 @@ class RVVIntrinsic {
RVVTypePtr getOutputType() const { return OutputType; }
const RVVTypes () const { return InputTypes; }
llvm::StringRef getBuiltinName() const { return BuiltinName; }
- llvm::StringRef getName() const { return Name; }
- llvm::StringRef getOverloadedName() const { return OverloadedName; }
+ llvm::StringRef getName() const { return "__riscv_" + Name; }
4vtomat wrote:
String literal is placed in data segment so its lifetime is the lifetime of the
program. StringRef doesn't take the ownership, but string literal is alive
until the whole program ends, so I guess it's ok for referencing it?
https://github.com/llvm/llvm-project/pull/77487
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