[clang] [clang][AVR] Restrict range of assembly constraint 'G' (PR #76561)
https://github.com/jacquesguan approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/76561 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [clang][RISCV] Change default abi with f extension but without d extension (PR #73489)
https://github.com/jacquesguan closed https://github.com/llvm/llvm-project/pull/73489 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [clang][RISCV] Change default abi with f extension but without d extension (PR #73489)
jacquesguan wrote: > > > I think the conclusion from the LLVM sync-up call was that everyone happy > > > to move in this direction, so please add the release note and we can do a > > > final review. Thanks! > > > > > > Done, added release note. > > > > Thanks! Sorry I wasn't specific about this, but we need a Clang release note > as well. Done, added Clang release note too. https://github.com/llvm/llvm-project/pull/73489 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [clang][RISCV] Change default abi with f extension but without d extension (PR #73489)
https://github.com/jacquesguan updated https://github.com/llvm/llvm-project/pull/73489 >From 4e5442531d5412e83399eb918ba405dcd580b227 Mon Sep 17 00:00:00 2001 From: Jianjian GUAN Date: Mon, 27 Nov 2023 16:14:04 +0800 Subject: [PATCH] [clang][RISCV] Change default abi with f extension but without d extension Now we have default abi lp64 for rv64if and ilp32 for rv32if, which is different with riscv-gnu-toolchain. In https://github.com/riscv-collab/riscv-gnu-toolchain/blob/8e9fb09a0c4b1e566492ee6f42e8c1fa5ef7e0c2/configure#L3385 when have f but not, it prefers lp64f/ilp32f but no soft float. This patch tries to make their behaviors consistent. --- clang/docs/ReleaseNotes.rst| 3 +++ clang/test/Driver/riscv-abi.c | 14 +- clang/test/Driver/riscv-cpus.c | 6 +++--- llvm/docs/ReleaseNotes.rst | 1 + llvm/lib/Support/RISCVISAInfo.cpp | 4 llvm/test/CodeGen/RISCV/callee-saved-fpr32s.ll | 4 ++-- llvm/test/CodeGen/RISCV/calling-conv-half.ll | 4 ++-- .../CodeGen/RISCV/calling-conv-rv32f-ilp32.ll | 2 +- .../CodeGen/RISCV/calling-conv-vector-float.ll | 2 +- .../RISCV/float-bitmanip-dagcombines.ll| 8 llvm/test/CodeGen/RISCV/float-frem.ll | 7 +-- llvm/test/CodeGen/RISCV/float-select-verify.ll | 2 +- .../CodeGen/RISCV/half-bitmanip-dagcombines.ll | 18 +- llvm/test/CodeGen/RISCV/half-fcmp.ll | 8 14 files changed, 45 insertions(+), 38 deletions(-) diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst index 28f9393e28437..317b1f7fdeca9 100644 --- a/clang/docs/ReleaseNotes.rst +++ b/clang/docs/ReleaseNotes.rst @@ -954,6 +954,9 @@ RISC-V Support - Unaligned memory accesses can be toggled by ``-m[no-]unaligned-access`` or the aliases ``-m[no-]strict-align``. +- Default ABI with F but without D was changed to ilp32f for RV32 and to lp64f + for RV64. + CUDA/HIP Language Changes ^ diff --git a/clang/test/Driver/riscv-abi.c b/clang/test/Driver/riscv-abi.c index e67f790e0de0e..16568271564c7 100644 --- a/clang/test/Driver/riscv-abi.c +++ b/clang/test/Driver/riscv-abi.c @@ -4,8 +4,6 @@ // RUN: | FileCheck -check-prefix=CHECK-ILP32 %s // RUN: %clang --target=riscv32-unknown-elf %s -### -march=rv32imc 2>&1 \ // RUN: | FileCheck -check-prefix=CHECK-ILP32 %s -// RUN: %clang --target=riscv32-unknown-elf %s -### -march=rv32imf 2>&1 \ -// RUN: | FileCheck -check-prefix=CHECK-ILP32 %s // RUN: %clang --target=riscv32-unknown-elf -x assembler %s -### 2>&1 \ // RUN: | FileCheck -check-prefix=CHECK-ILP32 %s // RUN: %clang --target=riscv32-unknown-elf -x assembler %s -### \ @@ -24,6 +22,10 @@ // RUN: %clang --target=riscv32-unknown-elf %s -### -march=rv32if -mabi=ilp32f 2>&1 \ // RUN: | FileCheck -check-prefix=CHECK-ILP32F %s +// RUN: %clang --target=riscv32-unknown-elf %s -### -mabi=ilp32f 2>&1 \ +// RUN: | FileCheck -check-prefix=CHECK-ILP32F %s +// RUN: %clang --target=riscv32-unknown-elf %s -### -march=rv32if 2>&1 \ +// RUN: | FileCheck -check-prefix=CHECK-ILP32F %s // CHECK-ILP32F: "-target-abi" "ilp32f" @@ -51,8 +53,6 @@ // RUN: | FileCheck -check-prefix=CHECK-LP64 %s // RUN: %clang --target=riscv64-unknown-elf %s -### -march=rv64imc 2>&1 \ // RUN: | FileCheck -check-prefix=CHECK-LP64 %s -// RUN: %clang --target=riscv64-unknown-elf %s -### -march=rv64imf 2>&1 \ -// RUN: | FileCheck -check-prefix=CHECK-LP64 %s // RUN: %clang --target=riscv64-unknown-elf -x assembler %s -### 2>&1 \ // RUN: | FileCheck -check-prefix=CHECK-LP64 %s // RUN: %clang --target=riscv64-unknown-elf -x assembler %s -### \ @@ -60,7 +60,11 @@ // CHECK-LP64: "-target-abi" "lp64" -// RUN: not %clang --target=riscv64-unknown-elf %s -### -march=rv64f -mabi=lp64f 2>&1 \ +// RUN: %clang --target=riscv64-unknown-elf %s -### -march=rv64if -mabi=lp64f 2>&1 \ +// RUN: | FileCheck -check-prefix=CHECK-LP64F %s +// RUN: %clang --target=riscv64-unknown-elf %s -### -mabi=lp64f 2>&1 \ +// RUN: | FileCheck -check-prefix=CHECK-LP64F %s +// RUN: %clang --target=riscv64-unknown-elf %s -### -march=rv64if 2>&1 \ // RUN: | FileCheck -check-prefix=CHECK-LP64F %s // CHECK-LP64F: "-target-abi" "lp64f" diff --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c index 6c31282d0c8d4..d7fa7c9854a48 100644 --- a/clang/test/Driver/riscv-cpus.c +++ b/clang/test/Driver/riscv-cpus.c @@ -113,7 +113,7 @@ // MCPU-SIFIVE-E24: "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+f" // MCPU-SIFIVE-E24: "-target-feature" "+c" // MCPU-SIFIVE-E24: "-target-feature" "+zicsr" "-target-feature" "+zifencei" -// MCPU-SIFIVE-E24: "-target-abi" "ilp32" +// MCPU-SIFIVE-E24: "-target-abi" "ilp32f" // mcpu with default march // RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=sifive-e34 | FileCheck -check-prefix=MCPU-SIFIVE-E34 %s @@ -121,7 +121,7 @@ //
[llvm] [clang] [clang][RISCV] Change default abi with f extension but without d extension (PR #73489)
jacquesguan wrote: > I think the conclusion from the LLVM sync-up call was that everyone happy to > move in this direction, so please add the release note and we can do a final > review. Thanks! Done, added release note. https://github.com/llvm/llvm-project/pull/73489 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [clang][RISCV] Change default abi with f extension but without d extension (PR #73489)
https://github.com/jacquesguan updated https://github.com/llvm/llvm-project/pull/73489 >From dcc71641695128e117b290cd1e63879e0beeb796 Mon Sep 17 00:00:00 2001 From: Jianjian GUAN Date: Mon, 27 Nov 2023 16:14:04 +0800 Subject: [PATCH] [clang][RISCV] Change default abi with f extension but without d extension Now we have default abi lp64 for rv64if and ilp32 for rv32if, which is different with riscv-gnu-toolchain. In https://github.com/riscv-collab/riscv-gnu-toolchain/blob/8e9fb09a0c4b1e566492ee6f42e8c1fa5ef7e0c2/configure#L3385 when have f but not, it prefers lp64f/ilp32f but no soft float. This patch tries to make their behaviors consistent. --- clang/test/Driver/riscv-abi.c | 14 +- clang/test/Driver/riscv-cpus.c | 6 +++--- llvm/docs/ReleaseNotes.rst | 1 + llvm/lib/Support/RISCVISAInfo.cpp | 4 llvm/test/CodeGen/RISCV/callee-saved-fpr32s.ll | 4 ++-- llvm/test/CodeGen/RISCV/calling-conv-half.ll | 4 ++-- .../CodeGen/RISCV/calling-conv-rv32f-ilp32.ll | 2 +- .../CodeGen/RISCV/calling-conv-vector-float.ll | 2 +- .../RISCV/float-bitmanip-dagcombines.ll| 8 llvm/test/CodeGen/RISCV/float-frem.ll | 7 +-- llvm/test/CodeGen/RISCV/float-select-verify.ll | 2 +- .../CodeGen/RISCV/half-bitmanip-dagcombines.ll | 18 +- llvm/test/CodeGen/RISCV/half-fcmp.ll | 8 13 files changed, 42 insertions(+), 38 deletions(-) diff --git a/clang/test/Driver/riscv-abi.c b/clang/test/Driver/riscv-abi.c index e67f790e0de0e..16568271564c7 100644 --- a/clang/test/Driver/riscv-abi.c +++ b/clang/test/Driver/riscv-abi.c @@ -4,8 +4,6 @@ // RUN: | FileCheck -check-prefix=CHECK-ILP32 %s // RUN: %clang --target=riscv32-unknown-elf %s -### -march=rv32imc 2>&1 \ // RUN: | FileCheck -check-prefix=CHECK-ILP32 %s -// RUN: %clang --target=riscv32-unknown-elf %s -### -march=rv32imf 2>&1 \ -// RUN: | FileCheck -check-prefix=CHECK-ILP32 %s // RUN: %clang --target=riscv32-unknown-elf -x assembler %s -### 2>&1 \ // RUN: | FileCheck -check-prefix=CHECK-ILP32 %s // RUN: %clang --target=riscv32-unknown-elf -x assembler %s -### \ @@ -24,6 +22,10 @@ // RUN: %clang --target=riscv32-unknown-elf %s -### -march=rv32if -mabi=ilp32f 2>&1 \ // RUN: | FileCheck -check-prefix=CHECK-ILP32F %s +// RUN: %clang --target=riscv32-unknown-elf %s -### -mabi=ilp32f 2>&1 \ +// RUN: | FileCheck -check-prefix=CHECK-ILP32F %s +// RUN: %clang --target=riscv32-unknown-elf %s -### -march=rv32if 2>&1 \ +// RUN: | FileCheck -check-prefix=CHECK-ILP32F %s // CHECK-ILP32F: "-target-abi" "ilp32f" @@ -51,8 +53,6 @@ // RUN: | FileCheck -check-prefix=CHECK-LP64 %s // RUN: %clang --target=riscv64-unknown-elf %s -### -march=rv64imc 2>&1 \ // RUN: | FileCheck -check-prefix=CHECK-LP64 %s -// RUN: %clang --target=riscv64-unknown-elf %s -### -march=rv64imf 2>&1 \ -// RUN: | FileCheck -check-prefix=CHECK-LP64 %s // RUN: %clang --target=riscv64-unknown-elf -x assembler %s -### 2>&1 \ // RUN: | FileCheck -check-prefix=CHECK-LP64 %s // RUN: %clang --target=riscv64-unknown-elf -x assembler %s -### \ @@ -60,7 +60,11 @@ // CHECK-LP64: "-target-abi" "lp64" -// RUN: not %clang --target=riscv64-unknown-elf %s -### -march=rv64f -mabi=lp64f 2>&1 \ +// RUN: %clang --target=riscv64-unknown-elf %s -### -march=rv64if -mabi=lp64f 2>&1 \ +// RUN: | FileCheck -check-prefix=CHECK-LP64F %s +// RUN: %clang --target=riscv64-unknown-elf %s -### -mabi=lp64f 2>&1 \ +// RUN: | FileCheck -check-prefix=CHECK-LP64F %s +// RUN: %clang --target=riscv64-unknown-elf %s -### -march=rv64if 2>&1 \ // RUN: | FileCheck -check-prefix=CHECK-LP64F %s // CHECK-LP64F: "-target-abi" "lp64f" diff --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c index 6c31282d0c8d4..d7fa7c9854a48 100644 --- a/clang/test/Driver/riscv-cpus.c +++ b/clang/test/Driver/riscv-cpus.c @@ -113,7 +113,7 @@ // MCPU-SIFIVE-E24: "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+f" // MCPU-SIFIVE-E24: "-target-feature" "+c" // MCPU-SIFIVE-E24: "-target-feature" "+zicsr" "-target-feature" "+zifencei" -// MCPU-SIFIVE-E24: "-target-abi" "ilp32" +// MCPU-SIFIVE-E24: "-target-abi" "ilp32f" // mcpu with default march // RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=sifive-e34 | FileCheck -check-prefix=MCPU-SIFIVE-E34 %s @@ -121,7 +121,7 @@ // MCPU-SIFIVE-E34: "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+f" // MCPU-SIFIVE-E34: "-target-feature" "+c" // MCPU-SIFIVE-E34: "-target-feature" "+zicsr" "-target-feature" "+zifencei" -// MCPU-SIFIVE-E34: "-target-abi" "ilp32" +// MCPU-SIFIVE-E34: "-target-abi" "ilp32f" // mcpu with mabi option // RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=sifive-s21 -mabi=lp64 | FileCheck -check-prefix=MCPU-ABI-SIFIVE-S21 %s @@ -178,7 +178,7 @@ // MCPU-SIFIVE-E76: "-target-feature" "+m" "-target-feature" "+a" "-target-feature"
[llvm] [clang] [clang][RISCV] Change default abi with f extension but without d extension (PR #73489)
@@ -1,4 +1,4 @@ -// Check target CPUs are correctly passed. +·// Check target CPUs are correctly passed. jacquesguan wrote: Fixed https://github.com/llvm/llvm-project/pull/73489 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [clang][RISCV] Change default abi with f extension but without d extension (PR #73489)
https://github.com/jacquesguan edited https://github.com/llvm/llvm-project/pull/73489 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [clang][RISCV] Change default abi when only have f extension but no d extension (PR #73489)
https://github.com/jacquesguan updated https://github.com/llvm/llvm-project/pull/73489 >From ce22351f42b0a641000d1aa4db86f090f9b4e6c8 Mon Sep 17 00:00:00 2001 From: Jianjian GUAN Date: Mon, 27 Nov 2023 16:14:04 +0800 Subject: [PATCH] [clang][RISCV] Change default abi with f extension but without d extension Now we have default abi lp64 for rv64if and ilp32 for rv32if, which is different with riscv-gnu-toolchain. In https://github.com/riscv-collab/riscv-gnu-toolchain/blob/8e9fb09a0c4b1e566492ee6f42e8c1fa5ef7e0c2/configure#L3385 when have f but not, it prefers lp64f/ilp32f but no soft float. This patch tries to make their behaviors consistent. --- clang/test/Driver/riscv-abi.c | 14 +- clang/test/Driver/riscv-cpus.c | 6 +++--- llvm/lib/Support/RISCVISAInfo.cpp | 4 llvm/test/CodeGen/RISCV/callee-saved-fpr32s.ll | 4 ++-- llvm/test/CodeGen/RISCV/calling-conv-half.ll | 4 ++-- .../CodeGen/RISCV/calling-conv-rv32f-ilp32.ll | 2 +- .../CodeGen/RISCV/calling-conv-vector-float.ll | 2 +- .../RISCV/float-bitmanip-dagcombines.ll| 8 llvm/test/CodeGen/RISCV/float-frem.ll | 7 +-- llvm/test/CodeGen/RISCV/float-select-verify.ll | 2 +- .../CodeGen/RISCV/half-bitmanip-dagcombines.ll | 18 +- llvm/test/CodeGen/RISCV/half-fcmp.ll | 8 12 files changed, 41 insertions(+), 38 deletions(-) diff --git a/clang/test/Driver/riscv-abi.c b/clang/test/Driver/riscv-abi.c index e67f790e0de0e..16568271564c7 100644 --- a/clang/test/Driver/riscv-abi.c +++ b/clang/test/Driver/riscv-abi.c @@ -4,8 +4,6 @@ // RUN: | FileCheck -check-prefix=CHECK-ILP32 %s // RUN: %clang --target=riscv32-unknown-elf %s -### -march=rv32imc 2>&1 \ // RUN: | FileCheck -check-prefix=CHECK-ILP32 %s -// RUN: %clang --target=riscv32-unknown-elf %s -### -march=rv32imf 2>&1 \ -// RUN: | FileCheck -check-prefix=CHECK-ILP32 %s // RUN: %clang --target=riscv32-unknown-elf -x assembler %s -### 2>&1 \ // RUN: | FileCheck -check-prefix=CHECK-ILP32 %s // RUN: %clang --target=riscv32-unknown-elf -x assembler %s -### \ @@ -24,6 +22,10 @@ // RUN: %clang --target=riscv32-unknown-elf %s -### -march=rv32if -mabi=ilp32f 2>&1 \ // RUN: | FileCheck -check-prefix=CHECK-ILP32F %s +// RUN: %clang --target=riscv32-unknown-elf %s -### -mabi=ilp32f 2>&1 \ +// RUN: | FileCheck -check-prefix=CHECK-ILP32F %s +// RUN: %clang --target=riscv32-unknown-elf %s -### -march=rv32if 2>&1 \ +// RUN: | FileCheck -check-prefix=CHECK-ILP32F %s // CHECK-ILP32F: "-target-abi" "ilp32f" @@ -51,8 +53,6 @@ // RUN: | FileCheck -check-prefix=CHECK-LP64 %s // RUN: %clang --target=riscv64-unknown-elf %s -### -march=rv64imc 2>&1 \ // RUN: | FileCheck -check-prefix=CHECK-LP64 %s -// RUN: %clang --target=riscv64-unknown-elf %s -### -march=rv64imf 2>&1 \ -// RUN: | FileCheck -check-prefix=CHECK-LP64 %s // RUN: %clang --target=riscv64-unknown-elf -x assembler %s -### 2>&1 \ // RUN: | FileCheck -check-prefix=CHECK-LP64 %s // RUN: %clang --target=riscv64-unknown-elf -x assembler %s -### \ @@ -60,7 +60,11 @@ // CHECK-LP64: "-target-abi" "lp64" -// RUN: not %clang --target=riscv64-unknown-elf %s -### -march=rv64f -mabi=lp64f 2>&1 \ +// RUN: %clang --target=riscv64-unknown-elf %s -### -march=rv64if -mabi=lp64f 2>&1 \ +// RUN: | FileCheck -check-prefix=CHECK-LP64F %s +// RUN: %clang --target=riscv64-unknown-elf %s -### -mabi=lp64f 2>&1 \ +// RUN: | FileCheck -check-prefix=CHECK-LP64F %s +// RUN: %clang --target=riscv64-unknown-elf %s -### -march=rv64if 2>&1 \ // RUN: | FileCheck -check-prefix=CHECK-LP64F %s // CHECK-LP64F: "-target-abi" "lp64f" diff --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c index 6c31282d0c8d4..d7fa7c9854a48 100644 --- a/clang/test/Driver/riscv-cpus.c +++ b/clang/test/Driver/riscv-cpus.c @@ -113,7 +113,7 @@ // MCPU-SIFIVE-E24: "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+f" // MCPU-SIFIVE-E24: "-target-feature" "+c" // MCPU-SIFIVE-E24: "-target-feature" "+zicsr" "-target-feature" "+zifencei" -// MCPU-SIFIVE-E24: "-target-abi" "ilp32" +// MCPU-SIFIVE-E24: "-target-abi" "ilp32f" // mcpu with default march // RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=sifive-e34 | FileCheck -check-prefix=MCPU-SIFIVE-E34 %s @@ -121,7 +121,7 @@ // MCPU-SIFIVE-E34: "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+f" // MCPU-SIFIVE-E34: "-target-feature" "+c" // MCPU-SIFIVE-E34: "-target-feature" "+zicsr" "-target-feature" "+zifencei" -// MCPU-SIFIVE-E34: "-target-abi" "ilp32" +// MCPU-SIFIVE-E34: "-target-abi" "ilp32f" // mcpu with mabi option // RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=sifive-s21 -mabi=lp64 | FileCheck -check-prefix=MCPU-ABI-SIFIVE-S21 %s @@ -178,7 +178,7 @@ // MCPU-SIFIVE-E76: "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+f" // MCPU-SIFIVE-E76: "-target-feature" "+c" //
[llvm] [clang] [clang][RISCV] Change default abi when only have f extension but no d extension (PR #73489)
jacquesguan wrote: soft ping... Any more advice? https://github.com/llvm/llvm-project/pull/73489 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [clang] [clang][RISCV] Change default abi when only have f extension but no d extension (PR #73489)
https://github.com/jacquesguan updated https://github.com/llvm/llvm-project/pull/73489 >From daaa69ada14be2b1c907acf961e3ceb4f355f927 Mon Sep 17 00:00:00 2001 From: Jianjian GUAN Date: Mon, 27 Nov 2023 16:14:04 +0800 Subject: [PATCH] [clang][RISCV] Change default abi when only have f extension but no d extension Now we have default abi lp64 for rv64if and ilp32 for rv32if, which is different with riscv-gnu-toolchain. In https://github.com/riscv-collab/riscv-gnu-toolchain/blob/8e9fb09a0c4b1e566492ee6f42e8c1fa5ef7e0c2/configure#L3385 when have f but not, it prefers lp64f/ilp32f but no soft float. This patch tries to make their behaviors consistent. --- clang/test/Driver/riscv-abi.c | 14 +- clang/test/Driver/riscv-cpus.c | 8 llvm/lib/Support/RISCVISAInfo.cpp | 4 llvm/test/CodeGen/RISCV/callee-saved-fpr32s.ll | 4 ++-- llvm/test/CodeGen/RISCV/calling-conv-half.ll | 4 ++-- .../CodeGen/RISCV/calling-conv-rv32f-ilp32.ll | 2 +- .../CodeGen/RISCV/calling-conv-vector-float.ll | 2 +- .../RISCV/float-bitmanip-dagcombines.ll| 8 llvm/test/CodeGen/RISCV/float-frem.ll | 7 +-- llvm/test/CodeGen/RISCV/float-select-verify.ll | 2 +- .../CodeGen/RISCV/half-bitmanip-dagcombines.ll | 18 +- llvm/test/CodeGen/RISCV/half-fcmp.ll | 8 12 files changed, 42 insertions(+), 39 deletions(-) diff --git a/clang/test/Driver/riscv-abi.c b/clang/test/Driver/riscv-abi.c index e67f790e0de0e59..16568271564c797 100644 --- a/clang/test/Driver/riscv-abi.c +++ b/clang/test/Driver/riscv-abi.c @@ -4,8 +4,6 @@ // RUN: | FileCheck -check-prefix=CHECK-ILP32 %s // RUN: %clang --target=riscv32-unknown-elf %s -### -march=rv32imc 2>&1 \ // RUN: | FileCheck -check-prefix=CHECK-ILP32 %s -// RUN: %clang --target=riscv32-unknown-elf %s -### -march=rv32imf 2>&1 \ -// RUN: | FileCheck -check-prefix=CHECK-ILP32 %s // RUN: %clang --target=riscv32-unknown-elf -x assembler %s -### 2>&1 \ // RUN: | FileCheck -check-prefix=CHECK-ILP32 %s // RUN: %clang --target=riscv32-unknown-elf -x assembler %s -### \ @@ -24,6 +22,10 @@ // RUN: %clang --target=riscv32-unknown-elf %s -### -march=rv32if -mabi=ilp32f 2>&1 \ // RUN: | FileCheck -check-prefix=CHECK-ILP32F %s +// RUN: %clang --target=riscv32-unknown-elf %s -### -mabi=ilp32f 2>&1 \ +// RUN: | FileCheck -check-prefix=CHECK-ILP32F %s +// RUN: %clang --target=riscv32-unknown-elf %s -### -march=rv32if 2>&1 \ +// RUN: | FileCheck -check-prefix=CHECK-ILP32F %s // CHECK-ILP32F: "-target-abi" "ilp32f" @@ -51,8 +53,6 @@ // RUN: | FileCheck -check-prefix=CHECK-LP64 %s // RUN: %clang --target=riscv64-unknown-elf %s -### -march=rv64imc 2>&1 \ // RUN: | FileCheck -check-prefix=CHECK-LP64 %s -// RUN: %clang --target=riscv64-unknown-elf %s -### -march=rv64imf 2>&1 \ -// RUN: | FileCheck -check-prefix=CHECK-LP64 %s // RUN: %clang --target=riscv64-unknown-elf -x assembler %s -### 2>&1 \ // RUN: | FileCheck -check-prefix=CHECK-LP64 %s // RUN: %clang --target=riscv64-unknown-elf -x assembler %s -### \ @@ -60,7 +60,11 @@ // CHECK-LP64: "-target-abi" "lp64" -// RUN: not %clang --target=riscv64-unknown-elf %s -### -march=rv64f -mabi=lp64f 2>&1 \ +// RUN: %clang --target=riscv64-unknown-elf %s -### -march=rv64if -mabi=lp64f 2>&1 \ +// RUN: | FileCheck -check-prefix=CHECK-LP64F %s +// RUN: %clang --target=riscv64-unknown-elf %s -### -mabi=lp64f 2>&1 \ +// RUN: | FileCheck -check-prefix=CHECK-LP64F %s +// RUN: %clang --target=riscv64-unknown-elf %s -### -march=rv64if 2>&1 \ // RUN: | FileCheck -check-prefix=CHECK-LP64F %s // CHECK-LP64F: "-target-abi" "lp64f" diff --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c index 6c31282d0c8d49c..bfef54de183ac5e 100644 --- a/clang/test/Driver/riscv-cpus.c +++ b/clang/test/Driver/riscv-cpus.c @@ -1,4 +1,4 @@ -// Check target CPUs are correctly passed. +·// Check target CPUs are correctly passed. // RUN: %clang --target=riscv32 -### -c %s 2>&1 -mcpu=rocket-rv32 | FileCheck -check-prefix=MCPU-ROCKET32 %s // MCPU-ROCKET32: "-nostdsysteminc" "-target-cpu" "rocket-rv32" @@ -113,7 +113,7 @@ // MCPU-SIFIVE-E24: "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+f" // MCPU-SIFIVE-E24: "-target-feature" "+c" // MCPU-SIFIVE-E24: "-target-feature" "+zicsr" "-target-feature" "+zifencei" -// MCPU-SIFIVE-E24: "-target-abi" "ilp32" +// MCPU-SIFIVE-E24: "-target-abi" "ilp32f" // mcpu with default march // RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=sifive-e34 | FileCheck -check-prefix=MCPU-SIFIVE-E34 %s @@ -121,7 +121,7 @@ // MCPU-SIFIVE-E34: "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+f" // MCPU-SIFIVE-E34: "-target-feature" "+c" // MCPU-SIFIVE-E34: "-target-feature" "+zicsr" "-target-feature" "+zifencei" -// MCPU-SIFIVE-E34: "-target-abi" "ilp32" +// MCPU-SIFIVE-E34: "-target-abi" "ilp32f" // mcpu with
[llvm] [clang] [clang][RISCV] Change default abi when only have f extension but no d extension (PR #73489)
https://github.com/jacquesguan updated https://github.com/llvm/llvm-project/pull/73489 >From e03da61c3ad76b76a99639ad1735ec556aaec10b Mon Sep 17 00:00:00 2001 From: Jianjian GUAN Date: Mon, 27 Nov 2023 16:14:04 +0800 Subject: [PATCH] [clang][RISCV] Change default abi when only have f extension but no d extension Now we have default abi lp64 for rv64if and ilp32 for rv32if, which is different with riscv-gnu-toolchain. In https://github.com/riscv-collab/riscv-gnu-toolchain/blob/8e9fb09a0c4b1e566492ee6f42e8c1fa5ef7e0c2/configure#L3385 when have f but not, it prefers lp64f/ilp32f but no soft float. This patch tries to make their behaviors consistent. --- clang/test/Driver/riscv-abi.c | 14 +- clang/test/Driver/riscv-cpus.c| 8 llvm/lib/Support/RISCVISAInfo.cpp | 4 3 files changed, 17 insertions(+), 9 deletions(-) diff --git a/clang/test/Driver/riscv-abi.c b/clang/test/Driver/riscv-abi.c index e67f790e0de0e59..16568271564c797 100644 --- a/clang/test/Driver/riscv-abi.c +++ b/clang/test/Driver/riscv-abi.c @@ -4,8 +4,6 @@ // RUN: | FileCheck -check-prefix=CHECK-ILP32 %s // RUN: %clang --target=riscv32-unknown-elf %s -### -march=rv32imc 2>&1 \ // RUN: | FileCheck -check-prefix=CHECK-ILP32 %s -// RUN: %clang --target=riscv32-unknown-elf %s -### -march=rv32imf 2>&1 \ -// RUN: | FileCheck -check-prefix=CHECK-ILP32 %s // RUN: %clang --target=riscv32-unknown-elf -x assembler %s -### 2>&1 \ // RUN: | FileCheck -check-prefix=CHECK-ILP32 %s // RUN: %clang --target=riscv32-unknown-elf -x assembler %s -### \ @@ -24,6 +22,10 @@ // RUN: %clang --target=riscv32-unknown-elf %s -### -march=rv32if -mabi=ilp32f 2>&1 \ // RUN: | FileCheck -check-prefix=CHECK-ILP32F %s +// RUN: %clang --target=riscv32-unknown-elf %s -### -mabi=ilp32f 2>&1 \ +// RUN: | FileCheck -check-prefix=CHECK-ILP32F %s +// RUN: %clang --target=riscv32-unknown-elf %s -### -march=rv32if 2>&1 \ +// RUN: | FileCheck -check-prefix=CHECK-ILP32F %s // CHECK-ILP32F: "-target-abi" "ilp32f" @@ -51,8 +53,6 @@ // RUN: | FileCheck -check-prefix=CHECK-LP64 %s // RUN: %clang --target=riscv64-unknown-elf %s -### -march=rv64imc 2>&1 \ // RUN: | FileCheck -check-prefix=CHECK-LP64 %s -// RUN: %clang --target=riscv64-unknown-elf %s -### -march=rv64imf 2>&1 \ -// RUN: | FileCheck -check-prefix=CHECK-LP64 %s // RUN: %clang --target=riscv64-unknown-elf -x assembler %s -### 2>&1 \ // RUN: | FileCheck -check-prefix=CHECK-LP64 %s // RUN: %clang --target=riscv64-unknown-elf -x assembler %s -### \ @@ -60,7 +60,11 @@ // CHECK-LP64: "-target-abi" "lp64" -// RUN: not %clang --target=riscv64-unknown-elf %s -### -march=rv64f -mabi=lp64f 2>&1 \ +// RUN: %clang --target=riscv64-unknown-elf %s -### -march=rv64if -mabi=lp64f 2>&1 \ +// RUN: | FileCheck -check-prefix=CHECK-LP64F %s +// RUN: %clang --target=riscv64-unknown-elf %s -### -mabi=lp64f 2>&1 \ +// RUN: | FileCheck -check-prefix=CHECK-LP64F %s +// RUN: %clang --target=riscv64-unknown-elf %s -### -march=rv64if 2>&1 \ // RUN: | FileCheck -check-prefix=CHECK-LP64F %s // CHECK-LP64F: "-target-abi" "lp64f" diff --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c index 6c31282d0c8d49c..bfef54de183ac5e 100644 --- a/clang/test/Driver/riscv-cpus.c +++ b/clang/test/Driver/riscv-cpus.c @@ -1,4 +1,4 @@ -// Check target CPUs are correctly passed. +·// Check target CPUs are correctly passed. // RUN: %clang --target=riscv32 -### -c %s 2>&1 -mcpu=rocket-rv32 | FileCheck -check-prefix=MCPU-ROCKET32 %s // MCPU-ROCKET32: "-nostdsysteminc" "-target-cpu" "rocket-rv32" @@ -113,7 +113,7 @@ // MCPU-SIFIVE-E24: "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+f" // MCPU-SIFIVE-E24: "-target-feature" "+c" // MCPU-SIFIVE-E24: "-target-feature" "+zicsr" "-target-feature" "+zifencei" -// MCPU-SIFIVE-E24: "-target-abi" "ilp32" +// MCPU-SIFIVE-E24: "-target-abi" "ilp32f" // mcpu with default march // RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=sifive-e34 | FileCheck -check-prefix=MCPU-SIFIVE-E34 %s @@ -121,7 +121,7 @@ // MCPU-SIFIVE-E34: "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+f" // MCPU-SIFIVE-E34: "-target-feature" "+c" // MCPU-SIFIVE-E34: "-target-feature" "+zicsr" "-target-feature" "+zifencei" -// MCPU-SIFIVE-E34: "-target-abi" "ilp32" +// MCPU-SIFIVE-E34: "-target-abi" "ilp32f" // mcpu with mabi option // RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=sifive-s21 -mabi=lp64 | FileCheck -check-prefix=MCPU-ABI-SIFIVE-S21 %s @@ -178,7 +178,7 @@ // MCPU-SIFIVE-E76: "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+f" // MCPU-SIFIVE-E76: "-target-feature" "+c" // MCPU-SIFIVE-E76: "-target-feature" "+zicsr" "-target-feature" "+zifencei" -// MCPU-SIFIVE-E76: "-target-abi" "ilp32" +// MCPU-SIFIVE-E76: "-target-abi" "ilp32f" // mcpu with mabi option // RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=sifive-u74 -mabi=lp64 | FileCheck
[clang] [llvm] [clang][RISCV] Change default abi when only have f extension but no d extension (PR #73489)
https://github.com/jacquesguan created
https://github.com/llvm/llvm-project/pull/73489
Now we have default abi lp64 for rv64if and ilp32 for rv32if, which is
different with riscv-gnu-toolchain. In
https://github.com/riscv-collab/riscv-gnu-toolchain/blob/8e9fb09a0c4b1e566492ee6f42e8c1fa5ef7e0c2/configure#L3385
when have f and not d, it prefers lp64f/ilp32f but no soft float. This patch
tries to make their behaviors consistent.
>From b41c0a913a4ef81e650762a5ede5ae702860f001 Mon Sep 17 00:00:00 2001
From: Jianjian GUAN
Date: Mon, 27 Nov 2023 16:14:04 +0800
Subject: [PATCH] [clang][RISCV] Change default abi when only have f extension
but no d extension
Now we have default abi lp64 for rv64if and ilp32 for rv32if, which is
different with riscv-gnu-toolchain.
In
https://github.com/riscv-collab/riscv-gnu-toolchain/blob/8e9fb09a0c4b1e566492ee6f42e8c1fa5ef7e0c2/configure#L3385
when have f but not, it prefers lp64f/ilp32f but no soft float. This patch
tries to make their behaviors consistent.
---
clang/test/Driver/riscv-abi.c | 14 +-
llvm/lib/Support/RISCVISAInfo.cpp | 4
2 files changed, 13 insertions(+), 5 deletions(-)
diff --git a/clang/test/Driver/riscv-abi.c b/clang/test/Driver/riscv-abi.c
index e67f790e0de0e59..16568271564c797 100644
--- a/clang/test/Driver/riscv-abi.c
+++ b/clang/test/Driver/riscv-abi.c
@@ -4,8 +4,6 @@
// RUN: | FileCheck -check-prefix=CHECK-ILP32 %s
// RUN: %clang --target=riscv32-unknown-elf %s -### -march=rv32imc 2>&1 \
// RUN: | FileCheck -check-prefix=CHECK-ILP32 %s
-// RUN: %clang --target=riscv32-unknown-elf %s -### -march=rv32imf 2>&1 \
-// RUN: | FileCheck -check-prefix=CHECK-ILP32 %s
// RUN: %clang --target=riscv32-unknown-elf -x assembler %s -### 2>&1 \
// RUN: | FileCheck -check-prefix=CHECK-ILP32 %s
// RUN: %clang --target=riscv32-unknown-elf -x assembler %s -### \
@@ -24,6 +22,10 @@
// RUN: %clang --target=riscv32-unknown-elf %s -### -march=rv32if -mabi=ilp32f
2>&1 \
// RUN: | FileCheck -check-prefix=CHECK-ILP32F %s
+// RUN: %clang --target=riscv32-unknown-elf %s -### -mabi=ilp32f 2>&1 \
+// RUN: | FileCheck -check-prefix=CHECK-ILP32F %s
+// RUN: %clang --target=riscv32-unknown-elf %s -### -march=rv32if 2>&1 \
+// RUN: | FileCheck -check-prefix=CHECK-ILP32F %s
// CHECK-ILP32F: "-target-abi" "ilp32f"
@@ -51,8 +53,6 @@
// RUN: | FileCheck -check-prefix=CHECK-LP64 %s
// RUN: %clang --target=riscv64-unknown-elf %s -### -march=rv64imc 2>&1 \
// RUN: | FileCheck -check-prefix=CHECK-LP64 %s
-// RUN: %clang --target=riscv64-unknown-elf %s -### -march=rv64imf 2>&1 \
-// RUN: | FileCheck -check-prefix=CHECK-LP64 %s
// RUN: %clang --target=riscv64-unknown-elf -x assembler %s -### 2>&1 \
// RUN: | FileCheck -check-prefix=CHECK-LP64 %s
// RUN: %clang --target=riscv64-unknown-elf -x assembler %s -### \
@@ -60,7 +60,11 @@
// CHECK-LP64: "-target-abi" "lp64"
-// RUN: not %clang --target=riscv64-unknown-elf %s -### -march=rv64f
-mabi=lp64f 2>&1 \
+// RUN: %clang --target=riscv64-unknown-elf %s -### -march=rv64if -mabi=lp64f
2>&1 \
+// RUN: | FileCheck -check-prefix=CHECK-LP64F %s
+// RUN: %clang --target=riscv64-unknown-elf %s -### -mabi=lp64f 2>&1 \
+// RUN: | FileCheck -check-prefix=CHECK-LP64F %s
+// RUN: %clang --target=riscv64-unknown-elf %s -### -march=rv64if 2>&1 \
// RUN: | FileCheck -check-prefix=CHECK-LP64F %s
// CHECK-LP64F: "-target-abi" "lp64f"
diff --git a/llvm/lib/Support/RISCVISAInfo.cpp
b/llvm/lib/Support/RISCVISAInfo.cpp
index 6322748430063ce..24d0d40cbc74ebc 100644
--- a/llvm/lib/Support/RISCVISAInfo.cpp
+++ b/llvm/lib/Support/RISCVISAInfo.cpp
@@ -1292,12 +1292,16 @@ StringRef RISCVISAInfo::computeDefaultABI() const {
if (XLen == 32) {
if (hasExtension("d"))
return "ilp32d";
+if (hasExtension("f"))
+ return "ilp32f";
if (hasExtension("e"))
return "ilp32e";
return "ilp32";
} else if (XLen == 64) {
if (hasExtension("d"))
return "lp64d";
+if (hasExtension("f"))
+ return "lp64f";
if (hasExtension("e"))
return "lp64e";
return "lp64";
___
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[clang] [RISCV] Use Float type instead of Half type for Fixed RVV vector type mangling (PR #73091)
https://github.com/jacquesguan closed https://github.com/llvm/llvm-project/pull/73091 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [RISCV] Use Float type instead of Half type for Fixed RVV vector type mangling (PR #73091)
jacquesguan wrote: > test? Done, add test case. https://github.com/llvm/llvm-project/pull/73091 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [RISCV] Use Float type instead of Half type for Fixed RVV vector type mangling (PR #73091)
https://github.com/jacquesguan updated
https://github.com/llvm/llvm-project/pull/73091
>From 5712baa1f74acec9a482d110e0a6bf9638006409 Mon Sep 17 00:00:00 2001
From: Jianjian GUAN
Date: Wed, 22 Nov 2023 14:34:49 +0800
Subject: [PATCH] [RISCV] Use Float type instead of Half type for Fixed RVV
vector type mangling
---
clang/lib/AST/ItaniumMangle.cpp | 2 +-
.../riscv-mangle-rvv-fixed-vectors.cpp| 85 +++
2 files changed, 71 insertions(+), 16 deletions(-)
diff --git a/clang/lib/AST/ItaniumMangle.cpp b/clang/lib/AST/ItaniumMangle.cpp
index 2a62ac0175afb72..b1678479888eb77 100644
--- a/clang/lib/AST/ItaniumMangle.cpp
+++ b/clang/lib/AST/ItaniumMangle.cpp
@@ -4029,7 +4029,7 @@ void CXXNameMangler::mangleRISCVFixedRVVVectorType(const
VectorType *T) {
case BuiltinType::ULong:
TypeNameOS << "uint64";
break;
- case BuiltinType::Half:
+ case BuiltinType::Float16:
TypeNameOS << "float16";
break;
case BuiltinType::Float:
diff --git a/clang/test/CodeGenCXX/riscv-mangle-rvv-fixed-vectors.cpp
b/clang/test/CodeGenCXX/riscv-mangle-rvv-fixed-vectors.cpp
index 98fb27b704fd81d..32bd49f4ff725db 100644
--- a/clang/test/CodeGenCXX/riscv-mangle-rvv-fixed-vectors.cpp
+++ b/clang/test/CodeGenCXX/riscv-mangle-rvv-fixed-vectors.cpp
@@ -1,23 +1,23 @@
// RUN: %clang_cc1 -triple riscv64-none-linux-gnu %s -emit-llvm -o - \
-// RUN: -target-feature +f -target-feature +d \
-// RUN: -target-feature +zve64d -mvscale-min=1 -mvscale-max=1 \
-// RUN: | FileCheck %s --check-prefix=CHECK-64
+// RUN: -target-feature +f -target-feature +d -target-feature +zfh \
+// RUN: -target-feature +zve64d -target-feature +zvfh -mvscale-min=1 \
+// RUN: -mvscale-max=1 | FileCheck %s --check-prefix=CHECK-64
// RUN: %clang_cc1 -triple riscv64-none-linux-gnu %s -emit-llvm -o - \
-// RUN: -target-feature +f -target-feature +d \
-// RUN: -target-feature +zve64d -mvscale-min=2 -mvscale-max=2 \
-// RUN: | FileCheck %s --check-prefix=CHECK-128
+// RUN: -target-feature +f -target-feature +d -target-feature +zfh \
+// RUN: -target-feature +zve64d -target-feature +zvfh -mvscale-min=2 \
+// RUN: -mvscale-max=2 | FileCheck %s --check-prefix=CHECK-128
// RUN: %clang_cc1 -triple riscv64-none-linux-gnu %s -emit-llvm -o - \
-// RUN: -target-feature +f -target-feature +d \
-// RUN: -target-feature +zve64d -mvscale-min=4 -mvscale-max=4 \
-// RUN: | FileCheck %s --check-prefix=CHECK-256
+// RUN: -target-feature +f -target-feature +d -target-feature +zfh \
+// RUN: -target-feature +zve64d -target-feature +zvfh -mvscale-min=4 \
+// RUN: -mvscale-max=4 | FileCheck %s --check-prefix=CHECK-256
// RUN: %clang_cc1 -triple riscv64-none-linux-gnu %s -emit-llvm -o - \
-// RUN: -target-feature +f -target-feature +d \
-// RUN: -target-feature +zve64d -mvscale-min=8 -mvscale-max=8 \
-// RUN: | FileCheck %s --check-prefix=CHECK-512
+// RUN: -target-feature +f -target-feature +d -target-feature +zfh \
+// RUN: -target-feature +zve64d -target-feature +zvfh -mvscale-min=8 \
+// RUN: -mvscale-max=8 | FileCheck %s --check-prefix=CHECK-512
// RUN: %clang_cc1 -triple riscv64-none-linux-gnu %s -emit-llvm -o - \
-// RUN: -target-feature +f -target-feature +d \
-// RUN: -target-feature +zve64d -mvscale-min=16 -mvscale-max=16 \
-// RUN: | FileCheck %s --check-prefix=CHECK-1024
+// RUN: -target-feature +f -target-feature +d -target-feature +zfh \
+// RUN: -target-feature +zve64d -target-feature +zvfh -mvscale-min=16 \
+// RUN: -mvscale-max=16 | FileCheck %s --check-prefix=CHECK-1024
typedef __rvv_int8mf8_t vint8mf8_t;
typedef __rvv_uint8mf8_t vuint8mf8_t;
@@ -26,6 +26,7 @@ typedef __rvv_int8mf4_t vint8mf4_t;
typedef __rvv_uint8mf4_t vuint8mf4_t;
typedef __rvv_int16mf4_t vint16mf4_t;
typedef __rvv_uint16mf4_t vuint16mf4_t;
+typedef __rvv_float16mf4_t vfloat16mf4_t;
typedef __rvv_int8mf2_t vint8mf2_t;
typedef __rvv_uint8mf2_t vuint8mf2_t;
@@ -33,6 +34,7 @@ typedef __rvv_int16mf2_t vint16mf2_t;
typedef __rvv_uint16mf2_t vuint16mf2_t;
typedef __rvv_int32mf2_t vint32mf2_t;
typedef __rvv_uint32mf2_t vuint32mf2_t;
+typedef __rvv_float16mf2_t vfloat16mf2_t;
typedef __rvv_float32mf2_t vfloat32mf2_t;
typedef __rvv_int8m1_t vint8m1_t;
@@ -43,6 +45,7 @@ typedef __rvv_int32m1_t vint32m1_t;
typedef __rvv_uint32m1_t vuint32m1_t;
typedef __rvv_int64m1_t vint64m1_t;
typedef __rvv_uint64m1_t vuint64m1_t;
+typedef __rvv_float16m1_t vfloat16m1_t;
typedef __rvv_float32m1_t vfloat32m1_t;
typedef __rvv_float64m1_t vfloat64m1_t;
@@ -54,6 +57,7 @@ typedef __rvv_int32m2_t vint32m2_t;
typedef __rvv_uint32m2_t vuint32m2_t;
typedef __rvv_int64m2_t vint64m2_t;
typedef __rvv_uint64m2_t vuint64m2_t;
+typedef __rvv_float16m2_t vfloat16m2_t;
typedef __rvv_float32m2_t vfloat32m2_t;
typedef __rvv_float64m2_t vfloat64m2_t;
@@ -65,6 +69,7 @@ typedef __rvv_int32m4_t vint32m4_t;
typedef __rvv_uint32m4_t vuint32m4_t;
typedef __rvv_int64m4_t vint64m4_t;
typedef __rvv_uint64m4_t vuint64m4_t;
+typedef
[clang] [RISCV] Use Float type instead of Half type for Fixed RVV vector type mangling (PR #73091)
https://github.com/jacquesguan created
https://github.com/llvm/llvm-project/pull/73091
None
>From f785a0a175f509dbc72e11c13eb5eb6f6eaebb43 Mon Sep 17 00:00:00 2001
From: Jianjian GUAN
Date: Wed, 22 Nov 2023 14:34:49 +0800
Subject: [PATCH] [RISCV] Use Float type instead of Half type for Fixed RVV
vector type mangling
---
clang/lib/AST/ItaniumMangle.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/clang/lib/AST/ItaniumMangle.cpp b/clang/lib/AST/ItaniumMangle.cpp
index 2a62ac0175afb72..b1678479888eb77 100644
--- a/clang/lib/AST/ItaniumMangle.cpp
+++ b/clang/lib/AST/ItaniumMangle.cpp
@@ -4029,7 +4029,7 @@ void CXXNameMangler::mangleRISCVFixedRVVVectorType(const
VectorType *T) {
case BuiltinType::ULong:
TypeNameOS << "uint64";
break;
- case BuiltinType::Half:
+ case BuiltinType::Float16:
TypeNameOS << "float16";
break;
case BuiltinType::Float:
___
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[clang] [clang][driver] Add avr-libc's default linker script to lld (PR #68507)
https://github.com/jacquesguan approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/68507 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [clang][RISCV] Fix the condition of checking signature in getIndex (PR #67403)
https://github.com/jacquesguan closed https://github.com/llvm/llvm-project/pull/67403 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [clang][driver] Support option '-r' for target AVR (PR #68484)
https://github.com/jacquesguan approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/68484 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [clang][RISCV] Fix the condition of checking signature in getIndex (PR #67403)
https://github.com/jacquesguan created
https://github.com/llvm/llvm-project/pull/67403
The current condition causes assert failing if try to add a new vendor vector
file which only contains the same type signature.
>From 3ad50442210c7303f0ac55339db778aa777532c8 Mon Sep 17 00:00:00 2001
From: Jianjian GUAN
Date: Tue, 26 Sep 2023 16:32:14 +0800
Subject: [PATCH] [clang][RISCV] Fix the condition of checking signature in
getIndex
The current condition causes assert failing if try to add a new vendor vector
file which only contains the same type signature.
---
clang/utils/TableGen/RISCVVEmitter.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/clang/utils/TableGen/RISCVVEmitter.cpp
b/clang/utils/TableGen/RISCVVEmitter.cpp
index 41025926058ed07..c08e48b3f44dfe3 100644
--- a/clang/utils/TableGen/RISCVVEmitter.cpp
+++ b/clang/utils/TableGen/RISCVVEmitter.cpp
@@ -290,7 +290,7 @@ unsigned
SemaSignatureTable::getIndex(ArrayRef Signature) {
return 0;
// Checking Signature already in table or not.
- if (Signature.size() < SignatureTable.size()) {
+ if (Signature.size() <= SignatureTable.size()) {
size_t Bound = SignatureTable.size() - Signature.size() + 1;
for (size_t Index = 0; Index < Bound; ++Index) {
if (equal(Signature.begin(), Signature.end(),
___
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[clang] [RISCV] Fix wrong implication for zvknhb. (PR #66860)
@@ -599,15 +599,21 @@ def HasStdExtZvkned : Predicate<"Subtarget->hasStdExtZvkned()">, def FeatureStdExtZvknha : SubtargetFeature<"experimental-zvknha", "HasStdExtZvknha", "true", "'Zvknha' (Vector SHA-2 (SHA-256 only))">; - -def FeatureStdExtZvknhb -: SubtargetFeature<"experimental-zvknhb", "HasStdExtZvknhb", "true", - "'Zvknhb' (Vector SHA-2 (SHA-256 and SHA-512))", - [FeatureStdExtZvknha]>; def HasStdExtZvknha : Predicate<"Subtarget->hasStdExtZvknha()">, AssemblerPredicate<(all_of FeatureStdExtZvknha), "'Zvknha' (Vector SHA-2 (SHA-256 only))">; +def FeatureStdExtZvknhb +: SubtargetFeature<"experimental-zvknhb", "HasStdExtZvknhb", "true", + "'Zvknhb' (Vector SHA-2 (SHA-256 and SHA-512))">; jacquesguan wrote: I think that Zvknhb requires Zve64x https://github.com/llvm/llvm-project/pull/66860 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [RISCV] Add missing V extensions for zvk-invalid-features.c (PR #66875)
https://github.com/jacquesguan approved this pull request. https://github.com/llvm/llvm-project/pull/66875 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [RISCV] Add missing V extensions for zvk-invalid-features.c (PR #66875)
jacquesguan wrote: LGTM https://github.com/llvm/llvm-project/pull/66875 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [RISCV] Update Zicntr and Zihpm to version 2p0 (PR #66323)
jacquesguan wrote: > Sorry, that was a mis-statement. There are two counter extensions you are > bumping. > > Anyway, rewording the commit message is a nit from me. OK, I retitle the commit. https://github.com/llvm/llvm-project/pull/66323 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [RISCV] Update counters to version 2p0 (PR #66323)
jacquesguan wrote: > Your commit bumps both the counter and timer extension, which makes your > commit message inaccurate. I think Counters in RISCV ISA include both "Zicntr" and "Zihpm", https://github.com/riscv/riscv-isa-manual/blob/main/src/counters.adoc. https://github.com/llvm/llvm-project/pull/66323 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] 4d2536c - [RISCV] Enable more builtin for zvfhmin without zvfh
Author: Jianjian GUAN
Date: 2023-09-08T10:55:17+08:00
New Revision: 4d2536c82fc426f0e622a09c0a3e048a0c734f3d
URL:
https://github.com/llvm/llvm-project/commit/4d2536c82fc426f0e622a09c0a3e048a0c734f3d
DIFF:
https://github.com/llvm/llvm-project/commit/4d2536c82fc426f0e622a09c0a3e048a0c734f3d.diff
LOG: [RISCV] Enable more builtin for zvfhmin without zvfh
This patch enables some fp16 vector type builtins that don't use fp arithmetic
instruction for zvfhmin without zvfh.
Include following builtins:
vector load/store,
vector reinterpret,
vmerge_vvm,
vmv_v.
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D151869
Added:
Modified:
clang/include/clang/Basic/riscv_vector.td
clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin.c
Removed:
diff --git a/clang/include/clang/Basic/riscv_vector.td
b/clang/include/clang/Basic/riscv_vector.td
index e8040a22d5862a9..e52ac661a61333a 100644
--- a/clang/include/clang/Basic/riscv_vector.td
+++ b/clang/include/clang/Basic/riscv_vector.td
@@ -577,7 +577,9 @@ multiclass RVVIndexedLoad {
foreach eew_list = EEWList[0-2] in {
defvar eew = eew_list[0];
defvar eew_type = eew_list[1];
-let Name = op # eew # "_v", IRName = op, MaskedIRName = op # "_mask"
in {
+let Name = op # eew # "_v", IRName = op, MaskedIRName = op # "_mask",
+RequiredFeatures = !if(!eq(type, "x"), ["ZvfhminOrZvfh"],
+ []) in {
def: RVVOutOp1Builtin<"v", "vPCe" # eew_type # "Uv", type>;
if !not(IsFloat.val) then {
def: RVVOutOp1Builtin<"Uv", "UvPCUe" # eew_type # "Uv", type>;
@@ -587,7 +589,8 @@ multiclass RVVIndexedLoad {
defvar eew64 = "64";
defvar eew64_type = "(Log2EEW:6)";
let Name = op # eew64 # "_v", IRName = op, MaskedIRName = op # "_mask",
- RequiredFeatures = ["RV64"] in {
+ RequiredFeatures = !if(!eq(type, "x"), ["ZvfhminOrZvfh", "RV64"],
+ ["RV64"]) in {
def: RVVOutOp1Builtin<"v", "vPCe" # eew64_type # "Uv", type>;
if !not(IsFloat.val) then {
def: RVVOutOp1Builtin<"Uv", "UvPCUe" # eew64_type # "Uv", type>;
@@ -682,7 +685,9 @@ multiclass RVVIndexedStore {
foreach eew_list = EEWList[0-2] in {
defvar eew = eew_list[0];
defvar eew_type = eew_list[1];
- let Name = op # eew # "_v", IRName = op, MaskedIRName = op #
"_mask" in {
+ let Name = op # eew # "_v", IRName = op, MaskedIRName = op #
"_mask",
+ RequiredFeatures = !if(!eq(type, "x"), ["ZvfhminOrZvfh"],
+ []) in {
def : RVVBuiltin<"v", "0Pe" # eew_type # "Uvv", type>;
if !not(IsFloat.val) then {
def : RVVBuiltin<"Uv", "0PUe" # eew_type # "UvUv", type>;
@@ -692,7 +697,8 @@ multiclass RVVIndexedStore {
defvar eew64 = "64";
defvar eew64_type = "(Log2EEW:6)";
let Name = op # eew64 # "_v", IRName = op, MaskedIRName = op #
"_mask",
-RequiredFeatures = ["RV64"] in {
+RequiredFeatures = !if(!eq(type, "x"), ["ZvfhminOrZvfh", "RV64"],
+ ["RV64"]) in {
def : RVVBuiltin<"v", "0Pe" # eew64_type # "Uvv", type>;
if !not(IsFloat.val) then {
def : RVVBuiltin<"Uv", "0PUe" # eew64_type # "UvUv", type>;
@@ -1112,24 +1118,32 @@ let HasBuiltinAlias = false,
// 7.4. Vector Unit-Stride Instructions
def vlm: RVVVLEMaskBuiltin;
defm vle8: RVVVLEBuiltin<["c"]>;
-defm vle16: RVVVLEBuiltin<["s","x"]>;
+defm vle16: RVVVLEBuiltin<["s"]>;
+let Name = "vle16_v", RequiredFeatures = ["ZvfhminOrZvfh"] in
+ defm vle16_h: RVVVLEBuiltin<["x"]>;
defm vle32: RVVVLEBuiltin<["i","f"]>;
defm vle64: RVVVLEBuiltin<["l","d"]>;
def vsm : RVVVSEMaskBuiltin;
defm vse8 : RVVVSEBuiltin<["c"]>;
-defm vse16: RVVVSEBuiltin<["s","x"]>;
+defm vse16: RVVVSEBuiltin<["s"]>;
+let Name = "vse16_v", RequiredFeatures = ["ZvfhminOrZvfh"] in
+ defm vse16_h: RVVVSEBuiltin<["x"]>;
defm vse32: RVVVSEBuiltin<["i","f"]>;
defm vse64: RVVVSEBuiltin<["l","d"]>;
// 7.5. Vector Strided Instructions
defm vlse8: RVVVLSEBuiltin<["c"]>;
-defm vlse16: RVVVLSEBuiltin<["s","x"]>;
+defm vlse16: RVVVLSEBuiltin<["s"]>;
+let Name = "vlse16_v", RequiredFeatures = ["ZvfhminOrZvfh"] in
+ defm vlse16_h: RVVVLSEBuiltin<["x"]>;
defm vlse32: RVVVLSEBuiltin<["i","f"]>;
defm vlse64: RVVVLSEBuiltin<["l","d"]>;
defm vsse8 : RVVVSSEBuiltin<["c"]>;
-defm vsse16: RVVVSSEBuiltin<["s","x"]>;
+defm vsse16: RVVVSSEBuiltin<["s"]>;
+let Name = "vsse16_v", RequiredFeatures = ["ZvfhminOrZvfh"] in
+ defm vsse16_h: RVVVSSEBuiltin<["x"]>;
defm vsse32: RVVVSSEBuiltin<["i","f"]>;
defm vsse64: RVVVSSEBuiltin<["l","d"]>;
@@ -1142,7 +1156,9
[clang] 654fa9a - [RISCV] Add Zvfhmin extension for clang
Author: Jianjian GUAN
Date: 2023-08-23T17:08:39+08:00
New Revision: 654fa9a7e898ce25a6d18f3a7c7b747e1059395b
URL:
https://github.com/llvm/llvm-project/commit/654fa9a7e898ce25a6d18f3a7c7b747e1059395b
DIFF:
https://github.com/llvm/llvm-project/commit/654fa9a7e898ce25a6d18f3a7c7b747e1059395b.diff
LOG: [RISCV] Add Zvfhmin extension for clang
This patch adds the Zvfhmin extension for clang.
Reviewed By: craig.topper, michaelmaitland
Differential Revision: https://reviews.llvm.org/D150253
Added:
clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin-error.c
clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin.c
Modified:
clang/include/clang/Basic/riscv_vector.td
clang/include/clang/Support/RISCVVIntrinsicUtils.h
clang/lib/Sema/SemaChecking.cpp
clang/lib/Sema/SemaRISCVVectorLookup.cpp
clang/test/Sema/riscv-vector-float16-check.c
clang/utils/TableGen/RISCVVEmitter.cpp
Removed:
diff --git a/clang/include/clang/Basic/riscv_vector.td
b/clang/include/clang/Basic/riscv_vector.td
index cf4dd8af2242de..7f0df6b729e296 100644
--- a/clang/include/clang/Basic/riscv_vector.td
+++ b/clang/include/clang/Basic/riscv_vector.td
@@ -2270,7 +2270,13 @@ let Log2LMUL = [-3, -2, -1, 0, 1, 2] in {
def vfwcvt_rtz_x_f_v : RVVConvToWidenSignedBuiltin<"vfwcvt_rtz_x">;
def vfwcvt_f_xu_v : RVVConvBuiltin<"Fw", "FwUv", "csi", "vfwcvt_f">;
def vfwcvt_f_x_v : RVVConvBuiltin<"Fw", "Fwv", "csi", "vfwcvt_f">;
- def vfwcvt_f_f_v : RVVConvBuiltin<"w", "wv", "xf", "vfwcvt_f">;
+ def vfwcvt_f_f_v : RVVConvBuiltin<"w", "wv", "f", "vfwcvt_f">;
+ let RequiredFeatures = ["ZvfhminOrZvfh"] in
+def vfwcvt_f_f_v_fp16 : RVVConvBuiltin<"w", "wv", "x", "vfwcvt_f"> {
+ let Name = "vfwcvt_f_f_v";
+ let IRName = "vfwcvt_f_f_v";
+ let MaskedIRName = "vfwcvt_f_f_v_mask";
+}
}
// 14.19. Narrowing Floating-Point/Integer Type-Convert Instructions
@@ -2360,9 +2366,11 @@ let ManualCodegen = [{
defm :
RVVConvBuiltinSet<"vfncvt_f_xu_w", "csi", [["Fv", "FvUwu"]]>;
}
- let OverloadedName = "vfncvt_f" in
-defm :
- RVVConvBuiltinSet<"vfncvt_f_f_w", "xf", [["v", "vwu"]]>;
+ let OverloadedName = "vfncvt_f" in {
+defm : RVVConvBuiltinSet<"vfncvt_f_f_w", "f", [["v", "vwu"]]>;
+let RequiredFeatures = ["ZvfhminOrZvfh"] in
+defm : RVVConvBuiltinSet<"vfncvt_f_f_w", "x", [["v", "vwu"]]>;
+ }
}
}
@@ -2403,9 +2411,11 @@ let ManualCodegen = [{
defm :
RVVConvBuiltinSet<"vfncvt_f_xu_w", "csi", [["Fv", "FvUw"]]>;
}
-let OverloadedName = "vfncvt_f" in
- defm :
-RVVConvBuiltinSet<"vfncvt_f_f_w", "xf", [["v", "vw"]]>;
+let OverloadedName = "vfncvt_f" in {
+ defm : RVVConvBuiltinSet<"vfncvt_f_f_w", "f", [["v", "vw"]]>;
+ let RequiredFeatures = ["ZvfhminOrZvfh"] in
+ defm : RVVConvBuiltinSet<"vfncvt_f_f_w", "x", [["v", "vw"]]>;
+}
}
}
}
diff --git a/clang/include/clang/Support/RISCVVIntrinsicUtils.h
b/clang/include/clang/Support/RISCVVIntrinsicUtils.h
index f8a7e505a1e4e4..72878368ce1a33 100644
--- a/clang/include/clang/Support/RISCVVIntrinsicUtils.h
+++ b/clang/include/clang/Support/RISCVVIntrinsicUtils.h
@@ -483,7 +483,8 @@ class RVVIntrinsic {
enum RVVRequire : uint8_t {
RVV_REQ_None = 0,
RVV_REQ_RV64 = 1 << 0,
- RVV_REQ_Xsfvcp = 1 << 1,
+ RVV_REQ_ZvfhminOrZvfh = 1 << 1,
+ RVV_REQ_Xsfvcp = 1 << 2,
LLVM_MARK_AS_BITMASK_ENUM(RVV_REQ_Xsfvcp)
};
diff --git a/clang/lib/Sema/SemaChecking.cpp b/clang/lib/Sema/SemaChecking.cpp
index 660c0b55df892d..e3b4d151536528 100644
--- a/clang/lib/Sema/SemaChecking.cpp
+++ b/clang/lib/Sema/SemaChecking.cpp
@@ -5506,8 +5506,9 @@ void Sema::checkRVVTypeSupport(QualType Ty,
SourceLocation Loc, ValueDecl *D) {
!TI.hasFeature("zve64x"))
Diag(Loc, diag::err_riscv_type_requires_extension, D) << Ty << "zve64x";
if (Ty->isRVVType(/* Bitwidth */ 16, /* IsFloat */ true) &&
- !TI.hasFeature("zvfh"))
-Diag(Loc, diag::err_riscv_type_requires_extension, D) << Ty << "zvfh";
+ !TI.hasFeature("zvfh") && !TI.hasFeature("zvfhmin"))
+Diag(Loc, diag::err_riscv_type_requires_extension, D)
+<< Ty << "zvfh or zvfhmin";
if (Ty->isRVVType(/* Bitwidth */ 32, /* IsFloat */ true) &&
!TI.hasFeature("zve32f"))
Diag(Loc, diag::err_riscv_type_requires_extension, D) << Ty << "zve32f";
diff --git a/clang/lib/Sema/SemaRISCVVectorLookup.cpp
b/clang/lib/Sema/SemaRISCVVectorLookup.cpp
index c5e076ffc70e5b..ebdd498cc7644a 100644
--- a/clang/lib/Sema/SemaRISCVVectorLookup.cpp
+++ b/clang/lib/Sema/SemaRISCVVectorLookup.cpp
@@ -262,6 +262,16 @@ void RISCVIntrinsicManagerImpl::ConstructRVVIntrinsics(
if ((BaseTypeI & Record.TypeRangeMask) != BaseTypeI)
continue;
+ if (BaseType == BasicType::Float16) {
+if ((Record.RequiredExtensions & RVV_REQ_ZvfhminOrZvfh)
[clang] 28741a2 - [clang][SVE] Rename isVLSTBuiltinType, NFC
Author: Jianjian GUAN
Date: 2023-08-17T14:18:32+08:00
New Revision: 28741a23c9fc5e9c9ba9cad8e71c3067544bcd66
URL:
https://github.com/llvm/llvm-project/commit/28741a23c9fc5e9c9ba9cad8e71c3067544bcd66
DIFF:
https://github.com/llvm/llvm-project/commit/28741a23c9fc5e9c9ba9cad8e71c3067544bcd66.diff
LOG: [clang][SVE] Rename isVLSTBuiltinType, NFC
Since we also have VLST for rvv now, it is not clear to keep using
`isVLSTBuiltinType`, so I added prefix SVE to it.
Reviewed By: paulwalker-arm
Differential Revision: https://reviews.llvm.org/D158045
Added:
Modified:
clang/include/clang/AST/Type.h
clang/lib/AST/ASTContext.cpp
clang/lib/AST/ExprConstant.cpp
clang/lib/AST/Type.cpp
clang/lib/CodeGen/CGExprScalar.cpp
clang/lib/Sema/SemaChecking.cpp
clang/lib/Sema/SemaExpr.cpp
clang/lib/Sema/SemaExprCXX.cpp
clang/lib/Sema/SemaType.cpp
Removed:
diff --git a/clang/include/clang/AST/Type.h b/clang/include/clang/AST/Type.h
index ed424ffb748014..46dbadd8b878bf 100644
--- a/clang/include/clang/AST/Type.h
+++ b/clang/include/clang/AST/Type.h
@@ -2075,7 +2075,7 @@ class alignas(8) Type : public ExtQualsTypeCommonBase {
/// Determines if this is a sizeless type supported by the
/// 'arm_sve_vector_bits' type attribute, which can be applied to a single
/// SVE vector or predicate, excluding tuple types such as svint32x4_t.
- bool isVLSTBuiltinType() const;
+ bool isSveVLSBuiltinType() const;
/// Returns the representative type for the element of an SVE builtin type.
/// This is used to represent fixed-length SVE vectors created with the
diff --git a/clang/lib/AST/ASTContext.cpp b/clang/lib/AST/ASTContext.cpp
index 7acacd7bf4f504..1ca53d00ea1a7f 100644
--- a/clang/lib/AST/ASTContext.cpp
+++ b/clang/lib/AST/ASTContext.cpp
@@ -9461,7 +9461,7 @@ bool ASTContext::areCompatibleVectorTypes(QualType
FirstVec,
/// getSVETypeSize - Return SVE vector or predicate register size.
static uint64_t getSVETypeSize(ASTContext , const BuiltinType *Ty) {
- assert(Ty->isVLSTBuiltinType() && "Invalid SVE Type");
+ assert(Ty->isSveVLSBuiltinType() && "Invalid SVE Type");
if (Ty->getKind() == BuiltinType::SveBool ||
Ty->getKind() == BuiltinType::SveCount)
return (Context.getLangOpts().VScaleMin * 128) / Context.getCharWidth();
diff --git a/clang/lib/AST/ExprConstant.cpp b/clang/lib/AST/ExprConstant.cpp
index e3569be5549cfe..9ee9fccfd461f5 100644
--- a/clang/lib/AST/ExprConstant.cpp
+++ b/clang/lib/AST/ExprConstant.cpp
@@ -8572,7 +8572,7 @@ bool LValueExprEvaluator::VisitMemberExpr(const
MemberExpr *E) {
bool LValueExprEvaluator::VisitArraySubscriptExpr(const ArraySubscriptExpr *E)
{
// FIXME: Deal with vectors as array subscript bases.
if (E->getBase()->getType()->isVectorType() ||
- E->getBase()->getType()->isVLSTBuiltinType())
+ E->getBase()->getType()->isSveVLSBuiltinType())
return Error(E);
APSInt Index;
diff --git a/clang/lib/AST/Type.cpp b/clang/lib/AST/Type.cpp
index e023cb46b9bb85..8173e082048207 100644
--- a/clang/lib/AST/Type.cpp
+++ b/clang/lib/AST/Type.cpp
@@ -1962,7 +1962,7 @@ bool Type::hasAutoForTrailingReturnType() const {
bool Type::hasIntegerRepresentation() const {
if (const auto *VT = dyn_cast(CanonicalType))
return VT->getElementType()->isIntegerType();
- if (CanonicalType->isVLSTBuiltinType()) {
+ if (CanonicalType->isSveVLSBuiltinType()) {
const auto *VT = cast(CanonicalType);
return VT->getKind() == BuiltinType::SveBool ||
(VT->getKind() >= BuiltinType::SveInt8 &&
@@ -2179,7 +2179,7 @@ bool Type::hasUnsignedIntegerRepresentation() const {
return VT->getElementType()->isUnsignedIntegerOrEnumerationType();
if (const auto *VT = dyn_cast(CanonicalType))
return VT->getElementType()->isUnsignedIntegerOrEnumerationType();
- if (CanonicalType->isVLSTBuiltinType()) {
+ if (CanonicalType->isSveVLSBuiltinType()) {
const auto *VT = cast(CanonicalType);
return VT->getKind() >= BuiltinType::SveUint8 &&
VT->getKind() <= BuiltinType::SveUint64;
@@ -2433,7 +2433,7 @@ bool Type::isRVVSizelessBuiltinType() const {
return false;
}
-bool Type::isVLSTBuiltinType() const {
+bool Type::isSveVLSBuiltinType() const {
if (const BuiltinType *BT = getAs()) {
switch (BT->getKind()) {
case BuiltinType::SveInt8:
@@ -2460,7 +2460,7 @@ bool Type::isVLSTBuiltinType() const {
}
QualType Type::getSveEltType(const ASTContext ) const {
- assert(isVLSTBuiltinType() && "unsupported type!");
+ assert(isSveVLSBuiltinType() && "unsupported type!");
const BuiltinType *BTy = castAs();
if (BTy->getKind() == BuiltinType::SveBool)
diff --git a/clang/lib/CodeGen/CGExprScalar.cpp
b/clang/lib/CodeGen/CGExprScalar.cpp
index 020b831f0c7bb2..6d5a61b24133e2 100644
--- a/clang/lib/CodeGen/CGExprScalar.cpp
+++ b/clang/lib/CodeGen/CGExprScalar.cpp
@@ -1798,7 +1798,7 @@
[clang] 9d0cf88 - [clang][doc] Mark _Float16 is support natively when Zfh or Zhinx is available
Author: Jianjian GUAN Date: 2023-08-14T11:27:15+08:00 New Revision: 9d0cf88e70860b29615253fbbd4d2d62eb08886a URL: https://github.com/llvm/llvm-project/commit/9d0cf88e70860b29615253fbbd4d2d62eb08886a DIFF: https://github.com/llvm/llvm-project/commit/9d0cf88e70860b29615253fbbd4d2d62eb08886a.diff LOG: [clang][doc] Mark _Float16 is support natively when Zfh or Zhinx is available Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D157693 Added: Modified: clang/docs/LanguageExtensions.rst Removed: diff --git a/clang/docs/LanguageExtensions.rst b/clang/docs/LanguageExtensions.rst index c771e3457af2b2..386ffa7b48eb93 100644 --- a/clang/docs/LanguageExtensions.rst +++ b/clang/docs/LanguageExtensions.rst @@ -814,6 +814,7 @@ to ``float``; see below for more information on this emulation. * AMDGPU (natively) * SPIR (natively) * X86 (if SSE2 is available; natively if AVX512-FP16 is also available) + * RISC-V (natively if Zfh or Zhinx is available) * ``__bf16`` is supported on the following targets (currently never natively): * 32-bit ARM ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] f808788 - [RISCV] Remove experimental for zihintntl
Author: Jianjian GUAN
Date: 2023-08-10T17:04:49+08:00
New Revision: f808788487ab9db7da262a0b43483fb07bf6b50f
URL:
https://github.com/llvm/llvm-project/commit/f808788487ab9db7da262a0b43483fb07bf6b50f
DIFF:
https://github.com/llvm/llvm-project/commit/f808788487ab9db7da262a0b43483fb07bf6b50f.diff
LOG: [RISCV] Remove experimental for zihintntl
Since zihintntl is ratified now, we could remove the experimental prefix and
change its version to 1.0.
Reviewed By: asb
Differential Revision: https://reviews.llvm.org/D151547
Added:
Modified:
clang/include/clang/Basic/BuiltinsRISCV.def
clang/test/CodeGen/RISCV/ntlh-intrinsics/riscv32-zihintntl.c
clang/test/Preprocessor/riscv-target-features.c
llvm/docs/RISCVUsage.rst
llvm/docs/ReleaseNotes.rst
llvm/lib/Support/RISCVISAInfo.cpp
llvm/lib/Target/RISCV/RISCVFeatures.td
llvm/test/CodeGen/RISCV/attributes.ll
llvm/test/CodeGen/RISCV/nontemporal-scalable.ll
llvm/test/CodeGen/RISCV/nontemporal.ll
llvm/test/CodeGen/RISCV/prefetch.ll
llvm/test/MC/RISCV/attribute-arch.s
llvm/test/MC/RISCV/rv32zihintntl-invalid.s
llvm/test/MC/RISCV/rv32zihintntl-valid.s
llvm/test/MC/RISCV/rv32zihintntlc-invalid.s
llvm/test/MC/RISCV/rv32zihintntlc-valid.s
Removed:
diff --git a/clang/include/clang/Basic/BuiltinsRISCV.def
b/clang/include/clang/Basic/BuiltinsRISCV.def
index 50e912c2c1c741..1528b18c82eade 100644
--- a/clang/include/clang/Basic/BuiltinsRISCV.def
+++ b/clang/include/clang/Basic/BuiltinsRISCV.def
@@ -86,8 +86,8 @@ TARGET_BUILTIN(__builtin_riscv_sm3p0, "UiUi", "nc", "zksh")
TARGET_BUILTIN(__builtin_riscv_sm3p1, "UiUi", "nc", "zksh")
// Zihintntl extension
-TARGET_BUILTIN(__builtin_riscv_ntl_load, "v.", "t", "experimental-zihintntl")
-TARGET_BUILTIN(__builtin_riscv_ntl_store, "v.", "t", "experimental-zihintntl")
+TARGET_BUILTIN(__builtin_riscv_ntl_load, "v.", "t", "zihintntl")
+TARGET_BUILTIN(__builtin_riscv_ntl_store, "v.", "t", "zihintntl")
#undef BUILTIN
#undef TARGET_BUILTIN
diff --git a/clang/test/CodeGen/RISCV/ntlh-intrinsics/riscv32-zihintntl.c
b/clang/test/CodeGen/RISCV/ntlh-intrinsics/riscv32-zihintntl.c
index f27f89df704858..897edbc6450af6 100644
--- a/clang/test/CodeGen/RISCV/ntlh-intrinsics/riscv32-zihintntl.c
+++ b/clang/test/CodeGen/RISCV/ntlh-intrinsics/riscv32-zihintntl.c
@@ -1,5 +1,5 @@
// REQUIRES: riscv-registered-target
-// RUN: %clang_cc1 -triple riscv32 -target-feature +v -target-feature
+experimental-zihintntl -emit-llvm %s -o - \
+// RUN: %clang_cc1 -triple riscv32 -target-feature +v -target-feature
+zihintntl -emit-llvm %s -o - \
// RUN: | FileCheck %s
#include
diff --git a/clang/test/Preprocessor/riscv-target-features.c
b/clang/test/Preprocessor/riscv-target-features.c
index dcf62e76149ccd..3f91d0d99f2290 100644
--- a/clang/test/Preprocessor/riscv-target-features.c
+++ b/clang/test/Preprocessor/riscv-target-features.c
@@ -143,13 +143,13 @@
// CHECK-C-EXT: __riscv_c 200{{$}}
// CHECK-C-EXT: __riscv_compressed 1
-// RUN: %clang -target riscv32-unknown-linux-gnu
-menable-experimental-extensions \
-// RUN: -march=rv32izihintntl0p2 -x c -E -dM %s \
-// RUN: -o - | FileCheck --check-prefix=CHECK-ZIHINTNTL-EXT %s
-// RUN: %clang -target riscv64-unknown-linux-gnu
-menable-experimental-extensions \
-// RUN: -march=rv64izihintntl0p2 -x c -E -dM %s \
-// RUN: -o - | FileCheck --check-prefix=CHECK-ZIHINTNTL-EXT %s
-// CHECK-ZIHINTNTL-EXT: __riscv_zihintntl 2000{{$}}
+// RUN: %clang -target riscv32-unknown-linux-gnu \
+// RUN: -march=rv32izihintntl1p0 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZIHINTNTL %s
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izihintntl1p0 -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZIHINTNTL %s
+// CHECK-ZIHINTNTL: __riscv_zihintntl 100{{$}}
// RUN: %clang -target riscv32-unknown-linux-gnu \
// RUN: -march=rv32izba1p0 -x c -E -dM %s \
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index 1c181d32511057..4d319fc6dc6a4b 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -120,6 +120,7 @@ on support follow.
``Zicntr`` (`See Note <#riscv-i2p1-note>`__)
``Zicsr``(`See Note <#riscv-i2p1-note>`__)
``Zifencei`` (`See Note <#riscv-i2p1-note>`__)
+ ``Zihintntl``Supported
``Zihintpause`` Assembly Support
``Zihpm``(`See Note <#riscv-i2p1-note>`__)
``Zkn`` Supported
@@ -204,9 +205,6 @@ The primary goal of experimental support is to assist in
the process of ratifica
``experimental-zicond``
LLVM implements the `1.0-rc1 draft specification
`__.
-``experimental-zihintntl``
- LLVM implements the `0.2 draft specification
[clang] 35a0079 - [RISCV] Add Zvfhmin extension for clang.
Author: Jianjian GUAN
Date: 2023-05-31T14:31:11+08:00
New Revision: 35a0079238ce9fc36cdc8c6a2895eb5538bf7b4a
URL:
https://github.com/llvm/llvm-project/commit/35a0079238ce9fc36cdc8c6a2895eb5538bf7b4a
DIFF:
https://github.com/llvm/llvm-project/commit/35a0079238ce9fc36cdc8c6a2895eb5538bf7b4a.diff
LOG: [RISCV] Add Zvfhmin extension for clang.
This patch adds the Zvfhmin extension for clang.
Reviewed By: craig.topper, michaelmaitland
Differential Revision: https://reviews.llvm.org/D150253
Added:
clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin-error.c
clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/zvfhmin.c
Modified:
clang/include/clang/Basic/riscv_vector.td
clang/include/clang/Support/RISCVVIntrinsicUtils.h
clang/lib/Sema/Sema.cpp
clang/lib/Sema/SemaRISCVVectorLookup.cpp
clang/test/Sema/riscv-vector-float16-check.c
clang/utils/TableGen/RISCVVEmitter.cpp
llvm/lib/Support/RISCVISAInfo.cpp
llvm/lib/Target/RISCV/RISCVFeatures.td
Removed:
diff --git a/clang/include/clang/Basic/riscv_vector.td
b/clang/include/clang/Basic/riscv_vector.td
index 4d48c38adb578..35b1536f72d3b 100644
--- a/clang/include/clang/Basic/riscv_vector.td
+++ b/clang/include/clang/Basic/riscv_vector.td
@@ -2215,7 +2215,13 @@ let Log2LMUL = [-3, -2, -1, 0, 1, 2] in {
def vfwcvt_rtz_x_f_v : RVVConvToWidenSignedBuiltin<"vfwcvt_rtz_x">;
def vfwcvt_f_xu_v : RVVConvBuiltin<"Fw", "FwUv", "csi", "vfwcvt_f">;
def vfwcvt_f_x_v : RVVConvBuiltin<"Fw", "Fwv", "csi", "vfwcvt_f">;
- def vfwcvt_f_f_v : RVVConvBuiltin<"w", "wv", "xf", "vfwcvt_f">;
+ def vfwcvt_f_f_v : RVVConvBuiltin<"w", "wv", "f", "vfwcvt_f">;
+ let RequiredFeatures = ["ZvfhminOrZvfh"] in
+def vfwcvt_f_f_v_fp16 : RVVConvBuiltin<"w", "wv", "x", "vfwcvt_f"> {
+ let Name = "vfwcvt_f_f_v";
+ let IRName = "vfwcvt_f_f_v";
+ let MaskedIRName = "vfwcvt_f_f_v_mask";
+}
}
// 14.19. Narrowing Floating-Point/Integer Type-Convert Instructions
@@ -2226,7 +2232,13 @@ let Log2LMUL = [-3, -2, -1, 0, 1, 2] in {
def vfncvt_rtz_x_f_w : RVVConvToNarrowingSignedBuiltin<"vfncvt_rtz_x">;
def vfncvt_f_xu_w : RVVConvBuiltin<"Fv", "FvUw", "csi", "vfncvt_f">;
def vfncvt_f_x_w : RVVConvBuiltin<"Fv", "Fvw", "csi", "vfncvt_f">;
- def vfncvt_f_f_w : RVVConvBuiltin<"v", "vw", "xf", "vfncvt_f">;
+ def vfncvt_f_f_w : RVVConvBuiltin<"v", "vw", "f", "vfncvt_f">;
+ let RequiredFeatures = ["ZvfhminOrZvfh"] in
+def vfncvt_f_f_w_fp16 : RVVConvBuiltin<"v", "vw", "x", "vfncvt_f"> {
+ let Name = "vfncvt_f_f_w";
+ let IRName = "vfncvt_f_f_w";
+ let MaskedIRName = "vfncvt_f_f_w_mask";
+}
def vfncvt_rod_f_f_w : RVVConvBuiltin<"v", "vw", "xf", "vfncvt_rod_f">;
}
}
diff --git a/clang/include/clang/Support/RISCVVIntrinsicUtils.h
b/clang/include/clang/Support/RISCVVIntrinsicUtils.h
index 2a81e7972358e..7f2b5d9c28c48 100644
--- a/clang/include/clang/Support/RISCVVIntrinsicUtils.h
+++ b/clang/include/clang/Support/RISCVVIntrinsicUtils.h
@@ -470,7 +470,8 @@ enum RVVRequire : uint8_t {
RVV_REQ_None = 0,
RVV_REQ_RV64 = 1 << 0,
RVV_REQ_FullMultiply = 1 << 1,
- RVV_REQ_Xsfvcp = 1 << 2,
+ RVV_REQ_ZvfhminOrZvfh = 1 << 2,
+ RVV_REQ_Xsfvcp = 1 << 3,
LLVM_MARK_AS_BITMASK_ENUM(RVV_REQ_Xsfvcp)
};
diff --git a/clang/lib/Sema/Sema.cpp b/clang/lib/Sema/Sema.cpp
index 9c6db547dbefd..7cc0d472fca02 100644
--- a/clang/lib/Sema/Sema.cpp
+++ b/clang/lib/Sema/Sema.cpp
@@ -2044,9 +2044,10 @@ void Sema::checkTypeSupport(QualType Ty, SourceLocation
Loc, ValueDecl *D) {
!TI.hasFeature("zve64x"))
Diag(Loc, diag::err_riscv_type_requires_extension, FD) << Ty << "zve64x";
if (Ty->isRVVType(/* Bitwidth */ 16, /* IsFloat */ true) &&
-!TI.hasFeature("experimental-zvfh"))
+!TI.hasFeature("experimental-zvfh") &&
+!TI.hasFeature("experimental-zvfhmin"))
Diag(Loc, diag::err_riscv_type_requires_extension, FD)
- << Ty << "zvfh";
+ << Ty << "zvfh or zvfhmin";
if (Ty->isRVVType(/* Bitwidth */ 32, /* IsFloat */ true) &&
!TI.hasFeature("zve32f"))
Diag(Loc, diag::err_riscv_type_requires_extension, FD) << Ty << "zve32f";
diff --git a/clang/lib/Sema/SemaRISCVVectorLookup.cpp
b/clang/lib/Sema/SemaRISCVVectorLookup.cpp
index 5599b9277cd79..be955a139c641 100644
--- a/clang/lib/Sema/SemaRISCVVectorLookup.cpp
+++ b/clang/lib/Sema/SemaRISCVVectorLookup.cpp
@@ -195,6 +195,8 @@ void RISCVIntrinsicManagerImpl::InitIntrinsicList() {
const TargetInfo = Context.getTargetInfo();
bool HasRV64 = TI.hasFeature("64bit");
bool HasFullMultiply = TI.hasFeature("v");
+ bool HasZvfh = TI.hasFeature("experimental-zvfh");
+ bool HasZvfhminOrZvfh = TI.hasFeature("experimental-zvfhmin") || HasZvfh;
auto ConstructRVVIntrinsics = [&](ArrayRef Recs,
IntrinsicKind K) {
@@ -257,6 +259,16 @@ void
[clang] 8e3a5a9 - [Driver][NFC] Simplify code.
Author: Jianjian GUAN Date: 2023-04-23T10:56:27+08:00 New Revision: 8e3a5a965a14f3d40c0ef07456e244509358abd7 URL: https://github.com/llvm/llvm-project/commit/8e3a5a965a14f3d40c0ef07456e244509358abd7 DIFF: https://github.com/llvm/llvm-project/commit/8e3a5a965a14f3d40c0ef07456e244509358abd7.diff LOG: [Driver][NFC] Simplify code. Reviewed By: benshi001, jhuber6 Differential Revision: https://reviews.llvm.org/D148908 Added: Modified: clang/lib/Driver/Driver.cpp Removed: diff --git a/clang/lib/Driver/Driver.cpp b/clang/lib/Driver/Driver.cpp index 591025cc10c4b..2e924960eda37 100644 --- a/clang/lib/Driver/Driver.cpp +++ b/clang/lib/Driver/Driver.cpp @@ -4095,16 +4095,15 @@ void Driver::BuildActions(Compilation , DerivedArgList , Current = NewCurrent; - // Use the current host action in any of the offloading actions, if - // required. - if (!UseNewOffloadingDriver) -if (OffloadBuilder->addHostDependenceToDeviceActions(Current, InputArg)) - break; - // Try to build the offloading actions and add the result as a dependency // to the host. if (UseNewOffloadingDriver) Current = BuildOffloadingActions(C, Args, I, Current); + // Use the current host action in any of the offloading actions, if + // required. + else if (OffloadBuilder->addHostDependenceToDeviceActions(Current, +InputArg)) +break; if (Current->getType() == types::TY_Nothing) break; ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
