[clang] [clang][PowerPC] Add flag to enable compatibility with GNU for complex arguments (PR #77732)
chmeeedalf wrote: > ping! @chmeeedalf @nemanjai I know nothing about the complex ABI, so all I can say is the code looks okay from a structural point, can't say anything to the logic. https://github.com/llvm/llvm-project/pull/77732 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] 4ca2cad - [PowerPC] Add clang -msvr4-struct-return for 32-bit ELF
Author: Justin Hibbits
Date: 2020-04-21T20:17:25-05:00
New Revision: 4ca2cad947d09ba0402f5b85d165aa7fcfbd9e3e
URL:
https://github.com/llvm/llvm-project/commit/4ca2cad947d09ba0402f5b85d165aa7fcfbd9e3e
DIFF:
https://github.com/llvm/llvm-project/commit/4ca2cad947d09ba0402f5b85d165aa7fcfbd9e3e.diff
LOG: [PowerPC] Add clang -msvr4-struct-return for 32-bit ELF
Summary:
Change the default ABI to be compatible with GCC. For 32-bit ELF
targets other than Linux, Clang now returns small structs in registers
r3/r4. This affects FreeBSD, NetBSD, OpenBSD. There is no change for
32-bit Linux, where Clang continues to return all structs in memory.
Add clang options -maix-struct-return (to return structs in memory) and
-msvr4-struct-return (to return structs in registers) to be compatible
with gcc. These options are only for PPC32; reject them on PPC64 and
other targets. The options are like -fpcc-struct-return and
-freg-struct-return for X86_32, and use similar code.
To actually return a struct in registers, coerce it to an integer of the
same size. LLVM may optimize the code to remove unnecessary accesses to
memory, and will return i32 in r3 or i64 in r3:r4.
Fixes PR#40736
Patch by George Koehler!
Reviewed By: jhibbits, nemanjai
Differential Revision: https://reviews.llvm.org/D73290
Added:
clang/test/CodeGen/ppc32-struct-return.c
clang/test/Driver/ppc-unsupported.c
Modified:
clang/docs/ClangCommandLineReference.rst
clang/include/clang/Driver/Options.td
clang/lib/CodeGen/TargetInfo.cpp
clang/lib/Driver/ToolChains/Clang.cpp
clang/lib/Frontend/CompilerInvocation.cpp
Removed:
diff --git a/clang/docs/ClangCommandLineReference.rst
b/clang/docs/ClangCommandLineReference.rst
index e5a649702037..c7afcf7cf605 100644
--- a/clang/docs/ClangCommandLineReference.rst
+++ b/clang/docs/ClangCommandLineReference.rst
@@ -2973,6 +2973,11 @@ Enable MT ASE (MIPS only)
PowerPC
---
+.. option:: -maix-struct-return
+
+Override the default ABI for 32-bit targets to return all structs in memory,
+as in the Power 32-bit ABI for Linux (2011), and on AIX and Darwin.
+
.. option:: -maltivec, -mno-altivec
.. option:: -mcmpb, -mno-cmpb
@@ -3009,6 +3014,11 @@ PowerPC
.. option:: -mspe, -mno-spe
+.. option:: -msvr4-struct-return
+
+Override the default ABI for 32-bit targets to return small structs in
+registers, as in the System V ABI (1995).
+
.. option:: -mvsx, -mno-vsx
WebAssembly
diff --git a/clang/include/clang/Driver/Options.td
b/clang/include/clang/Driver/Options.td
index fcfc3a387de8..889880cc86d6 100644
--- a/clang/include/clang/Driver/Options.td
+++ b/clang/include/clang/Driver/Options.td
@@ -2510,6 +2510,12 @@ def mlongcall: Flag<["-"], "mlongcall">,
Group;
def mno_longcall : Flag<["-"], "mno-longcall">,
Group;
+def maix_struct_return : Flag<["-"], "maix-struct-return">,
+ Group, Flags<[CC1Option]>,
+ HelpText<"Return all structs in memory (PPC32 only)">;
+def msvr4_struct_return : Flag<["-"], "msvr4-struct-return">,
+ Group, Flags<[CC1Option]>,
+ HelpText<"Return small structs in registers (PPC32 only)">;
def mvx : Flag<["-"], "mvx">, Group;
def mno_vx : Flag<["-"], "mno-vx">, Group;
diff --git a/clang/lib/CodeGen/TargetInfo.cpp
b/clang/lib/CodeGen/TargetInfo.cpp
index 22128534beda..0a5fb27ba015 100644
--- a/clang/lib/CodeGen/TargetInfo.cpp
+++ b/clang/lib/CodeGen/TargetInfo.cpp
@@ -4177,12 +4177,24 @@ namespace {
/// PPC32_SVR4_ABIInfo - The 32-bit PowerPC ELF (SVR4) ABI information.
class PPC32_SVR4_ABIInfo : public DefaultABIInfo {
bool IsSoftFloatABI;
+ bool IsRetSmallStructInRegABI;
CharUnits getParamTypeAlignment(QualType Ty) const;
public:
- PPC32_SVR4_ABIInfo(CodeGen::CodeGenTypes &CGT, bool SoftFloatABI)
- : DefaultABIInfo(CGT), IsSoftFloatABI(SoftFloatABI) {}
+ PPC32_SVR4_ABIInfo(CodeGen::CodeGenTypes &CGT, bool SoftFloatABI,
+ bool RetSmallStructInRegABI)
+ : DefaultABIInfo(CGT), IsSoftFloatABI(SoftFloatABI),
+IsRetSmallStructInRegABI(RetSmallStructInRegABI) {}
+
+ ABIArgInfo classifyReturnType(QualType RetTy) const;
+
+ void computeInfo(CGFunctionInfo &FI) const override {
+if (!getCXXABI().classifyReturnType(FI))
+ FI.getReturnInfo() = classifyReturnType(FI.getReturnType());
+for (auto &I : FI.arguments())
+ I.info = classifyArgumentType(I.type);
+ }
Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
QualType Ty) const override;
@@ -4190,8 +4202,13 @@ class PPC32_SVR4_ABIInfo : public DefaultABIInfo {
class PPC32TargetCodeGenInfo : public TargetCodeGenInfo {
public:
- PPC32TargetCodeGenInfo(CodeGenTypes &CGT, bool SoftFloatABI)
- : TargetCodeGenInfo(new PPC32_SVR4_ABIInfo(CGT, SoftFloatABI)) {}
+ PPC32TargetCodeGenInfo(CodeGenTypes &CGT, bool SoftFloatABI,
+ bool RetSmallStructInRegABI)
+ : TargetC
[clang] ff0311c - [PowerPC]: Add powerpcspe target triple subarch component
Author: Justin Hibbits
Date: 2020-01-08T19:10:53-06:00
New Revision: ff0311c4b3b9dce9d25d08e38aa163682b155513
URL:
https://github.com/llvm/llvm-project/commit/ff0311c4b3b9dce9d25d08e38aa163682b155513
DIFF:
https://github.com/llvm/llvm-project/commit/ff0311c4b3b9dce9d25d08e38aa163682b155513.diff
LOG: [PowerPC]: Add powerpcspe target triple subarch component
Summary:
This allows the use of '-target powerpcspe-unknown-linux-gnu' or
'powerpcspe-unknown-freebsd' to be used, instead of
'-target powerpc-unknown-linux-gnu -mspe'.
Reviewed By: dim
Differential Revision: https://reviews.llvm.org/D72014
Added:
Modified:
clang/lib/Basic/Targets/PPC.cpp
clang/lib/Basic/Targets/PPC.h
clang/test/Preprocessor/init.c
llvm/include/llvm/ADT/Triple.h
llvm/lib/Support/Triple.cpp
llvm/lib/Target/PowerPC/PPCSubtarget.cpp
llvm/unittests/ADT/TripleTest.cpp
Removed:
diff --git a/clang/lib/Basic/Targets/PPC.cpp b/clang/lib/Basic/Targets/PPC.cpp
index 1877d4a5ef70..bc0ffb7fa440 100644
--- a/clang/lib/Basic/Targets/PPC.cpp
+++ b/clang/lib/Basic/Targets/PPC.cpp
@@ -316,7 +316,8 @@ bool PPCTargetInfo::initFeatureMap(
.Case("pwr8", true)
.Default(false);
- Features["spe"] = llvm::StringSwitch(CPU)
+ Features["spe"] = getTriple().getSubArch() == llvm::Triple::PPCSubArch_spe ||
+llvm::StringSwitch(CPU)
.Case("8548", true)
.Case("e500", true)
.Default(false);
diff --git a/clang/lib/Basic/Targets/PPC.h b/clang/lib/Basic/Targets/PPC.h
index 3076025fc5b2..270aa7ff9181 100644
--- a/clang/lib/Basic/Targets/PPC.h
+++ b/clang/lib/Basic/Targets/PPC.h
@@ -87,8 +87,7 @@ class LLVM_LIBRARY_VISIBILITY PPCTargetInfo : public
TargetInfo {
// Note: GCC recognizes the following additional cpus:
// 401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801,
- // 821, 823, 8540, 8548, e300c2, e300c3, e500mc64, e6500, 860, cell,
- // titan, rs64.
+ // 821, 823, 8540, e300c2, e300c3, e500mc64, e6500, 860, cell, titan, rs64.
bool isValidCPUName(StringRef Name) const override;
void fillValidCPUList(SmallVectorImpl &Values) const override;
diff --git a/clang/test/Preprocessor/init.c b/clang/test/Preprocessor/init.c
index 4d8c6e5c46b6..a03725889360 100644
--- a/clang/test/Preprocessor/init.c
+++ b/clang/test/Preprocessor/init.c
@@ -6551,10 +6551,11 @@
// PPC32-LINUX-NOT: _CALL_LINUX
//
// RUN: %clang_cc1 -E -dM -ffreestanding -triple=powerpc-unknown-linux-gnu
-target-feature +spe < /dev/null | FileCheck -match-full-lines -check-prefix
PPC32-SPE %s
+// RUN: %clang_cc1 -E -dM -ffreestanding -triple=powerpcspe-unknown-linux-gnu
< /dev/null | FileCheck -match-full-lines -check-prefix PPC32-SPE %s
//
// PPC32-SPE:#define __NO_FPRS__ 1
// PPC32-SPE:#define __SPE__ 1
-//
+//
// RUN: %clang_cc1 -E -dM -ffreestanding -triple=powerpc-unknown-linux-gnu
-target-cpu 8548 < /dev/null | FileCheck -match-full-lines -check-prefix
PPC8548 %s
//
// PPC8548:#define __NO_FPRS__ 1
diff --git a/llvm/include/llvm/ADT/Triple.h b/llvm/include/llvm/ADT/Triple.h
index a2cae3754280..88a86bfa5ff3 100644
--- a/llvm/include/llvm/ADT/Triple.h
+++ b/llvm/include/llvm/ADT/Triple.h
@@ -128,7 +128,9 @@ class Triple {
KalimbaSubArch_v4,
KalimbaSubArch_v5,
-MipsSubArch_r6
+MipsSubArch_r6,
+
+PPCSubArch_spe
};
enum VendorType {
UnknownVendor,
diff --git a/llvm/lib/Support/Triple.cpp b/llvm/lib/Support/Triple.cpp
index 5bf93638a219..f2debc443d24 100644
--- a/llvm/lib/Support/Triple.cpp
+++ b/llvm/lib/Support/Triple.cpp
@@ -387,7 +387,7 @@ static Triple::ArchType parseArch(StringRef ArchName) {
// FIXME: Do we need to support these?
.Cases("i786", "i886", "i986", Triple::x86)
.Cases("amd64", "x86_64", "x86_64h", Triple::x86_64)
-.Cases("powerpc", "ppc", "ppc32", Triple::ppc)
+.Cases("powerpc", "powerpcspe", "ppc", "ppc32", Triple::ppc)
.Cases("powerpc64", "ppu", "ppc64", Triple::ppc64)
.Cases("powerpc64le", "ppc64le", Triple::ppc64le)
.Case("xscale", Triple::arm)
@@ -559,6 +559,9 @@ static Triple::SubArchType parseSubArch(StringRef
SubArchName) {
(SubArchName.endswith("r6el") || SubArchName.endswith("r6")))
return Triple::MipsSubArch_r6;
+ if (SubArchName == "powerpcspe")
+return Triple::PPCSubArch_spe;
+
StringRef ARMSubArch = ARM::getCanonicalArchName(SubArchName);
// For now, this is the small part. Early return.
diff --git a/llvm/lib/Target/PowerPC/PPCSubtarget.cpp
b/llvm/lib/Target/PowerPC/PPCSubtarget.cpp
index dc19cb0ac309..77122e62dd5f 100644
--- a/llvm/lib/Target/PowerPC/PPCSubtarget.cpp
+++ b/llvm/lib/Target/PowerPC/PPCSubtarget.cpp
@@ -151,6 +151,9 @@ void PPCSubtarget::initSubtargetFeatures(StringRef CPU,
StringRef FS) {
TargetTriple.isMusl())
Se
[clang] bc4bc5a - Add 8548 CPU definition and attributes
Author: Justin Hibbits
Date: 2019-11-12T20:34:34-06:00
New Revision: bc4bc5aa0d84413e4e3f082dee0d30cf839fb7ea
URL:
https://github.com/llvm/llvm-project/commit/bc4bc5aa0d84413e4e3f082dee0d30cf839fb7ea
DIFF:
https://github.com/llvm/llvm-project/commit/bc4bc5aa0d84413e4e3f082dee0d30cf839fb7ea.diff
LOG: Add 8548 CPU definition and attributes
8548 CPU is GCC's name for the e500v2, so accept this in clang. The
e500v2 doesn't support lwsync, so define __NO_LWSYNC__ for this as well,
as GCC does.
Differential Revision: https://reviews.llvm.org/D67787
Added:
Modified:
clang/lib/Basic/Targets/PPC.cpp
clang/lib/Basic/Targets/PPC.h
clang/lib/Driver/ToolChains/Arch/PPC.cpp
clang/test/Driver/clang-translation.c
clang/test/Misc/target-invalid-cpu-note.c
clang/test/Preprocessor/init.c
Removed:
diff --git a/clang/lib/Basic/Targets/PPC.cpp b/clang/lib/Basic/Targets/PPC.cpp
index a40991048873..baa96e21707b 100644
--- a/clang/lib/Basic/Targets/PPC.cpp
+++ b/clang/lib/Basic/Targets/PPC.cpp
@@ -157,6 +157,8 @@ void PPCTargetInfo::getTargetDefines(const LangOptions
&Opts,
Builder.defineMacro("_ARCH_A2Q");
Builder.defineMacro("_ARCH_QP");
}
+ if (ArchDefs & ArchDefineE500)
+Builder.defineMacro("__NO_LWSYNC__");
if (getTriple().getVendor() == llvm::Triple::BGQ) {
Builder.defineMacro("__bg__");
@@ -312,6 +314,11 @@ bool PPCTargetInfo::initFeatureMap(
.Case("pwr8", true)
.Default(false);
+ Features["spe"] = llvm::StringSwitch(CPU)
+.Case("8548", true)
+.Case("e500", true)
+.Default(false);
+
if (!ppcUserFeaturesCheck(Diags, FeaturesVec))
return false;
@@ -449,16 +456,16 @@ ArrayRef
PPCTargetInfo::getGCCAddlRegNames() const {
}
static constexpr llvm::StringLiteral ValidCPUNames[] = {
-{"generic"}, {"440"}, {"450"}, {"601"},{"602"},
-{"603"}, {"603e"},{"603ev"}, {"604"},{"604e"},
-{"620"}, {"630"}, {"g3"}, {"7400"}, {"g4"},
-{"7450"},{"g4+"}, {"750"}, {"970"},{"g5"},
-{"a2"}, {"a2q"}, {"e500mc"}, {"e5500"}, {"power3"},
-{"pwr3"},{"power4"}, {"pwr4"},{"power5"}, {"pwr5"},
-{"power5x"}, {"pwr5x"}, {"power6"}, {"pwr6"}, {"power6x"},
-{"pwr6x"}, {"power7"}, {"pwr7"},{"power8"}, {"pwr8"},
-{"power9"}, {"pwr9"},{"powerpc"}, {"ppc"},{"powerpc64"},
-{"ppc64"}, {"powerpc64le"}, {"ppc64le"},
+{"generic"}, {"440"}, {"450"}, {"601"}, {"602"},
+{"603"}, {"603e"}, {"603ev"}, {"604"}, {"604e"},
+{"620"}, {"630"}, {"g3"}, {"7400"},{"g4"},
+{"7450"}, {"g4+"}, {"750"}, {"8548"},{"970"},
+{"g5"},{"a2"},{"a2q"}, {"e500"},{"e500mc"},
+{"e5500"}, {"power3"},{"pwr3"},{"power4"}, {"pwr4"},
+{"power5"},{"pwr5"}, {"power5x"}, {"pwr5x"}, {"power6"},
+{"pwr6"}, {"power6x"}, {"pwr6x"}, {"power7"}, {"pwr7"},
+{"power8"},{"pwr8"}, {"power9"}, {"pwr9"},
{"powerpc"},
+{"ppc"}, {"powerpc64"}, {"ppc64"}, {"powerpc64le"},
{"ppc64le"},
};
bool PPCTargetInfo::isValidCPUName(StringRef Name) const {
diff --git a/clang/lib/Basic/Targets/PPC.h b/clang/lib/Basic/Targets/PPC.h
index 6c6421c28e23..847338bbac1b 100644
--- a/clang/lib/Basic/Targets/PPC.h
+++ b/clang/lib/Basic/Targets/PPC.h
@@ -44,7 +44,8 @@ class LLVM_LIBRARY_VISIBILITY PPCTargetInfo : public
TargetInfo {
ArchDefinePwr8 = 1 << 12,
ArchDefinePwr9 = 1 << 13,
ArchDefineA2 = 1 << 14,
-ArchDefineA2q = 1 << 15
+ArchDefineA2q = 1 << 15,
+ArchDefineE500 = 1 << 16
} ArchDefineTypes;
@@ -145,6 +146,7 @@ class LLVM_LIBRARY_VISIBILITY PPCTargetInfo : public
TargetInfo {
ArchDefinePwr9 | ArchDefinePwr8 | ArchDefinePwr7 |
ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 |
ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
+ .Cases("8548", "e500", ArchDefineE500)
.Default(ArchDefineNone);
}
return CPUKnown;
diff --git a/clang/lib/Driver/ToolChains/Arch/PPC.cpp
b/clang/lib/Driver/ToolChains/Arch/PPC.cpp
index 3e02e57e0f6c..e1b0311f2ad0 100644
--- a/clang/lib/Driver/ToolChains/Arch/PPC.cpp
+++ b/clang/lib/Driver/ToolChains/Arch/PPC.cpp
@@ -53,10 +53,12 @@ std::string ppc::getPPCTargetCPU(const ArgList &Args) {
.Case("7450", "7450")
.Case("G4+", "g4+")
.Case("750", "750")
+.Case("8548", "e500")
.Case("970", "970")
.Case("G5", "g5")
.Case("a2", "a2")
.Case("a2q", "a2q")
+
r371066 - Add -m(no)-spe to clang
Author: jhibbits
Date: Thu Sep 5 06:38:46 2019
New Revision: 371066
URL: http://llvm.org/viewvc/llvm-project?rev=371066&view=rev
Log:
Add -m(no)-spe to clang
Summary:
r337347 added support for the Signal Processing Engine (SPE) to LLVM.
This follows that up with the clang side.
This adds -mspe and -mno-spe, to match GCC.
Subscribers: nemanjai, kbarton, cfe-commits
Differential Revision: https://reviews.llvm.org/D49754
Modified:
cfe/trunk/include/clang/Driver/Options.td
cfe/trunk/lib/Basic/Targets/PPC.cpp
cfe/trunk/lib/Basic/Targets/PPC.h
cfe/trunk/lib/CodeGen/TargetInfo.cpp
cfe/trunk/test/Driver/ppc-features.cpp
cfe/trunk/test/Preprocessor/init.c
Modified: cfe/trunk/include/clang/Driver/Options.td
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/include/clang/Driver/Options.td?rev=371066&r1=371065&r2=371066&view=diff
==
--- cfe/trunk/include/clang/Driver/Options.td (original)
+++ cfe/trunk/include/clang/Driver/Options.td Thu Sep 5 06:38:46 2019
@@ -2269,6 +2269,8 @@ def faltivec : Flag<["-"], "faltivec">,
def fno_altivec : Flag<["-"], "fno-altivec">, Group,
Flags<[DriverOption]>;
def maltivec : Flag<["-"], "maltivec">, Group;
def mno_altivec : Flag<["-"], "mno-altivec">, Group;
+def mspe : Flag<["-"], "mspe">, Group;
+def mno_spe : Flag<["-"], "mno-spe">, Group;
def mvsx : Flag<["-"], "mvsx">, Group;
def mno_vsx : Flag<["-"], "mno-vsx">, Group;
def msecure_plt : Flag<["-"], "msecure-plt">, Group;
Modified: cfe/trunk/lib/Basic/Targets/PPC.cpp
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Basic/Targets/PPC.cpp?rev=371066&r1=371065&r2=371066&view=diff
==
--- cfe/trunk/lib/Basic/Targets/PPC.cpp (original)
+++ cfe/trunk/lib/Basic/Targets/PPC.cpp Thu Sep 5 06:38:46 2019
@@ -54,6 +54,10 @@ bool PPCTargetInfo::handleTargetFeatures
HasFloat128 = true;
} else if (Feature == "+power9-vector") {
HasP9Vector = true;
+} else if (Feature == "+spe") {
+ HasSPE = true;
+ LongDoubleWidth = LongDoubleAlign = 64;
+ LongDoubleFormat = &llvm::APFloat::IEEEdouble();
} else if (Feature == "-hard-float") {
FloatABI = SoftFloat;
}
@@ -165,6 +169,10 @@ void PPCTargetInfo::getTargetDefines(con
Builder.defineMacro("__VEC__", "10206");
Builder.defineMacro("__ALTIVEC__");
}
+ if (HasSPE) {
+Builder.defineMacro("__SPE__");
+Builder.defineMacro("__NO_FPRS__");
+ }
if (HasVSX)
Builder.defineMacro("__VSX__");
if (HasP8Vector)
@@ -203,7 +211,6 @@ void PPCTargetInfo::getTargetDefines(con
// __CMODEL_LARGE__
// _CALL_SYSV
// _CALL_DARWIN
- // __NO_FPRS__
}
// Handle explicit options being passed to the compiler here: if we've
@@ -332,6 +339,7 @@ bool PPCTargetInfo::hasFeature(StringRef
.Case("extdiv", HasExtDiv)
.Case("float128", HasFloat128)
.Case("power9-vector", HasP9Vector)
+ .Case("spe", HasSPE)
.Default(false);
}
Modified: cfe/trunk/lib/Basic/Targets/PPC.h
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Basic/Targets/PPC.h?rev=371066&r1=371065&r2=371066&view=diff
==
--- cfe/trunk/lib/Basic/Targets/PPC.h (original)
+++ cfe/trunk/lib/Basic/Targets/PPC.h Thu Sep 5 06:38:46 2019
@@ -66,6 +66,7 @@ class LLVM_LIBRARY_VISIBILITY PPCTargetI
bool HasBPERMD = false;
bool HasExtDiv = false;
bool HasP9Vector = false;
+ bool HasSPE = false;
protected:
std::string ABI;
Modified: cfe/trunk/lib/CodeGen/TargetInfo.cpp
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/CodeGen/TargetInfo.cpp?rev=371066&r1=371065&r2=371066&view=diff
==
--- cfe/trunk/lib/CodeGen/TargetInfo.cpp (original)
+++ cfe/trunk/lib/CodeGen/TargetInfo.cpp Thu Sep 5 06:38:46 2019
@@ -9726,7 +9726,8 @@ const TargetCodeGenInfo &CodeGenModule::
case llvm::Triple::ppc:
return SetCGInfo(
-new PPC32TargetCodeGenInfo(Types, CodeGenOpts.FloatABI == "soft"));
+new PPC32TargetCodeGenInfo(Types, CodeGenOpts.FloatABI == "soft" ||
+ getTarget().hasFeature("spe")));
case llvm::Triple::ppc64:
if (Triple.isOSBinFormatELF()) {
PPC64_SVR4_ABIInfo::ABIKind Kind = PPC64_SVR4_ABIInfo::ELFv1;
Modified: cfe/trunk/test/Driver/ppc-features.cpp
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/Driver/ppc-features.cpp?rev=371066&r1=371065&r2=371066&view=diff
==
--- cfe/trunk/test/Driver/ppc-features.cpp (original)
+++ cfe/trunk/test/Driver/ppc-features.cpp Thu Sep 5 06:38:46 2019
@@ -168,6 +168,9 @@
// RUN: %clang -target powerpc64-unknown-linux-gnu %s
-mno-invariant-function-descriptors -minvariant-function-descriptors -###
