[clang] [flang] [libclc] [llvm] [AMDGPU] Add a new target gfx1152 (PR #94534)

2024-06-06 Thread Konstantin Zhuravlyov via cfe-commits 

https://github.com/kzhuravl commented:

Also remove EF_AMDGPU_MACH_AMDGCN_RESERVED_0X55

https://github.com/llvm/llvm-project/pull/94534
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[clang] AMDGPU: Add missing gfx* generic targets handling in clang (NVPTX, OpenMP runtime) (PR #94483)

2024-06-05 Thread Konstantin Zhuravlyov via cfe-commits 

https://github.com/kzhuravl closed 
https://github.com/llvm/llvm-project/pull/94483
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[clang] AMDGPU: Add missing gfx* generic targets handling in clang (NVPTX, OpenMP runtime) (PR #94483)

2024-06-05 Thread Konstantin Zhuravlyov via cfe-commits 


@@ -121,6 +121,11 @@ enum class CudaArch {
   GFX1151,
   GFX1200,
   GFX1201,
+  GFX9_GENERIC,

kzhuravl wrote:

Done.

https://github.com/llvm/llvm-project/pull/94483
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[clang] AMDGPU: Add missing gfx* generic targets handling in clang (NVPTX, OpenMP runtime) (PR #94483)

2024-06-05 Thread Konstantin Zhuravlyov via cfe-commits 

https://github.com/kzhuravl updated 
https://github.com/llvm/llvm-project/pull/94483

>From 7d64f16e9bdc6b9a195a332a49e5fb9954d5f7c1 Mon Sep 17 00:00:00 2001
From: Konstantin Zhuravlyov 
Date: Wed, 5 Jun 2024 11:10:41 -0400
Subject: [PATCH 1/2] AMDGPU: Add missing gfx* generic targets handling in
 clang (NVPTX, OpenMP runtime)

---
 clang/include/clang/Basic/Cuda.h  | 5 +
 clang/lib/Basic/Cuda.cpp  | 5 +
 clang/lib/Basic/Targets/NVPTX.cpp | 5 +
 clang/lib/CodeGen/CGOpenMPRuntimeGPU.cpp  | 5 +
 clang/test/Misc/target-invalid-cpu-note.c | 2 +-
 5 files changed, 21 insertions(+), 1 deletion(-)

diff --git a/clang/include/clang/Basic/Cuda.h b/clang/include/clang/Basic/Cuda.h
index 2d67c4181d129..2e126cdbca000 100644
--- a/clang/include/clang/Basic/Cuda.h
+++ b/clang/include/clang/Basic/Cuda.h
@@ -121,6 +121,11 @@ enum class CudaArch {
   GFX1151,
   GFX1200,
   GFX1201,
+  GFX9_GENERIC,
+  GFX10_1_GENERIC,
+  GFX10_3_GENERIC,
+  GFX11_GENERIC,
+  GFX12_GENERIC,
   Generic, // A processor model named 'generic' if the target backend defines a
// public one.
   LAST,
diff --git a/clang/lib/Basic/Cuda.cpp b/clang/lib/Basic/Cuda.cpp
index e8ce15eb0decb..f8e02af599ba9 100644
--- a/clang/lib/Basic/Cuda.cpp
+++ b/clang/lib/Basic/Cuda.cpp
@@ -141,6 +141,11 @@ static const CudaArchToStringMap arch_names[] = {
 GFX(1151), // gfx1151
 GFX(1200), // gfx1200
 GFX(1201), // gfx1201
+{CudaArch::GFX9_GENERIC, "gfx9-generic", "compute_amdgcn"},
+{CudaArch::GFX10_1_GENERIC, "gfx10-1-generic", "compute_amdgcn"},
+{CudaArch::GFX10_3_GENERIC, "gfx10-3-generic", "compute_amdgcn"},
+{CudaArch::GFX11_GENERIC, "gfx11-generic", "compute_amdgcn"},
+{CudaArch::GFX12_GENERIC, "gfx12-generic", "compute_amdgcn"},
 {CudaArch::Generic, "generic", ""},
 // clang-format on
 };
diff --git a/clang/lib/Basic/Targets/NVPTX.cpp 
b/clang/lib/Basic/Targets/NVPTX.cpp
index 8ad9e6e5f5891..d4249a617b45c 100644
--- a/clang/lib/Basic/Targets/NVPTX.cpp
+++ b/clang/lib/Basic/Targets/NVPTX.cpp
@@ -226,6 +226,11 @@ void NVPTXTargetInfo::getTargetDefines(const LangOptions 
,
   case CudaArch::GFX1151:
   case CudaArch::GFX1200:
   case CudaArch::GFX1201:
+  case CudaArch::GFX9_GENERIC:
+  case CudaArch::GFX10_1_GENERIC:
+  case CudaArch::GFX10_3_GENERIC:
+  case CudaArch::GFX11_GENERIC:
+  case CudaArch::GFX12_GENERIC:
   case CudaArch::Generic:
   case CudaArch::LAST:
 break;
diff --git a/clang/lib/CodeGen/CGOpenMPRuntimeGPU.cpp 
b/clang/lib/CodeGen/CGOpenMPRuntimeGPU.cpp
index 28da8662f5f61..c4905f7f8b595 100644
--- a/clang/lib/CodeGen/CGOpenMPRuntimeGPU.cpp
+++ b/clang/lib/CodeGen/CGOpenMPRuntimeGPU.cpp
@@ -3535,6 +3535,11 @@ void CGOpenMPRuntimeGPU::processRequiresDirective(
   case CudaArch::GFX1151:
   case CudaArch::GFX1200:
   case CudaArch::GFX1201:
+  case CudaArch::GFX9_GENERIC:
+  case CudaArch::GFX10_1_GENERIC:
+  case CudaArch::GFX10_3_GENERIC:
+  case CudaArch::GFX11_GENERIC:
+  case CudaArch::GFX12_GENERIC:
   case CudaArch::Generic:
   case CudaArch::UNUSED:
   case CudaArch::UNKNOWN:
diff --git a/clang/test/Misc/target-invalid-cpu-note.c 
b/clang/test/Misc/target-invalid-cpu-note.c
index 6558fd753d1d1..d610f58b9c4ec 100644
--- a/clang/test/Misc/target-invalid-cpu-note.c
+++ b/clang/test/Misc/target-invalid-cpu-note.c
@@ -29,7 +29,7 @@
 
 // RUN: not %clang_cc1 -triple nvptx--- -target-cpu not-a-cpu -fsyntax-only %s 
2>&1 | FileCheck %s --check-prefix NVPTX
 // NVPTX: error: unknown target CPU 'not-a-cpu'
-// NVPTX-NEXT: note: valid target CPU values are: sm_20, sm_21, sm_30, sm_32, 
sm_35, sm_37, sm_50, sm_52, sm_53, sm_60, sm_61, sm_62, sm_70, sm_72, sm_75, 
sm_80, sm_86, sm_87, sm_89, sm_90, sm_90a, gfx600, gfx601, gfx602, gfx700, 
gfx701, gfx702, gfx703, gfx704, gfx705, gfx801, gfx802, gfx803, gfx805, gfx810, 
gfx900, gfx902, gfx904, gfx906, gfx908, gfx909, gfx90a, gfx90c, gfx940, gfx941, 
gfx942, gfx1010, gfx1011, gfx1012, gfx1013, gfx1030, gfx1031, gfx1032, gfx1033, 
gfx1034, gfx1035, gfx1036, gfx1100, gfx1101, gfx1102, gfx1103, gfx1150, 
gfx1151, gfx1200, gfx1201{{$}}
+// NVPTX-NEXT: note: valid target CPU values are: sm_20, sm_21, sm_30, sm_32, 
sm_35, sm_37, sm_50, sm_52, sm_53, sm_60, sm_61, sm_62, sm_70, sm_72, sm_75, 
sm_80, sm_86, sm_87, sm_89, sm_90, sm_90a, gfx600, gfx601, gfx602, gfx700, 
gfx701, gfx702, gfx703, gfx704, gfx705, gfx801, gfx802, gfx803, gfx805, gfx810, 
gfx900, gfx902, gfx904, gfx906, gfx908, gfx909, gfx90a, gfx90c, gfx940, gfx941, 
gfx942, gfx1010, gfx1011, gfx1012, gfx1013, gfx1030, gfx1031, gfx1032, gfx1033, 
gfx1034, gfx1035, gfx1036, gfx1100, gfx1101, gfx1102, gfx1103, gfx1150, 
gfx1151, gfx1200, gfx1201, gfx9-generic, gfx10-1-generic, gfx10-3-generic, 
gfx11-generic, gfx12-generic{{$}}
 
 // RUN: not %clang_cc1 -triple r600--- -target-cpu not-a-cpu -fsyntax-only %s 
2>&1 | FileCheck %s --check-prefix R600
 // R600:

[clang] AMDGPU: Add missing gfx* generic targets handling in clang (NVPTX, OpenMP runtime) (PR #94483)

2024-06-05 Thread Konstantin Zhuravlyov via cfe-commits 

https://github.com/kzhuravl created 
https://github.com/llvm/llvm-project/pull/94483

None

>From 7d64f16e9bdc6b9a195a332a49e5fb9954d5f7c1 Mon Sep 17 00:00:00 2001
From: Konstantin Zhuravlyov 
Date: Wed, 5 Jun 2024 11:10:41 -0400
Subject: [PATCH] AMDGPU: Add missing gfx* generic targets handling in clang
 (NVPTX, OpenMP runtime)

---
 clang/include/clang/Basic/Cuda.h  | 5 +
 clang/lib/Basic/Cuda.cpp  | 5 +
 clang/lib/Basic/Targets/NVPTX.cpp | 5 +
 clang/lib/CodeGen/CGOpenMPRuntimeGPU.cpp  | 5 +
 clang/test/Misc/target-invalid-cpu-note.c | 2 +-
 5 files changed, 21 insertions(+), 1 deletion(-)

diff --git a/clang/include/clang/Basic/Cuda.h b/clang/include/clang/Basic/Cuda.h
index 2d67c4181d129..2e126cdbca000 100644
--- a/clang/include/clang/Basic/Cuda.h
+++ b/clang/include/clang/Basic/Cuda.h
@@ -121,6 +121,11 @@ enum class CudaArch {
   GFX1151,
   GFX1200,
   GFX1201,
+  GFX9_GENERIC,
+  GFX10_1_GENERIC,
+  GFX10_3_GENERIC,
+  GFX11_GENERIC,
+  GFX12_GENERIC,
   Generic, // A processor model named 'generic' if the target backend defines a
// public one.
   LAST,
diff --git a/clang/lib/Basic/Cuda.cpp b/clang/lib/Basic/Cuda.cpp
index e8ce15eb0decb..f8e02af599ba9 100644
--- a/clang/lib/Basic/Cuda.cpp
+++ b/clang/lib/Basic/Cuda.cpp
@@ -141,6 +141,11 @@ static const CudaArchToStringMap arch_names[] = {
 GFX(1151), // gfx1151
 GFX(1200), // gfx1200
 GFX(1201), // gfx1201
+{CudaArch::GFX9_GENERIC, "gfx9-generic", "compute_amdgcn"},
+{CudaArch::GFX10_1_GENERIC, "gfx10-1-generic", "compute_amdgcn"},
+{CudaArch::GFX10_3_GENERIC, "gfx10-3-generic", "compute_amdgcn"},
+{CudaArch::GFX11_GENERIC, "gfx11-generic", "compute_amdgcn"},
+{CudaArch::GFX12_GENERIC, "gfx12-generic", "compute_amdgcn"},
 {CudaArch::Generic, "generic", ""},
 // clang-format on
 };
diff --git a/clang/lib/Basic/Targets/NVPTX.cpp 
b/clang/lib/Basic/Targets/NVPTX.cpp
index 8ad9e6e5f5891..d4249a617b45c 100644
--- a/clang/lib/Basic/Targets/NVPTX.cpp
+++ b/clang/lib/Basic/Targets/NVPTX.cpp
@@ -226,6 +226,11 @@ void NVPTXTargetInfo::getTargetDefines(const LangOptions 
,
   case CudaArch::GFX1151:
   case CudaArch::GFX1200:
   case CudaArch::GFX1201:
+  case CudaArch::GFX9_GENERIC:
+  case CudaArch::GFX10_1_GENERIC:
+  case CudaArch::GFX10_3_GENERIC:
+  case CudaArch::GFX11_GENERIC:
+  case CudaArch::GFX12_GENERIC:
   case CudaArch::Generic:
   case CudaArch::LAST:
 break;
diff --git a/clang/lib/CodeGen/CGOpenMPRuntimeGPU.cpp 
b/clang/lib/CodeGen/CGOpenMPRuntimeGPU.cpp
index 28da8662f5f61..c4905f7f8b595 100644
--- a/clang/lib/CodeGen/CGOpenMPRuntimeGPU.cpp
+++ b/clang/lib/CodeGen/CGOpenMPRuntimeGPU.cpp
@@ -3535,6 +3535,11 @@ void CGOpenMPRuntimeGPU::processRequiresDirective(
   case CudaArch::GFX1151:
   case CudaArch::GFX1200:
   case CudaArch::GFX1201:
+  case CudaArch::GFX9_GENERIC:
+  case CudaArch::GFX10_1_GENERIC:
+  case CudaArch::GFX10_3_GENERIC:
+  case CudaArch::GFX11_GENERIC:
+  case CudaArch::GFX12_GENERIC:
   case CudaArch::Generic:
   case CudaArch::UNUSED:
   case CudaArch::UNKNOWN:
diff --git a/clang/test/Misc/target-invalid-cpu-note.c 
b/clang/test/Misc/target-invalid-cpu-note.c
index 6558fd753d1d1..d610f58b9c4ec 100644
--- a/clang/test/Misc/target-invalid-cpu-note.c
+++ b/clang/test/Misc/target-invalid-cpu-note.c
@@ -29,7 +29,7 @@
 
 // RUN: not %clang_cc1 -triple nvptx--- -target-cpu not-a-cpu -fsyntax-only %s 
2>&1 | FileCheck %s --check-prefix NVPTX
 // NVPTX: error: unknown target CPU 'not-a-cpu'
-// NVPTX-NEXT: note: valid target CPU values are: sm_20, sm_21, sm_30, sm_32, 
sm_35, sm_37, sm_50, sm_52, sm_53, sm_60, sm_61, sm_62, sm_70, sm_72, sm_75, 
sm_80, sm_86, sm_87, sm_89, sm_90, sm_90a, gfx600, gfx601, gfx602, gfx700, 
gfx701, gfx702, gfx703, gfx704, gfx705, gfx801, gfx802, gfx803, gfx805, gfx810, 
gfx900, gfx902, gfx904, gfx906, gfx908, gfx909, gfx90a, gfx90c, gfx940, gfx941, 
gfx942, gfx1010, gfx1011, gfx1012, gfx1013, gfx1030, gfx1031, gfx1032, gfx1033, 
gfx1034, gfx1035, gfx1036, gfx1100, gfx1101, gfx1102, gfx1103, gfx1150, 
gfx1151, gfx1200, gfx1201{{$}}
+// NVPTX-NEXT: note: valid target CPU values are: sm_20, sm_21, sm_30, sm_32, 
sm_35, sm_37, sm_50, sm_52, sm_53, sm_60, sm_61, sm_62, sm_70, sm_72, sm_75, 
sm_80, sm_86, sm_87, sm_89, sm_90, sm_90a, gfx600, gfx601, gfx602, gfx700, 
gfx701, gfx702, gfx703, gfx704, gfx705, gfx801, gfx802, gfx803, gfx805, gfx810, 
gfx900, gfx902, gfx904, gfx906, gfx908, gfx909, gfx90a, gfx90c, gfx940, gfx941, 
gfx942, gfx1010, gfx1011, gfx1012, gfx1013, gfx1030, gfx1031, gfx1032, gfx1033, 
gfx1034, gfx1035, gfx1036, gfx1100, gfx1101, gfx1102, gfx1103, gfx1150, 
gfx1151, gfx1200, gfx1201, gfx9-generic, gfx10-1-generic, gfx10-3-generic, 
gfx11-generic, gfx12-generic{{$}}
 
 // RUN: not %clang_cc1 -triple r600--- -target-cpu not-a-cpu -fsyntax-only %s 
2>&1 | FileCheck %s --check-prefix R600
 // R600:

[clang] [llvm] AMDGPU: Add gfx12-generic target (PR #93875)

2024-05-31 Thread Konstantin Zhuravlyov via cfe-commits 

https://github.com/kzhuravl closed 
https://github.com/llvm/llvm-project/pull/93875
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[clang] [llvm] AMDGPU: Add gfx12-generic target (PR #93875)

2024-05-30 Thread Konstantin Zhuravlyov via cfe-commits 

https://github.com/kzhuravl updated 
https://github.com/llvm/llvm-project/pull/93875

>From be005a9baf0e7f0ae7b28b96ef7e562158800af4 Mon Sep 17 00:00:00 2001
From: Konstantin Zhuravlyov 
Date: Thu, 30 May 2024 16:27:42 -0400
Subject: [PATCH 1/3] AMDGPU: Add gfx12-generic target

---
 clang/test/Driver/amdgpu-macros.cl| 1 +
 clang/test/Driver/amdgpu-mcpu.cl  | 2 ++
 clang/test/Misc/target-invalid-cpu-note.c | 2 +-
 llvm/docs/AMDGPUUsage.rst | 8 
 llvm/include/llvm/BinaryFormat/ELF.h  | 3 ++-
 llvm/include/llvm/TargetParser/TargetParser.h | 3 ++-
 llvm/lib/Object/ELFObjectFile.cpp | 2 ++
 llvm/lib/ObjectYAML/ELFYAML.cpp   | 1 +
 llvm/lib/Target/AMDGPU/AMDGPU.td  | 4 
 llvm/lib/Target/AMDGPU/GCNProcessors.td   | 7 +--
 .../Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp   | 5 +
 llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h | 1 +
 llvm/lib/TargetParser/TargetParser.cpp| 6 ++
 llvm/test/CodeGen/AMDGPU/directive-amdgcn-target.ll   | 2 ++
 llvm/test/CodeGen/AMDGPU/elf-header-flags-mach.ll | 2 ++
 llvm/test/CodeGen/AMDGPU/generic-targets-require-v6.ll| 3 +++
 llvm/test/CodeGen/AMDGPU/hsa-generic-target-features.ll   | 2 ++
 llvm/test/Object/AMDGPU/elf-header-flags-mach.yaml| 7 +++
 llvm/test/tools/llvm-objdump/ELF/AMDGPU/subtarget.ll  | 5 +
 llvm/test/tools/llvm-readobj/ELF/AMDGPU/elf-headers.test  | 3 +++
 llvm/tools/llvm-readobj/ELFDumper.cpp | 3 ++-
 21 files changed, 66 insertions(+), 6 deletions(-)

diff --git a/clang/test/Driver/amdgpu-macros.cl 
b/clang/test/Driver/amdgpu-macros.cl
index 004619321b271..3dbe10dfcf1dc 100644
--- a/clang/test/Driver/amdgpu-macros.cl
+++ b/clang/test/Driver/amdgpu-macros.cl
@@ -135,6 +135,7 @@
 // RUN: %clang -E -dM -target amdgcn -mcpu=gfx10-1-generic %s 2>&1 | FileCheck 
--check-prefixes=ARCH-GCN,FAST_FMAF %s -DWAVEFRONT_SIZE=32 
-DCPU=gfx10_1_generic -DFAMILY=GFX10
 // RUN: %clang -E -dM -target amdgcn -mcpu=gfx10-3-generic %s 2>&1 | FileCheck 
--check-prefixes=ARCH-GCN,FAST_FMAF %s -DWAVEFRONT_SIZE=32 
-DCPU=gfx10_3_generic -DFAMILY=GFX10
 // RUN: %clang -E -dM -target amdgcn -mcpu=gfx11-generic %s 2>&1 | FileCheck 
--check-prefixes=ARCH-GCN,FAST_FMAF %s -DWAVEFRONT_SIZE=32 -DCPU=gfx11_generic 
-DFAMILY=GFX11
+// RUN: %clang -E -dM -target amdgcn -mcpu=gfx12-generic %s 2>&1 | FileCheck 
--check-prefixes=ARCH-GCN,FAST_FMAF %s -DWAVEFRONT_SIZE=32 -DCPU=gfx12_generic 
-DFAMILY=GFX12
 
 // ARCH-GCN-DAG: #define FP_FAST_FMA 1
 
diff --git a/clang/test/Driver/amdgpu-mcpu.cl b/clang/test/Driver/amdgpu-mcpu.cl
index 915fa6473ac07..5b6a22016f043 100644
--- a/clang/test/Driver/amdgpu-mcpu.cl
+++ b/clang/test/Driver/amdgpu-mcpu.cl
@@ -119,6 +119,7 @@
 // RUN: %clang -### -target amdgcn -mcpu=gfx10-1-generic %s 2>&1 | FileCheck 
--check-prefix=GFX10_1_GENERIC %s
 // RUN: %clang -### -target amdgcn -mcpu=gfx10-3-generic %s 2>&1 | FileCheck 
--check-prefix=GFX10_3_GENERIC %s
 // RUN: %clang -### -target amdgcn -mcpu=gfx11-generic %s 2>&1 | FileCheck 
--check-prefix=GFX11_GENERIC %s
+// RUN: %clang -### -target amdgcn -mcpu=gfx12-generic %s 2>&1 | FileCheck 
--check-prefix=GFX12_GENERIC %s
 
 // GCNDEFAULT-NOT: -target-cpu
 // GFX600:"-target-cpu" "gfx600"
@@ -170,3 +171,4 @@
 // GFX10_1_GENERIC:   "-target-cpu" "gfx10-1-generic"
 // GFX10_3_GENERIC:   "-target-cpu" "gfx10-3-generic"
 // GFX11_GENERIC: "-target-cpu" "gfx11-generic"
+// GFX12_GENERIC: "-target-cpu" "gfx12-generic"
diff --git a/clang/test/Misc/target-invalid-cpu-note.c 
b/clang/test/Misc/target-invalid-cpu-note.c
index 768b243b04e3a..6558fd753d1d1 100644
--- a/clang/test/Misc/target-invalid-cpu-note.c
+++ b/clang/test/Misc/target-invalid-cpu-note.c
@@ -37,7 +37,7 @@
 
 // RUN: not %clang_cc1 -triple amdgcn--- -target-cpu not-a-cpu -fsyntax-only 
%s 2>&1 | FileCheck %s --check-prefix AMDGCN
 // AMDGCN: error: unknown target CPU 'not-a-cpu'
-// AMDGCN-NEXT: note: valid target CPU values are: gfx600, tahiti, gfx601, 
pitcairn, verde, gfx602, hainan, oland, gfx700, kaveri, gfx701, hawaii, gfx702, 
gfx703, kabini, mullins, gfx704, bonaire, gfx705, gfx801, carrizo, gfx802, 
iceland, tonga, gfx803, fiji, polaris10, polaris11, gfx805, tongapro, gfx810, 
stoney, gfx900, gfx902, gfx904, gfx906, gfx908, gfx909, gfx90a, gfx90c, gfx940, 
gfx941, gfx942, gfx1010, gfx1011, gfx1012, gfx1013, gfx1030, gfx1031, gfx1032, 
gfx1033, gfx1034, gfx1035, gfx1036, gfx1100, gfx1101, gfx1102, gfx1103, 
gfx1150, gfx1151, gfx1200, gfx1201, gfx9-generic, gfx10-1-generic, 
gfx10-3-generic, gfx11-generic{{$}}
+// AMDGCN-NEXT: note: valid target CPU values are: gfx600, tahiti, gfx601, 
pitcairn, verde, gfx602, hainan, oland, gfx700, kaveri, gfx701, hawaii, gfx702, 
gfx703, kabini, mullins, gfx704, bonaire, gfx705,

[clang] [llvm] AMDGPU: Add gfx12-generic target (PR #93875)

2024-05-30 Thread Konstantin Zhuravlyov via cfe-commits 

https://github.com/kzhuravl updated 
https://github.com/llvm/llvm-project/pull/93875

>From be005a9baf0e7f0ae7b28b96ef7e562158800af4 Mon Sep 17 00:00:00 2001
From: Konstantin Zhuravlyov 
Date: Thu, 30 May 2024 16:27:42 -0400
Subject: [PATCH 1/2] AMDGPU: Add gfx12-generic target

---
 clang/test/Driver/amdgpu-macros.cl| 1 +
 clang/test/Driver/amdgpu-mcpu.cl  | 2 ++
 clang/test/Misc/target-invalid-cpu-note.c | 2 +-
 llvm/docs/AMDGPUUsage.rst | 8 
 llvm/include/llvm/BinaryFormat/ELF.h  | 3 ++-
 llvm/include/llvm/TargetParser/TargetParser.h | 3 ++-
 llvm/lib/Object/ELFObjectFile.cpp | 2 ++
 llvm/lib/ObjectYAML/ELFYAML.cpp   | 1 +
 llvm/lib/Target/AMDGPU/AMDGPU.td  | 4 
 llvm/lib/Target/AMDGPU/GCNProcessors.td   | 7 +--
 .../Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp   | 5 +
 llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h | 1 +
 llvm/lib/TargetParser/TargetParser.cpp| 6 ++
 llvm/test/CodeGen/AMDGPU/directive-amdgcn-target.ll   | 2 ++
 llvm/test/CodeGen/AMDGPU/elf-header-flags-mach.ll | 2 ++
 llvm/test/CodeGen/AMDGPU/generic-targets-require-v6.ll| 3 +++
 llvm/test/CodeGen/AMDGPU/hsa-generic-target-features.ll   | 2 ++
 llvm/test/Object/AMDGPU/elf-header-flags-mach.yaml| 7 +++
 llvm/test/tools/llvm-objdump/ELF/AMDGPU/subtarget.ll  | 5 +
 llvm/test/tools/llvm-readobj/ELF/AMDGPU/elf-headers.test  | 3 +++
 llvm/tools/llvm-readobj/ELFDumper.cpp | 3 ++-
 21 files changed, 66 insertions(+), 6 deletions(-)

diff --git a/clang/test/Driver/amdgpu-macros.cl 
b/clang/test/Driver/amdgpu-macros.cl
index 004619321b271..3dbe10dfcf1dc 100644
--- a/clang/test/Driver/amdgpu-macros.cl
+++ b/clang/test/Driver/amdgpu-macros.cl
@@ -135,6 +135,7 @@
 // RUN: %clang -E -dM -target amdgcn -mcpu=gfx10-1-generic %s 2>&1 | FileCheck 
--check-prefixes=ARCH-GCN,FAST_FMAF %s -DWAVEFRONT_SIZE=32 
-DCPU=gfx10_1_generic -DFAMILY=GFX10
 // RUN: %clang -E -dM -target amdgcn -mcpu=gfx10-3-generic %s 2>&1 | FileCheck 
--check-prefixes=ARCH-GCN,FAST_FMAF %s -DWAVEFRONT_SIZE=32 
-DCPU=gfx10_3_generic -DFAMILY=GFX10
 // RUN: %clang -E -dM -target amdgcn -mcpu=gfx11-generic %s 2>&1 | FileCheck 
--check-prefixes=ARCH-GCN,FAST_FMAF %s -DWAVEFRONT_SIZE=32 -DCPU=gfx11_generic 
-DFAMILY=GFX11
+// RUN: %clang -E -dM -target amdgcn -mcpu=gfx12-generic %s 2>&1 | FileCheck 
--check-prefixes=ARCH-GCN,FAST_FMAF %s -DWAVEFRONT_SIZE=32 -DCPU=gfx12_generic 
-DFAMILY=GFX12
 
 // ARCH-GCN-DAG: #define FP_FAST_FMA 1
 
diff --git a/clang/test/Driver/amdgpu-mcpu.cl b/clang/test/Driver/amdgpu-mcpu.cl
index 915fa6473ac07..5b6a22016f043 100644
--- a/clang/test/Driver/amdgpu-mcpu.cl
+++ b/clang/test/Driver/amdgpu-mcpu.cl
@@ -119,6 +119,7 @@
 // RUN: %clang -### -target amdgcn -mcpu=gfx10-1-generic %s 2>&1 | FileCheck 
--check-prefix=GFX10_1_GENERIC %s
 // RUN: %clang -### -target amdgcn -mcpu=gfx10-3-generic %s 2>&1 | FileCheck 
--check-prefix=GFX10_3_GENERIC %s
 // RUN: %clang -### -target amdgcn -mcpu=gfx11-generic %s 2>&1 | FileCheck 
--check-prefix=GFX11_GENERIC %s
+// RUN: %clang -### -target amdgcn -mcpu=gfx12-generic %s 2>&1 | FileCheck 
--check-prefix=GFX12_GENERIC %s
 
 // GCNDEFAULT-NOT: -target-cpu
 // GFX600:"-target-cpu" "gfx600"
@@ -170,3 +171,4 @@
 // GFX10_1_GENERIC:   "-target-cpu" "gfx10-1-generic"
 // GFX10_3_GENERIC:   "-target-cpu" "gfx10-3-generic"
 // GFX11_GENERIC: "-target-cpu" "gfx11-generic"
+// GFX12_GENERIC: "-target-cpu" "gfx12-generic"
diff --git a/clang/test/Misc/target-invalid-cpu-note.c 
b/clang/test/Misc/target-invalid-cpu-note.c
index 768b243b04e3a..6558fd753d1d1 100644
--- a/clang/test/Misc/target-invalid-cpu-note.c
+++ b/clang/test/Misc/target-invalid-cpu-note.c
@@ -37,7 +37,7 @@
 
 // RUN: not %clang_cc1 -triple amdgcn--- -target-cpu not-a-cpu -fsyntax-only 
%s 2>&1 | FileCheck %s --check-prefix AMDGCN
 // AMDGCN: error: unknown target CPU 'not-a-cpu'
-// AMDGCN-NEXT: note: valid target CPU values are: gfx600, tahiti, gfx601, 
pitcairn, verde, gfx602, hainan, oland, gfx700, kaveri, gfx701, hawaii, gfx702, 
gfx703, kabini, mullins, gfx704, bonaire, gfx705, gfx801, carrizo, gfx802, 
iceland, tonga, gfx803, fiji, polaris10, polaris11, gfx805, tongapro, gfx810, 
stoney, gfx900, gfx902, gfx904, gfx906, gfx908, gfx909, gfx90a, gfx90c, gfx940, 
gfx941, gfx942, gfx1010, gfx1011, gfx1012, gfx1013, gfx1030, gfx1031, gfx1032, 
gfx1033, gfx1034, gfx1035, gfx1036, gfx1100, gfx1101, gfx1102, gfx1103, 
gfx1150, gfx1151, gfx1200, gfx1201, gfx9-generic, gfx10-1-generic, 
gfx10-3-generic, gfx11-generic{{$}}
+// AMDGCN-NEXT: note: valid target CPU values are: gfx600, tahiti, gfx601, 
pitcairn, verde, gfx602, hainan, oland, gfx700, kaveri, gfx701, hawaii, gfx702, 
gfx703, kabini, mullins, gfx704, bonaire, gfx705,

[clang] [llvm] AMDGPU: Add gfx12-generic target (PR #93875)

2024-05-30 Thread Konstantin Zhuravlyov via cfe-commits 

https://github.com/kzhuravl created 
https://github.com/llvm/llvm-project/pull/93875

None

>From be005a9baf0e7f0ae7b28b96ef7e562158800af4 Mon Sep 17 00:00:00 2001
From: Konstantin Zhuravlyov 
Date: Thu, 30 May 2024 16:27:42 -0400
Subject: [PATCH] AMDGPU: Add gfx12-generic target

---
 clang/test/Driver/amdgpu-macros.cl| 1 +
 clang/test/Driver/amdgpu-mcpu.cl  | 2 ++
 clang/test/Misc/target-invalid-cpu-note.c | 2 +-
 llvm/docs/AMDGPUUsage.rst | 8 
 llvm/include/llvm/BinaryFormat/ELF.h  | 3 ++-
 llvm/include/llvm/TargetParser/TargetParser.h | 3 ++-
 llvm/lib/Object/ELFObjectFile.cpp | 2 ++
 llvm/lib/ObjectYAML/ELFYAML.cpp   | 1 +
 llvm/lib/Target/AMDGPU/AMDGPU.td  | 4 
 llvm/lib/Target/AMDGPU/GCNProcessors.td   | 7 +--
 .../Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp   | 5 +
 llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h | 1 +
 llvm/lib/TargetParser/TargetParser.cpp| 6 ++
 llvm/test/CodeGen/AMDGPU/directive-amdgcn-target.ll   | 2 ++
 llvm/test/CodeGen/AMDGPU/elf-header-flags-mach.ll | 2 ++
 llvm/test/CodeGen/AMDGPU/generic-targets-require-v6.ll| 3 +++
 llvm/test/CodeGen/AMDGPU/hsa-generic-target-features.ll   | 2 ++
 llvm/test/Object/AMDGPU/elf-header-flags-mach.yaml| 7 +++
 llvm/test/tools/llvm-objdump/ELF/AMDGPU/subtarget.ll  | 5 +
 llvm/test/tools/llvm-readobj/ELF/AMDGPU/elf-headers.test  | 3 +++
 llvm/tools/llvm-readobj/ELFDumper.cpp | 3 ++-
 21 files changed, 66 insertions(+), 6 deletions(-)

diff --git a/clang/test/Driver/amdgpu-macros.cl 
b/clang/test/Driver/amdgpu-macros.cl
index 004619321b271..3dbe10dfcf1dc 100644
--- a/clang/test/Driver/amdgpu-macros.cl
+++ b/clang/test/Driver/amdgpu-macros.cl
@@ -135,6 +135,7 @@
 // RUN: %clang -E -dM -target amdgcn -mcpu=gfx10-1-generic %s 2>&1 | FileCheck 
--check-prefixes=ARCH-GCN,FAST_FMAF %s -DWAVEFRONT_SIZE=32 
-DCPU=gfx10_1_generic -DFAMILY=GFX10
 // RUN: %clang -E -dM -target amdgcn -mcpu=gfx10-3-generic %s 2>&1 | FileCheck 
--check-prefixes=ARCH-GCN,FAST_FMAF %s -DWAVEFRONT_SIZE=32 
-DCPU=gfx10_3_generic -DFAMILY=GFX10
 // RUN: %clang -E -dM -target amdgcn -mcpu=gfx11-generic %s 2>&1 | FileCheck 
--check-prefixes=ARCH-GCN,FAST_FMAF %s -DWAVEFRONT_SIZE=32 -DCPU=gfx11_generic 
-DFAMILY=GFX11
+// RUN: %clang -E -dM -target amdgcn -mcpu=gfx12-generic %s 2>&1 | FileCheck 
--check-prefixes=ARCH-GCN,FAST_FMAF %s -DWAVEFRONT_SIZE=32 -DCPU=gfx12_generic 
-DFAMILY=GFX12
 
 // ARCH-GCN-DAG: #define FP_FAST_FMA 1
 
diff --git a/clang/test/Driver/amdgpu-mcpu.cl b/clang/test/Driver/amdgpu-mcpu.cl
index 915fa6473ac07..5b6a22016f043 100644
--- a/clang/test/Driver/amdgpu-mcpu.cl
+++ b/clang/test/Driver/amdgpu-mcpu.cl
@@ -119,6 +119,7 @@
 // RUN: %clang -### -target amdgcn -mcpu=gfx10-1-generic %s 2>&1 | FileCheck 
--check-prefix=GFX10_1_GENERIC %s
 // RUN: %clang -### -target amdgcn -mcpu=gfx10-3-generic %s 2>&1 | FileCheck 
--check-prefix=GFX10_3_GENERIC %s
 // RUN: %clang -### -target amdgcn -mcpu=gfx11-generic %s 2>&1 | FileCheck 
--check-prefix=GFX11_GENERIC %s
+// RUN: %clang -### -target amdgcn -mcpu=gfx12-generic %s 2>&1 | FileCheck 
--check-prefix=GFX12_GENERIC %s
 
 // GCNDEFAULT-NOT: -target-cpu
 // GFX600:"-target-cpu" "gfx600"
@@ -170,3 +171,4 @@
 // GFX10_1_GENERIC:   "-target-cpu" "gfx10-1-generic"
 // GFX10_3_GENERIC:   "-target-cpu" "gfx10-3-generic"
 // GFX11_GENERIC: "-target-cpu" "gfx11-generic"
+// GFX12_GENERIC: "-target-cpu" "gfx12-generic"
diff --git a/clang/test/Misc/target-invalid-cpu-note.c 
b/clang/test/Misc/target-invalid-cpu-note.c
index 768b243b04e3a..6558fd753d1d1 100644
--- a/clang/test/Misc/target-invalid-cpu-note.c
+++ b/clang/test/Misc/target-invalid-cpu-note.c
@@ -37,7 +37,7 @@
 
 // RUN: not %clang_cc1 -triple amdgcn--- -target-cpu not-a-cpu -fsyntax-only 
%s 2>&1 | FileCheck %s --check-prefix AMDGCN
 // AMDGCN: error: unknown target CPU 'not-a-cpu'
-// AMDGCN-NEXT: note: valid target CPU values are: gfx600, tahiti, gfx601, 
pitcairn, verde, gfx602, hainan, oland, gfx700, kaveri, gfx701, hawaii, gfx702, 
gfx703, kabini, mullins, gfx704, bonaire, gfx705, gfx801, carrizo, gfx802, 
iceland, tonga, gfx803, fiji, polaris10, polaris11, gfx805, tongapro, gfx810, 
stoney, gfx900, gfx902, gfx904, gfx906, gfx908, gfx909, gfx90a, gfx90c, gfx940, 
gfx941, gfx942, gfx1010, gfx1011, gfx1012, gfx1013, gfx1030, gfx1031, gfx1032, 
gfx1033, gfx1034, gfx1035, gfx1036, gfx1100, gfx1101, gfx1102, gfx1103, 
gfx1150, gfx1151, gfx1200, gfx1201, gfx9-generic, gfx10-1-generic, 
gfx10-3-generic, gfx11-generic{{$}}
+// AMDGCN-NEXT: note: valid target CPU values are: gfx600, tahiti, gfx601, 
pitcairn, verde, gfx602, hainan, oland, gfx700, kaveri, gfx701, hawaii, gfx702, 
gfx703, kabini, mullins, gfx704, bonaire, gfx705,

[clang] [llvm] [AMDGPU] Replace '.' with '-' in generic target names (PR #81718)

2024-02-14 Thread Konstantin Zhuravlyov via cfe-commits 

https://github.com/kzhuravl approved this pull request.

Thanks!

https://github.com/llvm/llvm-project/pull/81718
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[llvm] [clang] [lld] [flang] [AMDGPU] Introduce Code Object V6 (PR #76954)

2024-02-01 Thread Konstantin Zhuravlyov via cfe-commits 

https://github.com/kzhuravl approved this pull request.

Looks good, thanks!

https://github.com/llvm/llvm-project/pull/76954
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[clang] [flang] [llvm] [lld] [AMDGPU] Introduce GFX9/10.1/10.3/11 Generic Targets (PR #76955)

2024-02-01 Thread Konstantin Zhuravlyov via cfe-commits 

https://github.com/kzhuravl edited 
https://github.com/llvm/llvm-project/pull/76955
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[lld] [flang] [clang] [llvm] [AMDGPU] Introduce GFX9/10.1/10.3/11 Generic Targets (PR #76955)

2024-02-01 Thread Konstantin Zhuravlyov via cfe-commits 

https://github.com/kzhuravl approved this pull request.

LGTM! Thanks!

https://github.com/llvm/llvm-project/pull/76955
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[clang] [llvm] [flang] [lld] [AMDGPU] Introduce Code Object V6 (PR #76954)

2024-01-30 Thread Konstantin Zhuravlyov via cfe-commits 


@@ -44,8 +44,15 @@ constexpr uint32_t VersionMajorV5 = 1;
 /// HSA metadata minor version for code object V5.
 constexpr uint32_t VersionMinorV5 = 2;
 
+/// HSA metadata major version for code object V6.
+constexpr uint32_t VersionMajorV6 = 1;
+/// HSA metadata minor version for code object V6.
+constexpr uint32_t VersionMinorV6 = 3;

kzhuravl wrote:

As of now, there are no changes planned to the MD for v6

https://github.com/llvm/llvm-project/pull/76954
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[lld] [flang] [llvm] [clang] [AMDGPU] Introduce GFX9/10.1/10.3/11 Generic Targets (PR #76955)

2024-01-25 Thread Konstantin Zhuravlyov via cfe-commits 


@@ -49,6 +49,11 @@ constexpr uint32_t VersionMajorV5 = 1;
 /// HSA metadata minor version for code object V5.
 constexpr uint32_t VersionMinorV5 = 2;
 
+/// HSA metadata major version for code object V6.
+constexpr uint32_t VersionMajorV6 = 1;
+/// HSA metadata minor version for code object V6.
+constexpr uint32_t VersionMinorV6 = 3;

kzhuravl wrote:

@AlexVlx, this "HSA Metadata" is AMD-specific "HSA Metadata", so it is not part 
of the HSA standards. Maybe updating the comment to mention it is AMD-specific 
should be done.

I'd also prefer to not update the metadata version unless we change it.

https://github.com/llvm/llvm-project/pull/76955
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[clang] [lld] [flang] [llvm] [AMDGPU] Introduce GFX9/10.1/10.3/11 Generic Targets (PR #76955)

2024-01-24 Thread Konstantin Zhuravlyov via cfe-commits 


@@ -4135,6 +4283,33 @@ Code object V5 metadata is the same as
 
  == == = 

 
+.. _amdgpu-amdhsa-code-object-metadata-v6:
+
+Code Object V6 Metadata

+
+.. warning::
+  Code object V6 is not the default code object version emitted by this version
+  of LLVM.
+
+
+Code object V6 metadata is the same as
+:ref:`amdgpu-amdhsa-code-object-metadata-v5` with the changes defined in table
+:ref:`amdgpu-amdhsa-code-object-metadata-map-table-v6`.
+
+  .. table:: AMDHSA Code Object V6 Metadata Map Changes
+ :name: amdgpu-amdhsa-code-object-metadata-map-table-v6
+
+ = == = 
===
+ String KeyValue Type Required? Description
+ = == = 
===
+ "amdhsa.version"  sequence ofRequired  - The first integer is the 
major

kzhuravl wrote:

I'd probably drop metadata version bump unless we change it.

https://github.com/llvm/llvm-project/pull/76955
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[clang] [lld] [flang] [llvm] [AMDGPU] Introduce GFX9/10.1/10.3/11 Generic Targets (PR #76955)

2024-01-24 Thread Konstantin Zhuravlyov via cfe-commits 


@@ -520,6 +520,106 @@ Every processor supports every OS ABI (see 
:ref:`amdgpu-os`) with the following
 
  === ===  = = 
=== === ==
 
+Generic processors also exist. They group multiple processors into one,
+allowing to build code once and run it on multiple targets at the cost
+of less features being available.
+
+Generic processors are only available on Code Object V6 and up.
+
+  .. table:: AMDGPU Generic Processors
+ :name: amdgpu-generic-processor-table
+
+  == = 
=
+ Processor TargetSupported Target
+   TripleProcessorsFeatures
+   ArchitectureRestrictions
+
+
+
+
+
+
+
+
+  == = 
=
+ ``gfx9-generic`` ``amdgcn`` - ``gfx900``  - ``v_mad_mix`` 
instructions
+ - ``gfx902``are not available 
on
+ - ``gfx904````gfx900``, 
``gfx902``,
+ - ``gfx906````gfx909``, 
``gfx90c``
+ - ``gfx909``  - ``v_fma_mix`` 
instructions
+ - ``gfx90c``are not available 
on ``gfx904``
+   - sramecc is not 
available on

kzhuravl wrote:

Discussed with @Pierre-vh offline. @Pierre-vh will add a test making sure no 
d16 instructions produced for generic-gfx9.

https://github.com/llvm/llvm-project/pull/76955
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[clang] [lld] [flang] [llvm] [AMDGPU] Introduce GFX9/10.1/10.3/11 Generic Targets (PR #76955)

2024-01-24 Thread Konstantin Zhuravlyov via cfe-commits 


@@ -253,6 +274,12 @@ AMDGPU::IsaVersion AMDGPU::getIsaVersion(StringRef GPU) {
   case GK_GFX1151: return {11, 5, 1};
   case GK_GFX1200: return {12, 0, 0};
   case GK_GFX1201: return {12, 0, 1};
+
+  // Generic targets use the earliest ISA version in their group.

kzhuravl wrote:

Ok, works for me for now.

> should probably be refactored IMO

Agreed.

https://github.com/llvm/llvm-project/pull/76955
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[clang] [lld] [flang] [llvm] [AMDGPU] Introduce Code Object V6 (PR #76954)

2024-01-24 Thread Konstantin Zhuravlyov via cfe-commits 


@@ -620,6 +620,15 @@ void ScalarBitSetTraits::bitset(IO ,
   BCase(EF_AMDGPU_FEATURE_XNACK_V3);
   BCase(EF_AMDGPU_FEATURE_SRAMECC_V3);
   break;
+case ELF::ELFABIVERSION_AMDGPU_HSA_V6:

kzhuravl wrote:

I think we'd need to add a test for this?

https://github.com/llvm/llvm-project/pull/76954
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[flang] [lld] [llvm] [clang] [AMDGPU] Introduce Code Object V6 (PR #76954)

2024-01-24 Thread Konstantin Zhuravlyov via cfe-commits 


@@ -44,8 +44,15 @@ constexpr uint32_t VersionMajorV5 = 1;
 /// HSA metadata minor version for code object V5.
 constexpr uint32_t VersionMinorV5 = 2;
 
+/// HSA metadata major version for code object V6.
+constexpr uint32_t VersionMajorV6 = 1;
+/// HSA metadata minor version for code object V6.
+constexpr uint32_t VersionMinorV6 = 3;

kzhuravl wrote:

Did anything change in metadata?

https://github.com/llvm/llvm-project/pull/76954
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[lld] [clang] [flang] [llvm] [AMDGPU] Introduce Code Object V6 (PR #76954)

2024-01-24 Thread Konstantin Zhuravlyov via cfe-commits 


@@ -2585,7 +2585,7 @@ getAMDGPUCodeObjectArgument(const Driver , const 
llvm::opt::ArgList ) {
 void tools::checkAMDGPUCodeObjectVersion(const Driver ,
  const llvm::opt::ArgList ) {
   const unsigned MinCodeObjVer = 4;
-  const unsigned MaxCodeObjVer = 5;
+  const unsigned MaxCodeObjVer = 6;

kzhuravl wrote:

I think it is a good idea.

https://github.com/llvm/llvm-project/pull/76954
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[clang] [lld] [flang] [llvm] [AMDGPU] Introduce GFX9/10.1/10.3/11 Generic Targets (PR #76955)

2024-01-17 Thread Konstantin Zhuravlyov via cfe-commits 


@@ -253,6 +274,12 @@ AMDGPU::IsaVersion AMDGPU::getIsaVersion(StringRef GPU) {
   case GK_GFX1151: return {11, 5, 1};
   case GK_GFX1200: return {12, 0, 0};
   case GK_GFX1201: return {12, 0, 1};
+
+  // Generic targets use the earliest ISA version in their group.

kzhuravl wrote:

- maybe UINT32_MAX for the minor and stepping for gfx9-generic, gfx11-generic
- maybe UINT32_MAX for the stepping for gfx10.1 and gfx10.3

thoughts?

https://github.com/llvm/llvm-project/pull/76955
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[clang] [lld] [flang] [llvm] [AMDGPU] Introduce GFX9/10.1/10.3/11 Generic Targets (PR #76955)

2024-01-17 Thread Konstantin Zhuravlyov via cfe-commits 

kzhuravl wrote:

@t-tye, can you please help reviewing the documentation?

https://github.com/llvm/llvm-project/pull/76955
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[clang] [lld] [flang] [llvm] [AMDGPU] Introduce GFX9/10.1/10.3/11 Generic Targets (PR #76955)

2024-01-17 Thread Konstantin Zhuravlyov via cfe-commits 

kzhuravl wrote:

@AlexVlx, can you please go over versioning?

https://github.com/llvm/llvm-project/pull/76955
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[clang] [lld] [flang] [llvm] [AMDGPU] Introduce GFX9/10.1/10.3/11 Generic Targets (PR #76955)

2024-01-17 Thread Konstantin Zhuravlyov via cfe-commits 

kzhuravl wrote:

> @arsenm Hi, can you take a look - especially on the testing? I don't know if 
> this is tested well enough

I have not looked at the tests thoroughly. Would adding tests that make sure 
trimmed features are not used in generics be beneficial? E.g. testing that 
generic-gfx9 does not have the dl-insts feature.

https://github.com/llvm/llvm-project/pull/76955
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[clang] [lld] [flang] [llvm] [AMDGPU] Introduce GFX9/10.1/10.3/11 Generic Targets (PR #76955)

2024-01-17 Thread Konstantin Zhuravlyov via cfe-commits 


@@ -280,6 +295,11 @@ def : ProcessorModel<"gfx1151", GFX11SpeedModel,
   FeatureISAVersion11_5_1.Features
 >;
 
+// [gfx1100, gfx1101, gfx1102, gfx1103, 1150, 1151]

kzhuravl wrote:

gfx1150, gfx1151

https://github.com/llvm/llvm-project/pull/76955
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[lld] [clang] [flang] [llvm] [AMDGPU] Introduce GFX9/10.1/10.3/11 Generic Targets (PR #76955)

2024-01-17 Thread Konstantin Zhuravlyov via cfe-commits 


@@ -787,11 +788,15 @@ enum : unsigned {
   EF_AMDGPU_MACH_AMDGCN_GFX942= 0x04c,
   EF_AMDGPU_MACH_AMDGCN_RESERVED_0X4D = 0x04d,
   EF_AMDGPU_MACH_AMDGCN_GFX1201   = 0x04e,
+  EF_AMDGPU_MACH_AMDGCN_GFX9_GENERIC  = 0x04f,

kzhuravl wrote:

If you could add 0x04f as "reserved" in this (or other, separate) PR, it would 
be great.

e.g. EF_AMDGPU_MACH_AMDGCN_RESERVED_0X4D

https://github.com/llvm/llvm-project/pull/76955
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[lld] [llvm] [flang] [clang] [AMDGPU] Introduce GFX9/10.1/10.3/11 Generic Targets (PR #76955)

2024-01-17 Thread Konstantin Zhuravlyov via cfe-commits 


@@ -253,6 +274,12 @@ AMDGPU::IsaVersion AMDGPU::getIsaVersion(StringRef GPU) {
   case GK_GFX1151: return {11, 5, 1};
   case GK_GFX1200: return {12, 0, 0};
   case GK_GFX1201: return {12, 0, 1};
+
+  // Generic targets use the earliest ISA version in their group.

kzhuravl wrote:

Should it use something else instead of the earliest ISA version? I am not sure 
what it would be, but it feels uneasy for some reason.

If we leave it "as is", can this be misused? E.g. getIsaVersion will return 
{9,0,0} for gfx9-generic, which got the madmix instructions, which is not in 
{9,0,4}.

https://github.com/llvm/llvm-project/pull/76955
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[flang] [clang] [lld] [llvm] [AMDGPU] Introduce GFX9/10.1/10.3/11 Generic Targets (PR #76955)

2024-01-17 Thread Konstantin Zhuravlyov via cfe-commits 


@@ -787,11 +788,15 @@ enum : unsigned {
   EF_AMDGPU_MACH_AMDGCN_GFX942= 0x04c,
   EF_AMDGPU_MACH_AMDGCN_RESERVED_0X4D = 0x04d,
   EF_AMDGPU_MACH_AMDGCN_GFX1201   = 0x04e,
+  EF_AMDGPU_MACH_AMDGCN_GFX9_GENERIC  = 0x04f,
+  EF_AMDGPU_MACH_AMDGCN_GFX10_1_GENERIC   = 0x050,

kzhuravl wrote:

If you could add 0x050 as "reserved" in this (or other, separate) PR, it would 
be great.

e.g. EF_AMDGPU_MACH_AMDGCN_RESERVED_0X4D

https://github.com/llvm/llvm-project/pull/76955
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[llvm] [flang] [clang] [lld] [AMDGPU] Introduce GFX9/10.1/10.3/11 Generic Targets (PR #76955)

2024-01-17 Thread Konstantin Zhuravlyov via cfe-commits 


@@ -49,6 +49,11 @@ constexpr uint32_t VersionMajorV5 = 1;
 /// HSA metadata minor version for code object V5.
 constexpr uint32_t VersionMinorV5 = 2;
 
+/// HSA metadata major version for code object V5.
+constexpr uint32_t VersionMajorV6 = 1;
+/// HSA metadata minor version for code object V5.

kzhuravl wrote:

Ditto.

https://github.com/llvm/llvm-project/pull/76955
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[clang] [lld] [llvm] [flang] [AMDGPU] Introduce GFX9/10.1/10.3/11 Generic Targets (PR #76955)

2024-01-17 Thread Konstantin Zhuravlyov via cfe-commits 


@@ -280,6 +295,11 @@ def : ProcessorModel<"gfx1151", GFX11SpeedModel,
   FeatureISAVersion11_5_1.Features
 >;
 
+// [gfx1100, gfx1101, gfx1102, gfx1103, 1150, 1151]
+def : ProcessorModel<"gfx11-generic", GFX11SpeedModel,
+  FeatureISAVersion11_Generic.Features
+>;
+
 
//===--===//
 // GCN GFX12.

kzhuravl wrote:

Can you add a "todo" for generic-gfx12 since gfx12 is still wip?

https://github.com/llvm/llvm-project/pull/76955
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[clang] [lld] [flang] [llvm] [AMDGPU] Introduce GFX9/10.1/10.3/11 Generic Targets (PR #76955)

2024-01-17 Thread Konstantin Zhuravlyov via cfe-commits 


@@ -787,11 +788,15 @@ enum : unsigned {
   EF_AMDGPU_MACH_AMDGCN_GFX942= 0x04c,
   EF_AMDGPU_MACH_AMDGCN_RESERVED_0X4D = 0x04d,
   EF_AMDGPU_MACH_AMDGCN_GFX1201   = 0x04e,
+  EF_AMDGPU_MACH_AMDGCN_GFX9_GENERIC  = 0x04f,
+  EF_AMDGPU_MACH_AMDGCN_GFX10_1_GENERIC   = 0x050,

kzhuravl wrote:

0x050 is already allocated for another target. So 0x050 should not be used.

https://github.com/llvm/llvm-project/pull/76955
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[lld] [clang] [llvm] [flang] [AMDGPU] Introduce GFX9/10.1/10.3/11 Generic Targets (PR #76955)

2024-01-17 Thread Konstantin Zhuravlyov via cfe-commits 


@@ -49,6 +49,11 @@ constexpr uint32_t VersionMajorV5 = 1;
 /// HSA metadata minor version for code object V5.
 constexpr uint32_t VersionMinorV5 = 2;
 
+/// HSA metadata major version for code object V5.

kzhuravl wrote:

Typo, did you mean V6?

https://github.com/llvm/llvm-project/pull/76955
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[flang] [clang] [lld] [llvm] [AMDGPU] Introduce GFX9/10.1/10.3/11 Generic Targets (PR #76955)

2024-01-17 Thread Konstantin Zhuravlyov via cfe-commits 


@@ -787,11 +788,15 @@ enum : unsigned {
   EF_AMDGPU_MACH_AMDGCN_GFX942= 0x04c,
   EF_AMDGPU_MACH_AMDGCN_RESERVED_0X4D = 0x04d,
   EF_AMDGPU_MACH_AMDGCN_GFX1201   = 0x04e,
+  EF_AMDGPU_MACH_AMDGCN_GFX9_GENERIC  = 0x04f,

kzhuravl wrote:

0x04f is already allocated for another target. So 0x04f should not be used.

https://github.com/llvm/llvm-project/pull/76955
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[flang] [clang] [llvm] [lld] [AMDGPU] Introduce GFX9/10.1/10.3/11 Generic Targets (PR #76955)

2024-01-17 Thread Konstantin Zhuravlyov via cfe-commits 


@@ -840,6 +845,12 @@ enum : unsigned {
   EF_AMDGPU_FEATURE_SRAMECC_OFF_V4 = 0x800,
   // SRAMECC is on.
   EF_AMDGPU_FEATURE_SRAMECC_ON_V4 = 0xc00,
+
+  // Generic target versioning. This is contained in the list byte of EFLAGS.

kzhuravl wrote:

Should the versioning be done as part of this PR? Or 
https://github.com/llvm/llvm-project/pull/76954?

https://github.com/llvm/llvm-project/pull/76955
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[clang] [AMDGPU] Remove Code Object V3 (PR #67118)

2023-10-10 Thread Konstantin Zhuravlyov via cfe-commits 

https://github.com/kzhuravl approved this pull request.

This LGTM. But wait a couple of days to see if @arsenm or @yxsamliu have any 
objections?

https://github.com/llvm/llvm-project/pull/67118
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[clang] 9d05727 - AMDGPU: Add basic gfx942 target

2023-05-10 Thread Konstantin Zhuravlyov via cfe-commits 

Author: Konstantin Zhuravlyov
Date: 2023-05-10T11:51:06-04:00
New Revision: 9d0572797233857397f3fdc35fffcfb490354f56

URL: 
https://github.com/llvm/llvm-project/commit/9d0572797233857397f3fdc35fffcfb490354f56
DIFF: 
https://github.com/llvm/llvm-project/commit/9d0572797233857397f3fdc35fffcfb490354f56.diff

LOG: AMDGPU: Add basic gfx942 target

Differential Revision: https://reviews.llvm.org/D149983

Added: 


Modified: 
clang/include/clang/Basic/Cuda.h
clang/lib/Basic/Cuda.cpp
clang/lib/Basic/Targets/NVPTX.cpp
clang/lib/CodeGen/CGOpenMPRuntimeGPU.cpp
clang/test/CodeGenOpenCL/amdgpu-features.cl
clang/test/Driver/amdgpu-macros.cl
clang/test/Driver/amdgpu-mcpu.cl
clang/test/Misc/target-invalid-cpu-note.c
llvm/docs/AMDGPUUsage.rst
llvm/include/llvm/BinaryFormat/ELF.h
llvm/include/llvm/TargetParser/TargetParser.h
llvm/lib/Object/ELFObjectFile.cpp
llvm/lib/ObjectYAML/ELFYAML.cpp
llvm/lib/Target/AMDGPU/AMDGPU.td
llvm/lib/Target/AMDGPU/GCNProcessors.td
llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp
llvm/lib/TargetParser/TargetParser.cpp
llvm/test/CodeGen/AMDGPU/directive-amdgcn-target.ll
llvm/test/CodeGen/AMDGPU/elf-header-flags-mach.ll
llvm/test/Object/AMDGPU/elf-header-flags-mach.yaml
llvm/test/tools/llvm-objdump/ELF/AMDGPU/subtarget.ll
llvm/test/tools/llvm-readobj/ELF/amdgpu-elf-headers.test
llvm/tools/llvm-readobj/ELFDumper.cpp

Removed: 




diff  --git a/clang/include/clang/Basic/Cuda.h 
b/clang/include/clang/Basic/Cuda.h
index dddbd651054da..2b8fc2a0bb1c3 100644
--- a/clang/include/clang/Basic/Cuda.h
+++ b/clang/include/clang/Basic/Cuda.h
@@ -93,6 +93,7 @@ enum class CudaArch {
   GFX90c,
   GFX940,
   GFX941,
+  GFX942,
   GFX1010,
   GFX1011,
   GFX1012,

diff  --git a/clang/lib/Basic/Cuda.cpp b/clang/lib/Basic/Cuda.cpp
index baca1106b263b..db30142ad866d 100644
--- a/clang/lib/Basic/Cuda.cpp
+++ b/clang/lib/Basic/Cuda.cpp
@@ -115,6 +115,7 @@ static const CudaArchToStringMap arch_names[] = {
 GFX(90c),  // gfx90c
 GFX(940),  // gfx940
 GFX(941),  // gfx941
+GFX(942),  // gfx942
 GFX(1010), // gfx1010
 GFX(1011), // gfx1011
 GFX(1012), // gfx1012

diff  --git a/clang/lib/Basic/Targets/NVPTX.cpp 
b/clang/lib/Basic/Targets/NVPTX.cpp
index 17e38a4f1d299..cfcf4ca36f285 100644
--- a/clang/lib/Basic/Targets/NVPTX.cpp
+++ b/clang/lib/Basic/Targets/NVPTX.cpp
@@ -196,6 +196,7 @@ void NVPTXTargetInfo::getTargetDefines(const LangOptions 
,
   case CudaArch::GFX90c:
   case CudaArch::GFX940:
   case CudaArch::GFX941:
+  case CudaArch::GFX942:
   case CudaArch::GFX1010:
   case CudaArch::GFX1011:
   case CudaArch::GFX1012:

diff  --git a/clang/lib/CodeGen/CGOpenMPRuntimeGPU.cpp 
b/clang/lib/CodeGen/CGOpenMPRuntimeGPU.cpp
index dd0ed791588a9..74f8c19e1bc7e 100644
--- a/clang/lib/CodeGen/CGOpenMPRuntimeGPU.cpp
+++ b/clang/lib/CodeGen/CGOpenMPRuntimeGPU.cpp
@@ -3581,6 +3581,7 @@ void CGOpenMPRuntimeGPU::processRequiresDirective(
   case CudaArch::GFX90c:
   case CudaArch::GFX940:
   case CudaArch::GFX941:
+  case CudaArch::GFX942:
   case CudaArch::GFX1010:
   case CudaArch::GFX1011:
   case CudaArch::GFX1012:

diff  --git a/clang/test/CodeGenOpenCL/amdgpu-features.cl 
b/clang/test/CodeGenOpenCL/amdgpu-features.cl
index 5f452ae63925f..efa5759558cc5 100644
--- a/clang/test/CodeGenOpenCL/amdgpu-features.cl
+++ b/clang/test/CodeGenOpenCL/amdgpu-features.cl
@@ -31,6 +31,7 @@
 // RUN: %clang_cc1 -triple amdgcn -target-cpu gfx90c -S -emit-llvm -o - %s | 
FileCheck --check-prefix=GFX90C %s
 // RUN: %clang_cc1 -triple amdgcn -target-cpu gfx940 -S -emit-llvm -o - %s | 
FileCheck --check-prefix=GFX940 %s
 // RUN: %clang_cc1 -triple amdgcn -target-cpu gfx941 -S -emit-llvm -o - %s | 
FileCheck --check-prefix=GFX941 %s
+// RUN: %clang_cc1 -triple amdgcn -target-cpu gfx942 -S -emit-llvm -o - %s | 
FileCheck --check-prefix=GFX942 %s
 // RUN: %clang_cc1 -triple amdgcn -target-cpu gfx1010 -S -emit-llvm -o - %s | 
FileCheck --check-prefix=GFX1010 %s
 // RUN: %clang_cc1 -triple amdgcn -target-cpu gfx1011 -S -emit-llvm -o - %s | 
FileCheck --check-prefix=GFX1011 %s
 // RUN: %clang_cc1 -triple amdgcn -target-cpu gfx1012 -S -emit-llvm -o - %s | 
FileCheck --check-prefix=GFX1012 %s
@@ -77,6 +78,7 @@
 // GFX90C: 
"target-features"="+16-bit-insts,+ci-insts,+dpp,+gfx8-insts,+gfx9-insts,+s-memrealtime,+s-memtime-inst,+wavefrontsize64"
 // GFX940: 
"target-features"="+16-bit-insts,+atomic-buffer-global-pk-add-f16-insts,+atomic-ds-pk-add-16-insts,+atomic-fadd-rtn-insts,+atomic-flat-pk-add-16-insts,+atomic-global-pk-add-bf16-inst,+ci-insts,+dl-insts,+dot1-insts,+dot10-insts,+dot2-insts,+dot3-insts,+dot4-insts,+dot5-insts,+dot6-insts,+dot7-insts,+dpp,+fp8-insts,+gfx8-insts,+gfx9-insts,+gfx90a-insts,+gfx940-insts,+mai-insts,+s-memrealtime,+s-memtime-inst,+wavefrontsize64"
 //

[clang] 1fc7021 - AMDGPU: Add basic gfx941 target

2023-05-10 Thread Konstantin Zhuravlyov via cfe-commits 

Author: Konstantin Zhuravlyov
Date: 2023-05-10T11:51:06-04:00
New Revision: 1fc70210a6a585bad941f64bd3fca7909eeafdda

URL: 
https://github.com/llvm/llvm-project/commit/1fc70210a6a585bad941f64bd3fca7909eeafdda
DIFF: 
https://github.com/llvm/llvm-project/commit/1fc70210a6a585bad941f64bd3fca7909eeafdda.diff

LOG: AMDGPU: Add basic gfx941 target

Differential Revision: https://reviews.llvm.org/D149982

Added: 


Modified: 
clang/include/clang/Basic/Cuda.h
clang/lib/Basic/Cuda.cpp
clang/lib/Basic/Targets/NVPTX.cpp
clang/lib/CodeGen/CGOpenMPRuntimeGPU.cpp
clang/test/CodeGenOpenCL/amdgpu-features.cl
clang/test/Driver/amdgpu-macros.cl
clang/test/Driver/amdgpu-mcpu.cl
clang/test/Misc/target-invalid-cpu-note.c
llvm/docs/AMDGPUUsage.rst
llvm/include/llvm/BinaryFormat/ELF.h
llvm/include/llvm/TargetParser/TargetParser.h
llvm/lib/Object/ELFObjectFile.cpp
llvm/lib/ObjectYAML/ELFYAML.cpp
llvm/lib/Target/AMDGPU/AMDGPU.td
llvm/lib/Target/AMDGPU/GCNProcessors.td
llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp
llvm/lib/TargetParser/TargetParser.cpp
llvm/test/CodeGen/AMDGPU/directive-amdgcn-target.ll
llvm/test/CodeGen/AMDGPU/elf-header-flags-mach.ll
llvm/test/Object/AMDGPU/elf-header-flags-mach.yaml
llvm/test/tools/llvm-objdump/ELF/AMDGPU/subtarget.ll
llvm/test/tools/llvm-readobj/ELF/amdgpu-elf-headers.test
llvm/tools/llvm-readobj/ELFDumper.cpp

Removed: 




diff  --git a/clang/include/clang/Basic/Cuda.h 
b/clang/include/clang/Basic/Cuda.h
index 8ff28944f23d5..dddbd651054da 100644
--- a/clang/include/clang/Basic/Cuda.h
+++ b/clang/include/clang/Basic/Cuda.h
@@ -92,6 +92,7 @@ enum class CudaArch {
   GFX90a,
   GFX90c,
   GFX940,
+  GFX941,
   GFX1010,
   GFX1011,
   GFX1012,

diff  --git a/clang/lib/Basic/Cuda.cpp b/clang/lib/Basic/Cuda.cpp
index b4cf6cbe95f8b..baca1106b263b 100644
--- a/clang/lib/Basic/Cuda.cpp
+++ b/clang/lib/Basic/Cuda.cpp
@@ -114,6 +114,7 @@ static const CudaArchToStringMap arch_names[] = {
 GFX(90a),  // gfx90a
 GFX(90c),  // gfx90c
 GFX(940),  // gfx940
+GFX(941),  // gfx941
 GFX(1010), // gfx1010
 GFX(1011), // gfx1011
 GFX(1012), // gfx1012

diff  --git a/clang/lib/Basic/Targets/NVPTX.cpp 
b/clang/lib/Basic/Targets/NVPTX.cpp
index 5eaa21e1a8f6a..17e38a4f1d299 100644
--- a/clang/lib/Basic/Targets/NVPTX.cpp
+++ b/clang/lib/Basic/Targets/NVPTX.cpp
@@ -195,6 +195,7 @@ void NVPTXTargetInfo::getTargetDefines(const LangOptions 
,
   case CudaArch::GFX90a:
   case CudaArch::GFX90c:
   case CudaArch::GFX940:
+  case CudaArch::GFX941:
   case CudaArch::GFX1010:
   case CudaArch::GFX1011:
   case CudaArch::GFX1012:

diff  --git a/clang/lib/CodeGen/CGOpenMPRuntimeGPU.cpp 
b/clang/lib/CodeGen/CGOpenMPRuntimeGPU.cpp
index 68c4fc872e3b8..dd0ed791588a9 100644
--- a/clang/lib/CodeGen/CGOpenMPRuntimeGPU.cpp
+++ b/clang/lib/CodeGen/CGOpenMPRuntimeGPU.cpp
@@ -3580,6 +3580,7 @@ void CGOpenMPRuntimeGPU::processRequiresDirective(
   case CudaArch::GFX90a:
   case CudaArch::GFX90c:
   case CudaArch::GFX940:
+  case CudaArch::GFX941:
   case CudaArch::GFX1010:
   case CudaArch::GFX1011:
   case CudaArch::GFX1012:

diff  --git a/clang/test/CodeGenOpenCL/amdgpu-features.cl 
b/clang/test/CodeGenOpenCL/amdgpu-features.cl
index e000239cd03fe..5f452ae63925f 100644
--- a/clang/test/CodeGenOpenCL/amdgpu-features.cl
+++ b/clang/test/CodeGenOpenCL/amdgpu-features.cl
@@ -30,6 +30,7 @@
 // RUN: %clang_cc1 -triple amdgcn -target-cpu gfx90a -S -emit-llvm -o - %s | 
FileCheck --check-prefix=GFX90A %s
 // RUN: %clang_cc1 -triple amdgcn -target-cpu gfx90c -S -emit-llvm -o - %s | 
FileCheck --check-prefix=GFX90C %s
 // RUN: %clang_cc1 -triple amdgcn -target-cpu gfx940 -S -emit-llvm -o - %s | 
FileCheck --check-prefix=GFX940 %s
+// RUN: %clang_cc1 -triple amdgcn -target-cpu gfx941 -S -emit-llvm -o - %s | 
FileCheck --check-prefix=GFX941 %s
 // RUN: %clang_cc1 -triple amdgcn -target-cpu gfx1010 -S -emit-llvm -o - %s | 
FileCheck --check-prefix=GFX1010 %s
 // RUN: %clang_cc1 -triple amdgcn -target-cpu gfx1011 -S -emit-llvm -o - %s | 
FileCheck --check-prefix=GFX1011 %s
 // RUN: %clang_cc1 -triple amdgcn -target-cpu gfx1012 -S -emit-llvm -o - %s | 
FileCheck --check-prefix=GFX1012 %s
@@ -75,6 +76,7 @@
 // GFX90A: 
"target-features"="+16-bit-insts,+atomic-buffer-global-pk-add-f16-insts,+atomic-fadd-rtn-insts,+ci-insts,+dl-insts,+dot1-insts,+dot10-insts,+dot2-insts,+dot3-insts,+dot4-insts,+dot5-insts,+dot6-insts,+dot7-insts,+dpp,+gfx8-insts,+gfx9-insts,+gfx90a-insts,+mai-insts,+s-memrealtime,+s-memtime-inst,+wavefrontsize64"
 // GFX90C: 
"target-features"="+16-bit-insts,+ci-insts,+dpp,+gfx8-insts,+gfx9-insts,+s-memrealtime,+s-memtime-inst,+wavefrontsize64"
 // GFX940:

[clang] 4d9f852 - CUDA/HIP: Change device-use-host-var.cu's NOT "external" check to include variable name

2021-06-04 Thread Konstantin Zhuravlyov via cfe-commits 

Author: Konstantin Zhuravlyov
Date: 2021-06-04T13:10:00-04:00
New Revision: 4d9f8527dbfbc998baf35eec868c9dec1f8d1224

URL: 
https://github.com/llvm/llvm-project/commit/4d9f8527dbfbc998baf35eec868c9dec1f8d1224
DIFF: 
https://github.com/llvm/llvm-project/commit/4d9f8527dbfbc998baf35eec868c9dec1f8d1224.diff

LOG: CUDA/HIP: Change device-use-host-var.cu's NOT "external" check to include 
variable name

Otherwise it is causing one of our build jobs to fail,
it is using "external" as directory, and NOT is
failing because "external" is found in ModuleID.

Differential Revision: https://reviews.llvm.org/D103658

Added: 


Modified: 
clang/test/CodeGenCUDA/device-use-host-var.cu

Removed: 




diff  --git a/clang/test/CodeGenCUDA/device-use-host-var.cu 
b/clang/test/CodeGenCUDA/device-use-host-var.cu
index 1a504280e8488..4d3f60c2e83c7 100644
--- a/clang/test/CodeGenCUDA/device-use-host-var.cu
+++ b/clang/test/CodeGenCUDA/device-use-host-var.cu
@@ -65,7 +65,7 @@ const int var_host_only = 7;
 // NEG-NOT: @_ZN1BIiE1yE
 // NEG-NOT: @_Z1bIdE
 // NEG-NOT: @_ZL13var_host_only
-// NEG-NOT: external
+// NEG-NOT: {{^}}@{{.*}} = external
 
 // CHECK-LABEL: define{{.*}}@_Z7dev_funPiPPKi
 // CHECK: store i32 1



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[clang] 67f189e - Make sure both cc1 and cc1as process -m[no-]code-object-v3

2020-10-15 Thread Konstantin Zhuravlyov via cfe-commits 

Author: Konstantin Zhuravlyov
Date: 2020-10-15T14:03:26-04:00
New Revision: 67f189e93ce3c25db74697551a77831a72b34929

URL: 
https://github.com/llvm/llvm-project/commit/67f189e93ce3c25db74697551a77831a72b34929
DIFF: 
https://github.com/llvm/llvm-project/commit/67f189e93ce3c25db74697551a77831a72b34929.diff

LOG: Make sure both cc1 and cc1as process -m[no-]code-object-v3

Differential Revision: https://reviews.llvm.org/D89478

Added: 
clang/test/Driver/amdgpu-features-as.s

Modified: 
clang/lib/Driver/ToolChains/AMDGPU.cpp
clang/lib/Driver/ToolChains/Clang.cpp
clang/test/Driver/amdgpu-features.c

Removed: 




diff  --git a/clang/lib/Driver/ToolChains/AMDGPU.cpp 
b/clang/lib/Driver/ToolChains/AMDGPU.cpp
index 72ecc8cd9f3b..5df7236f0223 100644
--- a/clang/lib/Driver/ToolChains/AMDGPU.cpp
+++ b/clang/lib/Driver/ToolChains/AMDGPU.cpp
@@ -525,19 +525,6 @@ void AMDGPUToolChain::addClangTargetOptions(
 CC1Args.push_back("hidden");
 CC1Args.push_back("-fapply-global-visibility-to-externs");
   }
-
-  if (DriverArgs.hasArg(options::OPT_mcode_object_v3_legacy)) {
-getDriver().Diag(diag::warn_drv_deprecated_arg) << "-mcode-object-v3" <<
-  "-mllvm --amdhsa-code-object-version=3";
-CC1Args.push_back("-mllvm");
-CC1Args.push_back("--amdhsa-code-object-version=3");
-  }
-  if (DriverArgs.hasArg(options::OPT_mno_code_object_v3_legacy)) {
-getDriver().Diag(diag::warn_drv_deprecated_arg) << "-mno-code-object-v3" <<
-  "-mllvm --amdhsa-code-object-version=2";
-CC1Args.push_back("-mllvm");
-CC1Args.push_back("--amdhsa-code-object-version=2");
-  }
 }
 
 StringRef

diff  --git a/clang/lib/Driver/ToolChains/Clang.cpp 
b/clang/lib/Driver/ToolChains/Clang.cpp
index 39fcf240449c..d69dce650d94 100644
--- a/clang/lib/Driver/ToolChains/Clang.cpp
+++ b/clang/lib/Driver/ToolChains/Clang.cpp
@@ -1073,6 +1073,25 @@ static const char 
*RelocationModelName(llvm::Reloc::Model Model) {
   llvm_unreachable("Unknown Reloc::Model kind");
 }
 
+static void HandleAmdgcnLegacyOptions(const Driver ,
+  const ArgList ,
+  ArgStringList ) {
+  if (auto *CodeObjArg = Args.getLastArg(options::OPT_mcode_object_v3_legacy,
+ 
options::OPT_mno_code_object_v3_legacy)) {
+if (CodeObjArg->getOption().getID() == 
options::OPT_mcode_object_v3_legacy) {
+  D.Diag(diag::warn_drv_deprecated_arg) << "-mcode-object-v3" <<
+"-mllvm --amdhsa-code-object-version=3";
+  CmdArgs.push_back("-mllvm");
+  CmdArgs.push_back("--amdhsa-code-object-version=3");
+} else {
+  D.Diag(diag::warn_drv_deprecated_arg) << "-mno-code-object-v3" <<
+"-mllvm --amdhsa-code-object-version=2";
+  CmdArgs.push_back("-mllvm");
+  CmdArgs.push_back("--amdhsa-code-object-version=2");
+}
+  }
+}
+
 void Clang::AddPreprocessingOptions(Compilation , const JobAction ,
 const Driver , const ArgList ,
 ArgStringList ,
@@ -6122,6 +6141,8 @@ void Clang::ConstructJob(Compilation , const JobAction 
,
 }
   }
 
+  HandleAmdgcnLegacyOptions(D, Args, CmdArgs);
+
   // For all the host OpenMP offloading compile jobs we need to pass the 
targets
   // information using -fopenmp-targets= option.
   if (JA.isHostOffloading(Action::OFK_OpenMP)) {
@@ -7085,6 +7106,8 @@ void ClangAs::ConstructJob(Compilation , const 
JobAction ,
 CmdArgs.push_back(SplitDebugName(JA, Args, Input, Output));
   }
 
+  HandleAmdgcnLegacyOptions(D, Args, CmdArgs);
+
   assert(Input.isFilename() && "Invalid input.");
   CmdArgs.push_back(Input.getFilename());
 

diff  --git a/clang/test/Driver/amdgpu-features-as.s 
b/clang/test/Driver/amdgpu-features-as.s
new file mode 100644
index ..850afe701740
--- /dev/null
+++ b/clang/test/Driver/amdgpu-features-as.s
@@ -0,0 +1,11 @@
+// RUN: %clang -### -target amdgcn-amd-amdhsa -mcpu=gfx900 -mcode-object-v3 %s 
2>&1 | FileCheck --check-prefix=CODE-OBJECT-V3 %s
+// CODE-OBJECT-V3: warning: argument '-mcode-object-v3' is deprecated, use 
'-mllvm --amdhsa-code-object-version=3' instead [-Wdeprecated]
+// CODE-OBJECT-V3: "-mllvm" "--amdhsa-code-object-version=3"
+
+// RUN: %clang -### -target amdgcn-amd-amdhsa amdgcn -mcpu=gfx900 
-mno-code-object-v3 %s 2>&1 | FileCheck --check-prefix=NO-CODE-OBJECT-V3 %s
+// NO-CODE-OBJECT-V3: warning: argument '-mno-code-object-v3' is deprecated, 
use '-mllvm --amdhsa-code-object-version=2' instead [-Wdeprecated]
+// NO-CODE-OBJECT-V3: "-mllvm" "--amdhsa-code-object-version=2"
+
+// RUN: %clang -### -target amdgcn-amd-amdhsa -mcpu=gfx900 -mcode-object-v3 
-mno-code-object-v3 -mcode-object-v3 %s 2>&1 | FileCheck 
--check-prefix=MUL-CODE-OBJECT-V3 %s
+// MUL-CODE-OBJECT-V3: warning: argument '-mcode-object-v3' is deprecated, use 
'-mllvm --amdhsa-code-object-version=3' instead

[clang] e2eaa91 - AMDGPU: Remove -mamdgpu-debugger-abi option

2020-10-13 Thread Konstantin Zhuravlyov via cfe-commits 

Author: Konstantin Zhuravlyov
Date: 2020-10-13T12:20:28-04:00
New Revision: e2eaa914514c26c8e51c76148996a2e9cf74613c

URL: 
https://github.com/llvm/llvm-project/commit/e2eaa914514c26c8e51c76148996a2e9cf74613c
DIFF: 
https://github.com/llvm/llvm-project/commit/e2eaa914514c26c8e51c76148996a2e9cf74613c.diff

LOG: AMDGPU: Remove -mamdgpu-debugger-abi option

It has been unsupported for few years now.

Differential Revision: https://reviews.llvm.org/D89125

Added: 


Modified: 
clang/docs/ClangCommandLineReference.rst
clang/include/clang/Driver/Options.td
clang/lib/Driver/ToolChains/AMDGPU.cpp
clang/test/Driver/amdgpu-features.c

Removed: 




diff  --git a/clang/docs/ClangCommandLineReference.rst 
b/clang/docs/ClangCommandLineReference.rst
index ff3decbca70c..97a96631cc21 100644
--- a/clang/docs/ClangCommandLineReference.rst
+++ b/clang/docs/ClangCommandLineReference.rst
@@ -2655,10 +2655,6 @@ Align selected branches (fused, jcc, jmp) within 32-byte 
boundary
 
 .. option:: -mcmodel=, -mcmodel=medany (equivalent to -mcmodel=medium), 
-mcmodel=medlow (equivalent to -mcmodel=small)
 
-.. option:: -mcode-object-v3, -mno-code-object-v3
-
-Enable code object v3 (AMDGPU only)
-
 .. option:: -mconsole
 
 .. program:: clang1
@@ -2939,6 +2935,10 @@ Specify the size in bits of an SVE vector register. 
Defaults to the vector lengt
 
 AMDGPU
 --
+.. option:: -mcode-object-v3, -mno-code-object-v3
+
+Enable code object v3 (AMDGPU only)
+
 .. option:: -mcumode, -mno-cumode
 
 CU wavefront execution mode is used (AMDGPU only)

diff  --git a/clang/include/clang/Driver/Options.td 
b/clang/include/clang/Driver/Options.td
index 9980dda23bb0..f5e745b1dbe2 100644
--- a/clang/include/clang/Driver/Options.td
+++ b/clang/include/clang/Driver/Options.td
@@ -2461,12 +2461,6 @@ def mexec_model_EQ : Joined<["-"], "mexec-model=">, 
Group,
  HelpText<"Execution model (WebAssembly only)">;
 
-def mamdgpu_debugger_abi : Joined<["-"], "mamdgpu-debugger-abi=">,
-  Flags<[HelpHidden]>,
-  Group,
-  HelpText<"Generate additional code for specified  of debugger ABI 
(AMDGPU only)">,
-  MetaVarName<"">;
-
 def mcode_object_v3 : Flag<["-"], "mcode-object-v3">, 
Group,
   HelpText<"Enable code object v3 (AMDGPU only)">;
 def mno_code_object_v3 : Flag<["-"], "mno-code-object-v3">, 
Group,

diff  --git a/clang/lib/Driver/ToolChains/AMDGPU.cpp 
b/clang/lib/Driver/ToolChains/AMDGPU.cpp
index 6781045886f2..5df7236f0223 100644
--- a/clang/lib/Driver/ToolChains/AMDGPU.cpp
+++ b/clang/lib/Driver/ToolChains/AMDGPU.cpp
@@ -365,9 +365,6 @@ void amdgpu::getAMDGPUTargetFeatures(const Driver ,
  const llvm::Triple ,
  const llvm::opt::ArgList ,
  std::vector ) {
-  if (const Arg *dAbi = Args.getLastArg(options::OPT_mamdgpu_debugger_abi))
-D.Diag(diag::err_drv_clang_unsupported) << dAbi->getAsString(Args);
-
   // Add target ID features to -target-feature options. No diagnostics should
   // be emitted here since invalid target ID is diagnosed at other places.
   StringRef TargetID = Args.getLastArgValue(options::OPT_mcpu_EQ);

diff  --git a/clang/test/Driver/amdgpu-features.c 
b/clang/test/Driver/amdgpu-features.c
index 71fd63715e00..17142ae23d6d 100644
--- a/clang/test/Driver/amdgpu-features.c
+++ b/clang/test/Driver/amdgpu-features.c
@@ -1,11 +1,3 @@
-// RUN: %clang -### -target amdgcn -x cl -S -emit-llvm -mcpu=kaveri 
-mamdgpu-debugger-abi=0.0 %s -o - 2>&1 \
-// RUN:   | FileCheck --check-prefix=CHECK-MAMDGPU-DEBUGGER-ABI-0-0 %s
-// CHECK-MAMDGPU-DEBUGGER-ABI-0-0: the clang compiler does not support 
'-mamdgpu-debugger-abi=0.0'
-
-// RUN: %clang -### -target amdgcn -x cl -S -emit-llvm -mcpu=kaveri 
-mamdgpu-debugger-abi=1.0 %s -o - 2>&1 \
-// RUN:   | FileCheck --check-prefix=CHECK-MAMDGPU-DEBUGGER-ABI-1-0 %s
-// CHECK-MAMDGPU-DEBUGGER-ABI-1-0: the clang compiler does not support 
'-mamdgpu-debugger-abi=1.0'
-
 // RUN: %clang -### -target amdgcn -mcpu=gfx700 -mcode-object-v3 %s 2>&1 | 
FileCheck --check-prefix=CODE-OBJECT-V3 %s
 // CODE-OBJECT-V3: "-target-feature" "+code-object-v3"
 



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[clang] b581c5a - Regenerate ClangCommandLineReference.rst

2020-10-09 Thread Konstantin Zhuravlyov via cfe-commits 

Author: Konstantin Zhuravlyov
Date: 2020-10-09T08:29:53-04:00
New Revision: b581c5a42f052d4d02f1152d0e1ff2d54668e6a0

URL: 
https://github.com/llvm/llvm-project/commit/b581c5a42f052d4d02f1152d0e1ff2d54668e6a0
DIFF: 
https://github.com/llvm/llvm-project/commit/b581c5a42f052d4d02f1152d0e1ff2d54668e6a0.diff

LOG: Regenerate ClangCommandLineReference.rst

Differential Revision: https://reviews.llvm.org/D89091

Added: 


Modified: 
clang/docs/ClangCommandLineReference.rst

Removed: 




diff  --git a/clang/docs/ClangCommandLineReference.rst 
b/clang/docs/ClangCommandLineReference.rst
index 135495668e2d..10e0203ce241 100644
--- a/clang/docs/ClangCommandLineReference.rst
+++ b/clang/docs/ClangCommandLineReference.rst
@@ -144,8 +144,6 @@ Specifies configuration file
 
 .. option:: --constant-cfstrings
 
-.. option:: -coverage, --coverage
-
 .. option:: --cuda-compile-host-device
 
 Compile CUDA code for both host and device (default).  Has no effect on 
non-CUDA compilations.
@@ -178,6 +176,10 @@ Filename to write DOT-formatted header dependencies to
 
 Filename (or -) to write dependency output to
 
+.. option:: -dsym-dir
+
+Directory to output dSYM's (if any) to
+
 .. option:: -dumpmachine
 
 .. option:: -dumpversion
@@ -200,6 +202,10 @@ Filename (or -) to write dependency output to
 
 Emit Clang AST files for source inputs
 
+.. option:: --emit-static-lib
+
+Enable linker job to emit a static library.
+
 .. option:: 
-enable-trivial-auto-var-init-zero-knowing-it-will-be-removed-from-clang
 
 Trivial automatic variable initialization to zero is only here for benchmarks, 
it'll eventually be removed, and I'm OK with that because I'm only using it to 
benchmark
@@ -262,6 +268,10 @@ Emit type record hashes in a .debug$H section
 
 .. option:: -ginline-line-tables, -gno-inline-line-tables
 
+.. option:: --gpu-instrument-lib=
+
+Instrument device library for HIP, which is a LLVM bitcode containing 
\_\_cyg\_profile\_func\_enter and \_\_cyg\_profile\_func\_exit
+
 .. option:: --gpu-max-threads-per-block=
 
 Default max threads per block for kernel launch bounds for HIP
@@ -280,6 +290,10 @@ Display help for hidden options
 
 Link clang-offload-bundler bundles for HIP
 
+.. option:: --hip-version=
+
+HIP version in the format of major.minor.patch
+
 .. option:: -ibuiltininc
 
 Enable builtin #include directories even when -nostdinc is used before or 
after -ibuiltininc. Using -nobuiltininc after the option disables it
@@ -310,6 +324,10 @@ Make the next included directory (-I or -F) an indexer 
header map
 
 Enforce targets of indirect branches and function returns
 
+.. option:: -mharden-sls=
+
+Select straight-line speculation hardening scope
+
 .. option:: --migrate
 
 Run the migrator
@@ -374,8 +392,6 @@ Do not link device library for CUDA/HIP device compilation
 
 .. option:: -noseglinkedit
 
-.. option:: -nostartfiles
-
 .. option:: -nostdinc, --no-standard-includes
 
 .. program:: clang1
@@ -384,11 +400,7 @@ Do not link device library for CUDA/HIP device compilation
 
 Disable standard #include directories for the C++ standard library
 
-.. option:: -nostdlib, --no-standard-libraries
-
-.. program:: clang1
 .. option:: -nostdlib++
-.. program:: clang
 
 .. option:: -nostdlibinc
 
@@ -464,7 +476,7 @@ Only modify files with a filename contained in the provided 
directory path
 
 .. option:: --offload-arch=, --cuda-gpu-arch=, 
--no-offload-arch=
 
-CUDA/HIP offloading device architecture (e.g. sm\_35, gfx906).  May be 
specified more than once.
+CUDA offloading device architecture (e.g. sm\_35), or HIP offloading target ID 
in the form of a device architecture followed by target ID features delimited 
by a colon. Each target ID feature is a pre-defined string followed by a plus 
or minus sign (e.g. gfx908:xnack+:sram-ecc-).  May be specified more than once.
 
 .. option:: -p, --profile
 
@@ -474,8 +486,6 @@ CUDA/HIP offloading device architecture (e.g. sm\_35, 
gfx906).  May be specified
 
 Enable mcount instrumentation
 
-.. option:: -pie
-
 .. option:: -pipe, --pipe
 
 Use pipes between commands, when possible
@@ -538,8 +548,6 @@ Support POSIX threads in generated code
 
 .. option:: -pthreads
 
-.. option:: -rdynamic
-
 .. option:: -read\_only\_relocs 
 
 .. option:: -relocatable-pch, --relocatable-pch
@@ -602,8 +610,6 @@ Save intermediate compilation results.
 
 Serialize compiler diagnostics to a file
 
-.. option:: -shared, --shared
-
 .. option:: -shared-libgcc
 
 .. option:: -shared-libsan, -shared-libasan
@@ -612,10 +618,6 @@ Dynamically link the sanitizer runtime
 
 .. option:: -single\_module
 
-.. option:: -specs=, --specs=
-
-.. option:: -static, --static
-
 .. option:: -static-libgcc
 
 .. option:: -static-libsan
@@ -628,8 +630,6 @@ Statically link the sanitizer runtime
 
 Use the static host OpenMP runtime while linking.
 
-.. option:: -static-pie
-
 .. option:: -std-default=
 
 .. option:: -stdlib=,

r356947 - AMDGPU: Add support for cross address space synchronization scopes (clang)

2019-03-25 Thread Konstantin Zhuravlyov via cfe-commits 
Author: kzhuravl
Date: Mon Mar 25 13:54:00 2019
New Revision: 356947

URL: http://llvm.org/viewvc/llvm-project?rev=356947=rev
Log:
AMDGPU: Add support for cross address space synchronization scopes (clang)

Differential Revision: https://reviews.llvm.org/D59494

Modified:
cfe/trunk/lib/CodeGen/CGAtomic.cpp
cfe/trunk/lib/CodeGen/TargetInfo.cpp
cfe/trunk/lib/CodeGen/TargetInfo.h
cfe/trunk/test/CodeGenOpenCL/atomic-ops.cl

Modified: cfe/trunk/lib/CodeGen/CGAtomic.cpp
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/CodeGen/CGAtomic.cpp?rev=356947=356946=356947=diff
==
--- cfe/trunk/lib/CodeGen/CGAtomic.cpp (original)
+++ cfe/trunk/lib/CodeGen/CGAtomic.cpp Mon Mar 25 13:54:00 2019
@@ -679,7 +679,8 @@ static void EmitAtomicOp(CodeGenFunction
   // Handle constant scope.
   if (auto SC = dyn_cast(Scope)) {
 auto SCID = CGF.getTargetHooks().getLLVMSyncScopeID(
-ScopeModel->map(SC->getZExtValue()), CGF.CGM.getLLVMContext());
+CGF.CGM.getLangOpts(), ScopeModel->map(SC->getZExtValue()),
+Order, CGF.CGM.getLLVMContext());
 EmitAtomicOp(CGF, Expr, Dest, Ptr, Val1, Val2, IsWeak, FailureOrder, Size,
  Order, SCID);
 return;
@@ -708,7 +709,9 @@ static void EmitAtomicOp(CodeGenFunction
 Builder.SetInsertPoint(B);
 EmitAtomicOp(CGF, Expr, Dest, Ptr, Val1, Val2, IsWeak, FailureOrder, Size,
  Order,
- CGF.getTargetHooks().getLLVMSyncScopeID(ScopeModel->map(S),
+ CGF.getTargetHooks().getLLVMSyncScopeID(CGF.CGM.getLangOpts(),
+ ScopeModel->map(S),
+ Order,
  
CGF.getLLVMContext()));
 Builder.CreateBr(ContBB);
   }

Modified: cfe/trunk/lib/CodeGen/TargetInfo.cpp
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/CodeGen/TargetInfo.cpp?rev=356947=356946=356947=diff
==
--- cfe/trunk/lib/CodeGen/TargetInfo.cpp (original)
+++ cfe/trunk/lib/CodeGen/TargetInfo.cpp Mon Mar 25 13:54:00 2019
@@ -462,8 +462,11 @@ TargetCodeGenInfo::performAddrSpaceCast(
 }
 
 llvm::SyncScope::ID
-TargetCodeGenInfo::getLLVMSyncScopeID(SyncScope S, llvm::LLVMContext ) const 
{
-  return C.getOrInsertSyncScopeID(""); /* default sync scope */
+TargetCodeGenInfo::getLLVMSyncScopeID(const LangOptions ,
+  SyncScope Scope,
+  llvm::AtomicOrdering Ordering,
+  llvm::LLVMContext ) const {
+  return Ctx.getOrInsertSyncScopeID(""); /* default sync scope */
 }
 
 static bool isEmptyRecord(ASTContext , QualType T, bool AllowArrays);
@@ -7824,8 +7827,10 @@ public:
   }
   LangAS getGlobalVarAddressSpace(CodeGenModule ,
   const VarDecl *D) const override;
-  llvm::SyncScope::ID getLLVMSyncScopeID(SyncScope S,
- llvm::LLVMContext ) const override;
+  llvm::SyncScope::ID getLLVMSyncScopeID(const LangOptions ,
+ SyncScope Scope,
+ llvm::AtomicOrdering Ordering,
+ llvm::LLVMContext ) const 
override;
   llvm::Function *
   createEnqueuedBlockKernel(CodeGenFunction ,
 llvm::Function *BlockInvokeFunc,
@@ -7971,10 +7976,12 @@ AMDGPUTargetCodeGenInfo::getGlobalVarAdd
 }
 
 llvm::SyncScope::ID
-AMDGPUTargetCodeGenInfo::getLLVMSyncScopeID(SyncScope S,
-llvm::LLVMContext ) const {
-  StringRef Name;
-  switch (S) {
+AMDGPUTargetCodeGenInfo::getLLVMSyncScopeID(const LangOptions ,
+SyncScope Scope,
+llvm::AtomicOrdering Ordering,
+llvm::LLVMContext ) const {
+  std::string Name;
+  switch (Scope) {
   case SyncScope::OpenCLWorkGroup:
 Name = "workgroup";
 break;
@@ -7987,7 +7994,15 @@ AMDGPUTargetCodeGenInfo::getLLVMSyncScop
   case SyncScope::OpenCLSubGroup:
 Name = "wavefront";
   }
-  return C.getOrInsertSyncScopeID(Name);
+
+  if (Ordering != llvm::AtomicOrdering::SequentiallyConsistent) {
+if (!Name.empty())
+  Name = Twine(Twine(Name) + Twine("-")).str();
+
+Name = Twine(Twine(Name) + Twine("one-as")).str();
+  }
+
+  return Ctx.getOrInsertSyncScopeID(Name);
 }
 
 bool AMDGPUTargetCodeGenInfo::shouldEmitStaticExternCAliases() const {

Modified: cfe/trunk/lib/CodeGen/TargetInfo.h
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/CodeGen/TargetInfo.h?rev=356947=356946=356947=diff
==
--- cfe/trunk/lib/CodeGen/TargetInfo.h

r355549 - AMDGPU: Fix the mapping of sub group sync scope

2019-03-06 Thread Konstantin Zhuravlyov via cfe-commits 
Author: kzhuravl
Date: Wed Mar  6 12:54:48 2019
New Revision: 355549

URL: http://llvm.org/viewvc/llvm-project?rev=355549=rev
Log:
AMDGPU: Fix the mapping of sub group sync scope

Map memory_scope_sub_group to "wavefront" sync scope

Differential Revision: https://reviews.llvm.org/D58847

Modified:
cfe/trunk/lib/CodeGen/TargetInfo.cpp
cfe/trunk/test/CodeGenOpenCL/atomic-ops.cl

Modified: cfe/trunk/lib/CodeGen/TargetInfo.cpp
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/CodeGen/TargetInfo.cpp?rev=355549=355548=355549=diff
==
--- cfe/trunk/lib/CodeGen/TargetInfo.cpp (original)
+++ cfe/trunk/lib/CodeGen/TargetInfo.cpp Wed Mar  6 12:54:48 2019
@@ -7959,7 +7959,7 @@ AMDGPUTargetCodeGenInfo::getLLVMSyncScop
 Name = "";
 break;
   case SyncScope::OpenCLSubGroup:
-Name = "subgroup";
+Name = "wavefront";
   }
   return C.getOrInsertSyncScopeID(Name);
 }

Modified: cfe/trunk/test/CodeGenOpenCL/atomic-ops.cl
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGenOpenCL/atomic-ops.cl?rev=355549=355548=355549=diff
==
--- cfe/trunk/test/CodeGenOpenCL/atomic-ops.cl (original)
+++ cfe/trunk/test/CodeGenOpenCL/atomic-ops.cl Wed Mar  6 12:54:48 2019
@@ -41,7 +41,7 @@ void fi1(atomic_int *i) {
   // CHECK: load atomic i32, i32* %{{[.0-9A-Z_a-z]+}} seq_cst
   x = __opencl_atomic_load(i, memory_order_seq_cst, 
memory_scope_all_svm_devices);
 
-  // CHECK: load atomic i32, i32* %{{[.0-9A-Z_a-z]+}} syncscope("subgroup") 
seq_cst
+  // CHECK: load atomic i32, i32* %{{[.0-9A-Z_a-z]+}} syncscope("wavefront") 
seq_cst
   x = __opencl_atomic_load(i, memory_order_seq_cst, memory_scope_sub_group);
 }
 
@@ -109,7 +109,7 @@ void fi5(atomic_int *i, int scope) {
   // CHECK: load atomic i32, i32* %{{.*}} seq_cst
   // CHECK: br label %[[continue]]
   // CHECK: [[opencl_subgroup]]:
-  // CHECK: load atomic i32, i32* %{{.*}} syncscope("subgroup") seq_cst
+  // CHECK: load atomic i32, i32* %{{.*}} syncscope("wavefront") seq_cst
   // CHECK: br label %[[continue]]
   // CHECK: [[continue]]:
   int x = __opencl_atomic_load(i, memory_order_seq_cst, scope);
@@ -147,7 +147,7 @@ void fi6(atomic_int *i, int order, int s
   // CHECK: [[MON_ALL]]:
   // CHECK: load atomic i32, i32* %{{.*}} monotonic
   // CHECK: [[MON_SUB]]:
-  // CHECK: load atomic i32, i32* %{{.*}} syncscope("subgroup") monotonic
+  // CHECK: load atomic i32, i32* %{{.*}} syncscope("wavefront") monotonic
   // CHECK: [[ACQ_WG]]:
   // CHECK: load atomic i32, i32* %{{.*}} syncscope("workgroup") acquire
   // CHECK: [[ACQ_DEV]]:
@@ -155,7 +155,7 @@ void fi6(atomic_int *i, int order, int s
   // CHECK: [[ACQ_ALL]]:
   // CHECK: load atomic i32, i32* %{{.*}} acquire
   // CHECK: [[ACQ_SUB]]:
-  // CHECK: load atomic i32, i32* %{{.*}} syncscope("subgroup") acquire
+  // CHECK: load atomic i32, i32* %{{.*}} syncscope("wavefront") acquire
   // CHECK: [[SEQ_WG]]:
   // CHECK: load atomic i32, i32* %{{.*}} syncscope("workgroup") seq_cst
   // CHECK: [[SEQ_DEV]]:
@@ -163,7 +163,7 @@ void fi6(atomic_int *i, int order, int s
   // CHECK: [[SEQ_ALL]]:
   // CHECK: load atomic i32, i32* %{{.*}} seq_cst
   // CHECK: [[SEQ_SUB]]:
-  // CHECK: load atomic i32, i32* %{{.*}} syncscope("subgroup") seq_cst
+  // CHECK: load atomic i32, i32* %{{.*}} syncscope("wavefront") seq_cst
   int x = __opencl_atomic_load(i, order, scope);
 }
 


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r346178 - AMDGPU: Add sram-ecc feature options

2018-11-05 Thread Konstantin Zhuravlyov via cfe-commits 
Author: kzhuravl
Date: Mon Nov  5 14:44:59 2018
New Revision: 346178

URL: http://llvm.org/viewvc/llvm-project?rev=346178=rev
Log:
AMDGPU: Add sram-ecc feature options

Differential Revision: https://reviews.llvm.org/D53223

Modified:
cfe/trunk/include/clang/Driver/Options.td
cfe/trunk/test/Driver/amdgpu-features.c

Modified: cfe/trunk/include/clang/Driver/Options.td
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/include/clang/Driver/Options.td?rev=346178=346177=346178=diff
==
--- cfe/trunk/include/clang/Driver/Options.td (original)
+++ cfe/trunk/include/clang/Driver/Options.td Mon Nov  5 14:44:59 2018
@@ -2104,6 +2104,10 @@ def mxnack : Flag<["-"], "mxnack">, Grou
   HelpText<"Enable XNACK (AMDGPU only)">;
 def mno_xnack : Flag<["-"], "mno-xnack">, Group,
   HelpText<"Disable XNACK (AMDGPU only)">;
+def msram_ecc : Flag<["-"], "msram-ecc">, Group,
+  HelpText<"Enable SRAM ECC (AMDGPU only)">;
+def mno_sram_ecc : Flag<["-"], "mno-sram-ecc">, Group,
+  HelpText<"Disable SRAM ECC (AMDGPU only)">;
 
 def faltivec : Flag<["-"], "faltivec">, Group, Flags<[DriverOption]>;
 def fno_altivec : Flag<["-"], "fno-altivec">, Group, 
Flags<[DriverOption]>;

Modified: cfe/trunk/test/Driver/amdgpu-features.c
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/Driver/amdgpu-features.c?rev=346178=346177=346178=diff
==
--- cfe/trunk/test/Driver/amdgpu-features.c (original)
+++ cfe/trunk/test/Driver/amdgpu-features.c Mon Nov  5 14:44:59 2018
@@ -17,3 +17,9 @@
 
 // RUN: %clang -### -target amdgcn -mcpu=gfx700 -mno-xnack %s 2>&1 | FileCheck 
--check-prefix=NO-XNACK %s
 // NO-XNACK: "-target-feature" "-xnack"
+
+// RUN: %clang -### -target amdgcn -mcpu=gfx700 -msram-ecc %s 2>&1 | FileCheck 
--check-prefix=SRAM-ECC %s
+// SRAM-ECC: "-target-feature" "+sram-ecc"
+
+// RUN: %clang -### -target amdgcn -mcpu=gfx700 -mno-sram-ecc %s 2>&1 | 
FileCheck --check-prefix=NO-SRAM-ECC %s
+// NO-SRAM-ECC: "-target-feature" "-sram-ecc"


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r345181 - AMDGPU: Handle gfx909 in AMDGPUTargetInfo::initFeatureMap

2018-10-24 Thread Konstantin Zhuravlyov via cfe-commits 
Author: kzhuravl
Date: Wed Oct 24 12:07:56 2018
New Revision: 345181

URL: http://llvm.org/viewvc/llvm-project?rev=345181=rev
Log:
AMDGPU: Handle gfx909 in AMDGPUTargetInfo::initFeatureMap

+ add required tests

Modified:
cfe/trunk/lib/Basic/Targets/AMDGPU.cpp
cfe/trunk/test/Driver/amdgpu-macros.cl
cfe/trunk/test/Driver/amdgpu-mcpu.cl

Modified: cfe/trunk/lib/Basic/Targets/AMDGPU.cpp
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Basic/Targets/AMDGPU.cpp?rev=345181=345180=345181=diff
==
--- cfe/trunk/lib/Basic/Targets/AMDGPU.cpp (original)
+++ cfe/trunk/lib/Basic/Targets/AMDGPU.cpp Wed Oct 24 12:07:56 2018
@@ -138,6 +138,7 @@ bool AMDGPUTargetInfo::initFeatureMap(
 case GK_GFX906:
   Features["dl-insts"] = true;
   LLVM_FALLTHROUGH;
+case GK_GFX909:
 case GK_GFX904:
 case GK_GFX902:
 case GK_GFX900:

Modified: cfe/trunk/test/Driver/amdgpu-macros.cl
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/Driver/amdgpu-macros.cl?rev=345181=345180=345181=diff
==
--- cfe/trunk/test/Driver/amdgpu-macros.cl (original)
+++ cfe/trunk/test/Driver/amdgpu-macros.cl Wed Oct 24 12:07:56 2018
@@ -175,6 +175,7 @@
 // RUN: %clang -E -dM -target amdgcn -mcpu=gfx902 %s 2>&1 | FileCheck 
--check-prefixes=ARCH-GCN,GFX902 %s
 // RUN: %clang -E -dM -target amdgcn -mcpu=gfx904 %s 2>&1 | FileCheck 
--check-prefixes=ARCH-GCN,GFX904 %s
 // RUN: %clang -E -dM -target amdgcn -mcpu=gfx906 %s 2>&1 | FileCheck 
--check-prefixes=ARCH-GCN,GFX906 %s
+// RUN: %clang -E -dM -target amdgcn -mcpu=gfx909 %s 2>&1 | FileCheck 
--check-prefixes=ARCH-GCN,GFX909 %s
 
 // GFX600-DAG: #define FP_FAST_FMA 1
 // GFX601-DAG: #define FP_FAST_FMA 1
@@ -191,6 +192,7 @@
 // GFX902-DAG: #define FP_FAST_FMA 1
 // GFX904-DAG: #define FP_FAST_FMA 1
 // GFX906-DAG: #define FP_FAST_FMA 1
+// GFX909-DAG: #define FP_FAST_FMA 1
 
 // GFX600-DAG: #define FP_FAST_FMAF 1
 // GFX601-NOT: #define FP_FAST_FMAF 1
@@ -207,6 +209,7 @@
 // GFX902-DAG: #define FP_FAST_FMAF 1
 // GFX904-DAG: #define FP_FAST_FMAF 1
 // GFX906-DAG: #define FP_FAST_FMAF 1
+// GFX909-DAG: #define FP_FAST_FMAF 1
 
 // ARCH-GCN-DAG: #define __AMDGCN__ 1
 // ARCH-GCN-DAG: #define __AMDGPU__ 1
@@ -227,6 +230,7 @@
 // GFX902-DAG: #define __HAS_FMAF__ 1
 // GFX904-DAG: #define __HAS_FMAF__ 1
 // GFX906-DAG: #define __HAS_FMAF__ 1
+// GFX909-DAG: #define __HAS_FMAF__ 1
 
 // GFX600-DAG: #define __HAS_FP64__ 1
 // GFX601-DAG: #define __HAS_FP64__ 1
@@ -243,6 +247,7 @@
 // GFX902-DAG: #define __HAS_FP64__ 1
 // GFX904-DAG: #define __HAS_FP64__ 1
 // GFX906-DAG: #define __HAS_FP64__ 1
+// GFX909-DAG: #define __HAS_FP64__ 1
 
 // GFX600-DAG: #define __HAS_LDEXPF__ 1
 // GFX601-DAG: #define __HAS_LDEXPF__ 1
@@ -259,6 +264,7 @@
 // GFX902-DAG: #define __HAS_LDEXPF__ 1
 // GFX904-DAG: #define __HAS_LDEXPF__ 1
 // GFX906-DAG: #define __HAS_LDEXPF__ 1
+// GFX909-DAG: #define __HAS_LDEXPF__ 1
 
 // GFX600-DAG: #define __gfx600__ 1
 // GFX601-DAG: #define __gfx601__ 1
@@ -275,3 +281,4 @@
 // GFX902-DAG: #define __gfx902__ 1
 // GFX904-DAG: #define __gfx904__ 1
 // GFX906-DAG: #define __gfx906__ 1
+// GFX909-DAG: #define __gfx909__ 1

Modified: cfe/trunk/test/Driver/amdgpu-mcpu.cl
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/Driver/amdgpu-mcpu.cl?rev=345181=345180=345181=diff
==
--- cfe/trunk/test/Driver/amdgpu-mcpu.cl (original)
+++ cfe/trunk/test/Driver/amdgpu-mcpu.cl Wed Oct 24 12:07:56 2018
@@ -84,6 +84,7 @@
 // RUN: %clang -### -target amdgcn -mcpu=gfx902 %s 2>&1 | FileCheck 
--check-prefix=GFX902 %s
 // RUN: %clang -### -target amdgcn -mcpu=gfx904 %s 2>&1 | FileCheck 
--check-prefix=GFX904 %s
 // RUN: %clang -### -target amdgcn -mcpu=gfx906 %s 2>&1 | FileCheck 
--check-prefix=GFX906 %s
+// RUN: %clang -### -target amdgcn -mcpu=gfx909 %s 2>&1 | FileCheck 
--check-prefix=GFX909 %s
 
 // GFX600:"-target-cpu" "gfx600"
 // TAHITI:"-target-cpu" "tahiti"
@@ -117,3 +118,4 @@
 // GFX902:"-target-cpu" "gfx902"
 // GFX904:"-target-cpu" "gfx904"
 // GFX906:"-target-cpu" "gfx906"
+// GFX909:"-target-cpu" "gfx909"


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r344711 - AMDGPU: Add options to enable/disable code object v3

2018-10-17 Thread Konstantin Zhuravlyov via cfe-commits 
Author: kzhuravl
Date: Wed Oct 17 14:39:12 2018
New Revision: 344711

URL: http://llvm.org/viewvc/llvm-project?rev=344711=rev
Log:
AMDGPU: Add options to enable/disable code object v3

Differential Revision: https://reviews.llvm.org/D53386

Modified:
cfe/trunk/include/clang/Driver/Options.td
cfe/trunk/test/Driver/amdgpu-features.c

Modified: cfe/trunk/include/clang/Driver/Options.td
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/include/clang/Driver/Options.td?rev=344711=344710=344711=diff
==
--- cfe/trunk/include/clang/Driver/Options.td (original)
+++ cfe/trunk/include/clang/Driver/Options.td Wed Oct 17 14:39:12 2018
@@ -2085,6 +2085,11 @@ def mamdgpu_debugger_abi : Joined<["-"],
   Group,
   HelpText<"Generate additional code for specified  of debugger ABI 
(AMDGPU only)">,
   MetaVarName<"">;
+
+def mcode_object_v3 : Flag<["-"], "mcode-object-v3">, 
Group,
+  HelpText<"Enable code object v3 (AMDGPU only)">;
+def mno_code_object_v3 : Flag<["-"], "mno-code-object-v3">, 
Group,
+  HelpText<"Disable code object v3 (AMDGPU only)">;
 def mxnack : Flag<["-"], "mxnack">, Group,
   HelpText<"Enable XNACK (AMDGPU only)">;
 def mno_xnack : Flag<["-"], "mno-xnack">, Group,

Modified: cfe/trunk/test/Driver/amdgpu-features.c
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/Driver/amdgpu-features.c?rev=344711=344710=344711=diff
==
--- cfe/trunk/test/Driver/amdgpu-features.c (original)
+++ cfe/trunk/test/Driver/amdgpu-features.c Wed Oct 17 14:39:12 2018
@@ -6,6 +6,12 @@
 // RUN:   | FileCheck --check-prefix=CHECK-MAMDGPU-DEBUGGER-ABI-1-0 %s
 // CHECK-MAMDGPU-DEBUGGER-ABI-1-0: "-target-feature" 
"+amdgpu-debugger-insert-nops" "-target-feature" 
"+amdgpu-debugger-emit-prologue"
 
+// RUN: %clang -### -target amdgcn -mcpu=gfx700 -mcode-object-v3 %s 2>&1 | 
FileCheck --check-prefix=CODE-OBJECT-V3 %s
+// CODE-OBJECT-V3: "-target-feature" "+code-object-v3"
+
+// RUN: %clang -### -target amdgcn -mcpu=gfx700 -mno-code-object-v3 %s 2>&1 | 
FileCheck --check-prefix=NO-CODE-OBJECT-V3 %s
+// NO-CODE-OBJECT-V3: "-target-feature" "-code-object-v3"
+
 // RUN: %clang -### -target amdgcn -mcpu=gfx700 -mxnack %s 2>&1 | FileCheck 
--check-prefix=XNACK %s
 // XNACK: "-target-feature" "+xnack"
 


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r338471 - AMDGPU: Add clamp bit to dot builtins

2018-07-31 Thread Konstantin Zhuravlyov via cfe-commits 
Author: kzhuravl
Date: Tue Jul 31 18:32:21 2018
New Revision: 338471

URL: http://llvm.org/viewvc/llvm-project?rev=338471=rev
Log:
AMDGPU: Add clamp bit to dot builtins

Differential Revision: https://reviews.llvm.org/D50011

Added:
cfe/trunk/test/CodeGenOpenCL/builtins-amdgcn-dl-insts-err-clamp.cl
Modified:
cfe/trunk/include/clang/Basic/BuiltinsAMDGPU.def
cfe/trunk/test/CodeGenOpenCL/builtins-amdgcn-dl-insts-err.cl
cfe/trunk/test/CodeGenOpenCL/builtins-amdgcn-dl-insts.cl

Modified: cfe/trunk/include/clang/Basic/BuiltinsAMDGPU.def
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/include/clang/Basic/BuiltinsAMDGPU.def?rev=338471=338470=338471=diff
==
--- cfe/trunk/include/clang/Basic/BuiltinsAMDGPU.def (original)
+++ cfe/trunk/include/clang/Basic/BuiltinsAMDGPU.def Tue Jul 31 18:32:21 2018
@@ -124,13 +124,13 @@ TARGET_BUILTIN(__builtin_amdgcn_fmed3h,
 // Deep learning builtins.
 
//===--===//
 
-TARGET_BUILTIN(__builtin_amdgcn_fdot2, "fV2hV2hf", "nc", "dl-insts")
-TARGET_BUILTIN(__builtin_amdgcn_sdot2, "SiV2SsV2SsSi", "nc", "dl-insts")
-TARGET_BUILTIN(__builtin_amdgcn_udot2, "UiV2UsV2UsUi", "nc", "dl-insts")
-TARGET_BUILTIN(__builtin_amdgcn_sdot4, "SiSiSiSi", "nc", "dl-insts")
-TARGET_BUILTIN(__builtin_amdgcn_udot4, "UiUiUiUi", "nc", "dl-insts")
-TARGET_BUILTIN(__builtin_amdgcn_sdot8, "SiSiSiSi", "nc", "dl-insts")
-TARGET_BUILTIN(__builtin_amdgcn_udot8, "UiUiUiUi", "nc", "dl-insts")
+TARGET_BUILTIN(__builtin_amdgcn_fdot2, "fV2hV2hfIb", "nc", "dl-insts")
+TARGET_BUILTIN(__builtin_amdgcn_sdot2, "SiV2SsV2SsSiIb", "nc", "dl-insts")
+TARGET_BUILTIN(__builtin_amdgcn_udot2, "UiV2UsV2UsUiIb", "nc", "dl-insts")
+TARGET_BUILTIN(__builtin_amdgcn_sdot4, "SiSiSiSiIb", "nc", "dl-insts")
+TARGET_BUILTIN(__builtin_amdgcn_udot4, "UiUiUiUiIb", "nc", "dl-insts")
+TARGET_BUILTIN(__builtin_amdgcn_sdot8, "SiSiSiSiIb", "nc", "dl-insts")
+TARGET_BUILTIN(__builtin_amdgcn_udot8, "UiUiUiUiIb", "nc", "dl-insts")
 
 
//===--===//
 // Special builtins.

Added: cfe/trunk/test/CodeGenOpenCL/builtins-amdgcn-dl-insts-err-clamp.cl
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGenOpenCL/builtins-amdgcn-dl-insts-err-clamp.cl?rev=338471=auto
==
--- cfe/trunk/test/CodeGenOpenCL/builtins-amdgcn-dl-insts-err-clamp.cl (added)
+++ cfe/trunk/test/CodeGenOpenCL/builtins-amdgcn-dl-insts-err-clamp.cl Tue Jul 
31 18:32:21 2018
@@ -0,0 +1,25 @@
+// REQUIRES: amdgpu-registered-target
+
+// RUN: %clang_cc1 -triple amdgcn-unknown-unknown -target-cpu gfx906 -verify 
-S -emit-llvm -o - %s
+
+typedef unsigned int uint;
+typedef half __attribute__((ext_vector_type(2))) half2;
+typedef short __attribute__((ext_vector_type(2))) short2;
+typedef unsigned short __attribute__((ext_vector_type(2))) ushort2;
+
+kernel void builtins_amdgcn_dl_insts_err(
+global float *fOut, global int *siOut, global uint *uiOut,
+half2 v2hA, half2 v2hB, float fC,
+short2 v2ssA, short2 v2ssB, int siA, int siB, int siC,
+ushort2 v2usA, ushort2 v2usB, uint uiA, uint uiB, uint uiC, uint isClamp) {
+  fOut[0] = __builtin_amdgcn_fdot2(v2hA, v2hB, fC, isClamp == 0 ? false : 
true); // expected-error {{'__builtin_amdgcn_fdot2' must be a constant 
integer}}
+
+  siOut[0] = __builtin_amdgcn_sdot2(v2ssA, v2ssB, siC, isClamp == 0 ? false : 
true); // expected-error {{'__builtin_amdgcn_sdot2' must be a constant integer}}
+  uiOut[0] = __builtin_amdgcn_udot2(v2usA, v2usB, uiC, isClamp == 0 ? false : 
true); // expected-error {{'__builtin_amdgcn_udot2' must be a constant integer}}
+
+  siOut[1] = __builtin_amdgcn_sdot4(siA, siB, siC, isClamp == 0 ? false : 
true); // expected-error {{'__builtin_amdgcn_sdot4' must be a constant 
integer}}
+  uiOut[1] = __builtin_amdgcn_udot4(uiA, uiB, uiC, isClamp == 0 ? false : 
true); // expected-error {{'__builtin_amdgcn_udot4' must be a constant 
integer}}
+
+  siOut[2] = __builtin_amdgcn_sdot8(siA, siB, siC, isClamp == 0 ? false : 
true); // expected-error {{'__builtin_amdgcn_sdot8' must be a constant 
integer}}
+  uiOut[2] = __builtin_amdgcn_udot8(uiA, uiB, uiC, isClamp == 0 ? false : 
true); // expected-error {{'__builtin_amdgcn_udot8' must be a constant 
integer}}
+}

Modified: cfe/trunk/test/CodeGenOpenCL/builtins-amdgcn-dl-insts-err.cl
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGenOpenCL/builtins-amdgcn-dl-insts-err.cl?rev=338471=338470=338471=diff
==
--- cfe/trunk/test/CodeGenOpenCL/builtins-amdgcn-dl-insts-err.cl (original)
+++ cfe/trunk/test/CodeGenOpenCL/builtins-amdgcn-dl-insts-err.cl Tue Jul 31 
18:32:21 2018
@@ -12,14 +12,24 @@ kernel void builtins_amdgcn_dl_insts_err
 half2 v2hA, half2 v2hB, float fC,

r337612 - AMDGPU: Switch default dwarf version to 2

2018-07-20 Thread Konstantin Zhuravlyov via cfe-commits 
Author: kzhuravl
Date: Fri Jul 20 13:46:25 2018
New Revision: 337612

URL: http://llvm.org/viewvc/llvm-project?rev=337612=rev
Log:
AMDGPU: Switch default dwarf version to 2

There were some problems unearthed with version 5,
which I am going to look at.

Differential Revision: https://reviews.llvm.org/D49613


Modified:
cfe/trunk/lib/Driver/ToolChains/AMDGPU.h
cfe/trunk/test/Driver/amdgpu-toolchain.c

Modified: cfe/trunk/lib/Driver/ToolChains/AMDGPU.h
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Driver/ToolChains/AMDGPU.h?rev=337612=337611=337612=diff
==
--- cfe/trunk/lib/Driver/ToolChains/AMDGPU.h (original)
+++ cfe/trunk/lib/Driver/ToolChains/AMDGPU.h Fri Jul 20 13:46:25 2018
@@ -56,7 +56,7 @@ protected:
 public:
   AMDGPUToolChain(const Driver , const llvm::Triple ,
   const llvm::opt::ArgList );
-  unsigned GetDefaultDwarfVersion() const override { return 5; }
+  unsigned GetDefaultDwarfVersion() const override { return 2; }
   bool IsIntegratedAssemblerDefault() const override { return true; }
   llvm::opt::DerivedArgList *
   TranslateArgs(const llvm::opt::DerivedArgList , StringRef BoundArch,

Modified: cfe/trunk/test/Driver/amdgpu-toolchain.c
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/Driver/amdgpu-toolchain.c?rev=337612=337611=337612=diff
==
--- cfe/trunk/test/Driver/amdgpu-toolchain.c (original)
+++ cfe/trunk/test/Driver/amdgpu-toolchain.c Fri Jul 20 13:46:25 2018
@@ -3,4 +3,4 @@
 // AS_LINK: ld.lld{{.*}} "-shared"
 
 // RUN: %clang -### -g -target amdgcn--amdhsa -mcpu=kaveri %s 2>&1 | FileCheck 
-check-prefix=DWARF_VER %s
-// DWARF_VER: "-dwarf-version=5"
+// DWARF_VER: "-dwarf-version=2"


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r335287 - AMDGPU: Remove amdgpu-debugger-reserve-regs feature

2018-06-21 Thread Konstantin Zhuravlyov via cfe-commits 
Author: kzhuravl
Date: Thu Jun 21 13:27:47 2018
New Revision: 335287

URL: http://llvm.org/viewvc/llvm-project?rev=335287=rev
Log:
AMDGPU: Remove amdgpu-debugger-reserve-regs feature


Modified:
cfe/trunk/lib/Driver/ToolChains/AMDGPU.cpp
cfe/trunk/test/Driver/amdgpu-features.c

Modified: cfe/trunk/lib/Driver/ToolChains/AMDGPU.cpp
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Driver/ToolChains/AMDGPU.cpp?rev=335287=335286=335287=diff
==
--- cfe/trunk/lib/Driver/ToolChains/AMDGPU.cpp (original)
+++ cfe/trunk/lib/Driver/ToolChains/AMDGPU.cpp Thu Jun 21 13:27:47 2018
@@ -43,7 +43,6 @@ void amdgpu::getAMDGPUTargetFeatures(con
 StringRef value = dAbi->getValue();
 if (value == "1.0") {
   Features.push_back("+amdgpu-debugger-insert-nops");
-  Features.push_back("+amdgpu-debugger-reserve-regs");
   Features.push_back("+amdgpu-debugger-emit-prologue");
 } else {
   D.Diag(diag::err_drv_clang_unsupported) << dAbi->getAsString(Args);

Modified: cfe/trunk/test/Driver/amdgpu-features.c
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/Driver/amdgpu-features.c?rev=335287=335286=335287=diff
==
--- cfe/trunk/test/Driver/amdgpu-features.c (original)
+++ cfe/trunk/test/Driver/amdgpu-features.c Thu Jun 21 13:27:47 2018
@@ -4,7 +4,7 @@
 
 // RUN: %clang -### -target amdgcn -x cl -S -emit-llvm -mcpu=kaveri 
-mamdgpu-debugger-abi=1.0 %s -o - 2>&1 \
 // RUN:   | FileCheck --check-prefix=CHECK-MAMDGPU-DEBUGGER-ABI-1-0 %s
-// CHECK-MAMDGPU-DEBUGGER-ABI-1-0: "-target-feature" 
"+amdgpu-debugger-insert-nops" "-target-feature" 
"+amdgpu-debugger-reserve-regs" "-target-feature" 
"+amdgpu-debugger-emit-prologue"
+// CHECK-MAMDGPU-DEBUGGER-ABI-1-0: "-target-feature" 
"+amdgpu-debugger-insert-nops" "-target-feature" 
"+amdgpu-debugger-emit-prologue"
 
 // RUN: %clang -### -target amdgcn -mcpu=gfx700 -mxnack %s 2>&1 | FileCheck 
--check-prefix=XNACK %s
 // XNACK: "-target-feature" "+xnack"


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r326278 - AMDGPU: Move run and check lines around to match processor order in AMDGPU.h

2018-02-27 Thread Konstantin Zhuravlyov via cfe-commits 
Author: kzhuravl
Date: Tue Feb 27 16:27:00 2018
New Revision: 326278

URL: http://llvm.org/viewvc/llvm-project?rev=326278=rev
Log:
AMDGPU: Move run and check lines around to match processor order in AMDGPU.h

Modified:
cfe/trunk/test/Driver/amdgpu-mcpu.cl

Modified: cfe/trunk/test/Driver/amdgpu-mcpu.cl
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/Driver/amdgpu-mcpu.cl?rev=326278=326277=326278=diff
==
--- cfe/trunk/test/Driver/amdgpu-mcpu.cl (original)
+++ cfe/trunk/test/Driver/amdgpu-mcpu.cl Tue Feb 27 16:27:00 2018
@@ -27,9 +27,9 @@
 // RUN: %clang -### -target r600 -mcpu=sumo2 %s 2>&1 | FileCheck 
--check-prefix=SUMO %s
 // RUN: %clang -### -target r600 -mcpu=barts %s 2>&1 | FileCheck 
--check-prefix=BARTS %s
 // RUN: %clang -### -target r600 -mcpu=caicos %s 2>&1 | FileCheck 
--check-prefix=CAICOS %s
-// RUN: %clang -### -target r600 -mcpu=turks %s 2>&1 | FileCheck 
--check-prefix=TURKS %s
 // RUN: %clang -### -target r600 -mcpu=aruba %s 2>&1 | FileCheck 
--check-prefix=CAYMAN %s
 // RUN: %clang -### -target r600 -mcpu=cayman %s 2>&1 | FileCheck 
--check-prefix=CAYMAN %s
+// RUN: %clang -### -target r600 -mcpu=turks %s 2>&1 | FileCheck 
--check-prefix=TURKS %s
 
 // R600:"-target-cpu" "r600"
 // R630:"-target-cpu" "r630"
@@ -45,8 +45,8 @@
 // SUMO:"-target-cpu" "sumo"
 // BARTS:   "-target-cpu" "barts"
 // CAICOS:  "-target-cpu" "caicos"
-// TURKS:   "-target-cpu" "turks"
 // CAYMAN:  "-target-cpu" "cayman"
+// TURKS:   "-target-cpu" "turks"
 
 //
 // AMDGCN-based processors.


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r326254 - AMDGPU: Define FP_FAST_FMA{F} macros for amdgcn

2018-02-27 Thread Konstantin Zhuravlyov via cfe-commits 
Author: kzhuravl
Date: Tue Feb 27 13:48:05 2018
New Revision: 326254

URL: http://llvm.org/viewvc/llvm-project?rev=326254=rev
Log:
AMDGPU: Define FP_FAST_FMA{F} macros for amdgcn

- Expand GK_*s (i.e. GFX6 -> GFX600, GFX601, etc.)
  - This allows us to choose features correctly in some cases (for example, 
fast fmaf is available on gfx600, but not gfx601)
- Move HasFMAF, HasFP64, HasLDEXPF to GPUInfo tables
- Add HasFastFMA, HasFastFMAF to GPUInfo tables
- Add missing tests

Modified:
cfe/trunk/lib/Basic/Targets/AMDGPU.cpp
cfe/trunk/lib/Basic/Targets/AMDGPU.h
cfe/trunk/test/Driver/amdgpu-macros.cl
cfe/trunk/test/Misc/target-invalid-cpu-note.c

Modified: cfe/trunk/lib/Basic/Targets/AMDGPU.cpp
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Basic/Targets/AMDGPU.cpp?rev=326254=326253=326254=diff
==
--- cfe/trunk/lib/Basic/Targets/AMDGPU.cpp (original)
+++ cfe/trunk/lib/Basic/Targets/AMDGPU.cpp Tue Feb 27 13:48:05 2018
@@ -157,49 +157,62 @@ bool AMDGPUTargetInfo::initFeatureMap(
 const std::vector ) const {
 
   // XXX - What does the member GPU mean if device name string passed here?
-  if (getTriple().getArch() == llvm::Triple::amdgcn) {
+  if (isAMDGCN(getTriple())) {
 if (CPU.empty())
-  CPU = "tahiti";
+  CPU = "gfx600";
 
 switch (parseAMDGCNName(CPU).Kind) {
-case GK_GFX6:
-case GK_GFX7:
-  break;
-
-case GK_GFX9:
+case GK_GFX902:
+case GK_GFX900:
   Features["gfx9-insts"] = true;
   LLVM_FALLTHROUGH;
-case GK_GFX8:
-  Features["s-memrealtime"] = true;
+case GK_GFX810:
+case GK_GFX803:
+case GK_GFX802:
+case GK_GFX801:
   Features["16-bit-insts"] = true;
   Features["dpp"] = true;
+  Features["s-memrealtime"] = true;
+  break;
+case GK_GFX704:
+case GK_GFX703:
+case GK_GFX702:
+case GK_GFX701:
+case GK_GFX700:
+case GK_GFX601:
+case GK_GFX600:
   break;
-
 case GK_NONE:
   return false;
 default:
-  llvm_unreachable("unhandled subtarget");
+  llvm_unreachable("Unhandled GPU!");
 }
   } else {
 if (CPU.empty())
   CPU = "r600";
 
 switch (parseR600Name(CPU).Kind) {
-case GK_R600:
-case GK_R700:
-case GK_EVERGREEN:
-case GK_NORTHERN_ISLANDS:
-  break;
-case GK_R600_DOUBLE_OPS:
-case GK_R700_DOUBLE_OPS:
-case GK_EVERGREEN_DOUBLE_OPS:
 case GK_CAYMAN:
+case GK_CYPRESS:
+case GK_RV770:
+case GK_RV670:
   // TODO: Add fp64 when implemented.
   break;
-case GK_NONE:
-  return false;
+case GK_TURKS:
+case GK_CAICOS:
+case GK_BARTS:
+case GK_SUMO:
+case GK_REDWOOD:
+case GK_JUNIPER:
+case GK_CEDAR:
+case GK_RV730:
+case GK_RV710:
+case GK_RS880:
+case GK_R630:
+case GK_R600:
+  break;
 default:
-  llvm_unreachable("unhandled subtarget");
+  llvm_unreachable("Unhandled GPU!");
 }
   }
 
@@ -210,6 +223,7 @@ void AMDGPUTargetInfo::adjustTargetOptio
TargetOptions ) const {
   bool hasFP32Denormals = false;
   bool hasFP64Denormals = false;
+  GPUInfo CGOptsGPU = parseGPUName(TargetOpts.CPU);
   for (auto  : TargetOpts.FeaturesAsWritten) {
 if (I == "+fp32-denormals" || I == "-fp32-denormals")
   hasFP32Denormals = true;
@@ -218,46 +232,52 @@ void AMDGPUTargetInfo::adjustTargetOptio
   }
   if (!hasFP32Denormals)
 TargetOpts.Features.push_back(
-(Twine(hasFullSpeedFMAF32(TargetOpts.CPU) && !CGOpts.FlushDenorm
+(Twine(CGOptsGPU.HasFastFMAF && !CGOpts.FlushDenorm
? '+'
: '-') +
  Twine("fp32-denormals"))
 .str());
   // Always do not flush fp64 or fp16 denorms.
-  if (!hasFP64Denormals && hasFP64)
+  if (!hasFP64Denormals && CGOptsGPU.HasFP64)
 TargetOpts.Features.push_back("+fp64-fp16-denormals");
 }
 
 constexpr AMDGPUTargetInfo::GPUInfo AMDGPUTargetInfo::InvalidGPU;
-constexpr AMDGPUTargetInfo::GPUInfo AMDGPUTargetInfo::R600Names[];
-constexpr AMDGPUTargetInfo::GPUInfo AMDGPUTargetInfo::AMDGCNNames[];
+constexpr AMDGPUTargetInfo::GPUInfo AMDGPUTargetInfo::R600GPUs[];
+constexpr AMDGPUTargetInfo::GPUInfo AMDGPUTargetInfo::AMDGCNGPUs[];
+
 AMDGPUTargetInfo::GPUInfo AMDGPUTargetInfo::parseR600Name(StringRef Name) {
   const auto *Result = llvm::find_if(
-  R600Names, [Name](const GPUInfo ) { return GPU.Name == Name; });
+  R600GPUs, [Name](const GPUInfo ) { return GPU.Name == Name; });
 
-  if (Result == std::end(R600Names))
+  if (Result == std::end(R600GPUs))
 return InvalidGPU;
   return *Result;
 }
 
 AMDGPUTargetInfo::GPUInfo AMDGPUTargetInfo::parseAMDGCNName(StringRef Name) {
-  const auto *Result =
-  llvm::find_if(AMDGCNNames, [Name](const GPUInfo ) {
-return GPU.Name == Name;
-  });
+  const auto *Result = llvm::find_if(
+  AMDGCNGPUs, [Name](const GPUInfo ) {

r325203 - Reapply r325193

2018-02-14 Thread Konstantin Zhuravlyov via cfe-commits 
Author: kzhuravl
Date: Wed Feb 14 18:37:04 2018
New Revision: 325203

URL: http://llvm.org/viewvc/llvm-project?rev=325203=rev
Log:
Reapply r325193

Added:
cfe/trunk/test/Driver/amdgpu-macros.cl
  - copied unchanged from r325199, cfe/trunk/test/Driver/amdgpu-macros.cl
Modified:
cfe/trunk/lib/Basic/Targets/AMDGPU.cpp
cfe/trunk/lib/Basic/Targets/AMDGPU.h

Modified: cfe/trunk/lib/Basic/Targets/AMDGPU.cpp
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Basic/Targets/AMDGPU.cpp?rev=325203=325202=325203=diff
==
--- cfe/trunk/lib/Basic/Targets/AMDGPU.cpp (original)
+++ cfe/trunk/lib/Basic/Targets/AMDGPU.cpp Wed Feb 14 18:37:04 2018
@@ -161,7 +161,7 @@ bool AMDGPUTargetInfo::initFeatureMap(
 if (CPU.empty())
   CPU = "tahiti";
 
-switch (parseAMDGCNName(CPU)) {
+switch (parseAMDGCNName(CPU).Kind) {
 case GK_GFX6:
 case GK_GFX7:
   break;
@@ -184,7 +184,7 @@ bool AMDGPUTargetInfo::initFeatureMap(
 if (CPU.empty())
   CPU = "r600";
 
-switch (parseR600Name(CPU)) {
+switch (parseR600Name(CPU).Kind) {
 case GK_R600:
 case GK_R700:
 case GK_EVERGREEN:
@@ -229,36 +229,36 @@ void AMDGPUTargetInfo::adjustTargetOptio
 }
 
 constexpr AMDGPUTargetInfo::GPUInfo AMDGPUTargetInfo::InvalidGPU;
-constexpr AMDGPUTargetInfo::NameGPUKind AMDGPUTargetInfo::R600Names[];
-constexpr AMDGPUTargetInfo::NameGPUKind AMDGPUTargetInfo::AMDGCNNames[];
-AMDGPUTargetInfo::GPUKind AMDGPUTargetInfo::parseR600Name(StringRef Name) {
+constexpr AMDGPUTargetInfo::GPUInfo AMDGPUTargetInfo::R600Names[];
+constexpr AMDGPUTargetInfo::GPUInfo AMDGPUTargetInfo::AMDGCNNames[];
+AMDGPUTargetInfo::GPUInfo AMDGPUTargetInfo::parseR600Name(StringRef Name) {
   const auto *Result = llvm::find_if(
-  R600Names, [Name](const NameGPUKind ) { return Kind.Name == Name; 
});
+  R600Names, [Name](const GPUInfo ) { return GPU.Name == Name; });
 
   if (Result == std::end(R600Names))
-return GK_NONE;
-  return Result->Kind;
+return InvalidGPU;
+  return *Result;
 }
 
-AMDGPUTargetInfo::GPUKind AMDGPUTargetInfo::parseAMDGCNName(StringRef Name) {
+AMDGPUTargetInfo::GPUInfo AMDGPUTargetInfo::parseAMDGCNName(StringRef Name) {
   const auto *Result =
-  llvm::find_if(AMDGCNNames, [Name](const NameGPUKind ) {
-return Kind.Name == Name;
+  llvm::find_if(AMDGCNNames, [Name](const GPUInfo ) {
+return GPU.Name == Name;
   });
 
   if (Result == std::end(AMDGCNNames))
-return GK_NONE;
-  return Result->Kind;
+return InvalidGPU;
+  return *Result;
 }
 
 void AMDGPUTargetInfo::fillValidCPUList(
 SmallVectorImpl ) const {
   if (getTriple().getArch() == llvm::Triple::amdgcn)
-llvm::for_each(AMDGCNNames, [](const NameGPUKind ) {
-   Values.emplace_back(Kind.Name);});
+llvm::for_each(AMDGCNNames, [](const GPUInfo ) {
+   Values.emplace_back(GPU.Name);});
   else
-llvm::for_each(R600Names, [](const NameGPUKind ) {
-   Values.emplace_back(Kind.Name);});
+llvm::for_each(R600Names, [](const GPUInfo ) {
+   Values.emplace_back(GPU.Name);});
 }
 
 void AMDGPUTargetInfo::setAddressSpaceMap(bool DefaultIsPrivate) {
@@ -273,17 +273,17 @@ void AMDGPUTargetInfo::setAddressSpaceMa
 
 AMDGPUTargetInfo::AMDGPUTargetInfo(const llvm::Triple ,
const TargetOptions )
-: TargetInfo(Triple),
-  GPU(isAMDGCN(Triple) ? GK_GFX6 : parseR600Name(Opts.CPU)),
-  hasFP64(false), hasFMAF(false), hasLDEXPF(false),
-  AS(isGenericZero(Triple)) {
+  : TargetInfo(Triple),
+GPU(isAMDGCN(Triple) ? AMDGCNNames[0] : parseR600Name(Opts.CPU)),
+hasFP64(false), hasFMAF(false), hasLDEXPF(false),
+AS(isGenericZero(Triple)) {
   if (getTriple().getArch() == llvm::Triple::amdgcn) {
 hasFP64 = true;
 hasFMAF = true;
 hasLDEXPF = true;
   }
   if (getTriple().getArch() == llvm::Triple::r600) {
-if (GPU == GK_EVERGREEN_DOUBLE_OPS || GPU == GK_CAYMAN) {
+if (GPU.Kind == GK_EVERGREEN_DOUBLE_OPS || GPU.Kind == GK_CAYMAN) {
   hasFMAF = true;
 }
   }
@@ -324,11 +324,17 @@ ArrayRef AMDGPUTargetInfo
 
 void AMDGPUTargetInfo::getTargetDefines(const LangOptions ,
 MacroBuilder ) const {
+  Builder.defineMacro("__AMD__");
+  Builder.defineMacro("__AMDGPU__");
+
   if (getTriple().getArch() == llvm::Triple::amdgcn)
 Builder.defineMacro("__AMDGCN__");
   else
 Builder.defineMacro("__R600__");
 
+  if (GPU.Kind != GK_NONE)
+Builder.defineMacro(Twine("__") + Twine(GPU.CanonicalName) + Twine("__"));
+
   if (hasFMAF)
 Builder.defineMacro("__HAS_FMAF__");
   if (hasLDEXPF)

Modified: cfe/trunk/lib/Basic/Targets/AMDGPU.h
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Basic/Targets/AMDGPU.h?rev=325203=325202=325203=diff
==
---

Re: r325195 - Add missing definition for class static after r325193.

2018-02-14 Thread Konstantin Zhuravlyov via cfe-commits 
I did not see this. I will reapply the patch. Sorry for the noise.

From: cfe-commits  on behalf of Richard 
Smith via cfe-commits 
Sent: Wednesday, February 14, 2018 8:01 PM
To: cfe-commits@lists.llvm.org
Subject: r325195 - Add missing definition for class static after r325193.

Author: rsmith
Date: Wed Feb 14 17:01:06 2018
New Revision: 325195

URL: http://llvm.org/viewvc/llvm-project?rev=325195=rev
Log:
Add missing definition for class static after r325193.

Modified:
cfe/trunk/lib/Basic/Targets/AMDGPU.cpp

Modified: cfe/trunk/lib/Basic/Targets/AMDGPU.cpp
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Basic/Targets/AMDGPU.cpp?rev=325195=325194=325195=diff
==
--- cfe/trunk/lib/Basic/Targets/AMDGPU.cpp (original)
+++ cfe/trunk/lib/Basic/Targets/AMDGPU.cpp Wed Feb 14 17:01:06 2018
@@ -228,7 +228,7 @@ void AMDGPUTargetInfo::adjustTargetOptio
 TargetOpts.Features.push_back("+fp64-fp16-denormals");
 }

-
+constexpr AMDGPUTargetInfo::GPUInfo AMDGPUTargetInfo::InvalidGPU;
 constexpr AMDGPUTargetInfo::GPUInfo AMDGPUTargetInfo::R600Names[];
 constexpr AMDGPUTargetInfo::GPUInfo AMDGPUTargetInfo::AMDGCNNames[];
 AMDGPUTargetInfo::GPUInfo AMDGPUTargetInfo::parseR600Name(StringRef Name) {


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r325200 - Revert r325193 as it breaks buildbots

2018-02-14 Thread Konstantin Zhuravlyov via cfe-commits 
Author: kzhuravl
Date: Wed Feb 14 18:27:45 2018
New Revision: 325200

URL: http://llvm.org/viewvc/llvm-project?rev=325200=rev
Log:
Revert r325193 as it breaks buildbots

Removed:
cfe/trunk/test/Driver/amdgpu-macros.cl
Modified:
cfe/trunk/lib/Basic/Targets/AMDGPU.cpp
cfe/trunk/lib/Basic/Targets/AMDGPU.h

Modified: cfe/trunk/lib/Basic/Targets/AMDGPU.cpp
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Basic/Targets/AMDGPU.cpp?rev=325200=325199=325200=diff
==
--- cfe/trunk/lib/Basic/Targets/AMDGPU.cpp (original)
+++ cfe/trunk/lib/Basic/Targets/AMDGPU.cpp Wed Feb 14 18:27:45 2018
@@ -161,7 +161,7 @@ bool AMDGPUTargetInfo::initFeatureMap(
 if (CPU.empty())
   CPU = "tahiti";
 
-switch (parseAMDGCNName(CPU).Kind) {
+switch (parseAMDGCNName(CPU)) {
 case GK_GFX6:
 case GK_GFX7:
   break;
@@ -184,7 +184,7 @@ bool AMDGPUTargetInfo::initFeatureMap(
 if (CPU.empty())
   CPU = "r600";
 
-switch (parseR600Name(CPU).Kind) {
+switch (parseR600Name(CPU)) {
 case GK_R600:
 case GK_R700:
 case GK_EVERGREEN:
@@ -229,36 +229,36 @@ void AMDGPUTargetInfo::adjustTargetOptio
 }
 
 constexpr AMDGPUTargetInfo::GPUInfo AMDGPUTargetInfo::InvalidGPU;
-constexpr AMDGPUTargetInfo::GPUInfo AMDGPUTargetInfo::R600Names[];
-constexpr AMDGPUTargetInfo::GPUInfo AMDGPUTargetInfo::AMDGCNNames[];
-AMDGPUTargetInfo::GPUInfo AMDGPUTargetInfo::parseR600Name(StringRef Name) {
+constexpr AMDGPUTargetInfo::NameGPUKind AMDGPUTargetInfo::R600Names[];
+constexpr AMDGPUTargetInfo::NameGPUKind AMDGPUTargetInfo::AMDGCNNames[];
+AMDGPUTargetInfo::GPUKind AMDGPUTargetInfo::parseR600Name(StringRef Name) {
   const auto *Result = llvm::find_if(
-  R600Names, [Name](const GPUInfo ) { return GPU.Name == Name; });
+  R600Names, [Name](const NameGPUKind ) { return Kind.Name == Name; 
});
 
   if (Result == std::end(R600Names))
-return InvalidGPU;
-  return *Result;
+return GK_NONE;
+  return Result->Kind;
 }
 
-AMDGPUTargetInfo::GPUInfo AMDGPUTargetInfo::parseAMDGCNName(StringRef Name) {
+AMDGPUTargetInfo::GPUKind AMDGPUTargetInfo::parseAMDGCNName(StringRef Name) {
   const auto *Result =
-  llvm::find_if(AMDGCNNames, [Name](const GPUInfo ) {
-return GPU.Name == Name;
+  llvm::find_if(AMDGCNNames, [Name](const NameGPUKind ) {
+return Kind.Name == Name;
   });
 
   if (Result == std::end(AMDGCNNames))
-return InvalidGPU;
-  return *Result;
+return GK_NONE;
+  return Result->Kind;
 }
 
 void AMDGPUTargetInfo::fillValidCPUList(
 SmallVectorImpl ) const {
   if (getTriple().getArch() == llvm::Triple::amdgcn)
-llvm::for_each(AMDGCNNames, [](const GPUInfo ) {
-   Values.emplace_back(GPU.Name);});
+llvm::for_each(AMDGCNNames, [](const NameGPUKind ) {
+   Values.emplace_back(Kind.Name);});
   else
-llvm::for_each(R600Names, [](const GPUInfo ) {
-   Values.emplace_back(GPU.Name);});
+llvm::for_each(R600Names, [](const NameGPUKind ) {
+   Values.emplace_back(Kind.Name);});
 }
 
 void AMDGPUTargetInfo::setAddressSpaceMap(bool DefaultIsPrivate) {
@@ -273,17 +273,17 @@ void AMDGPUTargetInfo::setAddressSpaceMa
 
 AMDGPUTargetInfo::AMDGPUTargetInfo(const llvm::Triple ,
const TargetOptions )
-  : TargetInfo(Triple),
-GPU(isAMDGCN(Triple) ? AMDGCNNames[0] : parseR600Name(Opts.CPU)),
-hasFP64(false), hasFMAF(false), hasLDEXPF(false),
-AS(isGenericZero(Triple)) {
+: TargetInfo(Triple),
+  GPU(isAMDGCN(Triple) ? GK_GFX6 : parseR600Name(Opts.CPU)),
+  hasFP64(false), hasFMAF(false), hasLDEXPF(false),
+  AS(isGenericZero(Triple)) {
   if (getTriple().getArch() == llvm::Triple::amdgcn) {
 hasFP64 = true;
 hasFMAF = true;
 hasLDEXPF = true;
   }
   if (getTriple().getArch() == llvm::Triple::r600) {
-if (GPU.Kind == GK_EVERGREEN_DOUBLE_OPS || GPU.Kind == GK_CAYMAN) {
+if (GPU == GK_EVERGREEN_DOUBLE_OPS || GPU == GK_CAYMAN) {
   hasFMAF = true;
 }
   }
@@ -324,17 +324,11 @@ ArrayRef AMDGPUTargetInfo
 
 void AMDGPUTargetInfo::getTargetDefines(const LangOptions ,
 MacroBuilder ) const {
-  Builder.defineMacro("__AMD__");
-  Builder.defineMacro("__AMDGPU__");
-
   if (getTriple().getArch() == llvm::Triple::amdgcn)
 Builder.defineMacro("__AMDGCN__");
   else
 Builder.defineMacro("__R600__");
 
-  if (GPU.Kind != GK_NONE)
-Builder.defineMacro(Twine("__") + Twine(GPU.CanonicalName) + Twine("__"));
-
   if (hasFMAF)
 Builder.defineMacro("__HAS_FMAF__");
   if (hasLDEXPF)

Modified: cfe/trunk/lib/Basic/Targets/AMDGPU.h
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Basic/Targets/AMDGPU.h?rev=325200=325199=325200=diff
==
--- cfe/trunk/lib/Basic/Targets/AMDGPU.h (original)
+++

r325196 - AMDGPU: Enable PIC by default for amdgcn

2018-02-14 Thread Konstantin Zhuravlyov via cfe-commits 
Author: kzhuravl
Date: Wed Feb 14 17:01:53 2018
New Revision: 325196

URL: http://llvm.org/viewvc/llvm-project?rev=325196=rev
Log:
AMDGPU: Enable PIC by default for amdgcn

Differential Revision: https://reviews.llvm.org/D43094

Added:
cfe/trunk/test/Driver/amdgcn-toolchain-pic.cl
Modified:
cfe/trunk/lib/Driver/ToolChains/CommonArgs.cpp

Modified: cfe/trunk/lib/Driver/ToolChains/CommonArgs.cpp
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Driver/ToolChains/CommonArgs.cpp?rev=325196=325195=325196=diff
==
--- cfe/trunk/lib/Driver/ToolChains/CommonArgs.cpp (original)
+++ cfe/trunk/lib/Driver/ToolChains/CommonArgs.cpp Wed Feb 14 17:01:53 2018
@@ -864,6 +864,10 @@ tools::ParsePICArgs(const ToolChain 
 }
   }
 
+  // AMDGPU-specific defaults for PIC.
+  if (Triple.getArch() == llvm::Triple::amdgcn)
+PIC = true;
+
   // The last argument relating to either PIC or PIE wins, and no
   // other argument is used. If the last argument is any flavor of the
   // '-fno-...' arguments, both PIC and PIE are disabled. Any PIE

Added: cfe/trunk/test/Driver/amdgcn-toolchain-pic.cl
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/Driver/amdgcn-toolchain-pic.cl?rev=325196=auto
==
--- cfe/trunk/test/Driver/amdgcn-toolchain-pic.cl (added)
+++ cfe/trunk/test/Driver/amdgcn-toolchain-pic.cl Wed Feb 14 17:01:53 2018
@@ -0,0 +1,7 @@
+// RUN: %clang -### -target amdgcn-- -mcpu=gfx803 %s 2>&1 | FileCheck %s
+// RUN: %clang -### -target amdgcn-amd- -mcpu=gfx803 %s 2>&1 | FileCheck %s
+// RUN: %clang -### -target amdgcn-amd-amdhsa -mcpu=gfx803 %s 2>&1 | FileCheck 
%s
+// RUN: %clang -### -target amdgcn-amd-amdpal -mcpu=gfx803 %s 2>&1 | FileCheck 
%s
+// RUN: %clang -### -target amdgcn-amd-mesa3d -mcpu=gfx803 %s 2>&1 | FileCheck 
%s
+
+// CHECK: clang{{.*}} "-mrelocation-model" "pic" "-pic-level" "1"


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r325193 - AMDGPU: Cleanup most of the macros

2018-02-14 Thread Konstantin Zhuravlyov via cfe-commits 
Author: kzhuravl
Date: Wed Feb 14 16:20:26 2018
New Revision: 325193

URL: http://llvm.org/viewvc/llvm-project?rev=325193=rev
Log:
AMDGPU: Cleanup most of the macros

- Insert __AMD__ macro
- Insert __AMDGPU__ macro
- Insert __devicename__ macro
- Add missing tests for arch macros

Differential Revision: https://reviews.llvm.org/D36802

Added:
cfe/trunk/test/Driver/amdgpu-macros.cl
Modified:
cfe/trunk/lib/Basic/Targets/AMDGPU.cpp
cfe/trunk/lib/Basic/Targets/AMDGPU.h

Modified: cfe/trunk/lib/Basic/Targets/AMDGPU.cpp
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Basic/Targets/AMDGPU.cpp?rev=325193=325192=325193=diff
==
--- cfe/trunk/lib/Basic/Targets/AMDGPU.cpp (original)
+++ cfe/trunk/lib/Basic/Targets/AMDGPU.cpp Wed Feb 14 16:20:26 2018
@@ -161,7 +161,7 @@ bool AMDGPUTargetInfo::initFeatureMap(
 if (CPU.empty())
   CPU = "tahiti";
 
-switch (parseAMDGCNName(CPU)) {
+switch (parseAMDGCNName(CPU).Kind) {
 case GK_GFX6:
 case GK_GFX7:
   break;
@@ -184,7 +184,7 @@ bool AMDGPUTargetInfo::initFeatureMap(
 if (CPU.empty())
   CPU = "r600";
 
-switch (parseR600Name(CPU)) {
+switch (parseR600Name(CPU).Kind) {
 case GK_R600:
 case GK_R700:
 case GK_EVERGREEN:
@@ -229,36 +229,36 @@ void AMDGPUTargetInfo::adjustTargetOptio
 }
 
 
-constexpr AMDGPUTargetInfo::NameGPUKind AMDGPUTargetInfo::R600Names[];
-constexpr AMDGPUTargetInfo::NameGPUKind AMDGPUTargetInfo::AMDGCNNames[];
-AMDGPUTargetInfo::GPUKind AMDGPUTargetInfo::parseR600Name(StringRef Name) {
+constexpr AMDGPUTargetInfo::GPUInfo AMDGPUTargetInfo::R600Names[];
+constexpr AMDGPUTargetInfo::GPUInfo AMDGPUTargetInfo::AMDGCNNames[];
+AMDGPUTargetInfo::GPUInfo AMDGPUTargetInfo::parseR600Name(StringRef Name) {
   const auto *Result = llvm::find_if(
-  R600Names, [Name](const NameGPUKind ) { return Kind.Name == Name; 
});
+  R600Names, [Name](const GPUInfo ) { return GPU.Name == Name; });
 
   if (Result == std::end(R600Names))
-return GK_NONE;
-  return Result->Kind;
+return InvalidGPU;
+  return *Result;
 }
 
-AMDGPUTargetInfo::GPUKind AMDGPUTargetInfo::parseAMDGCNName(StringRef Name) {
+AMDGPUTargetInfo::GPUInfo AMDGPUTargetInfo::parseAMDGCNName(StringRef Name) {
   const auto *Result =
-  llvm::find_if(AMDGCNNames, [Name](const NameGPUKind ) {
-return Kind.Name == Name;
+  llvm::find_if(AMDGCNNames, [Name](const GPUInfo ) {
+return GPU.Name == Name;
   });
 
   if (Result == std::end(AMDGCNNames))
-return GK_NONE;
-  return Result->Kind;
+return InvalidGPU;
+  return *Result;
 }
 
 void AMDGPUTargetInfo::fillValidCPUList(
 SmallVectorImpl ) const {
   if (getTriple().getArch() == llvm::Triple::amdgcn)
-llvm::for_each(AMDGCNNames, [](const NameGPUKind ) {
-   Values.emplace_back(Kind.Name);});
+llvm::for_each(AMDGCNNames, [](const GPUInfo ) {
+   Values.emplace_back(GPU.Name);});
   else
-llvm::for_each(R600Names, [](const NameGPUKind ) {
-   Values.emplace_back(Kind.Name);});
+llvm::for_each(R600Names, [](const GPUInfo ) {
+   Values.emplace_back(GPU.Name);});
 }
 
 void AMDGPUTargetInfo::setAddressSpaceMap(bool DefaultIsPrivate) {
@@ -273,17 +273,17 @@ void AMDGPUTargetInfo::setAddressSpaceMa
 
 AMDGPUTargetInfo::AMDGPUTargetInfo(const llvm::Triple ,
const TargetOptions )
-: TargetInfo(Triple),
-  GPU(isAMDGCN(Triple) ? GK_GFX6 : parseR600Name(Opts.CPU)),
-  hasFP64(false), hasFMAF(false), hasLDEXPF(false),
-  AS(isGenericZero(Triple)) {
+  : TargetInfo(Triple),
+GPU(isAMDGCN(Triple) ? AMDGCNNames[0] : parseR600Name(Opts.CPU)),
+hasFP64(false), hasFMAF(false), hasLDEXPF(false),
+AS(isGenericZero(Triple)) {
   if (getTriple().getArch() == llvm::Triple::amdgcn) {
 hasFP64 = true;
 hasFMAF = true;
 hasLDEXPF = true;
   }
   if (getTriple().getArch() == llvm::Triple::r600) {
-if (GPU == GK_EVERGREEN_DOUBLE_OPS || GPU == GK_CAYMAN) {
+if (GPU.Kind == GK_EVERGREEN_DOUBLE_OPS || GPU.Kind == GK_CAYMAN) {
   hasFMAF = true;
 }
   }
@@ -324,11 +324,17 @@ ArrayRef AMDGPUTargetInfo
 
 void AMDGPUTargetInfo::getTargetDefines(const LangOptions ,
 MacroBuilder ) const {
+  Builder.defineMacro("__AMD__");
+  Builder.defineMacro("__AMDGPU__");
+
   if (getTriple().getArch() == llvm::Triple::amdgcn)
 Builder.defineMacro("__AMDGCN__");
   else
 Builder.defineMacro("__R600__");
 
+  if (GPU.Kind != GK_NONE)
+Builder.defineMacro(Twine("__") + Twine(GPU.CanonicalName) + Twine("__"));
+
   if (hasFMAF)
 Builder.defineMacro("__HAS_FMAF__");
   if (hasLDEXPF)

Modified: cfe/trunk/lib/Basic/Targets/AMDGPU.h
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Basic/Targets/AMDGPU.h?rev=325193=325192=325193=diff

r324714 - AMDGPU/GCN: Bring processors in sync with AMDGPUUsage

2018-02-08 Thread Konstantin Zhuravlyov via cfe-commits 
Author: kzhuravl
Date: Thu Feb  8 23:02:28 2018
New Revision: 324714

URL: http://llvm.org/viewvc/llvm-project?rev=324714=rev
Log:
AMDGPU/GCN: Bring processors in sync with AMDGPUUsage

- Remove gfx800
- Remove gfx804
- Remove gfx901
- Remove gfx903

Differential Revision: https://reviews.llvm.org/D40045

Modified:
cfe/trunk/lib/Basic/Targets/AMDGPU.h
cfe/trunk/test/Driver/amdgpu-mcpu.cl

Modified: cfe/trunk/lib/Basic/Targets/AMDGPU.h
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Basic/Targets/AMDGPU.h?rev=324714=324713=324714=diff
==
--- cfe/trunk/lib/Basic/Targets/AMDGPU.h (original)
+++ cfe/trunk/lib/Basic/Targets/AMDGPU.h Thu Feb  8 23:02:28 2018
@@ -69,51 +69,65 @@ class LLVM_LIBRARY_VISIBILITY AMDGPUTarg
 AMDGPUTargetInfo::GPUKind Kind;
   };
 
-  static constexpr NameGPUKind R600Names[25] = {
+  static constexpr NameGPUKind R600Names[26] = {
   {{"r600"}, GK_R600},
-  {{"rv610"}, GK_R600},
-  {{"rv620"}, GK_R600},
   {{"rv630"}, GK_R600},
   {{"rv635"}, GK_R600},
+  {{"r630"}, GK_R600},
   {{"rs780"}, GK_R600},
   {{"rs880"}, GK_R600},
+  {{"rv610"}, GK_R600},
+  {{"rv620"}, GK_R600},
   {{"rv670"}, GK_R600_DOUBLE_OPS},
   {{"rv710"}, GK_R700},
   {{"rv730"}, GK_R700},
   {{"rv740"}, GK_R700_DOUBLE_OPS},
   {{"rv770"}, GK_R700_DOUBLE_OPS},
-  {{"palm"}, GK_EVERGREEN},
   {{"cedar"}, GK_EVERGREEN},
+  {{"palm"}, GK_EVERGREEN},
+  {{"cypress"}, GK_EVERGREEN_DOUBLE_OPS},
+  {{"hemlock"}, GK_EVERGREEN_DOUBLE_OPS},
+  {{"juniper"}, GK_EVERGREEN},
+  {{"redwood"}, GK_EVERGREEN},
   {{"sumo"}, GK_EVERGREEN},
   {{"sumo2"}, GK_EVERGREEN},
-  {{"redwood"}, GK_EVERGREEN},
-  {{"juniper"}, GK_EVERGREEN},
-  {{"hemlock"}, GK_EVERGREEN_DOUBLE_OPS},
-  {{"cypress"}, GK_EVERGREEN_DOUBLE_OPS},
   {{"barts"}, GK_NORTHERN_ISLANDS},
-  {{"turks"}, GK_NORTHERN_ISLANDS},
   {{"caicos"}, GK_NORTHERN_ISLANDS},
-  {{"cayman"}, GK_CAYMAN},
+  {{"turks"}, GK_NORTHERN_ISLANDS},
   {{"aruba"}, GK_CAYMAN},
+  {{"cayman"}, GK_CAYMAN},
   };
-  static constexpr NameGPUKind AMDGCNNames[33] = {
-  {{"gfx600"}, GK_GFX6},{{"tahiti"}, GK_GFX6},
-  {{"gfx601"}, GK_GFX6},{{"pitcairn"}, GK_GFX6},
-  {{"verde"}, GK_GFX6}, {{"oland"}, GK_GFX6},
-  {{"hainan"}, GK_GFX6},{{"gfx700"}, GK_GFX7},
-  {{"bonaire"}, GK_GFX7},   {{"kaveri"}, GK_GFX7},
-  {{"gfx701"}, GK_GFX7},{{"hawaii"}, GK_GFX7},
-  {{"gfx702"}, GK_GFX7},{{"gfx703"}, GK_GFX7},
-  {{"kabini"}, GK_GFX7},{{"mullins"}, GK_GFX7},
-  {{"gfx800"}, GK_GFX8},{{"iceland"}, GK_GFX8},
-  {{"gfx801"}, GK_GFX8},{{"carrizo"}, GK_GFX8},
-  {{"gfx802"}, GK_GFX8},{{"tonga"}, GK_GFX8},
-  {{"gfx803"}, GK_GFX8},{{"fiji"}, GK_GFX8},
-  {{"polaris10"}, GK_GFX8}, {{"polaris11"}, GK_GFX8},
-  {{"gfx804"}, GK_GFX8},{{"gfx810"}, GK_GFX8},
-  {{"stoney"}, GK_GFX8},{{"gfx900"}, GK_GFX9},
-  {{"gfx901"}, GK_GFX9},{{"gfx902"}, GK_GFX9},
-  {{"gfx903"}, GK_GFX9},
+  static constexpr NameGPUKind AMDGCNNames[30] = {
+  {{"gfx600"}, GK_GFX6},
+  {{"tahiti"}, GK_GFX6},
+  {{"gfx601"}, GK_GFX6},
+  {{"hainan"}, GK_GFX6},
+  {{"oland"}, GK_GFX6},
+  {{"pitcairn"}, GK_GFX6},
+  {{"verde"}, GK_GFX6},
+  {{"gfx700"}, GK_GFX7},
+  {{"kaveri"}, GK_GFX7},
+  {{"gfx701"}, GK_GFX7},
+  {{"hawaii"}, GK_GFX7},
+  {{"gfx702"}, GK_GFX7},
+  {{"gfx703"}, GK_GFX7},
+  {{"kabini"}, GK_GFX7},
+  {{"mullins"}, GK_GFX7},
+  {{"gfx704"}, GK_GFX7},
+  {{"bonaire"}, GK_GFX7},
+  {{"gfx801"}, GK_GFX8},
+  {{"carrizo"}, GK_GFX8},
+  {{"gfx802"}, GK_GFX8},
+  {{"iceland"}, GK_GFX8},
+  {{"tonga"}, GK_GFX8},
+  {{"gfx803"}, GK_GFX8},
+  {{"fiji"}, GK_GFX8},
+  {{"polaris10"}, GK_GFX8},
+  {{"polaris11"}, GK_GFX8},
+  {{"gfx810"}, GK_GFX8},
+  {{"stoney"}, GK_GFX8},
+  {{"gfx900"}, GK_GFX9},
+  {{"gfx902"}, GK_GFX9},
   };
 
   bool hasFP64 : 1;

Modified: cfe/trunk/test/Driver/amdgpu-mcpu.cl
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/Driver/amdgpu-mcpu.cl?rev=324714=324713=324714=diff
==
--- cfe/trunk/test/Driver/amdgpu-mcpu.cl (original)
+++ cfe/trunk/test/Driver/amdgpu-mcpu.cl Thu Feb  8 23:02:28 2018
@@ -1,112 +1,115 @@
-t// Check that -mcpu works for all supported GPUs
+// Check that -mcpu works for all supported GPUs.
 
-// RUN: %clang -### -target r600 -x cl -S -emit-llvm -mcpu=r600 %s -o - 2>&1 | 
FileCheck --check-prefix=R600-CHECK %s
-// RUN: %clang -### -target r600 -x cl -S -emit-llvm -mcpu=rv630 %s -o - 2>&1 
| FileCheck --check-prefix=R600-CHECK %s
-// RUN: %clang -### -target r600 -x cl -S -emit-llvm -mcpu=rv635 %s -o - 2>&1 
| FileCheck --check-prefix=R600-CHECK

r317917 - AMDGPU: Add -mxnack/-mno-xnack options that set +/-xnack feature

2017-11-10 Thread Konstantin Zhuravlyov via cfe-commits 
Author: kzhuravl
Date: Fri Nov 10 11:28:25 2017
New Revision: 317917

URL: http://llvm.org/viewvc/llvm-project?rev=317917=rev
Log:
AMDGPU: Add -mxnack/-mno-xnack options that set +/-xnack feature

Differential Revision: https://reviews.llvm.org/D39878

Modified:
cfe/trunk/include/clang/Driver/Options.td
cfe/trunk/test/Driver/amdgpu-features.c

Modified: cfe/trunk/include/clang/Driver/Options.td
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/include/clang/Driver/Options.td?rev=317917=317916=317917=diff
==
--- cfe/trunk/include/clang/Driver/Options.td (original)
+++ cfe/trunk/include/clang/Driver/Options.td Fri Nov 10 11:28:25 2017
@@ -1822,7 +1822,6 @@ def mno_neg_immediates: Flag<["-"], "mno
 
 def mgeneral_regs_only : Flag<["-"], "mgeneral-regs-only">, 
Group,
   HelpText<"Generate code which only uses the general purpose registers 
(AArch64 only)">;
-
 def mfix_cortex_a53_835769 : Flag<["-"], "mfix-cortex-a53-835769">,
   Group,
   HelpText<"Workaround Cortex-A53 erratum 835769 (AArch64 only)">;
@@ -1840,6 +1839,10 @@ def mamdgpu_debugger_abi : Joined<["-"],
   Group,
   HelpText<"Generate additional code for specified  of debugger ABI 
(AMDGPU only)">,
   MetaVarName<"">;
+def mxnack : Flag<["-"], "mxnack">, Group,
+  HelpText<"Enable XNACK (AMDGPU only)">;
+def mno_xnack : Flag<["-"], "mno-xnack">, Group,
+  HelpText<"Disable XNACK (AMDGPU only)">;
 
 def faltivec : Flag<["-"], "faltivec">, Group, Flags<[DriverOption]>;
 def fno_altivec : Flag<["-"], "fno-altivec">, Group, 
Flags<[DriverOption]>;

Modified: cfe/trunk/test/Driver/amdgpu-features.c
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/Driver/amdgpu-features.c?rev=317917=317916=317917=diff
==
--- cfe/trunk/test/Driver/amdgpu-features.c (original)
+++ cfe/trunk/test/Driver/amdgpu-features.c Fri Nov 10 11:28:25 2017
@@ -5,3 +5,9 @@
 // RUN: %clang -### -target amdgcn -x cl -S -emit-llvm -mcpu=kaveri 
-mamdgpu-debugger-abi=1.0 %s -o - 2>&1 \
 // RUN:   | FileCheck --check-prefix=CHECK-MAMDGPU-DEBUGGER-ABI-1-0 %s
 // CHECK-MAMDGPU-DEBUGGER-ABI-1-0: "-target-feature" 
"+amdgpu-debugger-insert-nops" "-target-feature" 
"+amdgpu-debugger-reserve-regs" "-target-feature" 
"+amdgpu-debugger-emit-prologue"
+
+// RUN: %clang -### -target amdgcn -mcpu=gfx700 -mxnack %s 2>&1 | FileCheck 
--check-prefix=XNACK %s
+// XNACK: "-target-feature" "+xnack"
+
+// RUN: %clang -### -target amdgcn -mcpu=gfx700 -mno-xnack %s 2>&1 | FileCheck 
--check-prefix=NO-XNACK %s
+// NO-XNACK: "-target-feature" "-xnack"


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r317909 - AMDGPU/NFC: Move getAMDGPUTargetFeatures to AMDGPU toolchain

2017-11-10 Thread Konstantin Zhuravlyov via cfe-commits 
Author: kzhuravl
Date: Fri Nov 10 11:09:57 2017
New Revision: 317909

URL: http://llvm.org/viewvc/llvm-project?rev=317909=rev
Log:
AMDGPU/NFC: Move getAMDGPUTargetFeatures to AMDGPU toolchain

Differential Revision: https://reviews.llvm.org/D39877

Modified:
cfe/trunk/lib/Driver/ToolChains/AMDGPU.cpp
cfe/trunk/lib/Driver/ToolChains/AMDGPU.h
cfe/trunk/lib/Driver/ToolChains/Clang.cpp

Modified: cfe/trunk/lib/Driver/ToolChains/AMDGPU.cpp
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Driver/ToolChains/AMDGPU.cpp?rev=317909=317908=317909=diff
==
--- cfe/trunk/lib/Driver/ToolChains/AMDGPU.cpp (original)
+++ cfe/trunk/lib/Driver/ToolChains/AMDGPU.cpp Fri Nov 10 11:09:57 2017
@@ -11,6 +11,7 @@
 #include "CommonArgs.h"
 #include "InputInfo.h"
 #include "clang/Driver/Compilation.h"
+#include "clang/Driver/DriverDiagnostic.h"
 #include "llvm/Option/ArgList.h"
 
 using namespace clang::driver;
@@ -35,6 +36,24 @@ void amdgpu::Linker::ConstructJob(Compil
   CmdArgs, Inputs));
 }
 
+void amdgpu::getAMDGPUTargetFeatures(const Driver ,
+ const llvm::opt::ArgList ,
+ std::vector ) {
+  if (const Arg *dAbi = Args.getLastArg(options::OPT_mamdgpu_debugger_abi)) {
+StringRef value = dAbi->getValue();
+if (value == "1.0") {
+  Features.push_back("+amdgpu-debugger-insert-nops");
+  Features.push_back("+amdgpu-debugger-reserve-regs");
+  Features.push_back("+amdgpu-debugger-emit-prologue");
+} else {
+  D.Diag(diag::err_drv_clang_unsupported) << dAbi->getAsString(Args);
+}
+  }
+
+  handleTargetFeaturesGroup(
+Args, Features, options::OPT_m_amdgpu_Features_Group);
+}
+
 /// AMDGPU Toolchain
 AMDGPUToolChain::AMDGPUToolChain(const Driver , const llvm::Triple ,
  const ArgList )

Modified: cfe/trunk/lib/Driver/ToolChains/AMDGPU.h
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Driver/ToolChains/AMDGPU.h?rev=317909=317908=317909=diff
==
--- cfe/trunk/lib/Driver/ToolChains/AMDGPU.h (original)
+++ cfe/trunk/lib/Driver/ToolChains/AMDGPU.h Fri Nov 10 11:09:57 2017
@@ -19,7 +19,6 @@
 namespace clang {
 namespace driver {
 namespace tools {
-
 namespace amdgpu {
 
 class LLVM_LIBRARY_VISIBILITY Linker : public GnuTool {
@@ -33,6 +32,9 @@ public:
 const char *LinkingOutput) const override;
 };
 
+void getAMDGPUTargetFeatures(const Driver , const llvm::opt::ArgList ,
+ std::vector );
+
 } // end namespace amdgpu
 } // end namespace tools
 

Modified: cfe/trunk/lib/Driver/ToolChains/Clang.cpp
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Driver/ToolChains/Clang.cpp?rev=317909=317908=317909=diff
==
--- cfe/trunk/lib/Driver/ToolChains/Clang.cpp (original)
+++ cfe/trunk/lib/Driver/ToolChains/Clang.cpp Fri Nov 10 11:09:57 2017
@@ -15,6 +15,7 @@
 #include "Arch/Sparc.h"
 #include "Arch/SystemZ.h"
 #include "Arch/X86.h"
+#include "AMDGPU.h"
 #include "CommonArgs.h"
 #include "Hexagon.h"
 #include "InputInfo.h"
@@ -278,23 +279,6 @@ static void getWebAssemblyTargetFeatures
   handleTargetFeaturesGroup(Args, Features, 
options::OPT_m_wasm_Features_Group);
 }
 
-static void getAMDGPUTargetFeatures(const Driver , const ArgList ,
-std::vector ) {
-  if (const Arg *dAbi = Args.getLastArg(options::OPT_mamdgpu_debugger_abi)) {
-StringRef value = dAbi->getValue();
-if (value == "1.0") {
-  Features.push_back("+amdgpu-debugger-insert-nops");
-  Features.push_back("+amdgpu-debugger-reserve-regs");
-  Features.push_back("+amdgpu-debugger-emit-prologue");
-} else {
-  D.Diag(diag::err_drv_clang_unsupported) << dAbi->getAsString(Args);
-}
-  }
-
-  handleTargetFeaturesGroup(
-Args, Features, options::OPT_m_amdgpu_Features_Group);
-}
-
 static void getTargetFeatures(const ToolChain , const llvm::Triple ,
   const ArgList , ArgStringList ,
   bool ForAS) {
@@ -347,7 +331,7 @@ static void getTargetFeatures(const Tool
 break;
   case llvm::Triple::r600:
   case llvm::Triple::amdgcn:
-getAMDGPUTargetFeatures(D, Args, Features);
+amdgpu::getAMDGPUTargetFeatures(D, Args, Features);
 break;
   }
 


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r315831 - Revert "Mark test as unsupported until r315808 is fixed"

2017-10-14 Thread Konstantin Zhuravlyov via cfe-commits 
Author: kzhuravl
Date: Sat Oct 14 15:24:31 2017
New Revision: 315831

URL: http://llvm.org/viewvc/llvm-project?rev=315831=rev
Log:
Revert "Mark test as unsupported until r315808 is fixed"

Test is fixed in r315830

Modified:
cfe/trunk/test/Misc/backend-resource-limit-diagnostics.cl

Modified: cfe/trunk/test/Misc/backend-resource-limit-diagnostics.cl
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/Misc/backend-resource-limit-diagnostics.cl?rev=315831=315830=315831=diff
==
--- cfe/trunk/test/Misc/backend-resource-limit-diagnostics.cl (original)
+++ cfe/trunk/test/Misc/backend-resource-limit-diagnostics.cl Sat Oct 14 
15:24:31 2017
@@ -1,5 +1,4 @@
 // REQUIRES: amdgpu-registered-target
-// UNSUPPORTED: system-darwin
 // RUN: not %clang_cc1 -emit-codegen-only -triple=amdgcn-- %s 2>&1 | FileCheck 
%s
 
 // CHECK: error: local memory limit exceeded (48) in use_huge_lds


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r312795 - Add '\n' in ClangDataCollectorsEmitter

2017-09-08 Thread Konstantin Zhuravlyov via cfe-commits 
Author: kzhuravl
Date: Fri Sep  8 09:17:16 2017
New Revision: 312795

URL: http://llvm.org/viewvc/llvm-project?rev=312795=rev
Log:
Add '\n' in ClangDataCollectorsEmitter

Differential Revision: https://reviews.llvm.org/D37599

Modified:
cfe/trunk/utils/TableGen/ClangDataCollectorsEmitter.cpp

Modified: cfe/trunk/utils/TableGen/ClangDataCollectorsEmitter.cpp
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/utils/TableGen/ClangDataCollectorsEmitter.cpp?rev=312795=312794=312795=diff
==
--- cfe/trunk/utils/TableGen/ClangDataCollectorsEmitter.cpp (original)
+++ cfe/trunk/utils/TableGen/ClangDataCollectorsEmitter.cpp Fri Sep  8 09:17:16 
2017
@@ -8,7 +8,7 @@ void EmitClangDataCollectors(RecordKeepe
   const auto  = RK.getClasses();
   for (const auto  : Defs) {
 Record  = *Entry.second;
-OS << "DEF_ADD_DATA(" << R.getName() << ", {";
+OS << "DEF_ADD_DATA(" << R.getName() << ", {\n";
 auto Code = R.getValue("Code")->getValue();
 OS << Code->getAsUnquotedString() << "}\n)";
 OS << "\n";


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r311178 - AMDGPU: Rename r600-mcpu.cl->amdgpu-mcpu.cl

2017-08-18 Thread Konstantin Zhuravlyov via cfe-commits 
Author: kzhuravl
Date: Fri Aug 18 10:29:07 2017
New Revision: 311178

URL: http://llvm.org/viewvc/llvm-project?rev=311178=rev
Log:
AMDGPU: Rename r600-mcpu.cl->amdgpu-mcpu.cl

Added:
cfe/trunk/test/Driver/amdgpu-mcpu.cl
Removed:
cfe/trunk/test/Driver/r600-mcpu.cl

Added: cfe/trunk/test/Driver/amdgpu-mcpu.cl
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/Driver/amdgpu-mcpu.cl?rev=311178=auto
==
--- cfe/trunk/test/Driver/amdgpu-mcpu.cl (added)
+++ cfe/trunk/test/Driver/amdgpu-mcpu.cl Fri Aug 18 10:29:07 2017
@@ -0,0 +1,112 @@
+t// Check that -mcpu works for all supported GPUs
+
+// RUN: %clang -### -target r600 -x cl -S -emit-llvm -mcpu=r600 %s -o - 2>&1 | 
FileCheck --check-prefix=R600-CHECK %s
+// RUN: %clang -### -target r600 -x cl -S -emit-llvm -mcpu=rv630 %s -o - 2>&1 
| FileCheck --check-prefix=R600-CHECK %s
+// RUN: %clang -### -target r600 -x cl -S -emit-llvm -mcpu=rv635 %s -o - 2>&1 
| FileCheck --check-prefix=R600-CHECK %s
+// RUN: %clang -### -target r600 -x cl -S -emit-llvm -mcpu=rv610 %s -o - 2>&1 
| FileCheck --check-prefix=RS880-CHECK %s
+// RUN: %clang -### -target r600 -x cl -S -emit-llvm -mcpu=rv620 %s -o - 2>&1 
| FileCheck --check-prefix=RS880-CHECK %s
+// RUN: %clang -### -target r600 -x cl -S -emit-llvm -mcpu=rs780 %s -o - 2>&1 
| FileCheck --check-prefix=RS880-CHECK %s
+// RUN: %clang -### -target r600 -x cl -S -emit-llvm -mcpu=rs880 %s -o - 2>&1 
| FileCheck --check-prefix=RS880-CHECK %s
+// RUN: %clang -### -target r600 -x cl -S -emit-llvm -mcpu=rv670 %s -o - 2>&1 
| FileCheck --check-prefix=RV670-CHECK %s
+// RUN: %clang -### -target r600 -x cl -S -emit-llvm -mcpu=rv710 %s -o - 2>&1 
| FileCheck --check-prefix=RV710-CHECK %s
+// RUN: %clang -### -target r600 -x cl -S -emit-llvm -mcpu=rv730 %s -o - 2>&1 
| FileCheck --check-prefix=RV730-CHECK %s
+// RUN: %clang -### -target r600 -x cl -S -emit-llvm -mcpu=rv740 %s -o - 2>&1 
| FileCheck --check-prefix=RV770-CHECK %s
+// RUN: %clang -### -target r600 -x cl -S -emit-llvm -mcpu=rv770 %s -o - 2>&1 
| FileCheck --check-prefix=RV770-CHECK %s
+// RUN: %clang -### -target r600 -x cl -S -emit-llvm -mcpu=palm %s -o - 2>&1 | 
FileCheck --check-prefix=CEDAR-CHECK %s
+// RUN: %clang -### -target r600 -x cl -S -emit-llvm -mcpu=cedar %s -o - 2>&1 
| FileCheck --check-prefix=CEDAR-CHECK %s
+// RUN: %clang -### -target r600 -x cl -S -emit-llvm -mcpu=sumo %s -o - 2>&1 | 
FileCheck --check-prefix=SUMO-CHECK %s
+// RUN: %clang -### -target r600 -x cl -S -emit-llvm -mcpu=sumo2 %s -o - 2>&1 
| FileCheck --check-prefix=SUMO-CHECK %s
+// RUN: %clang -### -target r600 -x cl -S -emit-llvm -mcpu=redwood %s -o - 
2>&1 | FileCheck --check-prefix=REDWOOD-CHECK %s
+// RUN: %clang -### -target r600 -x cl -S -emit-llvm -mcpu=juniper %s -o - 
2>&1 | FileCheck --check-prefix=JUNIPER-CHECK %s
+// RUN: %clang -### -target r600 -x cl -S -emit-llvm -mcpu=juniper %s -o - 
2>&1 | FileCheck --check-prefix=JUNIPER-CHECK %s
+// RUN: %clang -### -target r600 -x cl -S -emit-llvm -mcpu=hemlock %s -o - 
2>&1 | FileCheck --check-prefix=CYPRESS-CHECK %s
+// RUN: %clang -### -target r600 -x cl -S -emit-llvm -mcpu=cypress %s -o - 
2>&1 | FileCheck --check-prefix=CYPRESS-CHECK %s
+// RUN: %clang -### -target r600 -x cl -S -emit-llvm -mcpu=barts %s -o - 2>&1 
| FileCheck --check-prefix=BARTS-CHECK %s
+// RUN: %clang -### -target r600 -x cl -S -emit-llvm -mcpu=turks %s -o - 2>&1 
| FileCheck --check-prefix=TURKS-CHECK %s
+// RUN: %clang -### -target r600 -x cl -S -emit-llvm -mcpu=caicos %s -o - 2>&1 
| FileCheck --check-prefix=CAICOS-CHECK %s
+// RUN: %clang -### -target r600 -x cl -S -emit-llvm -mcpu=cayman %s -o - 2>&1 
| FileCheck --check-prefix=CAYMAN-CHECK %s
+// RUN: %clang -### -target r600 -x cl -S -emit-llvm -mcpu=aruba %s -o - 2>&1 
| FileCheck --check-prefix=CAYMAN-CHECK %s
+
+// R600-CHECK:  "-target-cpu" "r600"
+// RS880-CHECK: "-target-cpu" "rs880"
+// RV670-CHECK: "-target-cpu" "rv670"
+// RV710-CHECK: "-target-cpu" "rv710"
+// RV730-CHECK: "-target-cpu" "rv730"
+// RV770-CHECK: "-target-cpu" "rv770"
+// CEDAR-CHECK: "-target-cpu" "cedar"
+// REDWOOD-CHECK: "-target-cpu" "redwood"
+// SUMO-CHECK: "-target-cpu" "sumo"
+// JUNIPER-CHECK: "-target-cpu" "juniper"
+// CYPRESS-CHECK: "-target-cpu" "cypress"
+// BARTS-CHECK: "-target-cpu" "barts"
+// TURKS-CHECK: "-target-cpu" "turks"
+// CAICOS-CHECK: "-target-cpu" "caicos"
+// CAYMAN-CHECK: "-target-cpu" "cayman"
+
+// RUN: %clang -### -target amdgcn -x cl -S -emit-llvm -mcpu=gfx600 %s -o - 
2>&1 | FileCheck --check-prefix=GFX600-CHECK %s
+// RUN: %clang -### -target amdgcn -x cl -S -emit-llvm -mcpu=tahiti %s -o - 
2>&1 | FileCheck --check-prefix=TAHITI-CHECK %s
+// RUN: %clang -### -target amdgcn -x cl -S -emit-llvm -mcpu=gfx601 %s -o - 
2>&1 | FileCheck --check-prefix=GFX601-CHECK %s
+// RUN: %clang -### -target amdgcn -x cl -S -emit-llvm -mcpu=pitcairn %s -o - 
2>&1 | FileCheck --check-prefix=PITCAIRN-CHECK %s
+// RUN: %clang -###

r311141 - AMDGPU: add missing amdgcn processors and tests

2017-08-17 Thread Konstantin Zhuravlyov via cfe-commits 
Author: kzhuravl
Date: Thu Aug 17 18:13:39 2017
New Revision: 311141

URL: http://llvm.org/viewvc/llvm-project?rev=311141=rev
Log:
AMDGPU: add missing amdgcn processors and tests

  - gfx600
  - gfx601
  - gfx703
  - gfx902
  - gfx903

Differential Revision: https://reviews.llvm.org/D36771

Modified:
cfe/trunk/lib/Basic/Targets/AMDGPU.cpp
cfe/trunk/test/Driver/r600-mcpu.cl

Modified: cfe/trunk/lib/Basic/Targets/AMDGPU.cpp
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Basic/Targets/AMDGPU.cpp?rev=311141=311140=311141=diff
==
--- cfe/trunk/lib/Basic/Targets/AMDGPU.cpp (original)
+++ cfe/trunk/lib/Basic/Targets/AMDGPU.cpp Thu Aug 17 18:13:39 2017
@@ -256,34 +256,39 @@ AMDGPUTargetInfo::GPUKind AMDGPUTargetIn
 
 AMDGPUTargetInfo::GPUKind AMDGPUTargetInfo::parseAMDGCNName(StringRef Name) {
   return llvm::StringSwitch(Name)
+  .Case("gfx600", GK_GFX6)
   .Case("tahiti", GK_GFX6)
+  .Case("gfx601", GK_GFX6)
   .Case("pitcairn", GK_GFX6)
   .Case("verde", GK_GFX6)
   .Case("oland", GK_GFX6)
   .Case("hainan", GK_GFX6)
+  .Case("gfx700", GK_GFX7)
   .Case("bonaire", GK_GFX7)
-  .Case("kabini", GK_GFX7)
   .Case("kaveri", GK_GFX7)
-  .Case("hawaii", GK_GFX7)
-  .Case("mullins", GK_GFX7)
-  .Case("gfx700", GK_GFX7)
   .Case("gfx701", GK_GFX7)
+  .Case("hawaii", GK_GFX7)
   .Case("gfx702", GK_GFX7)
-  .Case("tonga", GK_GFX8)
+  .Case("gfx703", GK_GFX7)
+  .Case("kabini", GK_GFX7)
+  .Case("mullins", GK_GFX7)
+  .Case("gfx800", GK_GFX8)
   .Case("iceland", GK_GFX8)
+  .Case("gfx801", GK_GFX8)
   .Case("carrizo", GK_GFX8)
+  .Case("gfx802", GK_GFX8)
+  .Case("tonga", GK_GFX8)
+  .Case("gfx803", GK_GFX8)
   .Case("fiji", GK_GFX8)
-  .Case("stoney", GK_GFX8)
   .Case("polaris10", GK_GFX8)
   .Case("polaris11", GK_GFX8)
-  .Case("gfx800", GK_GFX8)
-  .Case("gfx801", GK_GFX8)
-  .Case("gfx802", GK_GFX8)
-  .Case("gfx803", GK_GFX8)
   .Case("gfx804", GK_GFX8)
   .Case("gfx810", GK_GFX8)
+  .Case("stoney", GK_GFX8)
   .Case("gfx900", GK_GFX9)
   .Case("gfx901", GK_GFX9)
+  .Case("gfx902", GK_GFX9)
+  .Case("gfx903", GK_GFX9)
   .Default(GK_NONE);
 }
 

Modified: cfe/trunk/test/Driver/r600-mcpu.cl
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/Driver/r600-mcpu.cl?rev=311141=311140=311141=diff
==
--- cfe/trunk/test/Driver/r600-mcpu.cl (original)
+++ cfe/trunk/test/Driver/r600-mcpu.cl Thu Aug 17 18:13:39 2017
@@ -26,22 +26,6 @@ t// Check that -mcpu works for all suppo
 // RUN: %clang -### -target r600 -x cl -S -emit-llvm -mcpu=caicos %s -o - 2>&1 
| FileCheck --check-prefix=CAICOS-CHECK %s
 // RUN: %clang -### -target r600 -x cl -S -emit-llvm -mcpu=cayman %s -o - 2>&1 
| FileCheck --check-prefix=CAYMAN-CHECK %s
 // RUN: %clang -### -target r600 -x cl -S -emit-llvm -mcpu=aruba %s -o - 2>&1 
| FileCheck --check-prefix=CAYMAN-CHECK %s
-// RUN: %clang -### -target amdgcn -x cl -S -emit-llvm -mcpu=tahiti %s -o - 
2>&1 | FileCheck --check-prefix=TAHITI-CHECK %s
-// RUN: %clang -### -target amdgcn -x cl -S -emit-llvm -mcpu=pitcairn %s -o - 
2>&1 | FileCheck --check-prefix=PITCAIRN-CHECK %s
-// RUN: %clang -### -target amdgcn -x cl -S -emit-llvm -mcpu=verde %s -o - 
2>&1 | FileCheck --check-prefix=VERDE-CHECK %s
-// RUN: %clang -### -target amdgcn -x cl -S -emit-llvm -mcpu=oland %s -o - 
2>&1 | FileCheck --check-prefix=OLAND-CHECK %s
-// RUN: %clang -### -target amdgcn -x cl -S -emit-llvm -mcpu=bonaire %s -o - 
2>&1 | FileCheck --check-prefix=BONAIRE-CHECK %s
-// RUN: %clang -### -target amdgcn -x cl -S -emit-llvm -mcpu=kabini %s -o - 
2>&1 | FileCheck --check-prefix=KABINI-CHECK %s
-// RUN: %clang -### -target amdgcn -x cl -S -emit-llvm -mcpu=kaveri %s -o - 
2>&1 | FileCheck --check-prefix=KAVERI-CHECK %s
-// RUN: %clang -### -target amdgcn -x cl -S -emit-llvm -mcpu=hawaii %s -o - 
2>&1 | FileCheck --check-prefix=HAWAII-CHECK %s
-// RUN: %clang -### -target amdgcn -x cl -S -emit-llvm -mcpu=mullins %s -o - 
2>&1 | FileCheck --check-prefix=MULLINS-CHECK %s
-// RUN: %clang -### -target amdgcn -x cl -S -emit-llvm -mcpu=tonga %s -o - 
2>&1 | FileCheck --check-prefix=TONGA-CHECK %s
-// RUN: %clang -### -target amdgcn -x cl -S -emit-llvm -mcpu=iceland %s -o - 
2>&1 | FileCheck --check-prefix=ICELAND-CHECK %s
-// RUN: %clang -### -target amdgcn -x cl -S -emit-llvm -mcpu=carrizo %s -o - 
2>&1 | FileCheck --check-prefix=CARRIZO-CHECK %s
-// RUN: %clang -### -target amdgcn -x cl -S -emit-llvm -mcpu=fiji %s -o - 2>&1 
| FileCheck --check-prefix=FIJI-CHECK %s
-// RUN: %clang -### -target amdgcn -x cl -S -emit-llvm -mcpu=stoney %s -o - 
2>&1 | FileCheck --check-prefix=STONEY-CHECK %s
-// RUN: %clang -### -target amdgcn -x cl -S -emit-llvm -mcpu=gfx900 %s -o - 
2>&1 | FileCheck

r309193 - Convert mac file format to unix

2017-07-26 Thread Konstantin Zhuravlyov via cfe-commits 
Author: kzhuravl
Date: Wed Jul 26 14:59:45 2017
New Revision: 309193

URL: http://llvm.org/viewvc/llvm-project?rev=309193=rev
Log:
Convert mac file format to unix

Differential Revision: https://reviews.llvm.org/D35900

Modified:
cfe/trunk/include/clang/Lex/VariadicMacroSupport.h

Modified: cfe/trunk/include/clang/Lex/VariadicMacroSupport.h
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/include/clang/Lex/VariadicMacroSupport.h?rev=309193=309192=309193=diff
==
--- cfe/trunk/include/clang/Lex/VariadicMacroSupport.h (original)
+++ cfe/trunk/include/clang/Lex/VariadicMacroSupport.h Wed Jul 26 14:59:45 2017
@@ -1,56 +1,56 @@
-//===- VariadicMacroSupport.h - scope-guards etc. -*- C++ 
-*---===//
-//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===--===//
-//
-// This file defines support types to help with preprocessing variadic macro 
-// (i.e. macros that use: ellipses __VA_ARGS__ ) definitions and 
-// expansions.
-//
-//===--===//
-
-#ifndef LLVM_CLANG_LEX_VARIADICMACROSUPPORT_H
-#define LLVM_CLANG_LEX_VARIADICMACROSUPPORT_H
-
-#include "clang/Lex/Preprocessor.h"
-
-namespace clang {
-
-/// An RAII class that tracks when the Preprocessor starts and stops lexing the
-/// definition of a (ISO C/C++) variadic macro.  As an example, this is useful
-/// for unpoisoning and repoisoning certain identifiers (such as __VA_ARGS__)
-/// that are only allowed in this context.  Also, being a friend of the
-/// Preprocessor class allows it to access PP's cached identifiers directly (as
-/// opposed to performing a lookup each time).
-class VariadicMacroScopeGuard {
-  const Preprocessor 
-  IdentifierInfo __VA_ARGS__;
-
-public:
-  VariadicMacroScopeGuard(const Preprocessor )
-  : PP(P), Ident__VA_ARGS__(*PP.Ident__VA_ARGS__) {
-assert(Ident__VA_ARGS__.isPoisoned() && "__VA_ARGS__ should be poisoned "
-"outside an ISO C/C++ variadic "
-"macro definition!");
-  }
-
-  /// Client code should call this function just before the Preprocessor is
-  /// about to Lex tokens from the definition of a variadic (ISO C/C++) macro.
-  void enterScope() { Ident__VA_ARGS__.setIsPoisoned(false); }
-
-  /// Client code should call this function as soon as the Preprocessor has
-  /// either completed lexing the macro's definition tokens, or an error 
occured
-  /// and the context is being exited.  This function is idempotent (might be
-  /// explicitly called, and then reinvoked via the destructor).
-  void exitScope() { Ident__VA_ARGS__.setIsPoisoned(true); }
-  
-  ~VariadicMacroScopeGuard() { exitScope(); }
-};
-
-}  // end namespace clang
-
-#endif
+//===- VariadicMacroSupport.h - scope-guards etc. -*- C++ 
-*---===//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===--===//
+//
+// This file defines support types to help with preprocessing variadic macro
+// (i.e. macros that use: ellipses __VA_ARGS__ ) definitions and
+// expansions.
+//
+//===--===//
+
+#ifndef LLVM_CLANG_LEX_VARIADICMACROSUPPORT_H
+#define LLVM_CLANG_LEX_VARIADICMACROSUPPORT_H
+
+#include "clang/Lex/Preprocessor.h"
+
+namespace clang {
+
+/// An RAII class that tracks when the Preprocessor starts and stops lexing the
+/// definition of a (ISO C/C++) variadic macro.  As an example, this is useful
+/// for unpoisoning and repoisoning certain identifiers (such as __VA_ARGS__)
+/// that are only allowed in this context.  Also, being a friend of the
+/// Preprocessor class allows it to access PP's cached identifiers directly (as
+/// opposed to performing a lookup each time).
+class VariadicMacroScopeGuard {
+  const Preprocessor 
+  IdentifierInfo __VA_ARGS__;
+
+public:
+  VariadicMacroScopeGuard(const Preprocessor )
+  : PP(P), Ident__VA_ARGS__(*PP.Ident__VA_ARGS__) {
+assert(Ident__VA_ARGS__.isPoisoned() && "__VA_ARGS__ should be poisoned "
+"outside an ISO C/C++ variadic "
+"macro definition!");
+  }
+
+  /// Client code should call this function just before the Preprocessor is
+  /// about to Lex tokens from the definition of a variadic (ISO C/C++) macro.
+  void enterScope() { Ident__VA_ARGS__.setIsPoisoned(false); }
+
+  /// Client code should call this function as soon as the Preprocessor has
+  /// either completed lexing

r307723 - Enhance synchscope representation (clang)

2017-07-11 Thread Konstantin Zhuravlyov via cfe-commits 
Author: kzhuravl
Date: Tue Jul 11 15:23:37 2017
New Revision: 307723

URL: http://llvm.org/viewvc/llvm-project?rev=307723=rev
Log:
Enhance synchscope representation (clang)

Relevant changes required for r307722.

Differential Revision: https://reviews.llvm.org/D33109


Modified:
cfe/trunk/lib/CodeGen/CGBuiltin.cpp
cfe/trunk/test/CodeGen/ms-barriers-intrinsics.c

Modified: cfe/trunk/lib/CodeGen/CGBuiltin.cpp
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/CodeGen/CGBuiltin.cpp?rev=307723=307722=307723=diff
==
--- cfe/trunk/lib/CodeGen/CGBuiltin.cpp (original)
+++ cfe/trunk/lib/CodeGen/CGBuiltin.cpp Tue Jul 11 15:23:37 2017
@@ -1810,12 +1810,12 @@ RValue CodeGenFunction::EmitBuiltinExpr(
   case Builtin::BI__atomic_signal_fence:
   case Builtin::BI__c11_atomic_thread_fence:
   case Builtin::BI__c11_atomic_signal_fence: {
-llvm::SynchronizationScope Scope;
+llvm::SyncScope::ID SSID;
 if (BuiltinID == Builtin::BI__atomic_signal_fence ||
 BuiltinID == Builtin::BI__c11_atomic_signal_fence)
-  Scope = llvm::SingleThread;
+  SSID = llvm::SyncScope::SingleThread;
 else
-  Scope = llvm::CrossThread;
+  SSID = llvm::SyncScope::System;
 Value *Order = EmitScalarExpr(E->getArg(0));
 if (isa(Order)) {
   int ord = cast(Order)->getZExtValue();
@@ -1825,17 +1825,16 @@ RValue CodeGenFunction::EmitBuiltinExpr(
 break;
   case 1:  // memory_order_consume
   case 2:  // memory_order_acquire
-Builder.CreateFence(llvm::AtomicOrdering::Acquire, Scope);
+Builder.CreateFence(llvm::AtomicOrdering::Acquire, SSID);
 break;
   case 3:  // memory_order_release
-Builder.CreateFence(llvm::AtomicOrdering::Release, Scope);
+Builder.CreateFence(llvm::AtomicOrdering::Release, SSID);
 break;
   case 4:  // memory_order_acq_rel
-Builder.CreateFence(llvm::AtomicOrdering::AcquireRelease, Scope);
+Builder.CreateFence(llvm::AtomicOrdering::AcquireRelease, SSID);
 break;
   case 5:  // memory_order_seq_cst
-Builder.CreateFence(llvm::AtomicOrdering::SequentiallyConsistent,
-Scope);
+Builder.CreateFence(llvm::AtomicOrdering::SequentiallyConsistent, 
SSID);
 break;
   }
   return RValue::get(nullptr);
@@ -1852,23 +1851,23 @@ RValue CodeGenFunction::EmitBuiltinExpr(
 llvm::SwitchInst *SI = Builder.CreateSwitch(Order, ContBB);
 
 Builder.SetInsertPoint(AcquireBB);
-Builder.CreateFence(llvm::AtomicOrdering::Acquire, Scope);
+Builder.CreateFence(llvm::AtomicOrdering::Acquire, SSID);
 Builder.CreateBr(ContBB);
 SI->addCase(Builder.getInt32(1), AcquireBB);
 SI->addCase(Builder.getInt32(2), AcquireBB);
 
 Builder.SetInsertPoint(ReleaseBB);
-Builder.CreateFence(llvm::AtomicOrdering::Release, Scope);
+Builder.CreateFence(llvm::AtomicOrdering::Release, SSID);
 Builder.CreateBr(ContBB);
 SI->addCase(Builder.getInt32(3), ReleaseBB);
 
 Builder.SetInsertPoint(AcqRelBB);
-Builder.CreateFence(llvm::AtomicOrdering::AcquireRelease, Scope);
+Builder.CreateFence(llvm::AtomicOrdering::AcquireRelease, SSID);
 Builder.CreateBr(ContBB);
 SI->addCase(Builder.getInt32(4), AcqRelBB);
 
 Builder.SetInsertPoint(SeqCstBB);
-Builder.CreateFence(llvm::AtomicOrdering::SequentiallyConsistent, Scope);
+Builder.CreateFence(llvm::AtomicOrdering::SequentiallyConsistent, SSID);
 Builder.CreateBr(ContBB);
 SI->addCase(Builder.getInt32(5), SeqCstBB);
 
@@ -8039,13 +8038,13 @@ Value *CodeGenFunction::EmitX86BuiltinEx
 
   case X86::BI__faststorefence: {
 return Builder.CreateFence(llvm::AtomicOrdering::SequentiallyConsistent,
-   llvm::CrossThread);
+   llvm::SyncScope::System);
   }
   case X86::BI_ReadWriteBarrier:
   case X86::BI_ReadBarrier:
   case X86::BI_WriteBarrier: {
 return Builder.CreateFence(llvm::AtomicOrdering::SequentiallyConsistent,
-   llvm::SingleThread);
+   llvm::SyncScope::SingleThread);
   }
   case X86::BI_BitScanForward:
   case X86::BI_BitScanForward64:

Modified: cfe/trunk/test/CodeGen/ms-barriers-intrinsics.c
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGen/ms-barriers-intrinsics.c?rev=307723=307722=307723=diff
==
--- cfe/trunk/test/CodeGen/ms-barriers-intrinsics.c (original)
+++ cfe/trunk/test/CodeGen/ms-barriers-intrinsics.c Tue Jul 11 15:23:37 2017
@@ -13,19 +13,19 @@ typedef __SIZE_TYPE__ size_t;
 
 void test_ReadWriteBarrier() { _ReadWriteBarrier(); }
 // CHECK-LABEL: define void @test_ReadWriteBarrier
-// CHECK:   fence singlethread seq_cst
+// CHECK:   fence syncscope("singlethread") seq_cst
 // CHECK:   ret void
 // CHECK: }
 
 void test_ReadBarrier() {

r304033 - Resubmit r303861.

2017-05-26 Thread Konstantin Zhuravlyov via cfe-commits 
Author: kzhuravl
Date: Fri May 26 16:08:20 2017
New Revision: 304033

URL: http://llvm.org/viewvc/llvm-project?rev=304033=rev
Log:
Resubmit r303861.

[AMDGPU] add __builtin_amdgcn_s_getpc

Patch by Tim Corringham

Modified:
cfe/trunk/include/clang/Basic/BuiltinsAMDGPU.def
cfe/trunk/test/CodeGenOpenCL/builtins-amdgcn.cl

Modified: cfe/trunk/include/clang/Basic/BuiltinsAMDGPU.def
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/include/clang/Basic/BuiltinsAMDGPU.def?rev=304033=304032=304033=diff
==
--- cfe/trunk/include/clang/Basic/BuiltinsAMDGPU.def (original)
+++ cfe/trunk/include/clang/Basic/BuiltinsAMDGPU.def Fri May 26 16:08:20 2017
@@ -36,6 +36,7 @@ BUILTIN(__builtin_amdgcn_workitem_id_z,
 // Instruction builtins.
 
//===--===//
 BUILTIN(__builtin_amdgcn_s_getreg, "UiIi", "n")
+BUILTIN(__builtin_amdgcn_s_getpc, "LUi", "n")
 BUILTIN(__builtin_amdgcn_s_waitcnt, "vIi", "n")
 BUILTIN(__builtin_amdgcn_s_sendmsg, "vIiUi", "n")
 BUILTIN(__builtin_amdgcn_s_sendmsghalt, "vIiUi", "n")

Modified: cfe/trunk/test/CodeGenOpenCL/builtins-amdgcn.cl
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGenOpenCL/builtins-amdgcn.cl?rev=304033=304032=304033=diff
==
--- cfe/trunk/test/CodeGenOpenCL/builtins-amdgcn.cl (original)
+++ cfe/trunk/test/CodeGenOpenCL/builtins-amdgcn.cl Fri May 26 16:08:20 2017
@@ -481,6 +481,13 @@ void test_fmed3_f32(global float* out, f
   *out = __builtin_amdgcn_fmed3f(a, b, c);
 }
 
+// CHECK-LABEL: @test_s_getpc
+// CHECK: call i64 @llvm.amdgcn.s.getpc()
+void test_s_getpc(global ulong* out)
+{
+  *out = __builtin_amdgcn_s_getpc();
+}
+
 // CHECK-DAG: [[WI_RANGE]] = !{i32 0, i32 1024}
 // CHECK-DAG: attributes #[[NOUNWIND_READONLY:[0-9]+]] = { nounwind readonly }
 // CHECK-DAG: attributes #[[READ_EXEC_ATTRS]] = { convergent }


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r300306 - [AMDGPU][GFX9] Set +fp32-denormals for >=gfx900 unless -cl-denorms-are-zero is set

2017-04-13 Thread Konstantin Zhuravlyov via cfe-commits 
Author: kzhuravl
Date: Fri Apr 14 00:33:57 2017
New Revision: 300306

URL: http://llvm.org/viewvc/llvm-project?rev=300306=rev
Log:
[AMDGPU][GFX9] Set +fp32-denormals for >=gfx900 unless -cl-denorms-are-zero is 
set

Differential Revision: https://reviews.llvm.org/D31482

Added:
cfe/trunk/test/CodeGenOpenCL/gfx9-fp32-denorms.cl
Modified:
cfe/trunk/lib/Basic/Targets.cpp

Modified: cfe/trunk/lib/Basic/Targets.cpp
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Basic/Targets.cpp?rev=300306=300305=300306=diff
==
--- cfe/trunk/lib/Basic/Targets.cpp (original)
+++ cfe/trunk/lib/Basic/Targets.cpp Fri Apr 14 00:33:57 2017
@@ -2112,9 +2112,12 @@ class AMDGPUTargetInfo final : public Ta
   bool hasFP64:1;
   bool hasFMAF:1;
   bool hasLDEXPF:1;
-  bool hasFullSpeedFP32Denorms:1;
   const AddrSpace AS;
 
+  static bool hasFullSpeedFMAF32(StringRef GPUName) {
+return parseAMDGCNName(GPUName) >= GK_GFX9;
+  }
+
   static bool isAMDGCN(const llvm::Triple ) {
 return TT.getArch() == llvm::Triple::amdgcn;
   }
@@ -2130,7 +2133,6 @@ public:
   hasFP64(false),
   hasFMAF(false),
   hasLDEXPF(false),
-  hasFullSpeedFP32Denorms(false),
   AS(isGenericZero(Triple)){
 if (getTriple().getArch() == llvm::Triple::amdgcn) {
   hasFP64 = true;
@@ -2200,7 +2202,8 @@ public:
 hasFP64Denormals = true;
 }
 if (!hasFP32Denormals)
-  TargetOpts.Features.push_back((Twine(hasFullSpeedFP32Denorms &&
+  TargetOpts.Features.push_back(
+  (Twine(hasFullSpeedFMAF32(TargetOpts.CPU) &&
   !CGOpts.FlushDenorm ? '+' : '-') + Twine("fp32-denormals")).str());
 // Always do not flush fp64 or fp16 denorms.
 if (!hasFP64Denormals && hasFP64)

Added: cfe/trunk/test/CodeGenOpenCL/gfx9-fp32-denorms.cl
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGenOpenCL/gfx9-fp32-denorms.cl?rev=300306=auto
==
--- cfe/trunk/test/CodeGenOpenCL/gfx9-fp32-denorms.cl (added)
+++ cfe/trunk/test/CodeGenOpenCL/gfx9-fp32-denorms.cl Fri Apr 14 00:33:57 2017
@@ -0,0 +1,13 @@
+// REQUIRES: amdgpu-registered-target
+
+// RUN: %clang_cc1 -triple amdgcn-unknown-unknown -target-cpu gfx900 -S 
-emit-llvm -o - %s | FileCheck --check-prefix=DEFAULT %s
+// RUN: %clang_cc1 -triple amdgcn-unknown-unknown -target-cpu gfx900 -S 
-emit-llvm -o - -target-feature +fp32-denormals %s | FileCheck 
--check-prefix=FEATURE_FP32_DENORMALS_ON %s
+// RUN: %clang_cc1 -triple amdgcn-unknown-unknown -target-cpu gfx900 -S 
-emit-llvm -o - -target-feature -fp32-denormals %s | FileCheck 
--check-prefix=FEATURE_FP32_DENORMALS_OFF %s
+// RUN: %clang_cc1 -triple amdgcn-unknown-unknown -target-cpu gfx900 -S 
-emit-llvm -o - -cl-denorms-are-zero %s | FileCheck 
--check-prefix=OPT_DENORMS_ARE_ZERO %s
+
+// DEFAULT: +fp32-denormals
+// FEATURE_FP32_DENORMALS_ON: +fp32-denormals
+// FEATURE_FP32_DENORMALS_OFF: -fp32-denormals
+// OPT_DENORMS_ARE_ZERO: -fp32-denormals
+
+kernel void gfx9_fp32_denorms() {}


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r298420 - Fix array sizes where address space is not yet known

2017-03-21 Thread Konstantin Zhuravlyov via cfe-commits 
Author: kzhuravl
Date: Tue Mar 21 13:55:39 2017
New Revision: 298420

URL: http://llvm.org/viewvc/llvm-project?rev=298420=rev
Log:
Fix array sizes where address space is not yet known

For variables in generic address spaces, for example:

```
unsigned char V[6442450944];
...
```

the address space is not yet known when we get into
*getConstantArrayType*, it is 0. AMDGCN target's
address space 0 has 32 bits pointers, so when we
call *getPointerWidth* with 0, the array size is
trimmed to 32 bits, which is not right.

Differential Revision: https://reviews.llvm.org/D30845

Added:
cfe/trunk/test/CodeGenOpenCL/amdgcn-large-globals.cl
Modified:
cfe/trunk/lib/AST/ASTContext.cpp

Modified: cfe/trunk/lib/AST/ASTContext.cpp
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/AST/ASTContext.cpp?rev=298420=298419=298420=diff
==
--- cfe/trunk/lib/AST/ASTContext.cpp (original)
+++ cfe/trunk/lib/AST/ASTContext.cpp Tue Mar 21 13:55:39 2017
@@ -2692,8 +2692,7 @@ QualType ASTContext::getConstantArrayTyp
   // Convert the array size into a canonical width matching the pointer size 
for
   // the target.
   llvm::APInt ArySize(ArySizeIn);
-  ArySize =
-ArySize.zextOrTrunc(Target->getPointerWidth(getTargetAddressSpace(EltTy)));
+  ArySize = ArySize.zextOrTrunc(Target->getMaxPointerWidth());
 
   llvm::FoldingSetNodeID ID;
   ConstantArrayType::Profile(ID, EltTy, ArySize, ASM, IndexTypeQuals);

Added: cfe/trunk/test/CodeGenOpenCL/amdgcn-large-globals.cl
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGenOpenCL/amdgcn-large-globals.cl?rev=298420=auto
==
--- cfe/trunk/test/CodeGenOpenCL/amdgcn-large-globals.cl (added)
+++ cfe/trunk/test/CodeGenOpenCL/amdgcn-large-globals.cl Tue Mar 21 13:55:39 
2017
@@ -0,0 +1,12 @@
+// REQUIRES: amdgpu-registered-target
+// RUN: %clang_cc1 -cl-std=CL2.0 -triple amdgcn-unknown-unknown -S -emit-llvm 
-o - %s | FileCheck %s
+
+// CHECK: @One = common local_unnamed_addr addrspace(1) global [6442450944 x 
i8] zeroinitializer, align 1
+unsigned char One[6442450944];
+// CHECK: @Two = common local_unnamed_addr addrspace(1) global [6442450944 x 
i32] zeroinitializer, align 4
+global unsigned int Two[6442450944];
+ 
+kernel void large_globals(unsigned int id) {
+  One[id] = id;
+  Two[id + 1] = id + 1;
+}


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r297397 - [DebugInfo] Append extended dereferencing mechanism to variables' DIExpression for targets that support more than one address space

2017-03-09 Thread Konstantin Zhuravlyov via cfe-commits 
Author: kzhuravl
Date: Thu Mar  9 12:06:23 2017
New Revision: 297397

URL: http://llvm.org/viewvc/llvm-project?rev=297397=rev
Log:
[DebugInfo] Append extended dereferencing mechanism to variables' DIExpression 
for targets that support more than one address space

Differential Revision: https://reviews.llvm.org/D29673

Added:
cfe/trunk/test/CodeGenOpenCL/amdgpu-debug-info-variable-expression.cl
Modified:
cfe/trunk/lib/CodeGen/CGDebugInfo.cpp
cfe/trunk/lib/CodeGen/CGDebugInfo.h

Modified: cfe/trunk/lib/CodeGen/CGDebugInfo.cpp
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/CodeGen/CGDebugInfo.cpp?rev=297397=297396=297397=diff
==
--- cfe/trunk/lib/CodeGen/CGDebugInfo.cpp (original)
+++ cfe/trunk/lib/CodeGen/CGDebugInfo.cpp Thu Mar  9 12:06:23 2017
@@ -3272,6 +3272,20 @@ void CGDebugInfo::CreateLexicalBlock(Sou
   getColumnNumber(CurLoc)));
 }
 
+void CGDebugInfo::AppendAddressSpaceXDeref(
+unsigned AddressSpace,
+SmallVectorImpl ) const {
+  Optional DWARFAddressSpace =
+  CGM.getTarget().getDWARFAddressSpace(AddressSpace);
+  if (!DWARFAddressSpace)
+return;
+
+  Expr.push_back(llvm::dwarf::DW_OP_constu);
+  Expr.push_back(DWARFAddressSpace.getValue());
+  Expr.push_back(llvm::dwarf::DW_OP_swap);
+  Expr.push_back(llvm::dwarf::DW_OP_xderef);
+}
+
 void CGDebugInfo::EmitLexicalBlockStart(CGBuilderTy ,
 SourceLocation Loc) {
   // Set our current location.
@@ -3422,13 +3436,16 @@ void CGDebugInfo::EmitDeclare(const VarD
 Line = getLineNumber(VD->getLocation());
 Column = getColumnNumber(VD->getLocation());
   }
-  SmallVector Expr;
+  SmallVector Expr;
   llvm::DINode::DIFlags Flags = llvm::DINode::FlagZero;
   if (VD->isImplicit())
 Flags |= llvm::DINode::FlagArtificial;
 
   auto Align = getDeclAlignIfRequired(VD, CGM.getContext());
 
+  unsigned AddressSpace = 
CGM.getContext().getTargetAddressSpace(VD->getType());
+  AppendAddressSpaceXDeref(AddressSpace, Expr);
+
   // If this is the first argument and it is implicit then
   // give it an object pointer flag.
   // FIXME: There has to be a better way to do this, but for static
@@ -3857,9 +3874,16 @@ void CGDebugInfo::EmitGlobalVariable(llv
 GVE = CollectAnonRecordDecls(RD, Unit, LineNo, LinkageName, Var, DContext);
   } else {
 auto Align = getDeclAlignIfRequired(D, CGM.getContext());
+
+SmallVector Expr;
+unsigned AddressSpace =
+CGM.getContext().getTargetAddressSpace(D->getType());
+AppendAddressSpaceXDeref(AddressSpace, Expr);
+
 GVE = DBuilder.createGlobalVariableExpression(
 DContext, DeclName, LinkageName, Unit, LineNo, getOrCreateType(T, 
Unit),
-Var->hasLocalLinkage(), /*Expr=*/nullptr,
+Var->hasLocalLinkage(),
+Expr.empty() ? nullptr : DBuilder.createExpression(Expr),
 getOrCreateStaticDataMemberDeclarationOrNull(D), Align);
 Var->addDebugInfo(GVE);
   }

Modified: cfe/trunk/lib/CodeGen/CGDebugInfo.h
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/CodeGen/CGDebugInfo.h?rev=297397=297396=297397=diff
==
--- cfe/trunk/lib/CodeGen/CGDebugInfo.h (original)
+++ cfe/trunk/lib/CodeGen/CGDebugInfo.h Thu Mar  9 12:06:23 2017
@@ -293,6 +293,15 @@ class CGDebugInfo {
   /// Create a new lexical block node and push it on the stack.
   void CreateLexicalBlock(SourceLocation Loc);
 
+  /// If target-specific LLVM \p AddressSpace directly maps to target-specific
+  /// DWARF address space, appends extended dereferencing mechanism to complex
+  /// expression \p Expr. Otherwise, does nothing.
+  ///
+  /// Extended dereferencing mechanism is has the following format:
+  /// DW_OP_constu  DW_OP_swap DW_OP_xderef
+  void AppendAddressSpaceXDeref(unsigned AddressSpace,
+SmallVectorImpl ) const;
+
 public:
   CGDebugInfo(CodeGenModule );
   ~CGDebugInfo();

Added: cfe/trunk/test/CodeGenOpenCL/amdgpu-debug-info-variable-expression.cl
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGenOpenCL/amdgpu-debug-info-variable-expression.cl?rev=297397=auto
==
--- cfe/trunk/test/CodeGenOpenCL/amdgpu-debug-info-variable-expression.cl 
(added)
+++ cfe/trunk/test/CodeGenOpenCL/amdgpu-debug-info-variable-expression.cl Thu 
Mar  9 12:06:23 2017
@@ -0,0 +1,131 @@
+// RUN: %clang -cl-std=CL2.0 -emit-llvm -g -O0 -S -target amdgcn-amd-amdhsa 
-mcpu=fiji -o - %s | FileCheck %s
+
+// CHECK-DAG: ![[NONE:[0-9]+]] = !DIExpression()
+// CHECK-DAG: ![[LOCAL:[0-9]+]] = !DIExpression(DW_OP_constu, 2, DW_OP_swap, 
DW_OP_xderef)
+// CHECK-DAG: ![[PRIVATE:[0-9]+]] = !DIExpression(DW_OP_constu, 1, DW_OP_swap, 
DW_OP_xderef)
+
+// CHECK-DAG: ![[FILEVAR0:[0-9]+]] = distinct !DIGlobalVariable(name: 
"FileVar0", scope:

r297329 - Driver/ToolChains: Remove extra semicolons. NFC

2017-03-08 Thread Konstantin Zhuravlyov via cfe-commits 
Author: kzhuravl
Date: Wed Mar  8 18:14:57 2017
New Revision: 297329

URL: http://llvm.org/viewvc/llvm-project?rev=297329=rev
Log:
Driver/ToolChains: Remove extra semicolons. NFC

Modified:
cfe/trunk/lib/Driver/ToolChains/Haiku.cpp
cfe/trunk/lib/Driver/ToolChains/TCE.cpp
cfe/trunk/lib/Driver/ToolChains/XCore.cpp

Modified: cfe/trunk/lib/Driver/ToolChains/Haiku.cpp
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Driver/ToolChains/Haiku.cpp?rev=297329=297328=297329=diff
==
--- cfe/trunk/lib/Driver/ToolChains/Haiku.cpp (original)
+++ cfe/trunk/lib/Driver/ToolChains/Haiku.cpp Wed Mar  8 18:14:57 2017
@@ -11,7 +11,7 @@
 #include "CommonArgs.h"
 
 using namespace clang::driver;
-using namespace clang::driver::toolchains;;
+using namespace clang::driver::toolchains;
 using namespace clang;
 using namespace llvm::opt;
 

Modified: cfe/trunk/lib/Driver/ToolChains/TCE.cpp
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Driver/ToolChains/TCE.cpp?rev=297329=297328=297329=diff
==
--- cfe/trunk/lib/Driver/ToolChains/TCE.cpp (original)
+++ cfe/trunk/lib/Driver/ToolChains/TCE.cpp Wed Mar  8 18:14:57 2017
@@ -11,7 +11,7 @@
 #include "CommonArgs.h"
 
 using namespace clang::driver;
-using namespace clang::driver::toolchains;;
+using namespace clang::driver::toolchains;
 using namespace clang;
 using namespace llvm::opt;
 

Modified: cfe/trunk/lib/Driver/ToolChains/XCore.cpp
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Driver/ToolChains/XCore.cpp?rev=297329=297328=297329=diff
==
--- cfe/trunk/lib/Driver/ToolChains/XCore.cpp (original)
+++ cfe/trunk/lib/Driver/ToolChains/XCore.cpp Wed Mar  8 18:14:57 2017
@@ -16,7 +16,7 @@
 #include  // ::getenv
 
 using namespace clang::driver;
-using namespace clang::driver::toolchains;;
+using namespace clang::driver::toolchains;
 using namespace clang;
 using namespace llvm::opt;
 


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r297321 - [DebugInfo] Add address space when creating DIDerivedTypes

2017-03-08 Thread Konstantin Zhuravlyov via cfe-commits 
Author: kzhuravl
Date: Wed Mar  8 17:56:48 2017
New Revision: 297321

URL: http://llvm.org/viewvc/llvm-project?rev=297321=rev
Log:
[DebugInfo] Add address space when creating DIDerivedTypes

Differential Revision: https://reviews.llvm.org/D29671

Added:
cfe/trunk/test/CodeGenOpenCL/amdgpu-debug-info-pointer-address-space.cl
Modified:
cfe/trunk/include/clang/Basic/TargetInfo.h
cfe/trunk/lib/Basic/Targets.cpp
cfe/trunk/lib/CodeGen/CGDebugInfo.cpp

Modified: cfe/trunk/include/clang/Basic/TargetInfo.h
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/include/clang/Basic/TargetInfo.h?rev=297321=297320=297321=diff
==
--- cfe/trunk/include/clang/Basic/TargetInfo.h (original)
+++ cfe/trunk/include/clang/Basic/TargetInfo.h Wed Mar  8 17:56:48 2017
@@ -1032,6 +1032,21 @@ public:
 return LangAS::opencl_global;
   }
 
+  /// \returns Target specific vtbl ptr address space.
+  virtual unsigned getVtblPtrAddressSpace() const {
+return 0;
+  }
+
+  /// \returns If a target requires an address within a target specific address
+  /// space \p AddressSpace to be converted in order to be used, then return 
the
+  /// corresponding target specific DWARF address space.
+  ///
+  /// \returns Otherwise return None and no conversion will be emitted in the
+  /// DWARF.
+  virtual Optional getDWARFAddressSpace(unsigned AddressSpace) const 
{
+return None;
+  }
+
   /// \brief Check the target is valid after it is fully initialized.
   virtual bool validateTarget(DiagnosticsEngine ) const {
 return true;

Modified: cfe/trunk/lib/Basic/Targets.cpp
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Basic/Targets.cpp?rev=297321=297320=297321=diff
==
--- cfe/trunk/lib/Basic/Targets.cpp (original)
+++ cfe/trunk/lib/Basic/Targets.cpp Wed Mar  8 17:56:48 2017
@@ -2258,6 +2258,32 @@ public:
 return LangAS::opencl_constant;
   }
 
+  /// \returns Target specific vtbl ptr address space.
+  unsigned getVtblPtrAddressSpace() const override {
+// \todo: We currently have address spaces defined in AMDGPU Backend. It
+// would be nice if we could use it here instead of using bare numbers 
(same
+// applies to getDWARFAddressSpace).
+return 2; // constant.
+  }
+
+  /// \returns If a target requires an address within a target specific address
+  /// space \p AddressSpace to be converted in order to be used, then return 
the
+  /// corresponding target specific DWARF address space.
+  ///
+  /// \returns Otherwise return None and no conversion will be emitted in the
+  /// DWARF.
+  Optional getDWARFAddressSpace(
+  unsigned AddressSpace) const override {
+switch (AddressSpace) {
+case 0: // LLVM Private.
+  return 1; // DWARF Private.
+case 3: // LLVM Local.
+  return 2; // DWARF Local.
+default:
+  return None;
+}
+  }
+
   CallingConvCheckResult checkCallingConvention(CallingConv CC) const override 
{
 switch (CC) {
   default:

Modified: cfe/trunk/lib/CodeGen/CGDebugInfo.cpp
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/CodeGen/CGDebugInfo.cpp?rev=297321=297320=297321=diff
==
--- cfe/trunk/lib/CodeGen/CGDebugInfo.cpp (original)
+++ cfe/trunk/lib/CodeGen/CGDebugInfo.cpp Wed Mar  8 17:56:48 2017
@@ -816,17 +816,19 @@ llvm::DIType *CGDebugInfo::CreatePointer
   // Bit size, align and offset of the type.
   // Size is always the size of a pointer. We can't use getTypeSize here
   // because that does not return the correct value for references.
-  unsigned AS = CGM.getContext().getTargetAddressSpace(PointeeTy);
-  uint64_t Size = CGM.getTarget().getPointerWidth(AS);
+  unsigned AddressSpace = CGM.getContext().getTargetAddressSpace(PointeeTy);
+  uint64_t Size = CGM.getTarget().getPointerWidth(AddressSpace);
   auto Align = getTypeAlignIfRequired(Ty, CGM.getContext());
+  Optional DWARFAddressSpace =
+  CGM.getTarget().getDWARFAddressSpace(AddressSpace);
 
   if (Tag == llvm::dwarf::DW_TAG_reference_type ||
   Tag == llvm::dwarf::DW_TAG_rvalue_reference_type)
 return DBuilder.createReferenceType(Tag, getOrCreateType(PointeeTy, Unit),
-Size, Align);
+Size, Align, DWARFAddressSpace);
   else
 return DBuilder.createPointerType(getOrCreateType(PointeeTy, Unit), Size,
-  Align);
+  Align, DWARFAddressSpace);
 }
 
 llvm::DIType *CGDebugInfo::getOrCreateStructPtrType(StringRef Name,
@@ -1631,8 +1633,13 @@ llvm::DIType *CGDebugInfo::getOrCreateVT
   llvm::DITypeRefArray SElements = DBuilder.getOrCreateTypeArray(STy);
   llvm::DIType *SubTy = DBuilder.createSubroutineType(SElements);
   unsigned Size = Context.getTypeSize(Context.VoidPtrTy);
+  unsigned

r297312 - Driver/ToolChains: Mips -> MipsLinux

2017-03-08 Thread Konstantin Zhuravlyov via cfe-commits 
Author: kzhuravl
Date: Wed Mar  8 16:36:04 2017
New Revision: 297312

URL: http://llvm.org/viewvc/llvm-project?rev=297312=rev
Log:
Driver/ToolChains: Mips -> MipsLinux
  - Mips is architecture, not a toolchain
  - Might help eliminate the confusion in the future by not having header files 
with the same name

Differential Revision: https://reviews.llvm.org/D30753

Added:
cfe/trunk/lib/Driver/ToolChains/MipsLinux.cpp
cfe/trunk/lib/Driver/ToolChains/MipsLinux.h
Removed:
cfe/trunk/lib/Driver/ToolChains/Mips.cpp
cfe/trunk/lib/Driver/ToolChains/Mips.h
Modified:
cfe/trunk/lib/Driver/CMakeLists.txt
cfe/trunk/lib/Driver/Driver.cpp

Modified: cfe/trunk/lib/Driver/CMakeLists.txt
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Driver/CMakeLists.txt?rev=297312=297311=297312=diff
==
--- cfe/trunk/lib/Driver/CMakeLists.txt (original)
+++ cfe/trunk/lib/Driver/CMakeLists.txt Wed Mar  8 16:36:04 2017
@@ -44,7 +44,7 @@ add_clang_library(clangDriver
   ToolChains/Haiku.cpp
   ToolChains/Hexagon.cpp
   ToolChains/Linux.cpp
-  ToolChains/Mips.cpp
+  ToolChains/MipsLinux.cpp
   ToolChains/MinGW.cpp
   ToolChains/Minix.cpp
   ToolChains/MSVC.cpp

Modified: cfe/trunk/lib/Driver/Driver.cpp
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Driver/Driver.cpp?rev=297312=297311=297312=diff
==
--- cfe/trunk/lib/Driver/Driver.cpp (original)
+++ cfe/trunk/lib/Driver/Driver.cpp Wed Mar  8 16:36:04 2017
@@ -28,7 +28,7 @@
 #include "ToolChains/Linux.h"
 #include "ToolChains/MinGW.h"
 #include "ToolChains/Minix.h"
-#include "ToolChains/Mips.h"
+#include "ToolChains/MipsLinux.h"
 #include "ToolChains/MSVC.h"
 #include "ToolChains/Myriad.h"
 #include "ToolChains/NaCl.h"

Removed: cfe/trunk/lib/Driver/ToolChains/Mips.cpp
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Driver/ToolChains/Mips.cpp?rev=297311=auto
==
--- cfe/trunk/lib/Driver/ToolChains/Mips.cpp (original)
+++ cfe/trunk/lib/Driver/ToolChains/Mips.cpp (removed)
@@ -1,128 +0,0 @@
-//===--- Mips.cpp - Mips ToolChain Implementations --*- C++ 
-*-===//
-//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===--===//
-
-#include "Mips.h"
-#include "Arch/Mips.h"
-#include "CommonArgs.h"
-#include "clang/Config/config.h"
-#include "clang/Driver/Driver.h"
-#include "clang/Driver/DriverDiagnostic.h"
-#include "clang/Driver/Options.h"
-#include "llvm/Option/ArgList.h"
-#include "llvm/Support/FileSystem.h"
-#include "llvm/Support/Path.h"
-
-using namespace clang::driver;
-using namespace clang::driver::toolchains;
-using namespace clang;
-using namespace llvm::opt;
-
-/// Mips Toolchain
-MipsLLVMToolChain::MipsLLVMToolChain(const Driver ,
- const llvm::Triple ,
- const ArgList )
-: Linux(D, Triple, Args) {
-  // Select the correct multilib according to the given arguments.
-  DetectedMultilibs Result;
-  findMIPSMultilibs(D, Triple, "", Args, Result);
-  Multilibs = Result.Multilibs;
-  SelectedMultilib = Result.SelectedMultilib;
-
-  // Find out the library suffix based on the ABI.
-  LibSuffix = tools::mips::getMipsABILibSuffix(Args, Triple);
-  getFilePaths().clear();
-  getFilePaths().push_back(computeSysRoot() + "/usr/lib" + LibSuffix);
-}
-
-void MipsLLVMToolChain::AddClangSystemIncludeArgs(
-const ArgList , ArgStringList ) const {
-  if (DriverArgs.hasArg(clang::driver::options::OPT_nostdinc))
-return;
-
-  const Driver  = getDriver();
-
-  if (!DriverArgs.hasArg(options::OPT_nobuiltininc)) {
-SmallString<128> P(D.ResourceDir);
-llvm::sys::path::append(P, "include");
-addSystemInclude(DriverArgs, CC1Args, P);
-  }
-
-  if (DriverArgs.hasArg(options::OPT_nostdlibinc))
-return;
-
-  const auto  = Multilibs.includeDirsCallback();
-  if (Callback) {
-for (const auto  : Callback(SelectedMultilib))
-  addExternCSystemIncludeIfExists(DriverArgs, CC1Args,
-  D.getInstalledDir() + Path);
-  }
-}
-
-Tool *MipsLLVMToolChain::buildLinker() const {
-  return new tools::gnutools::Linker(*this);
-}
-
-std::string MipsLLVMToolChain::computeSysRoot() const {
-  if (!getDriver().SysRoot.empty())
-return getDriver().SysRoot + SelectedMultilib.osSuffix();
-
-  const std::string InstalledDir(getDriver().getInstalledDir());
-  std::string SysRootPath =
-  InstalledDir + "/../sysroot" + SelectedMultilib.osSuffix();
-  if (llvm::sys::fs::exists(SysRootPath))
-return SysRootPath;
-
-  return std::string();
-}
-
-ToolChain::CXXStdlibType
-MipsLLVMToolChain::GetCXXStdlibType(const

r291243 - [OpenCL] Re-enable supported core extensions based on opencl version when disabling all extensions using pragma

2017-01-06 Thread Konstantin Zhuravlyov via cfe-commits 
Author: kzhuravl
Date: Fri Jan  6 10:14:41 2017
New Revision: 291243

URL: http://llvm.org/viewvc/llvm-project?rev=291243=rev
Log:
[OpenCL] Re-enable supported core extensions based on opencl version when 
disabling all extensions using pragma

Differential Revision: https://reviews.llvm.org/D28257

Modified:
cfe/trunk/lib/Parse/ParsePragma.cpp
cfe/trunk/test/SemaOpenCL/extensions.cl

Modified: cfe/trunk/lib/Parse/ParsePragma.cpp
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Parse/ParsePragma.cpp?rev=291243=291242=291243=diff
==
--- cfe/trunk/lib/Parse/ParsePragma.cpp (original)
+++ cfe/trunk/lib/Parse/ParsePragma.cpp Fri Jan  6 10:14:41 2017
@@ -506,10 +506,12 @@ void Parser::HandlePragmaOpenCLExtension
   // overriding all previously issued extension directives, but only if the
   // behavior is set to disable."
   if (Name == "all") {
-if (State == Disable)
+if (State == Disable) {
   Opt.disableAll();
-else
+  Opt.enableSupportedCore(getLangOpts().OpenCLVersion);
+} else {
   PP.Diag(NameLoc, diag::warn_pragma_expected_predicate) << 1;
+}
   } else if (State == Begin) {
 if (!Opt.isKnown(Name) ||
 !Opt.isSupported(Name, getLangOpts().OpenCLVersion)) {

Modified: cfe/trunk/test/SemaOpenCL/extensions.cl
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/SemaOpenCL/extensions.cl?rev=291243=291242=291243=diff
==
--- cfe/trunk/test/SemaOpenCL/extensions.cl (original)
+++ cfe/trunk/test/SemaOpenCL/extensions.cl Fri Jan  6 10:14:41 2017
@@ -22,6 +22,17 @@
 // RUN: %clang_cc1 %s -triple spir-unknown-unknown -verify -pedantic 
-fsyntax-only -cl-ext=-all -cl-ext=+cl_khr_fp64 -cl-ext=+cl_khr_fp16 
-cl-ext=-cl_khr_fp64 -DNOFP64
 // RUN: %clang_cc1 %s -triple spir-unknown-unknown -verify -pedantic 
-fsyntax-only -cl-ext=-all -cl-ext=+cl_khr_fp64,-cl_khr_fp64,+cl_khr_fp16 
-DNOFP64
 
+// Test with -finclude-default-header, which includes opencl-c.h. opencl-c.h
+// disables all extensions by default, but supported core extensions for a
+// particular OpenCL version must be re-enabled (for example, cl_khr_fp64 is
+// enabled by default with -cl-std=CL2.0).
+//
+// RUN: %clang_cc1 %s -triple amdgcn-unknown-unknown -verify -pedantic 
-fsyntax-only -cl-std=CL2.0 -finclude-default-header
+
+#ifdef _OPENCL_H_
+// expected-no-diagnostics
+#endif
+
 #ifdef FP64
 // expected-no-diagnostics
 #endif
@@ -33,6 +44,7 @@ void f1(double da) { // expected-error {
 }
 #endif
 
+#ifndef _OPENCL_H_
 int isnan(float x) {
 return __builtin_isnan(x);
 }
@@ -40,6 +52,7 @@ int isnan(float x) {
 int isfinite(float x) {
 return __builtin_isfinite(x);
 }
+#endif
 
 #pragma OPENCL EXTENSION cl_khr_fp64 : enable
 #ifdef NOFP64


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[PATCH] D26863: [AMDGPU] Change frexp.exp builtin to return i16 for f16 input

2016-11-18 Thread Konstantin Zhuravlyov via cfe-commits 
This revision was automatically updated to reflect the committed changes.
Closed by commit rL287390: [AMDGPU] Change frexp.exp builtin to return i16 for 
f16 input (authored by kzhuravl).

Changed prior to commit:
  https://reviews.llvm.org/D26863?vs=78546=78586#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D26863

Files:
  cfe/trunk/include/clang/Basic/BuiltinsAMDGPU.def
  cfe/trunk/lib/CodeGen/CGBuiltin.cpp
  cfe/trunk/test/CodeGenOpenCL/builtins-amdgcn-vi.cl
  cfe/trunk/test/CodeGenOpenCL/builtins-amdgcn.cl


Index: cfe/trunk/test/CodeGenOpenCL/builtins-amdgcn-vi.cl
===
--- cfe/trunk/test/CodeGenOpenCL/builtins-amdgcn-vi.cl
+++ cfe/trunk/test/CodeGenOpenCL/builtins-amdgcn-vi.cl
@@ -55,7 +55,7 @@
 }
 
 // CHECK-LABEL: @test_frexp_exp_f16
-// CHECK: call i32 @llvm.amdgcn.frexp.exp.f16
+// CHECK: call i16 @llvm.amdgcn.frexp.exp.i16.f16
 void test_frexp_exp_f16(global short* out, half a)
 {
   *out = __builtin_amdgcn_frexp_exph(a);
Index: cfe/trunk/test/CodeGenOpenCL/builtins-amdgcn.cl
===
--- cfe/trunk/test/CodeGenOpenCL/builtins-amdgcn.cl
+++ cfe/trunk/test/CodeGenOpenCL/builtins-amdgcn.cl
@@ -166,14 +166,14 @@
 }
 
 // CHECK-LABEL: @test_frexp_exp_f32
-// CHECK: call i32 @llvm.amdgcn.frexp.exp.f32
+// CHECK: call i32 @llvm.amdgcn.frexp.exp.i32.f32
 void test_frexp_exp_f32(global int* out, float a)
 {
   *out = __builtin_amdgcn_frexp_expf(a);
 }
 
 // CHECK-LABEL: @test_frexp_exp_f64
-// CHECK: call i32 @llvm.amdgcn.frexp.exp.f64
+// CHECK: call i32 @llvm.amdgcn.frexp.exp.i32.f64
 void test_frexp_exp_f64(global int* out, double a)
 {
   *out = __builtin_amdgcn_frexp_exp(a);
Index: cfe/trunk/lib/CodeGen/CGBuiltin.cpp
===
--- cfe/trunk/lib/CodeGen/CGBuiltin.cpp
+++ cfe/trunk/lib/CodeGen/CGBuiltin.cpp
@@ -8250,9 +8250,18 @@
   case AMDGPU::BI__builtin_amdgcn_frexp_manth:
 return emitUnaryBuiltin(*this, E, Intrinsic::amdgcn_frexp_mant);
   case AMDGPU::BI__builtin_amdgcn_frexp_exp:
-  case AMDGPU::BI__builtin_amdgcn_frexp_expf:
-  case AMDGPU::BI__builtin_amdgcn_frexp_exph:
-return emitUnaryBuiltin(*this, E, Intrinsic::amdgcn_frexp_exp);
+  case AMDGPU::BI__builtin_amdgcn_frexp_expf: {
+Value *Src0 = EmitScalarExpr(E->getArg(0));
+Value *F = CGM.getIntrinsic(Intrinsic::amdgcn_frexp_exp,
+{ Builder.getInt32Ty(), Src0->getType() });
+return Builder.CreateCall(F, Src0);
+  }
+  case AMDGPU::BI__builtin_amdgcn_frexp_exph: {
+Value *Src0 = EmitScalarExpr(E->getArg(0));
+Value *F = CGM.getIntrinsic(Intrinsic::amdgcn_frexp_exp,
+{ Builder.getInt16Ty(), Src0->getType() });
+return Builder.CreateCall(F, Src0);
+  }
   case AMDGPU::BI__builtin_amdgcn_fract:
   case AMDGPU::BI__builtin_amdgcn_fractf:
   case AMDGPU::BI__builtin_amdgcn_fracth:
Index: cfe/trunk/include/clang/Basic/BuiltinsAMDGPU.def
===
--- cfe/trunk/include/clang/Basic/BuiltinsAMDGPU.def
+++ cfe/trunk/include/clang/Basic/BuiltinsAMDGPU.def
@@ -92,7 +92,7 @@
 TARGET_BUILTIN(__builtin_amdgcn_cosh, "hh", "nc", "16-bit-insts")
 TARGET_BUILTIN(__builtin_amdgcn_ldexph, "hhi", "nc", "16-bit-insts")
 TARGET_BUILTIN(__builtin_amdgcn_frexp_manth, "hh", "nc", "16-bit-insts")
-TARGET_BUILTIN(__builtin_amdgcn_frexp_exph, "ih", "nc", "16-bit-insts")
+TARGET_BUILTIN(__builtin_amdgcn_frexp_exph, "sh", "nc", "16-bit-insts")
 TARGET_BUILTIN(__builtin_amdgcn_fracth, "hh", "nc", "16-bit-insts")
 TARGET_BUILTIN(__builtin_amdgcn_classh, "bhi", "nc", "16-bit-insts")
 TARGET_BUILTIN(__builtin_amdgcn_s_memrealtime, "LUi", "n", "s-memrealtime")


Index: cfe/trunk/test/CodeGenOpenCL/builtins-amdgcn-vi.cl
===
--- cfe/trunk/test/CodeGenOpenCL/builtins-amdgcn-vi.cl
+++ cfe/trunk/test/CodeGenOpenCL/builtins-amdgcn-vi.cl
@@ -55,7 +55,7 @@
 }
 
 // CHECK-LABEL: @test_frexp_exp_f16
-// CHECK: call i32 @llvm.amdgcn.frexp.exp.f16
+// CHECK: call i16 @llvm.amdgcn.frexp.exp.i16.f16
 void test_frexp_exp_f16(global short* out, half a)
 {
   *out = __builtin_amdgcn_frexp_exph(a);
Index: cfe/trunk/test/CodeGenOpenCL/builtins-amdgcn.cl
===
--- cfe/trunk/test/CodeGenOpenCL/builtins-amdgcn.cl
+++ cfe/trunk/test/CodeGenOpenCL/builtins-amdgcn.cl
@@ -166,14 +166,14 @@
 }
 
 // CHECK-LABEL: @test_frexp_exp_f32
-// CHECK: call i32 @llvm.amdgcn.frexp.exp.f32
+// CHECK: call i32 @llvm.amdgcn.frexp.exp.i32.f32
 void test_frexp_exp_f32(global int* out, float a)
 {
   *out = __builtin_amdgcn_frexp_expf(a);
 }
 
 // CHECK-LABEL: @test_frexp_exp_f64
-// CHECK: call i32 @llvm.amdgcn.frexp.exp.f64
+// CHECK: call i32 @llvm.amdgcn.frexp.exp.i32.f64
 void test_frexp_exp_f64(global int* out, double a)
 {
   *out =

r287390 - [AMDGPU] Change frexp.exp builtin to return i16 for f16 input

2016-11-18 Thread Konstantin Zhuravlyov via cfe-commits 
Author: kzhuravl
Date: Fri Nov 18 16:31:51 2016
New Revision: 287390

URL: http://llvm.org/viewvc/llvm-project?rev=287390=rev
Log:
[AMDGPU] Change frexp.exp builtin to return i16 for f16 input

Differential Revision: https://reviews.llvm.org/D26863

Modified:
cfe/trunk/include/clang/Basic/BuiltinsAMDGPU.def
cfe/trunk/lib/CodeGen/CGBuiltin.cpp
cfe/trunk/test/CodeGenOpenCL/builtins-amdgcn-vi.cl
cfe/trunk/test/CodeGenOpenCL/builtins-amdgcn.cl

Modified: cfe/trunk/include/clang/Basic/BuiltinsAMDGPU.def
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/include/clang/Basic/BuiltinsAMDGPU.def?rev=287390=287389=287390=diff
==
--- cfe/trunk/include/clang/Basic/BuiltinsAMDGPU.def (original)
+++ cfe/trunk/include/clang/Basic/BuiltinsAMDGPU.def Fri Nov 18 16:31:51 2016
@@ -92,7 +92,7 @@ TARGET_BUILTIN(__builtin_amdgcn_sinh, "h
 TARGET_BUILTIN(__builtin_amdgcn_cosh, "hh", "nc", "16-bit-insts")
 TARGET_BUILTIN(__builtin_amdgcn_ldexph, "hhi", "nc", "16-bit-insts")
 TARGET_BUILTIN(__builtin_amdgcn_frexp_manth, "hh", "nc", "16-bit-insts")
-TARGET_BUILTIN(__builtin_amdgcn_frexp_exph, "ih", "nc", "16-bit-insts")
+TARGET_BUILTIN(__builtin_amdgcn_frexp_exph, "sh", "nc", "16-bit-insts")
 TARGET_BUILTIN(__builtin_amdgcn_fracth, "hh", "nc", "16-bit-insts")
 TARGET_BUILTIN(__builtin_amdgcn_classh, "bhi", "nc", "16-bit-insts")
 TARGET_BUILTIN(__builtin_amdgcn_s_memrealtime, "LUi", "n", "s-memrealtime")

Modified: cfe/trunk/lib/CodeGen/CGBuiltin.cpp
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/CodeGen/CGBuiltin.cpp?rev=287390=287389=287390=diff
==
--- cfe/trunk/lib/CodeGen/CGBuiltin.cpp (original)
+++ cfe/trunk/lib/CodeGen/CGBuiltin.cpp Fri Nov 18 16:31:51 2016
@@ -8250,9 +8250,18 @@ Value *CodeGenFunction::EmitAMDGPUBuilti
   case AMDGPU::BI__builtin_amdgcn_frexp_manth:
 return emitUnaryBuiltin(*this, E, Intrinsic::amdgcn_frexp_mant);
   case AMDGPU::BI__builtin_amdgcn_frexp_exp:
-  case AMDGPU::BI__builtin_amdgcn_frexp_expf:
-  case AMDGPU::BI__builtin_amdgcn_frexp_exph:
-return emitUnaryBuiltin(*this, E, Intrinsic::amdgcn_frexp_exp);
+  case AMDGPU::BI__builtin_amdgcn_frexp_expf: {
+Value *Src0 = EmitScalarExpr(E->getArg(0));
+Value *F = CGM.getIntrinsic(Intrinsic::amdgcn_frexp_exp,
+{ Builder.getInt32Ty(), Src0->getType() });
+return Builder.CreateCall(F, Src0);
+  }
+  case AMDGPU::BI__builtin_amdgcn_frexp_exph: {
+Value *Src0 = EmitScalarExpr(E->getArg(0));
+Value *F = CGM.getIntrinsic(Intrinsic::amdgcn_frexp_exp,
+{ Builder.getInt16Ty(), Src0->getType() });
+return Builder.CreateCall(F, Src0);
+  }
   case AMDGPU::BI__builtin_amdgcn_fract:
   case AMDGPU::BI__builtin_amdgcn_fractf:
   case AMDGPU::BI__builtin_amdgcn_fracth:

Modified: cfe/trunk/test/CodeGenOpenCL/builtins-amdgcn-vi.cl
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGenOpenCL/builtins-amdgcn-vi.cl?rev=287390=287389=287390=diff
==
--- cfe/trunk/test/CodeGenOpenCL/builtins-amdgcn-vi.cl (original)
+++ cfe/trunk/test/CodeGenOpenCL/builtins-amdgcn-vi.cl Fri Nov 18 16:31:51 2016
@@ -55,7 +55,7 @@ void test_frexp_mant_f16(global half* ou
 }
 
 // CHECK-LABEL: @test_frexp_exp_f16
-// CHECK: call i32 @llvm.amdgcn.frexp.exp.f16
+// CHECK: call i16 @llvm.amdgcn.frexp.exp.i16.f16
 void test_frexp_exp_f16(global short* out, half a)
 {
   *out = __builtin_amdgcn_frexp_exph(a);

Modified: cfe/trunk/test/CodeGenOpenCL/builtins-amdgcn.cl
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGenOpenCL/builtins-amdgcn.cl?rev=287390=287389=287390=diff
==
--- cfe/trunk/test/CodeGenOpenCL/builtins-amdgcn.cl (original)
+++ cfe/trunk/test/CodeGenOpenCL/builtins-amdgcn.cl Fri Nov 18 16:31:51 2016
@@ -166,14 +166,14 @@ void test_frexp_mant_f64(global double*
 }
 
 // CHECK-LABEL: @test_frexp_exp_f32
-// CHECK: call i32 @llvm.amdgcn.frexp.exp.f32
+// CHECK: call i32 @llvm.amdgcn.frexp.exp.i32.f32
 void test_frexp_exp_f32(global int* out, float a)
 {
   *out = __builtin_amdgcn_frexp_expf(a);
 }
 
 // CHECK-LABEL: @test_frexp_exp_f64
-// CHECK: call i32 @llvm.amdgcn.frexp.exp.f64
+// CHECK: call i32 @llvm.amdgcn.frexp.exp.i32.f64
 void test_frexp_exp_f64(global int* out, double a)
 {
   *out = __builtin_amdgcn_frexp_exp(a);


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[PATCH] D26863: [AMDGPU] Change frexp.exp builtin to return i16 for f16 input

2016-11-18 Thread Konstantin Zhuravlyov via cfe-commits 
kzhuravl created this revision.
kzhuravl added reviewers: tstellarAMD, arsenm.
kzhuravl added subscribers: b-sumner, cfe-commits.
Herald added subscribers: tony-tye, yaxunl, nhaehnle, wdng.

https://reviews.llvm.org/D26863

Files:
  include/clang/Basic/BuiltinsAMDGPU.def
  lib/CodeGen/CGBuiltin.cpp
  test/CodeGenOpenCL/builtins-amdgcn-vi.cl
  test/CodeGenOpenCL/builtins-amdgcn.cl


Index: test/CodeGenOpenCL/builtins-amdgcn.cl
===
--- test/CodeGenOpenCL/builtins-amdgcn.cl
+++ test/CodeGenOpenCL/builtins-amdgcn.cl
@@ -166,14 +166,14 @@
 }
 
 // CHECK-LABEL: @test_frexp_exp_f32
-// CHECK: call i32 @llvm.amdgcn.frexp.exp.f32
+// CHECK: call i32 @llvm.amdgcn.frexp.exp.i32.f32
 void test_frexp_exp_f32(global int* out, float a)
 {
   *out = __builtin_amdgcn_frexp_expf(a);
 }
 
 // CHECK-LABEL: @test_frexp_exp_f64
-// CHECK: call i32 @llvm.amdgcn.frexp.exp.f64
+// CHECK: call i32 @llvm.amdgcn.frexp.exp.i32.f64
 void test_frexp_exp_f64(global int* out, double a)
 {
   *out = __builtin_amdgcn_frexp_exp(a);
Index: test/CodeGenOpenCL/builtins-amdgcn-vi.cl
===
--- test/CodeGenOpenCL/builtins-amdgcn-vi.cl
+++ test/CodeGenOpenCL/builtins-amdgcn-vi.cl
@@ -55,7 +55,7 @@
 }
 
 // CHECK-LABEL: @test_frexp_exp_f16
-// CHECK: call i32 @llvm.amdgcn.frexp.exp.f16
+// CHECK: call i16 @llvm.amdgcn.frexp.exp.i16.f16
 void test_frexp_exp_f16(global short* out, half a)
 {
   *out = __builtin_amdgcn_frexp_exph(a);
Index: lib/CodeGen/CGBuiltin.cpp
===
--- lib/CodeGen/CGBuiltin.cpp
+++ lib/CodeGen/CGBuiltin.cpp
@@ -8250,9 +8250,18 @@
   case AMDGPU::BI__builtin_amdgcn_frexp_manth:
 return emitUnaryBuiltin(*this, E, Intrinsic::amdgcn_frexp_mant);
   case AMDGPU::BI__builtin_amdgcn_frexp_exp:
-  case AMDGPU::BI__builtin_amdgcn_frexp_expf:
-  case AMDGPU::BI__builtin_amdgcn_frexp_exph:
-return emitUnaryBuiltin(*this, E, Intrinsic::amdgcn_frexp_exp);
+  case AMDGPU::BI__builtin_amdgcn_frexp_expf: {
+Value *Src0 = EmitScalarExpr(E->getArg(0));
+Value *F = CGM.getIntrinsic(Intrinsic::amdgcn_frexp_exp,
+{ Builder.getInt32Ty(), Src0->getType() });
+return Builder.CreateCall(F, Src0);
+  }
+  case AMDGPU::BI__builtin_amdgcn_frexp_exph: {
+Value *Src0 = EmitScalarExpr(E->getArg(0));
+Value *F = CGM.getIntrinsic(Intrinsic::amdgcn_frexp_exp,
+{ Builder.getInt16Ty(), Src0->getType() });
+return Builder.CreateCall(F, Src0);
+  }
   case AMDGPU::BI__builtin_amdgcn_fract:
   case AMDGPU::BI__builtin_amdgcn_fractf:
   case AMDGPU::BI__builtin_amdgcn_fracth:
Index: include/clang/Basic/BuiltinsAMDGPU.def
===
--- include/clang/Basic/BuiltinsAMDGPU.def
+++ include/clang/Basic/BuiltinsAMDGPU.def
@@ -92,7 +92,7 @@
 TARGET_BUILTIN(__builtin_amdgcn_cosh, "hh", "nc", "16-bit-insts")
 TARGET_BUILTIN(__builtin_amdgcn_ldexph, "hhi", "nc", "16-bit-insts")
 TARGET_BUILTIN(__builtin_amdgcn_frexp_manth, "hh", "nc", "16-bit-insts")
-TARGET_BUILTIN(__builtin_amdgcn_frexp_exph, "ih", "nc", "16-bit-insts")
+TARGET_BUILTIN(__builtin_amdgcn_frexp_exph, "sh", "nc", "16-bit-insts")
 TARGET_BUILTIN(__builtin_amdgcn_fracth, "hh", "nc", "16-bit-insts")
 TARGET_BUILTIN(__builtin_amdgcn_classh, "bhi", "nc", "16-bit-insts")
 TARGET_BUILTIN(__builtin_amdgcn_s_memrealtime, "LUi", "n", "s-memrealtime")


Index: test/CodeGenOpenCL/builtins-amdgcn.cl
===
--- test/CodeGenOpenCL/builtins-amdgcn.cl
+++ test/CodeGenOpenCL/builtins-amdgcn.cl
@@ -166,14 +166,14 @@
 }
 
 // CHECK-LABEL: @test_frexp_exp_f32
-// CHECK: call i32 @llvm.amdgcn.frexp.exp.f32
+// CHECK: call i32 @llvm.amdgcn.frexp.exp.i32.f32
 void test_frexp_exp_f32(global int* out, float a)
 {
   *out = __builtin_amdgcn_frexp_expf(a);
 }
 
 // CHECK-LABEL: @test_frexp_exp_f64
-// CHECK: call i32 @llvm.amdgcn.frexp.exp.f64
+// CHECK: call i32 @llvm.amdgcn.frexp.exp.i32.f64
 void test_frexp_exp_f64(global int* out, double a)
 {
   *out = __builtin_amdgcn_frexp_exp(a);
Index: test/CodeGenOpenCL/builtins-amdgcn-vi.cl
===
--- test/CodeGenOpenCL/builtins-amdgcn-vi.cl
+++ test/CodeGenOpenCL/builtins-amdgcn-vi.cl
@@ -55,7 +55,7 @@
 }
 
 // CHECK-LABEL: @test_frexp_exp_f16
-// CHECK: call i32 @llvm.amdgcn.frexp.exp.f16
+// CHECK: call i16 @llvm.amdgcn.frexp.exp.i16.f16
 void test_frexp_exp_f16(global short* out, half a)
 {
   *out = __builtin_amdgcn_frexp_exph(a);
Index: lib/CodeGen/CGBuiltin.cpp
===
--- lib/CodeGen/CGBuiltin.cpp
+++ lib/CodeGen/CGBuiltin.cpp
@@ -8250,9 +8250,18 @@
   case AMDGPU::BI__builtin_amdgcn_frexp_manth:
 return emitUnaryBuiltin(*this, E, Intrinsic::amdgcn_frexp_mant);
   case

[PATCH] D26476: [AMDGPU] Add support for f16 builtin functions for VI+

2016-11-12 Thread Konstantin Zhuravlyov via cfe-commits 
This revision was automatically updated to reflect the committed changes.
Closed by commit rL286741: [AMDGPU] Add f16 builtin functions (VI+) (authored 
by kzhuravl).

Changed prior to commit:
  https://reviews.llvm.org/D26476?vs=77654=77732#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D26476

Files:
  cfe/trunk/include/clang/Basic/BuiltinsAMDGPU.def
  cfe/trunk/lib/CodeGen/CGBuiltin.cpp
  cfe/trunk/test/CodeGenOpenCL/builtins-amdgcn-error.cl
  cfe/trunk/test/CodeGenOpenCL/builtins-amdgcn-vi.cl
  cfe/trunk/test/SemaOpenCL/builtins-amdgcn-error-f16.cl
  cfe/trunk/test/SemaOpenCL/builtins-amdgcn-error.cl

Index: cfe/trunk/include/clang/Basic/BuiltinsAMDGPU.def
===
--- cfe/trunk/include/clang/Basic/BuiltinsAMDGPU.def
+++ cfe/trunk/include/clang/Basic/BuiltinsAMDGPU.def
@@ -84,6 +84,16 @@
 // VI+ only builtins.
 //===--===//
 
+TARGET_BUILTIN(__builtin_amdgcn_div_fixuph, "", "nc", "16-bit-insts")
+TARGET_BUILTIN(__builtin_amdgcn_rcph, "hh", "nc", "16-bit-insts")
+TARGET_BUILTIN(__builtin_amdgcn_rsqh, "hh", "nc", "16-bit-insts")
+TARGET_BUILTIN(__builtin_amdgcn_sinh, "hh", "nc", "16-bit-insts")
+TARGET_BUILTIN(__builtin_amdgcn_cosh, "hh", "nc", "16-bit-insts")
+TARGET_BUILTIN(__builtin_amdgcn_ldexph, "hhi", "nc", "16-bit-insts")
+TARGET_BUILTIN(__builtin_amdgcn_frexp_manth, "hh", "nc", "16-bit-insts")
+TARGET_BUILTIN(__builtin_amdgcn_frexp_exph, "ih", "nc", "16-bit-insts")
+TARGET_BUILTIN(__builtin_amdgcn_fracth, "hh", "nc", "16-bit-insts")
+TARGET_BUILTIN(__builtin_amdgcn_classh, "bhi", "nc", "16-bit-insts")
 TARGET_BUILTIN(__builtin_amdgcn_s_memrealtime, "LUi", "n", "s-memrealtime")
 
 //===--===//
Index: cfe/trunk/test/CodeGenOpenCL/builtins-amdgcn-vi.cl
===
--- cfe/trunk/test/CodeGenOpenCL/builtins-amdgcn-vi.cl
+++ cfe/trunk/test/CodeGenOpenCL/builtins-amdgcn-vi.cl
@@ -1,8 +1,79 @@
 // REQUIRES: amdgpu-registered-target
 // RUN: %clang_cc1 -triple amdgcn-unknown-unknown -target-cpu tonga -S -emit-llvm -o - %s | FileCheck %s
 
+#pragma OPENCL EXTENSION cl_khr_fp16 : enable
+
 typedef unsigned long ulong;
 
+// CHECK-LABEL: @test_div_fixup_f16
+// CHECK: call half @llvm.amdgcn.div.fixup.f16
+void test_div_fixup_f16(global half* out, half a, half b, half c)
+{
+  *out = __builtin_amdgcn_div_fixuph(a, b, c);
+}
+
+// CHECK-LABEL: @test_rcp_f16
+// CHECK: call half @llvm.amdgcn.rcp.f16
+void test_rcp_f16(global half* out, half a)
+{
+  *out = __builtin_amdgcn_rcph(a);
+}
+
+// CHECK-LABEL: @test_rsq_f16
+// CHECK: call half @llvm.amdgcn.rsq.f16
+void test_rsq_f16(global half* out, half a)
+{
+  *out = __builtin_amdgcn_rsqh(a);
+}
+
+// CHECK-LABEL: @test_sin_f16
+// CHECK: call half @llvm.amdgcn.sin.f16
+void test_sin_f16(global half* out, half a)
+{
+  *out = __builtin_amdgcn_sinh(a);
+}
+
+// CHECK-LABEL: @test_cos_f16
+// CHECK: call half @llvm.amdgcn.cos.f16
+void test_cos_f16(global half* out, half a)
+{
+  *out = __builtin_amdgcn_cosh(a);
+}
+
+// CHECK-LABEL: @test_ldexp_f16
+// CHECK: call half @llvm.amdgcn.ldexp.f16
+void test_ldexp_f16(global half* out, half a, int b)
+{
+  *out = __builtin_amdgcn_ldexph(a, b);
+}
+
+// CHECK-LABEL: @test_frexp_mant_f16
+// CHECK: call half @llvm.amdgcn.frexp.mant.f16
+void test_frexp_mant_f16(global half* out, half a)
+{
+  *out = __builtin_amdgcn_frexp_manth(a);
+}
+
+// CHECK-LABEL: @test_frexp_exp_f16
+// CHECK: call i32 @llvm.amdgcn.frexp.exp.f16
+void test_frexp_exp_f16(global short* out, half a)
+{
+  *out = __builtin_amdgcn_frexp_exph(a);
+}
+
+// CHECK-LABEL: @test_fract_f16
+// CHECK: call half @llvm.amdgcn.fract.f16
+void test_fract_f16(global half* out, half a)
+{
+  *out = __builtin_amdgcn_fracth(a);
+}
+
+// CHECK-LABEL: @test_class_f16
+// CHECK: call i1 @llvm.amdgcn.class.f16
+void test_class_f16(global half* out, half a, int b)
+{
+  *out = __builtin_amdgcn_classh(a, b);
+}
 
 // CHECK-LABEL: @test_s_memrealtime
 // CHECK: call i64 @llvm.amdgcn.s.memrealtime()
Index: cfe/trunk/test/CodeGenOpenCL/builtins-amdgcn-error.cl
===
--- cfe/trunk/test/CodeGenOpenCL/builtins-amdgcn-error.cl
+++ cfe/trunk/test/CodeGenOpenCL/builtins-amdgcn-error.cl
@@ -1,64 +0,0 @@
-// REQUIRES: amdgpu-registered-target
-// RUN: %clang_cc1 -triple amdgcn-unknown-amdhsa -target-cpu tahiti -verify -S -o - %s
-
-// FIXME: We only get one error if the functions are the other order in the
-// file.
-
-#pragma OPENCL EXTENSION cl_khr_fp64 : enable
-typedef unsigned long ulong;
-typedef unsigned int uint;
-
-ulong test_s_memrealtime()
-{
-  return __builtin_amdgcn_s_memrealtime(); // expected-error {{'__builtin_amdgcn_s_memrealtime' needs target feature s-memrealtime}}
-}
-
-void test_s_sleep(int x)
-{
-  __builtin_amdgcn_s_sleep(x); // expected-error

r286741 - [AMDGPU] Add f16 builtin functions (VI+)

2016-11-12 Thread Konstantin Zhuravlyov via cfe-commits 
Author: kzhuravl
Date: Sat Nov 12 20:37:05 2016
New Revision: 286741

URL: http://llvm.org/viewvc/llvm-project?rev=286741=rev
Log:
[AMDGPU] Add f16 builtin functions (VI+)

Differential Revision: https://reviews.llvm.org/D26476

Added:
cfe/trunk/test/SemaOpenCL/builtins-amdgcn-error-f16.cl
cfe/trunk/test/SemaOpenCL/builtins-amdgcn-error.cl
Removed:
cfe/trunk/test/CodeGenOpenCL/builtins-amdgcn-error.cl
Modified:
cfe/trunk/include/clang/Basic/BuiltinsAMDGPU.def
cfe/trunk/lib/CodeGen/CGBuiltin.cpp
cfe/trunk/test/CodeGenOpenCL/builtins-amdgcn-vi.cl

Modified: cfe/trunk/include/clang/Basic/BuiltinsAMDGPU.def
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/include/clang/Basic/BuiltinsAMDGPU.def?rev=286741=286740=286741=diff
==
--- cfe/trunk/include/clang/Basic/BuiltinsAMDGPU.def (original)
+++ cfe/trunk/include/clang/Basic/BuiltinsAMDGPU.def Sat Nov 12 20:37:05 2016
@@ -84,6 +84,16 @@ BUILTIN(__builtin_amdgcn_ds_swizzle, "ii
 // VI+ only builtins.
 
//===--===//
 
+TARGET_BUILTIN(__builtin_amdgcn_div_fixuph, "", "nc", "16-bit-insts")
+TARGET_BUILTIN(__builtin_amdgcn_rcph, "hh", "nc", "16-bit-insts")
+TARGET_BUILTIN(__builtin_amdgcn_rsqh, "hh", "nc", "16-bit-insts")
+TARGET_BUILTIN(__builtin_amdgcn_sinh, "hh", "nc", "16-bit-insts")
+TARGET_BUILTIN(__builtin_amdgcn_cosh, "hh", "nc", "16-bit-insts")
+TARGET_BUILTIN(__builtin_amdgcn_ldexph, "hhi", "nc", "16-bit-insts")
+TARGET_BUILTIN(__builtin_amdgcn_frexp_manth, "hh", "nc", "16-bit-insts")
+TARGET_BUILTIN(__builtin_amdgcn_frexp_exph, "ih", "nc", "16-bit-insts")
+TARGET_BUILTIN(__builtin_amdgcn_fracth, "hh", "nc", "16-bit-insts")
+TARGET_BUILTIN(__builtin_amdgcn_classh, "bhi", "nc", "16-bit-insts")
 TARGET_BUILTIN(__builtin_amdgcn_s_memrealtime, "LUi", "n", "s-memrealtime")
 
 
//===--===//

Modified: cfe/trunk/lib/CodeGen/CGBuiltin.cpp
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/CodeGen/CGBuiltin.cpp?rev=286741=286740=286741=diff
==
--- cfe/trunk/lib/CodeGen/CGBuiltin.cpp (original)
+++ cfe/trunk/lib/CodeGen/CGBuiltin.cpp Sat Nov 12 20:37:05 2016
@@ -8190,38 +8190,45 @@ Value *CodeGenFunction::EmitAMDGPUBuilti
 return emitBinaryBuiltin(*this, E, Intrinsic::amdgcn_ds_swizzle);
   case AMDGPU::BI__builtin_amdgcn_div_fixup:
   case AMDGPU::BI__builtin_amdgcn_div_fixupf:
+  case AMDGPU::BI__builtin_amdgcn_div_fixuph:
 return emitTernaryBuiltin(*this, E, Intrinsic::amdgcn_div_fixup);
   case AMDGPU::BI__builtin_amdgcn_trig_preop:
   case AMDGPU::BI__builtin_amdgcn_trig_preopf:
 return emitFPIntBuiltin(*this, E, Intrinsic::amdgcn_trig_preop);
   case AMDGPU::BI__builtin_amdgcn_rcp:
   case AMDGPU::BI__builtin_amdgcn_rcpf:
+  case AMDGPU::BI__builtin_amdgcn_rcph:
 return emitUnaryBuiltin(*this, E, Intrinsic::amdgcn_rcp);
   case AMDGPU::BI__builtin_amdgcn_rsq:
   case AMDGPU::BI__builtin_amdgcn_rsqf:
+  case AMDGPU::BI__builtin_amdgcn_rsqh:
 return emitUnaryBuiltin(*this, E, Intrinsic::amdgcn_rsq);
   case AMDGPU::BI__builtin_amdgcn_rsq_clamp:
   case AMDGPU::BI__builtin_amdgcn_rsq_clampf:
 return emitUnaryBuiltin(*this, E, Intrinsic::amdgcn_rsq_clamp);
   case AMDGPU::BI__builtin_amdgcn_sinf:
+  case AMDGPU::BI__builtin_amdgcn_sinh:
 return emitUnaryBuiltin(*this, E, Intrinsic::amdgcn_sin);
   case AMDGPU::BI__builtin_amdgcn_cosf:
+  case AMDGPU::BI__builtin_amdgcn_cosh:
 return emitUnaryBuiltin(*this, E, Intrinsic::amdgcn_cos);
   case AMDGPU::BI__builtin_amdgcn_log_clampf:
 return emitUnaryBuiltin(*this, E, Intrinsic::amdgcn_log_clamp);
   case AMDGPU::BI__builtin_amdgcn_ldexp:
   case AMDGPU::BI__builtin_amdgcn_ldexpf:
+  case AMDGPU::BI__builtin_amdgcn_ldexph:
 return emitFPIntBuiltin(*this, E, Intrinsic::amdgcn_ldexp);
   case AMDGPU::BI__builtin_amdgcn_frexp_mant:
-  case AMDGPU::BI__builtin_amdgcn_frexp_mantf: {
+  case AMDGPU::BI__builtin_amdgcn_frexp_mantf:
+  case AMDGPU::BI__builtin_amdgcn_frexp_manth:
 return emitUnaryBuiltin(*this, E, Intrinsic::amdgcn_frexp_mant);
-  }
   case AMDGPU::BI__builtin_amdgcn_frexp_exp:
-  case AMDGPU::BI__builtin_amdgcn_frexp_expf: {
+  case AMDGPU::BI__builtin_amdgcn_frexp_expf:
+  case AMDGPU::BI__builtin_amdgcn_frexp_exph:
 return emitUnaryBuiltin(*this, E, Intrinsic::amdgcn_frexp_exp);
-  }
   case AMDGPU::BI__builtin_amdgcn_fract:
   case AMDGPU::BI__builtin_amdgcn_fractf:
+  case AMDGPU::BI__builtin_amdgcn_fracth:
 return emitUnaryBuiltin(*this, E, Intrinsic::amdgcn_fract);
   case AMDGPU::BI__builtin_amdgcn_lerp:
 return emitTernaryBuiltin(*this, E, Intrinsic::amdgcn_lerp);
@@ -8235,6 +8242,7 @@ Value *CodeGenFunction::EmitAMDGPUBuilti
 return emitTernaryBuiltin(*this, E, Intrinsic::amdgcn_fcmp);
   case

[PATCH] D26476: [AMDGPU] Add support for f16 builtin functions for VI+

2016-11-11 Thread Konstantin Zhuravlyov via cfe-commits 
kzhuravl updated this revision to Diff 77654.
kzhuravl added a comment.

Leave the return type of `frexp_exph` unchanged


https://reviews.llvm.org/D26476

Files:
  include/clang/Basic/BuiltinsAMDGPU.def
  lib/CodeGen/CGBuiltin.cpp
  test/CodeGenOpenCL/builtins-amdgcn-error.cl
  test/CodeGenOpenCL/builtins-amdgcn-vi.cl
  test/SemaOpenCL/builtins-amdgcn-error-f16.cl
  test/SemaOpenCL/builtins-amdgcn-error.cl

Index: test/SemaOpenCL/builtins-amdgcn-error.cl
===
--- /dev/null
+++ test/SemaOpenCL/builtins-amdgcn-error.cl
@@ -0,0 +1,64 @@
+// REQUIRES: amdgpu-registered-target
+// RUN: %clang_cc1 -triple amdgcn-- -target-cpu tahiti -verify -S -o - %s
+
+// FIXME: We only get one error if the functions are the other order in the
+// file.
+
+#pragma OPENCL EXTENSION cl_khr_fp64 : enable
+typedef unsigned long ulong;
+typedef unsigned int uint;
+
+ulong test_s_memrealtime()
+{
+  return __builtin_amdgcn_s_memrealtime(); // expected-error {{'__builtin_amdgcn_s_memrealtime' needs target feature s-memrealtime}}
+}
+
+void test_s_sleep(int x)
+{
+  __builtin_amdgcn_s_sleep(x); // expected-error {{argument to '__builtin_amdgcn_s_sleep' must be a constant integer}}
+}
+
+void test_s_incperflevel(int x)
+{
+  __builtin_amdgcn_s_incperflevel(x); // expected-error {{argument to '__builtin_amdgcn_s_incperflevel' must be a constant integer}}
+}
+
+void test_s_decperflevel(int x)
+{
+  __builtin_amdgcn_s_decperflevel(x); // expected-error {{argument to '__builtin_amdgcn_s_decperflevel' must be a constant integer}}
+}
+
+void test_sicmp_i32(global ulong* out, int a, int b, uint c)
+{
+  *out = __builtin_amdgcn_sicmp(a, b, c); // expected-error {{argument to '__builtin_amdgcn_sicmp' must be a constant integer}}
+}
+
+void test_uicmp_i32(global ulong* out, uint a, uint b, uint c)
+{
+  *out = __builtin_amdgcn_uicmp(a, b, c); // expected-error {{argument to '__builtin_amdgcn_uicmp' must be a constant integer}}
+}
+
+void test_sicmp_i64(global ulong* out, long a, long b, uint c)
+{
+  *out = __builtin_amdgcn_sicmpl(a, b, c); // expected-error {{argument to '__builtin_amdgcn_sicmpl' must be a constant integer}}
+}
+
+void test_uicmp_i64(global ulong* out, ulong a, ulong b, uint c)
+{
+  *out = __builtin_amdgcn_uicmpl(a, b, c); // expected-error {{argument to '__builtin_amdgcn_uicmpl' must be a constant integer}}
+}
+
+void test_fcmp_f32(global ulong* out, float a, float b, uint c)
+{
+  *out = __builtin_amdgcn_fcmpf(a, b, c); // expected-error {{argument to '__builtin_amdgcn_fcmpf' must be a constant integer}}
+}
+
+void test_fcmp_f64(global ulong* out, double a, double b, uint c)
+{
+  *out = __builtin_amdgcn_fcmp(a, b, c); // expected-error {{argument to '__builtin_amdgcn_fcmp' must be a constant integer}}
+}
+
+void test_ds_swizzle(global int* out, int a, int b)
+{
+  *out = __builtin_amdgcn_ds_swizzle(a, b); // expected-error {{argument to '__builtin_amdgcn_ds_swizzle' must be a constant integer}}
+}
Index: test/SemaOpenCL/builtins-amdgcn-error-f16.cl
===
--- /dev/null
+++ test/SemaOpenCL/builtins-amdgcn-error-f16.cl
@@ -0,0 +1,18 @@
+// REQUIRES: amdgpu-registered-target
+// RUN: %clang_cc1 -triple amdgcn-- -target-cpu tahiti -verify -S -o - %s
+
+#pragma OPENCL EXTENSION cl_khr_fp16 : enable
+
+void test_f16(global half *out, half a, half b, half c)
+{
+  *out = __builtin_amdgcn_div_fixuph(a, b, c); // expected-error {{'__builtin_amdgcn_div_fixuph' needs target feature 16-bit-insts}}
+  *out = __builtin_amdgcn_rcph(a); // expected-error {{'__builtin_amdgcn_rcph' needs target feature 16-bit-insts}}
+  *out = __builtin_amdgcn_rsqh(a); // expected-error {{'__builtin_amdgcn_rsqh' needs target feature 16-bit-insts}}
+  *out = __builtin_amdgcn_sinh(a); // expected-error {{'__builtin_amdgcn_sinh' needs target feature 16-bit-insts}}
+  *out = __builtin_amdgcn_cosh(a); // expected-error {{'__builtin_amdgcn_cosh' needs target feature 16-bit-insts}}
+  *out = __builtin_amdgcn_ldexph(a, b); // expected-error {{'__builtin_amdgcn_ldexph' needs target feature 16-bit-insts}}
+  *out = __builtin_amdgcn_frexp_manth(a); // expected-error {{'__builtin_amdgcn_frexp_manth' needs target feature 16-bit-insts}}
+  *out = __builtin_amdgcn_frexp_exph(a); // expected-error {{'__builtin_amdgcn_frexp_exph' needs target feature 16-bit-insts}}
+  *out = __builtin_amdgcn_fracth(a); // expected-error {{'__builtin_amdgcn_fracth' needs target feature 16-bit-insts}}
+  *out = __builtin_amdgcn_classh(a, b); // expected-error {{'__builtin_amdgcn_classh' needs target feature 16-bit-insts}}
+}
Index: test/CodeGenOpenCL/builtins-amdgcn-vi.cl
===
--- test/CodeGenOpenCL/builtins-amdgcn-vi.cl
+++ test/CodeGenOpenCL/builtins-amdgcn-vi.cl
@@ -1,8 +1,79 @@
 // REQUIRES: amdgpu-registered-target
 // RUN: %clang_cc1 -triple amdgcn-unknown-unknown -target-cpu tonga -S -emit-llvm -o -

[PATCH] D26476: [AMDGPU] Add support for f16 builtin functions for VI+

2016-11-11 Thread Konstantin Zhuravlyov via cfe-commits 
kzhuravl updated this revision to Diff 77634.
kzhuravl added a comment.

Also update run line to exclude `amdhsa` from another error file.


https://reviews.llvm.org/D26476

Files:
  include/clang/Basic/BuiltinsAMDGPU.def
  lib/CodeGen/CGBuiltin.cpp
  test/CodeGenOpenCL/builtins-amdgcn-error.cl
  test/CodeGenOpenCL/builtins-amdgcn-vi.cl
  test/CodeGenOpenCL/builtins-amdgcn.cl
  test/SemaOpenCL/builtins-amdgcn-error-f16.cl
  test/SemaOpenCL/builtins-amdgcn-error.cl

Index: test/SemaOpenCL/builtins-amdgcn-error.cl
===
--- /dev/null
+++ test/SemaOpenCL/builtins-amdgcn-error.cl
@@ -0,0 +1,64 @@
+// REQUIRES: amdgpu-registered-target
+// RUN: %clang_cc1 -triple amdgcn-- -target-cpu tahiti -verify -S -o - %s
+
+// FIXME: We only get one error if the functions are the other order in the
+// file.
+
+#pragma OPENCL EXTENSION cl_khr_fp64 : enable
+typedef unsigned long ulong;
+typedef unsigned int uint;
+
+ulong test_s_memrealtime()
+{
+  return __builtin_amdgcn_s_memrealtime(); // expected-error {{'__builtin_amdgcn_s_memrealtime' needs target feature s-memrealtime}}
+}
+
+void test_s_sleep(int x)
+{
+  __builtin_amdgcn_s_sleep(x); // expected-error {{argument to '__builtin_amdgcn_s_sleep' must be a constant integer}}
+}
+
+void test_s_incperflevel(int x)
+{
+  __builtin_amdgcn_s_incperflevel(x); // expected-error {{argument to '__builtin_amdgcn_s_incperflevel' must be a constant integer}}
+}
+
+void test_s_decperflevel(int x)
+{
+  __builtin_amdgcn_s_decperflevel(x); // expected-error {{argument to '__builtin_amdgcn_s_decperflevel' must be a constant integer}}
+}
+
+void test_sicmp_i32(global ulong* out, int a, int b, uint c)
+{
+  *out = __builtin_amdgcn_sicmp(a, b, c); // expected-error {{argument to '__builtin_amdgcn_sicmp' must be a constant integer}}
+}
+
+void test_uicmp_i32(global ulong* out, uint a, uint b, uint c)
+{
+  *out = __builtin_amdgcn_uicmp(a, b, c); // expected-error {{argument to '__builtin_amdgcn_uicmp' must be a constant integer}}
+}
+
+void test_sicmp_i64(global ulong* out, long a, long b, uint c)
+{
+  *out = __builtin_amdgcn_sicmpl(a, b, c); // expected-error {{argument to '__builtin_amdgcn_sicmpl' must be a constant integer}}
+}
+
+void test_uicmp_i64(global ulong* out, ulong a, ulong b, uint c)
+{
+  *out = __builtin_amdgcn_uicmpl(a, b, c); // expected-error {{argument to '__builtin_amdgcn_uicmpl' must be a constant integer}}
+}
+
+void test_fcmp_f32(global ulong* out, float a, float b, uint c)
+{
+  *out = __builtin_amdgcn_fcmpf(a, b, c); // expected-error {{argument to '__builtin_amdgcn_fcmpf' must be a constant integer}}
+}
+
+void test_fcmp_f64(global ulong* out, double a, double b, uint c)
+{
+  *out = __builtin_amdgcn_fcmp(a, b, c); // expected-error {{argument to '__builtin_amdgcn_fcmp' must be a constant integer}}
+}
+
+void test_ds_swizzle(global int* out, int a, int b)
+{
+  *out = __builtin_amdgcn_ds_swizzle(a, b); // expected-error {{argument to '__builtin_amdgcn_ds_swizzle' must be a constant integer}}
+}
Index: test/SemaOpenCL/builtins-amdgcn-error-f16.cl
===
--- /dev/null
+++ test/SemaOpenCL/builtins-amdgcn-error-f16.cl
@@ -0,0 +1,18 @@
+// REQUIRES: amdgpu-registered-target
+// RUN: %clang_cc1 -triple amdgcn-- -target-cpu tahiti -verify -S -o - %s
+
+#pragma OPENCL EXTENSION cl_khr_fp16 : enable
+
+void test_f16(global half *out, half a, half b, half c)
+{
+  *out = __builtin_amdgcn_div_fixuph(a, b, c); // expected-error {{'__builtin_amdgcn_div_fixuph' needs target feature 16-bit-insts}}
+  *out = __builtin_amdgcn_rcph(a); // expected-error {{'__builtin_amdgcn_rcph' needs target feature 16-bit-insts}}
+  *out = __builtin_amdgcn_rsqh(a); // expected-error {{'__builtin_amdgcn_rsqh' needs target feature 16-bit-insts}}
+  *out = __builtin_amdgcn_sinh(a); // expected-error {{'__builtin_amdgcn_sinh' needs target feature 16-bit-insts}}
+  *out = __builtin_amdgcn_cosh(a); // expected-error {{'__builtin_amdgcn_cosh' needs target feature 16-bit-insts}}
+  *out = __builtin_amdgcn_ldexph(a, b); // expected-error {{'__builtin_amdgcn_ldexph' needs target feature 16-bit-insts}}
+  *out = __builtin_amdgcn_frexp_manth(a); // expected-error {{'__builtin_amdgcn_frexp_manth' needs target feature 16-bit-insts}}
+  *out = __builtin_amdgcn_frexp_exph(a); // expected-error {{'__builtin_amdgcn_frexp_exph' needs target feature 16-bit-insts}}
+  *out = __builtin_amdgcn_fracth(a); // expected-error {{'__builtin_amdgcn_fracth' needs target feature 16-bit-insts}}
+  *out = __builtin_amdgcn_classh(a, b); // expected-error {{'__builtin_amdgcn_classh' needs target feature 16-bit-insts}}
+}
Index: test/CodeGenOpenCL/builtins-amdgcn.cl
===
--- test/CodeGenOpenCL/builtins-amdgcn.cl
+++ test/CodeGenOpenCL/builtins-amdgcn.cl
@@ -166,14 +166,14 @@
 }
 
 // CHECK-LABEL: @test_frexp_exp_f32
-// CHECK: call i32

[PATCH] D26476: [AMDGPU] Add support for f16 builtin functions for VI+

2016-11-11 Thread Konstantin Zhuravlyov via cfe-commits 
kzhuravl updated this revision to Diff 77633.
kzhuravl marked 4 inline comments as done.
kzhuravl added a comment.

Address review feedback: put tests in the same file, update run line, move 
error tests to SemaOpenCL directory


https://reviews.llvm.org/D26476

Files:
  include/clang/Basic/BuiltinsAMDGPU.def
  lib/CodeGen/CGBuiltin.cpp
  test/CodeGenOpenCL/builtins-amdgcn-error.cl
  test/CodeGenOpenCL/builtins-amdgcn-vi.cl
  test/CodeGenOpenCL/builtins-amdgcn.cl
  test/SemaOpenCL/builtins-amdgcn-error-f16.cl
  test/SemaOpenCL/builtins-amdgcn-error.cl

Index: test/SemaOpenCL/builtins-amdgcn-error.cl
===
--- /dev/null
+++ test/SemaOpenCL/builtins-amdgcn-error.cl
@@ -0,0 +1,64 @@
+// REQUIRES: amdgpu-registered-target
+// RUN: %clang_cc1 -triple amdgcn-unknown-amdhsa -target-cpu tahiti -verify -S -o - %s
+
+// FIXME: We only get one error if the functions are the other order in the
+// file.
+
+#pragma OPENCL EXTENSION cl_khr_fp64 : enable
+typedef unsigned long ulong;
+typedef unsigned int uint;
+
+ulong test_s_memrealtime()
+{
+  return __builtin_amdgcn_s_memrealtime(); // expected-error {{'__builtin_amdgcn_s_memrealtime' needs target feature s-memrealtime}}
+}
+
+void test_s_sleep(int x)
+{
+  __builtin_amdgcn_s_sleep(x); // expected-error {{argument to '__builtin_amdgcn_s_sleep' must be a constant integer}}
+}
+
+void test_s_incperflevel(int x)
+{
+  __builtin_amdgcn_s_incperflevel(x); // expected-error {{argument to '__builtin_amdgcn_s_incperflevel' must be a constant integer}}
+}
+
+void test_s_decperflevel(int x)
+{
+  __builtin_amdgcn_s_decperflevel(x); // expected-error {{argument to '__builtin_amdgcn_s_decperflevel' must be a constant integer}}
+}
+
+void test_sicmp_i32(global ulong* out, int a, int b, uint c)
+{
+  *out = __builtin_amdgcn_sicmp(a, b, c); // expected-error {{argument to '__builtin_amdgcn_sicmp' must be a constant integer}}
+}
+
+void test_uicmp_i32(global ulong* out, uint a, uint b, uint c)
+{
+  *out = __builtin_amdgcn_uicmp(a, b, c); // expected-error {{argument to '__builtin_amdgcn_uicmp' must be a constant integer}}
+}
+
+void test_sicmp_i64(global ulong* out, long a, long b, uint c)
+{
+  *out = __builtin_amdgcn_sicmpl(a, b, c); // expected-error {{argument to '__builtin_amdgcn_sicmpl' must be a constant integer}}
+}
+
+void test_uicmp_i64(global ulong* out, ulong a, ulong b, uint c)
+{
+  *out = __builtin_amdgcn_uicmpl(a, b, c); // expected-error {{argument to '__builtin_amdgcn_uicmpl' must be a constant integer}}
+}
+
+void test_fcmp_f32(global ulong* out, float a, float b, uint c)
+{
+  *out = __builtin_amdgcn_fcmpf(a, b, c); // expected-error {{argument to '__builtin_amdgcn_fcmpf' must be a constant integer}}
+}
+
+void test_fcmp_f64(global ulong* out, double a, double b, uint c)
+{
+  *out = __builtin_amdgcn_fcmp(a, b, c); // expected-error {{argument to '__builtin_amdgcn_fcmp' must be a constant integer}}
+}
+
+void test_ds_swizzle(global int* out, int a, int b)
+{
+  *out = __builtin_amdgcn_ds_swizzle(a, b); // expected-error {{argument to '__builtin_amdgcn_ds_swizzle' must be a constant integer}}
+}
Index: test/SemaOpenCL/builtins-amdgcn-error-f16.cl
===
--- /dev/null
+++ test/SemaOpenCL/builtins-amdgcn-error-f16.cl
@@ -0,0 +1,18 @@
+// REQUIRES: amdgpu-registered-target
+// RUN: %clang_cc1 -triple amdgcn-- -target-cpu tahiti -verify -S -o - %s
+
+#pragma OPENCL EXTENSION cl_khr_fp16 : enable
+
+void test_f16(global half *out, half a, half b, half c)
+{
+  *out = __builtin_amdgcn_div_fixuph(a, b, c); // expected-error {{'__builtin_amdgcn_div_fixuph' needs target feature 16-bit-insts}}
+  *out = __builtin_amdgcn_rcph(a); // expected-error {{'__builtin_amdgcn_rcph' needs target feature 16-bit-insts}}
+  *out = __builtin_amdgcn_rsqh(a); // expected-error {{'__builtin_amdgcn_rsqh' needs target feature 16-bit-insts}}
+  *out = __builtin_amdgcn_sinh(a); // expected-error {{'__builtin_amdgcn_sinh' needs target feature 16-bit-insts}}
+  *out = __builtin_amdgcn_cosh(a); // expected-error {{'__builtin_amdgcn_cosh' needs target feature 16-bit-insts}}
+  *out = __builtin_amdgcn_ldexph(a, b); // expected-error {{'__builtin_amdgcn_ldexph' needs target feature 16-bit-insts}}
+  *out = __builtin_amdgcn_frexp_manth(a); // expected-error {{'__builtin_amdgcn_frexp_manth' needs target feature 16-bit-insts}}
+  *out = __builtin_amdgcn_frexp_exph(a); // expected-error {{'__builtin_amdgcn_frexp_exph' needs target feature 16-bit-insts}}
+  *out = __builtin_amdgcn_fracth(a); // expected-error {{'__builtin_amdgcn_fracth' needs target feature 16-bit-insts}}
+  *out = __builtin_amdgcn_classh(a, b); // expected-error {{'__builtin_amdgcn_classh' needs target feature 16-bit-insts}}
+}
Index: test/CodeGenOpenCL/builtins-amdgcn.cl
===
--- test/CodeGenOpenCL/builtins-amdgcn.cl
+++

[PATCH] D26476: [AMDGPU] Add support for f16 builtin functions for VI+

2016-11-11 Thread Konstantin Zhuravlyov via cfe-commits 
kzhuravl added inline comments.



Comment at: test/CodeGenOpenCL/builtins-amdgcn-error-f16-class.cl:1-9
+// REQUIRES: amdgpu-registered-target
+// RUN: %clang_cc1 -triple amdgcn-unknown-amdhsa -target-cpu tahiti -verify -S 
-o - %s
+
+#pragma OPENCL EXTENSION cl_khr_fp16 : enable
+
+void test_class_f16(global half* out, half a, int b)
+{

arsenm wrote:
> These tests can all be in the same file 
The problem is if I put them into the same file only the first function gives 
the error `'__builtin_amdgcn_*h' needs target feature 16-bit-insts` and I did 
not have time to investigate why, but I was planning to do it once I finish 
something else.

Would leaving them in the separate files be acceptable short-term?


https://reviews.llvm.org/D26476



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[PATCH] D26476: [AMDGPU] Add support for f16 builtin functions for VI+

2016-11-09 Thread Konstantin Zhuravlyov via cfe-commits 
kzhuravl created this revision.
kzhuravl added reviewers: tstellarAMD, arsenm.
kzhuravl added a subscriber: cfe-commits.
Herald added subscribers: tony-tye, yaxunl, nhaehnle, wdng.

https://reviews.llvm.org/D26476

Files:
  include/clang/Basic/BuiltinsAMDGPU.def
  lib/CodeGen/CGBuiltin.cpp
  test/CodeGenOpenCL/builtins-amdgcn-error-f16-class.cl
  test/CodeGenOpenCL/builtins-amdgcn-error-f16-cos.cl
  test/CodeGenOpenCL/builtins-amdgcn-error-f16-div-fixup.cl
  test/CodeGenOpenCL/builtins-amdgcn-error-f16-fract.cl
  test/CodeGenOpenCL/builtins-amdgcn-error-f16-frexp-exp.cl
  test/CodeGenOpenCL/builtins-amdgcn-error-f16-frexp-mant.cl
  test/CodeGenOpenCL/builtins-amdgcn-error-f16-ldexp.cl
  test/CodeGenOpenCL/builtins-amdgcn-error-f16-rcp.cl
  test/CodeGenOpenCL/builtins-amdgcn-error-f16-rsq.cl
  test/CodeGenOpenCL/builtins-amdgcn-error-f16-sin.cl
  test/CodeGenOpenCL/builtins-amdgcn-vi.cl
  test/CodeGenOpenCL/builtins-amdgcn.cl

Index: test/CodeGenOpenCL/builtins-amdgcn.cl
===
--- test/CodeGenOpenCL/builtins-amdgcn.cl
+++ test/CodeGenOpenCL/builtins-amdgcn.cl
@@ -166,14 +166,14 @@
 }
 
 // CHECK-LABEL: @test_frexp_exp_f32
-// CHECK: call i32 @llvm.amdgcn.frexp.exp.f32
+// CHECK: call i32 @llvm.amdgcn.frexp.exp.i32.f32
 void test_frexp_exp_f32(global int* out, float a)
 {
   *out = __builtin_amdgcn_frexp_expf(a);
 }
 
 // CHECK-LABEL: @test_frexp_exp_f64
-// CHECK: call i32 @llvm.amdgcn.frexp.exp.f64
+// CHECK: call i32 @llvm.amdgcn.frexp.exp.i32.f64
 void test_frexp_exp_f64(global int* out, double a)
 {
   *out = __builtin_amdgcn_frexp_exp(a);
Index: test/CodeGenOpenCL/builtins-amdgcn-vi.cl
===
--- test/CodeGenOpenCL/builtins-amdgcn-vi.cl
+++ test/CodeGenOpenCL/builtins-amdgcn-vi.cl
@@ -1,8 +1,79 @@
 // REQUIRES: amdgpu-registered-target
 // RUN: %clang_cc1 -triple amdgcn-unknown-unknown -target-cpu tonga -S -emit-llvm -o - %s | FileCheck %s
 
+#pragma OPENCL EXTENSION cl_khr_fp16 : enable
+
 typedef unsigned long ulong;
 
+// CHECK-LABEL: @test_div_fixup_f16
+// CHECK: call half @llvm.amdgcn.div.fixup.f16
+void test_div_fixup_f16(global half* out, half a, half b, half c)
+{
+  *out = __builtin_amdgcn_div_fixuph(a, b, c);
+}
+
+// CHECK-LABEL: @test_rcp_f16
+// CHECK: call half @llvm.amdgcn.rcp.f16
+void test_rcp_f16(global half* out, half a)
+{
+  *out = __builtin_amdgcn_rcph(a);
+}
+
+// CHECK-LABEL: @test_rsq_f16
+// CHECK: call half @llvm.amdgcn.rsq.f16
+void test_rsq_f16(global half* out, half a)
+{
+  *out = __builtin_amdgcn_rsqh(a);
+}
+
+// CHECK-LABEL: @test_sin_f16
+// CHECK: call half @llvm.amdgcn.sin.f16
+void test_sin_f16(global half* out, half a)
+{
+  *out = __builtin_amdgcn_sinh(a);
+}
+
+// CHECK-LABEL: @test_cos_f16
+// CHECK: call half @llvm.amdgcn.cos.f16
+void test_cos_f16(global half* out, half a)
+{
+  *out = __builtin_amdgcn_cosh(a);
+}
+
+// CHECK-LABEL: @test_ldexp_f16
+// CHECK: call half @llvm.amdgcn.ldexp.f16
+void test_ldexp_f16(global half* out, half a, int b)
+{
+  *out = __builtin_amdgcn_ldexph(a, b);
+}
+
+// CHECK-LABEL: @test_frexp_mant_f16
+// CHECK: call half @llvm.amdgcn.frexp.mant.f16
+void test_frexp_mant_f16(global half* out, half a)
+{
+  *out = __builtin_amdgcn_frexp_manth(a);
+}
+
+// CHECK-LABEL: @test_frexp_exp_f16
+// CHECK: call i16 @llvm.amdgcn.frexp.exp.i16.f16
+void test_frexp_exp_f16(global short* out, half a)
+{
+  *out = __builtin_amdgcn_frexp_exph(a);
+}
+
+// CHECK-LABEL: @test_fract_f16
+// CHECK: call half @llvm.amdgcn.fract.f16
+void test_fract_f16(global half* out, half a)
+{
+  *out = __builtin_amdgcn_fracth(a);
+}
+
+// CHECK-LABEL: @test_class_f16
+// CHECK: call i1 @llvm.amdgcn.class.f16
+void test_class_f16(global half* out, half a, int b)
+{
+  *out = __builtin_amdgcn_classh(a, b);
+}
 
 // CHECK-LABEL: @test_s_memrealtime
 // CHECK: call i64 @llvm.amdgcn.s.memrealtime()
Index: test/CodeGenOpenCL/builtins-amdgcn-error-f16-sin.cl
===
--- /dev/null
+++ test/CodeGenOpenCL/builtins-amdgcn-error-f16-sin.cl
@@ -0,0 +1,9 @@
+// REQUIRES: amdgpu-registered-target
+// RUN: %clang_cc1 -triple amdgcn-unknown-amdhsa -target-cpu tahiti -verify -S -o - %s
+
+#pragma OPENCL EXTENSION cl_khr_fp16 : enable
+
+void test_sin_f16(global half* out, half a)
+{
+  *out = __builtin_amdgcn_sinh(a); // expected-error {{'__builtin_amdgcn_sinh' needs target feature 16-bit-insts}}
+}
Index: test/CodeGenOpenCL/builtins-amdgcn-error-f16-rsq.cl
===
--- /dev/null
+++ test/CodeGenOpenCL/builtins-amdgcn-error-f16-rsq.cl
@@ -0,0 +1,9 @@
+// REQUIRES: amdgpu-registered-target
+// RUN: %clang_cc1 -triple amdgcn-unknown-amdhsa -target-cpu tahiti -verify -S -o - %s
+
+#pragma OPENCL EXTENSION cl_khr_fp16 : enable
+
+void test_rsq_f16(global half* out, half a)
+{
+  *out = __builtin_amdgcn_rsqh(a); // expected-error

r282371 - [AMDGPU] Expose flat work group size, register and wave control attributes

2016-09-25 Thread Konstantin Zhuravlyov via cfe-commits 
Author: kzhuravl
Date: Sun Sep 25 20:02:57 2016
New Revision: 282371

URL: http://llvm.org/viewvc/llvm-project?rev=282371=rev
Log:
[AMDGPU] Expose flat work group size, register and wave control attributes

__attribute__((amdgpu_flat_work_group_size(, ))) - request minimum 
and maximum flat work group size
__attribute__((amdgpu_waves_per_eu([, ]))) - request minimum and/or 
maximum waves per execution unit

Differential Revision: https://reviews.llvm.org/D24513

Added:
cfe/trunk/test/CodeGenOpenCL/amdgpu-attrs.cl
cfe/trunk/test/SemaCUDA/amdgpu-attrs.cu
cfe/trunk/test/SemaOpenCL/amdgpu-attrs.cl
Removed:
cfe/trunk/test/CodeGenOpenCL/amdgpu-num-gpr-attr.cl
cfe/trunk/test/SemaCUDA/amdgpu-num-gpr-attr.cu
cfe/trunk/test/SemaOpenCL/amdgpu-num-register-attrs.cl
Modified:
cfe/trunk/include/clang/Basic/Attr.td
cfe/trunk/include/clang/Basic/AttrDocs.td
cfe/trunk/include/clang/Basic/DiagnosticSemaKinds.td
cfe/trunk/lib/CodeGen/TargetInfo.cpp
cfe/trunk/lib/Sema/SemaDeclAttr.cpp

Modified: cfe/trunk/include/clang/Basic/Attr.td
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/include/clang/Basic/Attr.td?rev=282371=282370=282371=diff
==
--- cfe/trunk/include/clang/Basic/Attr.td (original)
+++ cfe/trunk/include/clang/Basic/Attr.td Sun Sep 25 20:02:57 2016
@@ -1050,24 +1050,37 @@ def NoMips16 : InheritableAttr, TargetSp
 //
 // FIXME: This provides a sub-optimal error message if you attempt to
 // use this in CUDA, since CUDA does not use the same terminology.
-def AMDGPUNumVGPR : InheritableAttr {
-  let Spellings = [GNU<"amdgpu_num_vgpr">];
-  let Args = [UnsignedArgument<"NumVGPR">];
-  let Documentation = [AMDGPUNumVGPRDocs];
-
-// FIXME: This should be for OpenCLKernelFunction, but is not to
+//
+// FIXME: SubjectList should be for OpenCLKernelFunction, but is not to
 // workaround needing to see kernel attribute before others to know if
 // this should be rejected on non-kernels.
-  let Subjects = SubjectList<[Function], ErrorDiag,
- "ExpectedKernelFunction">;
+
+def AMDGPUFlatWorkGroupSize : InheritableAttr {
+  let Spellings = [GNU<"amdgpu_flat_work_group_size">];
+  let Args = [UnsignedArgument<"Min">, UnsignedArgument<"Max">];
+  let Documentation = [AMDGPUFlatWorkGroupSizeDocs];
+  let Subjects = SubjectList<[Function], ErrorDiag, "ExpectedKernelFunction">;
+}
+
+def AMDGPUWavesPerEU : InheritableAttr {
+  let Spellings = [GNU<"amdgpu_waves_per_eu">];
+  let Args = [UnsignedArgument<"Min">, UnsignedArgument<"Max", 1>];
+  let Documentation = [AMDGPUWavesPerEUDocs];
+  let Subjects = SubjectList<[Function], ErrorDiag, "ExpectedKernelFunction">;
 }
 
 def AMDGPUNumSGPR : InheritableAttr {
   let Spellings = [GNU<"amdgpu_num_sgpr">];
   let Args = [UnsignedArgument<"NumSGPR">];
-  let Documentation = [AMDGPUNumSGPRDocs];
-  let Subjects = SubjectList<[Function], ErrorDiag,
-  "ExpectedKernelFunction">;
+  let Documentation = [AMDGPUNumSGPRNumVGPRDocs];
+  let Subjects = SubjectList<[Function], ErrorDiag, "ExpectedKernelFunction">;
+}
+
+def AMDGPUNumVGPR : InheritableAttr {
+  let Spellings = [GNU<"amdgpu_num_vgpr">];
+  let Args = [UnsignedArgument<"NumVGPR">];
+  let Documentation = [AMDGPUNumSGPRNumVGPRDocs];
+  let Subjects = SubjectList<[Function], ErrorDiag, "ExpectedKernelFunction">;
 }
 
 def NoSplitStack : InheritableAttr {

Modified: cfe/trunk/include/clang/Basic/AttrDocs.td
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/include/clang/Basic/AttrDocs.td?rev=282371=282370=282371=diff
==
--- cfe/trunk/include/clang/Basic/AttrDocs.td (original)
+++ cfe/trunk/include/clang/Basic/AttrDocs.td Sun Sep 25 20:02:57 2016
@@ -889,12 +889,12 @@ variable, a function or method, a functi
 enumerator, a non-static data member, or a label.
 
 .. code-block: c++
-  #include 
-
-  [[maybe_unused]] void f([[maybe_unused]] bool thing1,
-  [[maybe_unused]] bool thing2) {
-[[maybe_unused]] bool b = thing1 && thing2;
-assert(b);
+  #include 
+
+  [[maybe_unused]] void f([[maybe_unused]] bool thing1,
+  [[maybe_unused]] bool thing2) {
+[[maybe_unused]] bool b = thing1 && thing2;
+assert(b);
   }
   }];
 }
@@ -911,15 +911,15 @@ potentially-evaluated discarded-value ex
 `void`.
 
 .. code-block: c++
-  struct [[nodiscard]] error_info { /*...*/ };
-  error_info enable_missile_safety_mode();
-  
-  void launch_missiles();
-  void test_missiles() {
-enable_missile_safety_mode(); // diagnoses
-launch_missiles();
-  }
-  error_info ();
+  struct [[nodiscard]] error_info { /*...*/ };
+  error_info enable_missile_safety_mode();
+  
+  void launch_missiles();
+  void test_missiles() {
+enable_missile_safety_mode(); // diagnoses
+launch_missiles();
+  }
+  error_info ();
   void f() { foo(); } // Does not

Re: [PATCH] D24513: [AMDGPU] Expose flat work group size, register and wave control attributes

2016-09-25 Thread Konstantin Zhuravlyov via cfe-commits 
This revision was automatically updated to reflect the committed changes.
Closed by commit rL282371: [AMDGPU] Expose flat work group size, register and 
wave control attributes (authored by kzhuravl).

Changed prior to commit:
  https://reviews.llvm.org/D24513?vs=71970=72436#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D24513

Files:
  cfe/trunk/include/clang/Basic/Attr.td
  cfe/trunk/include/clang/Basic/AttrDocs.td
  cfe/trunk/include/clang/Basic/DiagnosticSemaKinds.td
  cfe/trunk/lib/CodeGen/TargetInfo.cpp
  cfe/trunk/lib/Sema/SemaDeclAttr.cpp
  cfe/trunk/test/CodeGenOpenCL/amdgpu-attrs.cl
  cfe/trunk/test/CodeGenOpenCL/amdgpu-num-gpr-attr.cl
  cfe/trunk/test/SemaCUDA/amdgpu-attrs.cu
  cfe/trunk/test/SemaCUDA/amdgpu-num-gpr-attr.cu
  cfe/trunk/test/SemaOpenCL/amdgpu-attrs.cl
  cfe/trunk/test/SemaOpenCL/amdgpu-num-register-attrs.cl

Index: cfe/trunk/include/clang/Basic/Attr.td
===
--- cfe/trunk/include/clang/Basic/Attr.td
+++ cfe/trunk/include/clang/Basic/Attr.td
@@ -1050,24 +1050,37 @@
 //
 // FIXME: This provides a sub-optimal error message if you attempt to
 // use this in CUDA, since CUDA does not use the same terminology.
-def AMDGPUNumVGPR : InheritableAttr {
-  let Spellings = [GNU<"amdgpu_num_vgpr">];
-  let Args = [UnsignedArgument<"NumVGPR">];
-  let Documentation = [AMDGPUNumVGPRDocs];
-
-// FIXME: This should be for OpenCLKernelFunction, but is not to
+//
+// FIXME: SubjectList should be for OpenCLKernelFunction, but is not to
 // workaround needing to see kernel attribute before others to know if
 // this should be rejected on non-kernels.
-  let Subjects = SubjectList<[Function], ErrorDiag,
- "ExpectedKernelFunction">;
+
+def AMDGPUFlatWorkGroupSize : InheritableAttr {
+  let Spellings = [GNU<"amdgpu_flat_work_group_size">];
+  let Args = [UnsignedArgument<"Min">, UnsignedArgument<"Max">];
+  let Documentation = [AMDGPUFlatWorkGroupSizeDocs];
+  let Subjects = SubjectList<[Function], ErrorDiag, "ExpectedKernelFunction">;
+}
+
+def AMDGPUWavesPerEU : InheritableAttr {
+  let Spellings = [GNU<"amdgpu_waves_per_eu">];
+  let Args = [UnsignedArgument<"Min">, UnsignedArgument<"Max", 1>];
+  let Documentation = [AMDGPUWavesPerEUDocs];
+  let Subjects = SubjectList<[Function], ErrorDiag, "ExpectedKernelFunction">;
 }
 
 def AMDGPUNumSGPR : InheritableAttr {
   let Spellings = [GNU<"amdgpu_num_sgpr">];
   let Args = [UnsignedArgument<"NumSGPR">];
-  let Documentation = [AMDGPUNumSGPRDocs];
-  let Subjects = SubjectList<[Function], ErrorDiag,
-  "ExpectedKernelFunction">;
+  let Documentation = [AMDGPUNumSGPRNumVGPRDocs];
+  let Subjects = SubjectList<[Function], ErrorDiag, "ExpectedKernelFunction">;
+}
+
+def AMDGPUNumVGPR : InheritableAttr {
+  let Spellings = [GNU<"amdgpu_num_vgpr">];
+  let Args = [UnsignedArgument<"NumVGPR">];
+  let Documentation = [AMDGPUNumSGPRNumVGPRDocs];
+  let Subjects = SubjectList<[Function], ErrorDiag, "ExpectedKernelFunction">;
 }
 
 def NoSplitStack : InheritableAttr {
Index: cfe/trunk/include/clang/Basic/DiagnosticSemaKinds.td
===
--- cfe/trunk/include/clang/Basic/DiagnosticSemaKinds.td
+++ cfe/trunk/include/clang/Basic/DiagnosticSemaKinds.td
@@ -2382,6 +2382,9 @@
   "'%0' parameter must have pointer%select{| to unqualified pointer}1 type; "
   "type here is %2">;
 
+def err_attribute_argument_invalid : Error<
+  "%0 attribute argument is invalid: %select{max must be 0 since min is 0|"
+  "min must not be greater than max}1">;
 def err_attribute_argument_is_zero : Error<
   "%0 attribute must be greater than 0">;
 def warn_attribute_argument_n_negative : Warning<
Index: cfe/trunk/include/clang/Basic/AttrDocs.td
===
--- cfe/trunk/include/clang/Basic/AttrDocs.td
+++ cfe/trunk/include/clang/Basic/AttrDocs.td
@@ -889,12 +889,12 @@
 enumerator, a non-static data member, or a label.
 
 .. code-block: c++
-  #include 
-
-  [[maybe_unused]] void f([[maybe_unused]] bool thing1,
-  [[maybe_unused]] bool thing2) {
-[[maybe_unused]] bool b = thing1 && thing2;
-assert(b);
+  #include 
+
+  [[maybe_unused]] void f([[maybe_unused]] bool thing1,
+  [[maybe_unused]] bool thing2) {
+[[maybe_unused]] bool b = thing1 && thing2;
+assert(b);
   }
   }];
 }
@@ -911,15 +911,15 @@
 `void`.
 
 .. code-block: c++
-  struct [[nodiscard]] error_info { /*...*/ };
-  error_info enable_missile_safety_mode();
-  
-  void launch_missiles();
-  void test_missiles() {
-enable_missile_safety_mode(); // diagnoses
-launch_missiles();
-  }
-  error_info ();
+  struct [[nodiscard]] error_info { /*...*/ };
+  error_info enable_missile_safety_mode();
+  
+  void launch_missiles();
+  void test_missiles() {
+enable_missile_safety_mode(); // diagnoses
+launch_missiles();
+  }
+

Re: [PATCH] D24513: [AMDGPU] Expose flat work group size, register and wave control attributes

2016-09-21 Thread Konstantin Zhuravlyov via cfe-commits 
kzhuravl added a comment.

Thanks for the review Aaron!

Tom, would you be able to do a final glance over?


https://reviews.llvm.org/D24513



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Re: [PATCH] D24513: [AMDGPU] Expose flat work group size, register and wave control attributes

2016-09-20 Thread Konstantin Zhuravlyov via cfe-commits 
kzhuravl added inline comments.


Comment at: lib/Sema/SemaDeclAttr.cpp:4967
@@ +4966,3 @@
+
+  D->addAttr(::new (S.Context)
+ AMDGPUFlatWorkGroupSizeAttr(Attr.getLoc(), S.Context, Min, Max,

aaron.ballman wrote:
> Is it okay to supply `0, 0` as the min, max arguments?
Yes, I mentioned `0, 0` case in the docs.


Comment at: lib/Sema/SemaDeclAttr.cpp:4997
@@ +4996,3 @@
+
+  D->addAttr(::new (S.Context)
+ AMDGPUWavesPerEUAttr(Attr.getLoc(), S.Context, Min, Max,

aaron.ballman wrote:
> Is it okay to supply `0, 0` as the min, max arguments?
Yes, I mentioned `0, 0` case in the docs.


Comment at: lib/Sema/SemaDeclAttr.cpp:6039-6043
@@ -5976,3 +6038,7 @@
   D->setInvalidDecl();
-} else if (Attr *A = D->getAttr()) {
+} else if (Attr *A = D->getAttr()) {
+  Diag(D->getLocation(), diag::err_attribute_wrong_decl_type)
+<< A << ExpectedKernelFunction;
+  D->setInvalidDecl();
+} else if (Attr *A = D->getAttr()) {
   Diag(D->getLocation(), diag::err_attribute_wrong_decl_type)

aaron.ballman wrote:
> Yes, totally fine to be a follow-up patch. I was hoping it would look 
> something like (we can bikeshed the name):
> ```
> def SomeAttr {
>   /* Blah */
> }
> 
> def SomeOtherAttr {
>   let RequiredCompanionAttributes = [SomeAttr];
> }
> ```
This seems like a good start. Thanks :)


https://reviews.llvm.org/D24513



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Re: [PATCH] D24513: [AMDGPU] Expose flat work group size, register and wave control attributes

2016-09-20 Thread Konstantin Zhuravlyov via cfe-commits 
kzhuravl updated this revision to Diff 71970.
kzhuravl added a comment.
Herald added a subscriber: kzhuravl.

Mention `0, 0` case in the docs.


https://reviews.llvm.org/D24513

Files:
  include/clang/Basic/Attr.td
  include/clang/Basic/AttrDocs.td
  include/clang/Basic/DiagnosticSemaKinds.td
  lib/CodeGen/TargetInfo.cpp
  lib/Sema/SemaDeclAttr.cpp
  test/CodeGenOpenCL/amdgpu-attrs.cl
  test/CodeGenOpenCL/amdgpu-num-gpr-attr.cl
  test/SemaCUDA/amdgpu-attrs.cu
  test/SemaCUDA/amdgpu-num-gpr-attr.cu
  test/SemaOpenCL/amdgpu-attrs.cl
  test/SemaOpenCL/amdgpu-num-register-attrs.cl

Index: test/SemaOpenCL/amdgpu-num-register-attrs.cl
===
--- test/SemaOpenCL/amdgpu-num-register-attrs.cl
+++ test/SemaOpenCL/amdgpu-num-register-attrs.cl
@@ -1,40 +0,0 @@
-// RUN: %clang_cc1 -triple r600-- -verify -fsyntax-only %s
-
-typedef __attribute__((amdgpu_num_vgpr(128))) struct FooStruct { // expected-error {{'amdgpu_num_vgpr' attribute only applies to kernel functions}}
-  int x;
-  float y;
-} FooStruct;
-
-
-__attribute__((amdgpu_num_vgpr("ABC"))) kernel void foo2() {} // expected-error {{'amdgpu_num_vgpr' attribute requires an integer constant}}
-__attribute__((amdgpu_num_sgpr("ABC"))) kernel void foo3() {} // expected-error {{'amdgpu_num_sgpr' attribute requires an integer constant}}
-
-
-__attribute__((amdgpu_num_vgpr(40))) void foo4() {} // expected-error {{'amdgpu_num_vgpr' attribute only applies to kernel functions}}
-__attribute__((amdgpu_num_sgpr(64))) void foo5() {} // expected-error {{'amdgpu_num_sgpr' attribute only applies to kernel functions}}
-
-__attribute__((amdgpu_num_vgpr(40))) kernel void foo7() {}
-__attribute__((amdgpu_num_sgpr(64))) kernel void foo8() {}
-__attribute__((amdgpu_num_vgpr(40), amdgpu_num_sgpr(64))) kernel void foo9() {}
-
-// Check 0 VGPR is accepted.
-__attribute__((amdgpu_num_vgpr(0))) kernel void foo10() {}
-
-// Check 0 SGPR is accepted.
-__attribute__((amdgpu_num_sgpr(0))) kernel void foo11() {}
-
-// Check both 0 SGPR and VGPR is accepted.
-__attribute__((amdgpu_num_vgpr(0), amdgpu_num_sgpr(0))) kernel void foo12() {}
-
-// Too large VGPR value.
-__attribute__((amdgpu_num_vgpr(4294967296))) kernel void foo13() {} // expected-error {{integer constant expression evaluates to value 4294967296 that cannot be represented in a 32-bit unsigned integer type}}
-
-__attribute__((amdgpu_num_sgpr(4294967296))) kernel void foo14() {} // expected-error {{integer constant expression evaluates to value 4294967296 that cannot be represented in a 32-bit unsigned integer type}}
-
-__attribute__((amdgpu_num_sgpr(4294967296), amdgpu_num_vgpr(4294967296))) kernel void foo15() {} // expected-error 2 {{integer constant expression evaluates to value 4294967296 that cannot be represented in a 32-bit unsigned integer type}}
-
-
-// Make sure it is accepted with kernel keyword before the attribute.
-kernel __attribute__((amdgpu_num_vgpr(40))) void foo16() {}
-
-kernel __attribute__((amdgpu_num_sgpr(40))) void foo17() {}
Index: test/SemaOpenCL/amdgpu-attrs.cl
===
--- test/SemaOpenCL/amdgpu-attrs.cl
+++ test/SemaOpenCL/amdgpu-attrs.cl
@@ -0,0 +1,66 @@
+// RUN: %clang_cc1 -triple amdgcn-- -verify -fsyntax-only %s
+
+typedef __attribute__((amdgpu_flat_work_group_size(32, 64))) struct struct_flat_work_group_size_32_64 { // expected-error {{'amdgpu_flat_work_group_size' attribute only applies to kernel functions}}
+  int x;
+  float y;
+} struct_flat_work_group_size_32_64;
+typedef __attribute__((amdgpu_waves_per_eu(2))) struct struct_waves_per_eu_2 { // expected-error {{'amdgpu_waves_per_eu' attribute only applies to kernel functions}}
+  int x;
+  float y;
+} struct_waves_per_eu_2;
+typedef __attribute__((amdgpu_waves_per_eu(2, 4))) struct struct_waves_per_eu_2_4 { // expected-error {{'amdgpu_waves_per_eu' attribute only applies to kernel functions}}
+  int x;
+  float y;
+} struct_waves_per_eu_2_4;
+typedef __attribute__((amdgpu_num_sgpr(32))) struct struct_num_sgpr_32 { // expected-error {{'amdgpu_num_sgpr' attribute only applies to kernel functions}}
+  int x;
+  float y;
+} struct_num_sgpr_32;
+typedef __attribute__((amdgpu_num_vgpr(64))) struct struct_num_vgpr_64 { // expected-error {{'amdgpu_num_vgpr' attribute only applies to kernel functions}}
+  int x;
+  float y;
+} struct_num_vgpr_64;
+
+__attribute__((amdgpu_flat_work_group_size(32, 64))) void func_flat_work_group_size_32_64() {} // expected-error {{'amdgpu_flat_work_group_size' attribute only applies to kernel functions}}
+__attribute__((amdgpu_waves_per_eu(2))) void func_waves_per_eu_2() {} // expected-error {{'amdgpu_waves_per_eu' attribute only applies to kernel functions}}
+__attribute__((amdgpu_waves_per_eu(2, 4))) void func_waves_per_eu_2_4() {} // expected-error {{'amdgpu_waves_per_eu' attribute only applies to kernel functions}}
+__attribute__((amdgpu_num_sgpr(32))) void func_num_sgpr_32() {} // expected-error

Re: [PATCH] D24513: [AMDGPU] Expose flat work group size, register and wave control attributes

2016-09-14 Thread Konstantin Zhuravlyov via cfe-commits 
kzhuravl added inline comments.


Comment at: include/clang/Basic/Attr.td:1067
@@ +1066,3 @@
+  let Spellings = [GNU<"amdgpu_waves_per_eu">];
+  let Args = [UnsignedArgument<"Min">, VariadicUnsignedArgument<"Max">];
+  let Documentation = [AMDGPUWavesPerEUDocs];

aaron.ballman wrote:
> Looking at the documentation, are you sure this should be a 
> `VariadicUnsignedArgument`? It seems like this should be an 
> `UnsignedArgument` with the optional bit set. Or can you pass multiple Max 
> values?
You are right. Switched to UnsignedArgument since only one Max is allowed. 
Thanks.


Comment at: lib/Sema/SemaDeclAttr.cpp:6048
@@ -5976,2 +6047,3 @@
   D->setInvalidDecl();
-} else if (Attr *A = D->getAttr()) {
+} else if (Attr *A = D->getAttr()) {
+  Diag(D->getLocation(), diag::err_attribute_wrong_decl_type)

aaron.ballman wrote:
> This list is getting to the point where we really need to start handling this 
> in Attr.td soon. Are you planning to work on more AMDGPU attributes in the 
> near future?
I agree, and yes, few more attributes will need to be added in the near future. 
Would it be ok if I change it to start handling in Attr.td after this change, 
but before other attributes are added?


https://reviews.llvm.org/D24513



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Re: [PATCH] D24513: [AMDGPU] Expose flat work group size, register and wave control attributes

2016-09-14 Thread Konstantin Zhuravlyov via cfe-commits 
kzhuravl updated this revision to Diff 71449.
kzhuravl marked 15 inline comments as done.
kzhuravl added a comment.

Address review feedback


https://reviews.llvm.org/D24513

Files:
  include/clang/Basic/Attr.td
  include/clang/Basic/AttrDocs.td
  include/clang/Basic/DiagnosticSemaKinds.td
  lib/CodeGen/TargetInfo.cpp
  lib/Sema/SemaDeclAttr.cpp
  test/CodeGenOpenCL/amdgpu-attrs.cl
  test/CodeGenOpenCL/amdgpu-num-gpr-attr.cl
  test/SemaCUDA/amdgpu-attrs.cu
  test/SemaCUDA/amdgpu-num-gpr-attr.cu
  test/SemaOpenCL/amdgpu-attrs.cl
  test/SemaOpenCL/amdgpu-num-register-attrs.cl

Index: test/SemaOpenCL/amdgpu-num-register-attrs.cl
===
--- test/SemaOpenCL/amdgpu-num-register-attrs.cl
+++ test/SemaOpenCL/amdgpu-num-register-attrs.cl
@@ -1,40 +0,0 @@
-// RUN: %clang_cc1 -triple r600-- -verify -fsyntax-only %s
-
-typedef __attribute__((amdgpu_num_vgpr(128))) struct FooStruct { // expected-error {{'amdgpu_num_vgpr' attribute only applies to kernel functions}}
-  int x;
-  float y;
-} FooStruct;
-
-
-__attribute__((amdgpu_num_vgpr("ABC"))) kernel void foo2() {} // expected-error {{'amdgpu_num_vgpr' attribute requires an integer constant}}
-__attribute__((amdgpu_num_sgpr("ABC"))) kernel void foo3() {} // expected-error {{'amdgpu_num_sgpr' attribute requires an integer constant}}
-
-
-__attribute__((amdgpu_num_vgpr(40))) void foo4() {} // expected-error {{'amdgpu_num_vgpr' attribute only applies to kernel functions}}
-__attribute__((amdgpu_num_sgpr(64))) void foo5() {} // expected-error {{'amdgpu_num_sgpr' attribute only applies to kernel functions}}
-
-__attribute__((amdgpu_num_vgpr(40))) kernel void foo7() {}
-__attribute__((amdgpu_num_sgpr(64))) kernel void foo8() {}
-__attribute__((amdgpu_num_vgpr(40), amdgpu_num_sgpr(64))) kernel void foo9() {}
-
-// Check 0 VGPR is accepted.
-__attribute__((amdgpu_num_vgpr(0))) kernel void foo10() {}
-
-// Check 0 SGPR is accepted.
-__attribute__((amdgpu_num_sgpr(0))) kernel void foo11() {}
-
-// Check both 0 SGPR and VGPR is accepted.
-__attribute__((amdgpu_num_vgpr(0), amdgpu_num_sgpr(0))) kernel void foo12() {}
-
-// Too large VGPR value.
-__attribute__((amdgpu_num_vgpr(4294967296))) kernel void foo13() {} // expected-error {{integer constant expression evaluates to value 4294967296 that cannot be represented in a 32-bit unsigned integer type}}
-
-__attribute__((amdgpu_num_sgpr(4294967296))) kernel void foo14() {} // expected-error {{integer constant expression evaluates to value 4294967296 that cannot be represented in a 32-bit unsigned integer type}}
-
-__attribute__((amdgpu_num_sgpr(4294967296), amdgpu_num_vgpr(4294967296))) kernel void foo15() {} // expected-error 2 {{integer constant expression evaluates to value 4294967296 that cannot be represented in a 32-bit unsigned integer type}}
-
-
-// Make sure it is accepted with kernel keyword before the attribute.
-kernel __attribute__((amdgpu_num_vgpr(40))) void foo16() {}
-
-kernel __attribute__((amdgpu_num_sgpr(40))) void foo17() {}
Index: test/SemaOpenCL/amdgpu-attrs.cl
===
--- test/SemaOpenCL/amdgpu-attrs.cl
+++ test/SemaOpenCL/amdgpu-attrs.cl
@@ -0,0 +1,66 @@
+// RUN: %clang_cc1 -triple amdgcn-- -verify -fsyntax-only %s
+
+typedef __attribute__((amdgpu_flat_work_group_size(32, 64))) struct struct_flat_work_group_size_32_64 { // expected-error {{'amdgpu_flat_work_group_size' attribute only applies to kernel functions}}
+  int x;
+  float y;
+} struct_flat_work_group_size_32_64;
+typedef __attribute__((amdgpu_waves_per_eu(2))) struct struct_waves_per_eu_2 { // expected-error {{'amdgpu_waves_per_eu' attribute only applies to kernel functions}}
+  int x;
+  float y;
+} struct_waves_per_eu_2;
+typedef __attribute__((amdgpu_waves_per_eu(2, 4))) struct struct_waves_per_eu_2_4 { // expected-error {{'amdgpu_waves_per_eu' attribute only applies to kernel functions}}
+  int x;
+  float y;
+} struct_waves_per_eu_2_4;
+typedef __attribute__((amdgpu_num_sgpr(32))) struct struct_num_sgpr_32 { // expected-error {{'amdgpu_num_sgpr' attribute only applies to kernel functions}}
+  int x;
+  float y;
+} struct_num_sgpr_32;
+typedef __attribute__((amdgpu_num_vgpr(64))) struct struct_num_vgpr_64 { // expected-error {{'amdgpu_num_vgpr' attribute only applies to kernel functions}}
+  int x;
+  float y;
+} struct_num_vgpr_64;
+
+__attribute__((amdgpu_flat_work_group_size(32, 64))) void func_flat_work_group_size_32_64() {} // expected-error {{'amdgpu_flat_work_group_size' attribute only applies to kernel functions}}
+__attribute__((amdgpu_waves_per_eu(2))) void func_waves_per_eu_2() {} // expected-error {{'amdgpu_waves_per_eu' attribute only applies to kernel functions}}
+__attribute__((amdgpu_waves_per_eu(2, 4))) void func_waves_per_eu_2_4() {} // expected-error {{'amdgpu_waves_per_eu' attribute only applies to kernel functions}}
+__attribute__((amdgpu_num_sgpr(32))) void func_num_sgpr_32() {} // expected-error

Re: [PATCH] D24513: [AMDGPU] Expose flat work group size, register and wave control attributes

2016-09-14 Thread Konstantin Zhuravlyov via cfe-commits 
kzhuravl updated this revision to Diff 71382.
kzhuravl added a comment.

Fix minor typos


https://reviews.llvm.org/D24513

Files:
  include/clang/Basic/Attr.td
  include/clang/Basic/AttrDocs.td
  include/clang/Basic/DiagnosticSemaKinds.td
  lib/CodeGen/TargetInfo.cpp
  lib/Sema/SemaDeclAttr.cpp
  test/CodeGenOpenCL/amdgpu-attrs.cl
  test/CodeGenOpenCL/amdgpu-num-gpr-attr.cl
  test/SemaCUDA/amdgpu-attrs.cu
  test/SemaCUDA/amdgpu-num-gpr-attr.cu
  test/SemaOpenCL/amdgpu-attrs.cl
  test/SemaOpenCL/amdgpu-num-register-attrs.cl

Index: test/SemaOpenCL/amdgpu-num-register-attrs.cl
===
--- test/SemaOpenCL/amdgpu-num-register-attrs.cl
+++ test/SemaOpenCL/amdgpu-num-register-attrs.cl
@@ -1,40 +0,0 @@
-// RUN: %clang_cc1 -triple r600-- -verify -fsyntax-only %s
-
-typedef __attribute__((amdgpu_num_vgpr(128))) struct FooStruct { // expected-error {{'amdgpu_num_vgpr' attribute only applies to kernel functions}}
-  int x;
-  float y;
-} FooStruct;
-
-
-__attribute__((amdgpu_num_vgpr("ABC"))) kernel void foo2() {} // expected-error {{'amdgpu_num_vgpr' attribute requires an integer constant}}
-__attribute__((amdgpu_num_sgpr("ABC"))) kernel void foo3() {} // expected-error {{'amdgpu_num_sgpr' attribute requires an integer constant}}
-
-
-__attribute__((amdgpu_num_vgpr(40))) void foo4() {} // expected-error {{'amdgpu_num_vgpr' attribute only applies to kernel functions}}
-__attribute__((amdgpu_num_sgpr(64))) void foo5() {} // expected-error {{'amdgpu_num_sgpr' attribute only applies to kernel functions}}
-
-__attribute__((amdgpu_num_vgpr(40))) kernel void foo7() {}
-__attribute__((amdgpu_num_sgpr(64))) kernel void foo8() {}
-__attribute__((amdgpu_num_vgpr(40), amdgpu_num_sgpr(64))) kernel void foo9() {}
-
-// Check 0 VGPR is accepted.
-__attribute__((amdgpu_num_vgpr(0))) kernel void foo10() {}
-
-// Check 0 SGPR is accepted.
-__attribute__((amdgpu_num_sgpr(0))) kernel void foo11() {}
-
-// Check both 0 SGPR and VGPR is accepted.
-__attribute__((amdgpu_num_vgpr(0), amdgpu_num_sgpr(0))) kernel void foo12() {}
-
-// Too large VGPR value.
-__attribute__((amdgpu_num_vgpr(4294967296))) kernel void foo13() {} // expected-error {{integer constant expression evaluates to value 4294967296 that cannot be represented in a 32-bit unsigned integer type}}
-
-__attribute__((amdgpu_num_sgpr(4294967296))) kernel void foo14() {} // expected-error {{integer constant expression evaluates to value 4294967296 that cannot be represented in a 32-bit unsigned integer type}}
-
-__attribute__((amdgpu_num_sgpr(4294967296), amdgpu_num_vgpr(4294967296))) kernel void foo15() {} // expected-error 2 {{integer constant expression evaluates to value 4294967296 that cannot be represented in a 32-bit unsigned integer type}}
-
-
-// Make sure it is accepted with kernel keyword before the attribute.
-kernel __attribute__((amdgpu_num_vgpr(40))) void foo16() {}
-
-kernel __attribute__((amdgpu_num_sgpr(40))) void foo17() {}
Index: test/SemaOpenCL/amdgpu-attrs.cl
===
--- test/SemaOpenCL/amdgpu-attrs.cl
+++ test/SemaOpenCL/amdgpu-attrs.cl
@@ -0,0 +1,64 @@
+// RUN: %clang_cc1 -triple amdgcn-- -verify -fsyntax-only %s
+
+typedef __attribute__((amdgpu_flat_work_group_size(32, 64))) struct struct_flat_work_group_size_32_64 { // expected-error {{'amdgpu_flat_work_group_size' attribute only applies to kernel functions}}
+  int x;
+  float y;
+} struct_flat_work_group_size_32_64;
+typedef __attribute__((amdgpu_waves_per_eu(2))) struct struct_waves_per_eu_2 { // expected-error {{'amdgpu_waves_per_eu' attribute only applies to kernel functions}}
+  int x;
+  float y;
+} struct_waves_per_eu_2;
+typedef __attribute__((amdgpu_waves_per_eu(2, 4))) struct struct_waves_per_eu_2_4 { // expected-error {{'amdgpu_waves_per_eu' attribute only applies to kernel functions}}
+  int x;
+  float y;
+} struct_waves_per_eu_2_4;
+typedef __attribute__((amdgpu_num_sgpr(32))) struct struct_num_sgpr_32 { // expected-error {{'amdgpu_num_sgpr' attribute only applies to kernel functions}}
+  int x;
+  float y;
+} struct_num_sgpr_32;
+typedef __attribute__((amdgpu_num_vgpr(64))) struct struct_num_vgpr_64 { // expected-error {{'amdgpu_num_vgpr' attribute only applies to kernel functions}}
+  int x;
+  float y;
+} struct_num_vgpr_64;
+
+__attribute__((amdgpu_flat_work_group_size(32, 64))) void func_flat_work_group_size_32_64() {} // expected-error {{'amdgpu_flat_work_group_size' attribute only applies to kernel functions}}
+__attribute__((amdgpu_waves_per_eu(2))) void func_waves_per_eu_2() {} // expected-error {{'amdgpu_waves_per_eu' attribute only applies to kernel functions}}
+__attribute__((amdgpu_waves_per_eu(2, 4))) void func_waves_per_eu_2_4() {} // expected-error {{'amdgpu_waves_per_eu' attribute only applies to kernel functions}}
+__attribute__((amdgpu_num_sgpr(32))) void func_num_sgpr_32() {} // expected-error {{'amdgpu_num_sgpr' attribute only applies to kernel

Re: [PATCH] D24513: [AMDGPU] Expose flat work group size, register and wave control attributes

2016-09-14 Thread Konstantin Zhuravlyov via cfe-commits 
kzhuravl updated the summary for this revision.
kzhuravl updated this revision to Diff 71311.
kzhuravl added a comment.

Update docs in AttrDocs.td


https://reviews.llvm.org/D24513

Files:
  include/clang/Basic/Attr.td
  include/clang/Basic/AttrDocs.td
  include/clang/Basic/DiagnosticSemaKinds.td
  lib/CodeGen/TargetInfo.cpp
  lib/Sema/SemaDeclAttr.cpp
  test/CodeGenOpenCL/amdgpu-attrs.cl
  test/CodeGenOpenCL/amdgpu-num-gpr-attr.cl
  test/SemaCUDA/amdgpu-attrs.cu
  test/SemaCUDA/amdgpu-num-gpr-attr.cu
  test/SemaOpenCL/amdgpu-attrs.cl
  test/SemaOpenCL/amdgpu-num-register-attrs.cl

Index: test/SemaOpenCL/amdgpu-num-register-attrs.cl
===
--- test/SemaOpenCL/amdgpu-num-register-attrs.cl
+++ test/SemaOpenCL/amdgpu-num-register-attrs.cl
@@ -1,40 +0,0 @@
-// RUN: %clang_cc1 -triple r600-- -verify -fsyntax-only %s
-
-typedef __attribute__((amdgpu_num_vgpr(128))) struct FooStruct { // expected-error {{'amdgpu_num_vgpr' attribute only applies to kernel functions}}
-  int x;
-  float y;
-} FooStruct;
-
-
-__attribute__((amdgpu_num_vgpr("ABC"))) kernel void foo2() {} // expected-error {{'amdgpu_num_vgpr' attribute requires an integer constant}}
-__attribute__((amdgpu_num_sgpr("ABC"))) kernel void foo3() {} // expected-error {{'amdgpu_num_sgpr' attribute requires an integer constant}}
-
-
-__attribute__((amdgpu_num_vgpr(40))) void foo4() {} // expected-error {{'amdgpu_num_vgpr' attribute only applies to kernel functions}}
-__attribute__((amdgpu_num_sgpr(64))) void foo5() {} // expected-error {{'amdgpu_num_sgpr' attribute only applies to kernel functions}}
-
-__attribute__((amdgpu_num_vgpr(40))) kernel void foo7() {}
-__attribute__((amdgpu_num_sgpr(64))) kernel void foo8() {}
-__attribute__((amdgpu_num_vgpr(40), amdgpu_num_sgpr(64))) kernel void foo9() {}
-
-// Check 0 VGPR is accepted.
-__attribute__((amdgpu_num_vgpr(0))) kernel void foo10() {}
-
-// Check 0 SGPR is accepted.
-__attribute__((amdgpu_num_sgpr(0))) kernel void foo11() {}
-
-// Check both 0 SGPR and VGPR is accepted.
-__attribute__((amdgpu_num_vgpr(0), amdgpu_num_sgpr(0))) kernel void foo12() {}
-
-// Too large VGPR value.
-__attribute__((amdgpu_num_vgpr(4294967296))) kernel void foo13() {} // expected-error {{integer constant expression evaluates to value 4294967296 that cannot be represented in a 32-bit unsigned integer type}}
-
-__attribute__((amdgpu_num_sgpr(4294967296))) kernel void foo14() {} // expected-error {{integer constant expression evaluates to value 4294967296 that cannot be represented in a 32-bit unsigned integer type}}
-
-__attribute__((amdgpu_num_sgpr(4294967296), amdgpu_num_vgpr(4294967296))) kernel void foo15() {} // expected-error 2 {{integer constant expression evaluates to value 4294967296 that cannot be represented in a 32-bit unsigned integer type}}
-
-
-// Make sure it is accepted with kernel keyword before the attribute.
-kernel __attribute__((amdgpu_num_vgpr(40))) void foo16() {}
-
-kernel __attribute__((amdgpu_num_sgpr(40))) void foo17() {}
Index: test/SemaOpenCL/amdgpu-attrs.cl
===
--- test/SemaOpenCL/amdgpu-attrs.cl
+++ test/SemaOpenCL/amdgpu-attrs.cl
@@ -0,0 +1,64 @@
+// RUN: %clang_cc1 -triple amdgcn-- -verify -fsyntax-only %s
+
+typedef __attribute__((amdgpu_flat_work_group_size(32, 64))) struct struct_flat_work_group_size_32_64 { // expected-error {{'amdgpu_flat_work_group_size' attribute only applies to kernel functions}}
+  int x;
+  float y;
+} struct_flat_work_group_size_32_64;
+typedef __attribute__((amdgpu_waves_per_eu(2))) struct struct_waves_per_eu_2 { // expected-error {{'amdgpu_waves_per_eu' attribute only applies to kernel functions}}
+  int x;
+  float y;
+} struct_waves_per_eu_2;
+typedef __attribute__((amdgpu_waves_per_eu(2, 4))) struct struct_waves_per_eu_2_4 { // expected-error {{'amdgpu_waves_per_eu' attribute only applies to kernel functions}}
+  int x;
+  float y;
+} struct_waves_per_eu_2_4;
+typedef __attribute__((amdgpu_num_sgpr(32))) struct struct_num_sgpr_32 { // expected-error {{'amdgpu_num_sgpr' attribute only applies to kernel functions}}
+  int x;
+  float y;
+} struct_num_sgpr_32;
+typedef __attribute__((amdgpu_num_vgpr(64))) struct struct_num_vgpr_64 { // expected-error {{'amdgpu_num_vgpr' attribute only applies to kernel functions}}
+  int x;
+  float y;
+} struct_num_vgpr_64;
+
+__attribute__((amdgpu_flat_work_group_size(32, 64))) void func_flat_work_group_size_32_64() {} // expected-error {{'amdgpu_flat_work_group_size' attribute only applies to kernel functions}}
+__attribute__((amdgpu_waves_per_eu(2))) void func_waves_per_eu_2() {} // expected-error {{'amdgpu_waves_per_eu' attribute only applies to kernel functions}}
+__attribute__((amdgpu_waves_per_eu(2, 4))) void func_waves_per_eu_2_4() {} // expected-error {{'amdgpu_waves_per_eu' attribute only applies to kernel functions}}
+__attribute__((amdgpu_num_sgpr(32))) void func_num_sgpr_32() {} // expected-error

[PATCH] D24513: [AMDGPU] Expose flat work group size, register and wave control attributes

2016-09-13 Thread Konstantin Zhuravlyov via cfe-commits 
kzhuravl created this revision.
kzhuravl added reviewers: arsenm, aaron.ballman.
kzhuravl added subscribers: yaxunl, kanarayan, cfe-commits.
Herald added a reviewer: tstellarAMD.
Herald added subscribers: nhaehnle, wdng.

__attribute__((amdgpu_flat_work_group_size(, ))) - request minimum 
and maximum flat work group size
__attribute__((amdgpu_waves_per_eu([, ]))) - request minimum and/or 
maximum waves per execution unit

TODO: need to update docs in AttrDocs.td

https://reviews.llvm.org/D24513

Files:
  include/clang/Basic/Attr.td
  include/clang/Basic/AttrDocs.td
  include/clang/Basic/DiagnosticSemaKinds.td
  lib/CodeGen/TargetInfo.cpp
  lib/Sema/SemaDeclAttr.cpp
  test/CodeGenOpenCL/amdgpu-attrs.cl
  test/CodeGenOpenCL/amdgpu-num-gpr-attr.cl
  test/SemaCUDA/amdgpu-attrs.cu
  test/SemaCUDA/amdgpu-num-gpr-attr.cu
  test/SemaOpenCL/amdgpu-attrs.cl
  test/SemaOpenCL/amdgpu-num-register-attrs.cl

Index: test/SemaOpenCL/amdgpu-num-register-attrs.cl
===
--- test/SemaOpenCL/amdgpu-num-register-attrs.cl
+++ test/SemaOpenCL/amdgpu-num-register-attrs.cl
@@ -1,40 +0,0 @@
-// RUN: %clang_cc1 -triple r600-- -verify -fsyntax-only %s
-
-typedef __attribute__((amdgpu_num_vgpr(128))) struct FooStruct { // expected-error {{'amdgpu_num_vgpr' attribute only applies to kernel functions}}
-  int x;
-  float y;
-} FooStruct;
-
-
-__attribute__((amdgpu_num_vgpr("ABC"))) kernel void foo2() {} // expected-error {{'amdgpu_num_vgpr' attribute requires an integer constant}}
-__attribute__((amdgpu_num_sgpr("ABC"))) kernel void foo3() {} // expected-error {{'amdgpu_num_sgpr' attribute requires an integer constant}}
-
-
-__attribute__((amdgpu_num_vgpr(40))) void foo4() {} // expected-error {{'amdgpu_num_vgpr' attribute only applies to kernel functions}}
-__attribute__((amdgpu_num_sgpr(64))) void foo5() {} // expected-error {{'amdgpu_num_sgpr' attribute only applies to kernel functions}}
-
-__attribute__((amdgpu_num_vgpr(40))) kernel void foo7() {}
-__attribute__((amdgpu_num_sgpr(64))) kernel void foo8() {}
-__attribute__((amdgpu_num_vgpr(40), amdgpu_num_sgpr(64))) kernel void foo9() {}
-
-// Check 0 VGPR is accepted.
-__attribute__((amdgpu_num_vgpr(0))) kernel void foo10() {}
-
-// Check 0 SGPR is accepted.
-__attribute__((amdgpu_num_sgpr(0))) kernel void foo11() {}
-
-// Check both 0 SGPR and VGPR is accepted.
-__attribute__((amdgpu_num_vgpr(0), amdgpu_num_sgpr(0))) kernel void foo12() {}
-
-// Too large VGPR value.
-__attribute__((amdgpu_num_vgpr(4294967296))) kernel void foo13() {} // expected-error {{integer constant expression evaluates to value 4294967296 that cannot be represented in a 32-bit unsigned integer type}}
-
-__attribute__((amdgpu_num_sgpr(4294967296))) kernel void foo14() {} // expected-error {{integer constant expression evaluates to value 4294967296 that cannot be represented in a 32-bit unsigned integer type}}
-
-__attribute__((amdgpu_num_sgpr(4294967296), amdgpu_num_vgpr(4294967296))) kernel void foo15() {} // expected-error 2 {{integer constant expression evaluates to value 4294967296 that cannot be represented in a 32-bit unsigned integer type}}
-
-
-// Make sure it is accepted with kernel keyword before the attribute.
-kernel __attribute__((amdgpu_num_vgpr(40))) void foo16() {}
-
-kernel __attribute__((amdgpu_num_sgpr(40))) void foo17() {}
Index: test/SemaOpenCL/amdgpu-attrs.cl
===
--- test/SemaOpenCL/amdgpu-attrs.cl
+++ test/SemaOpenCL/amdgpu-attrs.cl
@@ -0,0 +1,64 @@
+// RUN: %clang_cc1 -triple amdgcn-- -verify -fsyntax-only %s
+
+typedef __attribute__((amdgpu_flat_work_group_size(32, 64))) struct struct_flat_work_group_size_32_64 { // expected-error {{'amdgpu_flat_work_group_size' attribute only applies to kernel functions}}
+  int x;
+  float y;
+} struct_flat_work_group_size_32_64;
+typedef __attribute__((amdgpu_waves_per_eu(2))) struct struct_waves_per_eu_2 { // expected-error {{'amdgpu_waves_per_eu' attribute only applies to kernel functions}}
+  int x;
+  float y;
+} struct_waves_per_eu_2;
+typedef __attribute__((amdgpu_waves_per_eu(2, 4))) struct struct_waves_per_eu_2_4 { // expected-error {{'amdgpu_waves_per_eu' attribute only applies to kernel functions}}
+  int x;
+  float y;
+} struct_waves_per_eu_2_4;
+typedef __attribute__((amdgpu_num_sgpr(32))) struct struct_num_sgpr_32 { // expected-error {{'amdgpu_num_sgpr' attribute only applies to kernel functions}}
+  int x;
+  float y;
+} struct_num_sgpr_32;
+typedef __attribute__((amdgpu_num_vgpr(64))) struct struct_num_vgpr_64 { // expected-error {{'amdgpu_num_vgpr' attribute only applies to kernel functions}}
+  int x;
+  float y;
+} struct_num_vgpr_64;
+
+__attribute__((amdgpu_flat_work_group_size(32, 64))) void func_flat_work_group_size_32_64() {} // expected-error {{'amdgpu_flat_work_group_size' attribute only applies to kernel functions}}
+__attribute__((amdgpu_waves_per_eu(2))) void func_waves_per_eu_2() {} //

Re: [PATCH] D21724: [RFC] Enhance synchscope representation (clang)

2016-08-17 Thread Konstantin Zhuravlyov via cfe-commits 
kzhuravl abandoned this revision.
kzhuravl added a comment.

This patch is not required at this point since we left SynchronizationScope 
enum intact and did not rename existing members


https://reviews.llvm.org/D21724



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Re: [PATCH] D21724: [RFC] Enhance synchscope representation (clang)

2016-07-25 Thread Konstantin Zhuravlyov via cfe-commits 
kzhuravl updated this revision to Diff 65343.
kzhuravl added a comment.

Remove metadata generation


https://reviews.llvm.org/D21724

Files:
  lib/CodeGen/CGBuiltin.cpp

Index: lib/CodeGen/CGBuiltin.cpp
===
--- lib/CodeGen/CGBuiltin.cpp
+++ lib/CodeGen/CGBuiltin.cpp
@@ -1539,12 +1539,13 @@
   case Builtin::BI__atomic_signal_fence:
   case Builtin::BI__c11_atomic_thread_fence:
   case Builtin::BI__c11_atomic_signal_fence: {
-llvm::SynchronizationScope Scope;
+unsigned Scope;
 if (BuiltinID == Builtin::BI__atomic_signal_fence ||
-BuiltinID == Builtin::BI__c11_atomic_signal_fence)
-  Scope = llvm::SingleThread;
-else
-  Scope = llvm::CrossThread;
+BuiltinID == Builtin::BI__c11_atomic_signal_fence) {
+  Scope = llvm::SynchScope::SingleThread;
+} else {
+  Scope = llvm::SynchScope::System;
+}
 Value *Order = EmitScalarExpr(E->getArg(0));
 if (isa(Order)) {
   int ord = cast(Order)->getZExtValue();


Index: lib/CodeGen/CGBuiltin.cpp
===
--- lib/CodeGen/CGBuiltin.cpp
+++ lib/CodeGen/CGBuiltin.cpp
@@ -1539,12 +1539,13 @@
   case Builtin::BI__atomic_signal_fence:
   case Builtin::BI__c11_atomic_thread_fence:
   case Builtin::BI__c11_atomic_signal_fence: {
-llvm::SynchronizationScope Scope;
+unsigned Scope;
 if (BuiltinID == Builtin::BI__atomic_signal_fence ||
-BuiltinID == Builtin::BI__c11_atomic_signal_fence)
-  Scope = llvm::SingleThread;
-else
-  Scope = llvm::CrossThread;
+BuiltinID == Builtin::BI__c11_atomic_signal_fence) {
+  Scope = llvm::SynchScope::SingleThread;
+} else {
+  Scope = llvm::SynchScope::System;
+}
 Value *Order = EmitScalarExpr(E->getArg(0));
 if (isa(Order)) {
   int ord = cast(Order)->getZExtValue();
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Re: [PATCH] D21724: [RFC] Enhance synchscope representation (clang)

2016-07-06 Thread Konstantin Zhuravlyov via cfe-commits 
kzhuravl updated this revision to Diff 62971.
kzhuravl added a comment.

Rebase


http://reviews.llvm.org/D21724

Files:
  lib/CodeGen/CGBuiltin.cpp
  lib/CodeGen/CodeGenModule.cpp
  lib/CodeGen/CodeGenModule.h
  test/CodeGen/synchscopes.cpp

Index: test/CodeGen/synchscopes.cpp
===
--- test/CodeGen/synchscopes.cpp
+++ test/CodeGen/synchscopes.cpp
@@ -0,0 +1,17 @@
+// RUN: %clang -emit-llvm -S -std=c++11 %s -o - | FileCheck %s
+
+// CHECK: !synchscopes = !{!0, !1}
+// CHECK: !0 = !{i32 0, !"System"}
+// CHECK: !1 = !{i32 -1, !"SingleThread"}
+
+#include 
+
+void synchscopes_acquire() {
+  atomic_thread_fence(std::memory_order_acquire);
+  atomic_signal_fence(std::memory_order_acquire);
+}
+
+void synchscopes_release() {
+  atomic_thread_fence(std::memory_order_release);
+  atomic_signal_fence(std::memory_order_release);
+}
Index: lib/CodeGen/CodeGenModule.h
===
--- lib/CodeGen/CodeGenModule.h
+++ lib/CodeGen/CodeGenModule.h
@@ -374,6 +374,9 @@
   llvm::DenseMap AtomicSetterHelperFnMap;
   llvm::DenseMap AtomicGetterHelperFnMap;
 
+  /// \brief Mapping from synchronization scope to it's string representation.
+  std::map SynchScopeMap;
+
   /// Map used to get unique type descriptor constants for sanitizers.
   llvm::DenseMap TypeDescriptorMap;
 
@@ -582,6 +585,8 @@
 AtomicGetterHelperFnMap[Ty] = Fn;
   }
 
+  void setSynchScopeMap(unsigned SynchScope, const std::string );
+
   llvm::Constant *getTypeDescriptorFromMap(QualType Ty) {
 return TypeDescriptorMap[Ty];
   }
@@ -1233,6 +1238,9 @@
 
   void EmitDeclMetadata();
 
+  /// \brief Emit synchronization scope metadata.
+  void EmitSynchScopeMetadata();
+
   /// \brief Emit the Clang version as llvm.ident metadata.
   void EmitVersionIdentMetadata();
 
Index: lib/CodeGen/CodeGenModule.cpp
===
--- lib/CodeGen/CodeGenModule.cpp
+++ lib/CodeGen/CodeGenModule.cpp
@@ -495,6 +495,8 @@
   if (DebugInfo)
 DebugInfo->finalize();
 
+  EmitSynchScopeMetadata();
+
   EmitVersionIdentMetadata();
 
   EmitTargetMetadata();
@@ -4079,6 +4081,15 @@
   return true;
 }
 
+void CodeGenModule::setSynchScopeMap(unsigned SynchScope,
+ const std::string ) {
+  auto Res = SynchScopeMap.find(SynchScope);
+  if (Res == SynchScopeMap.end())
+SynchScopeMap.insert(std::make_pair(SynchScope, SynchScopeName));
+  else
+assert(Res->second == SynchScopeName);
+}
+
 /// Emits metadata nodes associating all the global values in the
 /// current module with the Decls they came from.  This is useful for
 /// projects using IR gen as a subroutine.
@@ -4125,6 +4136,22 @@
   }
 }
 
+void CodeGenModule::EmitSynchScopeMetadata() {
+  if (!SynchScopeMap.size())
+return;
+
+  llvm::LLVMContext  = TheModule.getContext();
+  llvm::NamedMDNode *SynchScopeMetadata =
+TheModule.getOrInsertNamedMetadata("synchscopes");
+  for (auto  : SynchScopeMap) {
+llvm::Metadata *SynchScopeNode[2] = {
+  llvm::ConstantAsMetadata::get(llvm::ConstantInt::get(Int32Ty, I.first)),
+  llvm::MDString::get(Ctx, I.second)
+};
+SynchScopeMetadata->addOperand(llvm::MDNode::get(Ctx, SynchScopeNode));
+  }
+}
+
 void CodeGenModule::EmitVersionIdentMetadata() {
   llvm::NamedMDNode *IdentMetadata =
 TheModule.getOrInsertNamedMetadata("llvm.ident");
Index: lib/CodeGen/CGBuiltin.cpp
===
--- lib/CodeGen/CGBuiltin.cpp
+++ lib/CodeGen/CGBuiltin.cpp
@@ -1527,12 +1527,17 @@
   case Builtin::BI__atomic_signal_fence:
   case Builtin::BI__c11_atomic_thread_fence:
   case Builtin::BI__c11_atomic_signal_fence: {
-llvm::SynchronizationScope Scope;
+unsigned Scope;
+std::string ScopeName;
 if (BuiltinID == Builtin::BI__atomic_signal_fence ||
-BuiltinID == Builtin::BI__c11_atomic_signal_fence)
-  Scope = llvm::SingleThread;
-else
-  Scope = llvm::CrossThread;
+BuiltinID == Builtin::BI__c11_atomic_signal_fence) {
+  Scope = llvm::SynchScopeSingleThread;
+  ScopeName = "SingleThread";
+} else {
+  Scope = llvm::SynchScopeSystem;
+  ScopeName = "System";
+}
+CGM.setSynchScopeMap(Scope, ScopeName);
 Value *Order = EmitScalarExpr(E->getArg(0));
 if (isa(Order)) {
   int ord = cast(Order)->getZExtValue();
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[PATCH] D21724: [RFC] Enhance synchscope representation (clang)

2016-06-25 Thread Konstantin Zhuravlyov via cfe-commits 
kzhuravl created this revision.
kzhuravl added reviewers: tstellarAMD, arsenm, rampitec.
kzhuravl added subscribers: cfe-commits, llvm-commits, resistor.

As described in this proposal: 
https://groups.google.com/forum/#!topic/llvm-dev/GtWfCc5j-4U

http://reviews.llvm.org/D21724

Files:
  lib/CodeGen/CGBuiltin.cpp
  lib/CodeGen/CodeGenModule.cpp
  lib/CodeGen/CodeGenModule.h
  test/CodeGen/synchscopes.cpp

Index: test/CodeGen/synchscopes.cpp
===
--- test/CodeGen/synchscopes.cpp
+++ test/CodeGen/synchscopes.cpp
@@ -0,0 +1,17 @@
+// RUN: %clang -emit-llvm -S -std=c++11 %s -o - | FileCheck %s
+
+// CHECK: !synchscopes = !{!0, !1}
+// CHECK: !0 = !{i32 0, !"System"}
+// CHECK: !1 = !{i32 -1, !"SingleThread"}
+
+#include 
+
+void synchscopes_acquire() {
+  atomic_thread_fence(std::memory_order_acquire);
+  atomic_signal_fence(std::memory_order_acquire);
+}
+
+void synchscopes_release() {
+  atomic_thread_fence(std::memory_order_release);
+  atomic_signal_fence(std::memory_order_release);
+}
Index: lib/CodeGen/CodeGenModule.h
===
--- lib/CodeGen/CodeGenModule.h
+++ lib/CodeGen/CodeGenModule.h
@@ -374,6 +374,9 @@
   llvm::DenseMap AtomicSetterHelperFnMap;
   llvm::DenseMap AtomicGetterHelperFnMap;
 
+  /// \brief Mapping from synchronization scope to it's string representation.
+  std::map SynchScopeMap;
+
   /// Map used to get unique type descriptor constants for sanitizers.
   llvm::DenseMap TypeDescriptorMap;
 
@@ -582,6 +585,8 @@
 AtomicGetterHelperFnMap[Ty] = Fn;
   }
 
+  void setSynchScopeMap(unsigned SynchScope, const std::string );
+
   llvm::Constant *getTypeDescriptorFromMap(QualType Ty) {
 return TypeDescriptorMap[Ty];
   }
@@ -1233,6 +1238,9 @@
 
   void EmitDeclMetadata();
 
+  /// \brief Emit synchronization scope metadata.
+  void EmitSynchScopeMetadata();
+
   /// \brief Emit the Clang version as llvm.ident metadata.
   void EmitVersionIdentMetadata();
 
Index: lib/CodeGen/CodeGenModule.cpp
===
--- lib/CodeGen/CodeGenModule.cpp
+++ lib/CodeGen/CodeGenModule.cpp
@@ -495,6 +495,8 @@
   if (DebugInfo)
 DebugInfo->finalize();
 
+  EmitSynchScopeMetadata();
+
   EmitVersionIdentMetadata();
 
   EmitTargetMetadata();
@@ -4049,6 +4051,15 @@
   return true;
 }
 
+void CodeGenModule::setSynchScopeMap(unsigned SynchScope,
+ const std::string ) {
+  auto Res = SynchScopeMap.find(SynchScope);
+  if (Res == SynchScopeMap.end())
+SynchScopeMap.insert(std::make_pair(SynchScope, SynchScopeName));
+  else
+assert(Res->second == SynchScopeName);
+}
+
 /// Emits metadata nodes associating all the global values in the
 /// current module with the Decls they came from.  This is useful for
 /// projects using IR gen as a subroutine.
@@ -4095,6 +4106,22 @@
   }
 }
 
+void CodeGenModule::EmitSynchScopeMetadata() {
+  if (!SynchScopeMap.size())
+return;
+
+  llvm::LLVMContext  = TheModule.getContext();
+  llvm::NamedMDNode *SynchScopeMetadata =
+TheModule.getOrInsertNamedMetadata("synchscopes");
+  for (auto  : SynchScopeMap) {
+llvm::Metadata *SynchScopeNode[2] = {
+  llvm::ConstantAsMetadata::get(llvm::ConstantInt::get(Int32Ty, I.first)),
+  llvm::MDString::get(Ctx, I.second)
+};
+SynchScopeMetadata->addOperand(llvm::MDNode::get(Ctx, SynchScopeNode));
+  }
+}
+
 void CodeGenModule::EmitVersionIdentMetadata() {
   llvm::NamedMDNode *IdentMetadata =
 TheModule.getOrInsertNamedMetadata("llvm.ident");
Index: lib/CodeGen/CGBuiltin.cpp
===
--- lib/CodeGen/CGBuiltin.cpp
+++ lib/CodeGen/CGBuiltin.cpp
@@ -1474,12 +1474,17 @@
   case Builtin::BI__atomic_signal_fence:
   case Builtin::BI__c11_atomic_thread_fence:
   case Builtin::BI__c11_atomic_signal_fence: {
-llvm::SynchronizationScope Scope;
+unsigned Scope;
+std::string ScopeName;
 if (BuiltinID == Builtin::BI__atomic_signal_fence ||
-BuiltinID == Builtin::BI__c11_atomic_signal_fence)
-  Scope = llvm::SingleThread;
-else
-  Scope = llvm::CrossThread;
+BuiltinID == Builtin::BI__c11_atomic_signal_fence) {
+  Scope = llvm::SynchScopeSingleThread;
+  ScopeName = "SingleThread";
+} else {
+  Scope = llvm::SynchScopeSystem;
+  ScopeName = "System";
+}
+CGM.setSynchScopeMap(Scope, ScopeName);
 Value *Order = EmitScalarExpr(E->getArg(0));
 if (isa(Order)) {
   int ord = cast(Order)->getZExtValue();
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Re: [PATCH] D20640: [AMDGPU] Set default dwarf version to 2

2016-05-31 Thread Konstantin Zhuravlyov via cfe-commits 
This revision was automatically updated to reflect the committed changes.
Closed by commit rL271347: [AMDGPU] Set default dwarf version to 2 (authored by 
kzhuravl).

Changed prior to commit:
  http://reviews.llvm.org/D20640?vs=58481=59144#toc

Repository:
  rL LLVM

http://reviews.llvm.org/D20640

Files:
  cfe/trunk/lib/Driver/ToolChains.h
  cfe/trunk/test/Driver/amdgpu-toolchain.c

Index: cfe/trunk/lib/Driver/ToolChains.h
===
--- cfe/trunk/lib/Driver/ToolChains.h
+++ cfe/trunk/lib/Driver/ToolChains.h
@@ -943,6 +943,7 @@
 public:
   AMDGPUToolChain(const Driver , const llvm::Triple ,
 const llvm::opt::ArgList );
+  unsigned GetDefaultDwarfVersion() const override { return 2; }
   bool IsIntegratedAssemblerDefault() const override { return true; }
 };
 
Index: cfe/trunk/test/Driver/amdgpu-toolchain.c
===
--- cfe/trunk/test/Driver/amdgpu-toolchain.c
+++ cfe/trunk/test/Driver/amdgpu-toolchain.c
@@ -1,3 +1,6 @@
 // RUN: %clang -### -target amdgcn--amdhsa -x assembler -mcpu=kaveri %s 2>&1 | 
FileCheck -check-prefix=AS_LINK %s
 // AS_LINK: clang{{.*}} "-cc1as"
 // AS_LINK: ld.lld{{.*}} "-shared"
+
+// RUN: %clang -### -g -target amdgcn--amdhsa -mcpu=kaveri %s 2>&1 | FileCheck 
-check-prefix=DWARF_VER %s
+// DWARF_VER: "-dwarf-version=2"


Index: cfe/trunk/lib/Driver/ToolChains.h
===
--- cfe/trunk/lib/Driver/ToolChains.h
+++ cfe/trunk/lib/Driver/ToolChains.h
@@ -943,6 +943,7 @@
 public:
   AMDGPUToolChain(const Driver , const llvm::Triple ,
 const llvm::opt::ArgList );
+  unsigned GetDefaultDwarfVersion() const override { return 2; }
   bool IsIntegratedAssemblerDefault() const override { return true; }
 };
 
Index: cfe/trunk/test/Driver/amdgpu-toolchain.c
===
--- cfe/trunk/test/Driver/amdgpu-toolchain.c
+++ cfe/trunk/test/Driver/amdgpu-toolchain.c
@@ -1,3 +1,6 @@
 // RUN: %clang -### -target amdgcn--amdhsa -x assembler -mcpu=kaveri %s 2>&1 | FileCheck -check-prefix=AS_LINK %s
 // AS_LINK: clang{{.*}} "-cc1as"
 // AS_LINK: ld.lld{{.*}} "-shared"
+
+// RUN: %clang -### -g -target amdgcn--amdhsa -mcpu=kaveri %s 2>&1 | FileCheck -check-prefix=DWARF_VER %s
+// DWARF_VER: "-dwarf-version=2"
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r271347 - [AMDGPU] Set default dwarf version to 2

2016-05-31 Thread Konstantin Zhuravlyov via cfe-commits 
Author: kzhuravl
Date: Tue May 31 17:47:11 2016
New Revision: 271347

URL: http://llvm.org/viewvc/llvm-project?rev=271347=rev
Log:
[AMDGPU] Set default dwarf version to 2

Differential Revision: http://reviews.llvm.org/D20640

Modified:
cfe/trunk/lib/Driver/ToolChains.h
cfe/trunk/test/Driver/amdgpu-toolchain.c

Modified: cfe/trunk/lib/Driver/ToolChains.h
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Driver/ToolChains.h?rev=271347=271346=271347=diff
==
--- cfe/trunk/lib/Driver/ToolChains.h (original)
+++ cfe/trunk/lib/Driver/ToolChains.h Tue May 31 17:47:11 2016
@@ -943,6 +943,7 @@ protected:
 public:
   AMDGPUToolChain(const Driver , const llvm::Triple ,
 const llvm::opt::ArgList );
+  unsigned GetDefaultDwarfVersion() const override { return 2; }
   bool IsIntegratedAssemblerDefault() const override { return true; }
 };
 

Modified: cfe/trunk/test/Driver/amdgpu-toolchain.c
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/Driver/amdgpu-toolchain.c?rev=271347=271346=271347=diff
==
--- cfe/trunk/test/Driver/amdgpu-toolchain.c (original)
+++ cfe/trunk/test/Driver/amdgpu-toolchain.c Tue May 31 17:47:11 2016
@@ -1,3 +1,6 @@
 // RUN: %clang -### -target amdgcn--amdhsa -x assembler -mcpu=kaveri %s 2>&1 | 
FileCheck -check-prefix=AS_LINK %s
 // AS_LINK: clang{{.*}} "-cc1as"
 // AS_LINK: ld.lld{{.*}} "-shared"
+
+// RUN: %clang -### -g -target amdgcn--amdhsa -mcpu=kaveri %s 2>&1 | FileCheck 
-check-prefix=DWARF_VER %s
+// DWARF_VER: "-dwarf-version=2"


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