[PATCH] D132843: [RISCV] Ensure target features get passed to the LTO linker for RISC-V

[Lewis Revill via Phabricator via cfe-commits]

lewis-revill created this revision.
lewis-revill added reviewers: efriedma, lenary, jrtc27, asb.
Herald added subscribers: sunshaoce, VincentWu, luke957, ormris, StephenFan, 
vkmr, frasercrmck, evandro, luismarques, apazos, sameer.abuasal, simoncook, 
s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, 
rogfer01, steven_wu, edward-jones, zzheng, shiva0217, kito-cheng, niosHD, 
sabuasal, johnrusso, rbar, hiraditya, arichardson, inglorion.
Herald added a project: All.
lewis-revill requested review of this revision.
Herald added subscribers: cfe-commits, pcwang-thead, eopXD, MaskRay.
Herald added a project: clang.

This patch fixes an issue whereby the LTO linker would not receive any 
information about target features, so things like architecture extensions would 
not be accounted for during codegen.

There is perhaps an outstanding question as to why this is required versus 
obtaining the target features from bitcode. This is the approach I implemented 
for now, but would be happy to look into whether I can make it work via bitcode 
if desired.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D132843

Files:
  clang/lib/Driver/ToolChains/Arch/RISCV.cpp
  clang/lib/Driver/ToolChains/Arch/RISCV.h
  clang/lib/Driver/ToolChains/CommonArgs.cpp
  clang/test/Driver/lto.c


Index: clang/test/Driver/lto.c
===
--- clang/test/Driver/lto.c
+++ clang/test/Driver/lto.c
@@ -155,3 +155,8 @@
 // RISCV-SPEC-ABI-2: "-plugin-opt=-target-abi=ilp32d"
 // RISCV-SPEC-ABI-3: "-plugin-opt=-target-abi=lp64"
 // RISCV-SPEC-ABI-4: "-plugin-opt=-target-abi=lp64f"
+
+// RUN: %clang -target riscv32-unknown-elf %s -fuse-ld=gold -flto -mrelax \
+// RUN:   -### 2>&1 | FileCheck %s --check-prefix=RV32-RELAX-ATTR
+//
+// RV32-RELAX-ATTR: "-plugin-opt=-mattr=+relax"
Index: clang/lib/Driver/ToolChains/CommonArgs.cpp
===
--- clang/lib/Driver/ToolChains/CommonArgs.cpp
+++ clang/lib/Driver/ToolChains/CommonArgs.cpp
@@ -637,6 +637,7 @@
   case llvm::Triple::riscv32:
   case llvm::Triple::riscv64: {
 riscv::addRISCVTargetABIArgs(ToolChain, Args, CmdArgs);
+riscv::addRISCVTargetFeatureArgs(ToolChain, Args, CmdArgs);
 break;
   }
   }
Index: clang/lib/Driver/ToolChains/Arch/RISCV.h
===
--- clang/lib/Driver/ToolChains/Arch/RISCV.h
+++ clang/lib/Driver/ToolChains/Arch/RISCV.h
@@ -30,6 +30,10 @@
 void addRISCVTargetABIArgs(const ToolChain ,
const llvm::opt::ArgList ,
llvm::opt::ArgStringList );
+
+void addRISCVTargetFeatureArgs(const ToolChain ,
+   const llvm::opt::ArgList ,
+   llvm::opt::ArgStringList );
 } // end namespace riscv
 } // namespace tools
 } // end namespace driver
Index: clang/lib/Driver/ToolChains/Arch/RISCV.cpp
===
--- clang/lib/Driver/ToolChains/Arch/RISCV.cpp
+++ clang/lib/Driver/ToolChains/Arch/RISCV.cpp
@@ -313,3 +313,15 @@
   CmdArgs.push_back(
   Args.MakeArgString(Twine("-plugin-opt=-target-abi=") + ABIName));
 }
+
+void riscv::addRISCVTargetFeatureArgs(const ToolChain ,
+  const llvm::opt::ArgList ,
+  llvm::opt::ArgStringList ) {
+  const Driver  = ToolChain.getDriver();
+
+  // Pass a plugin-opt for each of the target features to the LTO linker.
+  std::vector Features;
+  riscv::getRISCVTargetFeatures(D, ToolChain.getTriple(), Args, Features);
+  for (StringRef F : Features)
+CmdArgs.push_back(Args.MakeArgString("-plugin-opt=-mattr=" + F));
+}


Index: clang/test/Driver/lto.c
===
--- clang/test/Driver/lto.c
+++ clang/test/Driver/lto.c
@@ -155,3 +155,8 @@
 // RISCV-SPEC-ABI-2: "-plugin-opt=-target-abi=ilp32d"
 // RISCV-SPEC-ABI-3: "-plugin-opt=-target-abi=lp64"
 // RISCV-SPEC-ABI-4: "-plugin-opt=-target-abi=lp64f"
+
+// RUN: %clang -target riscv32-unknown-elf %s -fuse-ld=gold -flto -mrelax \
+// RUN:   -### 2>&1 | FileCheck %s --check-prefix=RV32-RELAX-ATTR
+//
+// RV32-RELAX-ATTR: "-plugin-opt=-mattr=+relax"
Index: clang/lib/Driver/ToolChains/CommonArgs.cpp
===
--- clang/lib/Driver/ToolChains/CommonArgs.cpp
+++ clang/lib/Driver/ToolChains/CommonArgs.cpp
@@ -637,6 +637,7 @@
   case llvm::Triple::riscv32:
   case llvm::Triple::riscv64: {
 riscv::addRISCVTargetABIArgs(ToolChain, Args, CmdArgs);
+riscv::addRISCVTargetFeatureArgs(ToolChain, Args, CmdArgs);
 break;
   }
   }
Index: clang/lib/Driver/ToolChains/Arch/RISCV.h
===
--- clang/lib/Driver/ToolChains/Arch/RISCV.h
+++ clang/lib/Driver/ToolChains/Arch/RISCV.h
@@ -30,6 +30,10 @@
 

[PATCH] D71387: pass -mabi to LTO linker only in RISC-V targets, enable RISC-V LTO

[Lewis Revill via Phabricator via cfe-commits]

lewis-revill added a comment.
Herald added subscribers: sunshaoce, pcwang-thead, VincentWu, luke957, 
StephenFan, arichardson.
Herald added a project: All.

I believe this patch is still relevant/necessary when using LTO for RISCV, so 
can I ask if @khchen is able to update it to rebase/address the feedback? If 
not, are there are any objections to me commandeering this revision to get it 
landed?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D71387/new/

https://reviews.llvm.org/D71387

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D73891: [RISCV] Support experimental/unratified extensions

[Lewis Revill via Phabricator via cfe-commits]

lewis-revill accepted this revision.
lewis-revill added a comment.
This revision is now accepted and ready to land.

Thanks, this is looking in good shape now. As long as everyone agrees on this 
scheme I think the implementation is good to go (pending the bitmanip extension 
support).


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D73891/new/

https://reviews.llvm.org/D73891



___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D62686: [RISCV] Add support for save/restore of callee-saved registers via libcalls

[Lewis Revill via Phabricator via cfe-commits]

This revision was not accepted when it landed; it landed in state "Needs 
Review".
This revision was automatically updated to reflect the committed changes.
Closed by commit rG07f7c00208b3: [RISCV] Add support for save/restore of 
callee-saved registers via libcalls (authored by lewis-revill).

Changed prior to commit:
  https://reviews.llvm.org/D62686?vs=242723=243978#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D62686/new/

https://reviews.llvm.org/D62686

Files:
  clang/lib/Driver/ToolChains/Arch/RISCV.cpp
  clang/test/Driver/riscv-features.c
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
  llvm/lib/Target/RISCV/RISCVFrameLowering.h
  llvm/lib/Target/RISCV/RISCVMachineFunctionInfo.h
  llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
  llvm/lib/Target/RISCV/RISCVRegisterInfo.h
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/CodeGen/RISCV/saverestore.ll
  llvm/test/CodeGen/RISCV/shrinkwrap.ll

Index: llvm/test/CodeGen/RISCV/shrinkwrap.ll
===
--- llvm/test/CodeGen/RISCV/shrinkwrap.ll
+++ llvm/test/CodeGen/RISCV/shrinkwrap.ll
@@ -1,6 +1,8 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple riscv32 < %s | FileCheck %s -check-prefix=RV32I-NOSW
 ; RUN: llc -mtriple riscv32 -enable-shrink-wrap < %s | FileCheck %s -check-prefix=RV32I-SW
+; RUN: llc -mtriple riscv32 -enable-shrink-wrap -mattr=+save-restore < %s \
+; RUN: | FileCheck %s -check-prefix=RV32I-SW-SR
 
 
 declare void @abort()
@@ -29,6 +31,16 @@
 ; RV32I-SW-NEXT:addi sp, sp, -16
 ; RV32I-SW-NEXT:sw ra, 12(sp)
 ; RV32I-SW-NEXT:call abort
+;
+; RV32I-SW-SR-LABEL: eliminate_restore:
+; RV32I-SW-SR:   # %bb.0:
+; RV32I-SW-SR-NEXT:addi a1, zero, 32
+; RV32I-SW-SR-NEXT:bgeu a1, a0, .LBB0_2
+; RV32I-SW-SR-NEXT:  # %bb.1: # %if.end
+; RV32I-SW-SR-NEXT:ret
+; RV32I-SW-SR-NEXT:  .LBB0_2: # %if.then
+; RV32I-SW-SR-NEXT:call t0, __riscv_save_0
+; RV32I-SW-SR-NEXT:call abort
   %cmp = icmp ule i32 %n, 32
   br i1 %cmp, label %if.then, label %if.end
 
@@ -84,6 +96,23 @@
 ; RV32I-SW-NEXT:addi sp, sp, 16
 ; RV32I-SW-NEXT:  .LBB1_2: # %if.end
 ; RV32I-SW-NEXT:ret
+;
+; RV32I-SW-SR-LABEL: conditional_alloca:
+; RV32I-SW-SR:   # %bb.0:
+; RV32I-SW-SR-NEXT:addi a1, zero, 32
+; RV32I-SW-SR-NEXT:bltu a1, a0, .LBB1_2
+; RV32I-SW-SR-NEXT:  # %bb.1: # %if.then
+; RV32I-SW-SR-NEXT:call t0, __riscv_save_1
+; RV32I-SW-SR-NEXT:addi s0, sp, 16
+; RV32I-SW-SR-NEXT:addi a0, a0, 15
+; RV32I-SW-SR-NEXT:andi a0, a0, -16
+; RV32I-SW-SR-NEXT:sub a0, sp, a0
+; RV32I-SW-SR-NEXT:mv sp, a0
+; RV32I-SW-SR-NEXT:call notdead
+; RV32I-SW-SR-NEXT:addi sp, s0, -16
+; RV32I-SW-SR-NEXT:tail __riscv_restore_1
+; RV32I-SW-SR-NEXT:  .LBB1_2: # %if.end
+; RV32I-SW-SR-NEXT:ret
   %cmp = icmp ule i32 %n, 32
   br i1 %cmp, label %if.then, label %if.end
 
Index: llvm/test/CodeGen/RISCV/saverestore.ll
===
--- /dev/null
+++ llvm/test/CodeGen/RISCV/saverestore.ll
@@ -0,0 +1,299 @@
+; RUN: llc -mtriple=riscv32 < %s | FileCheck %s -check-prefix=RV32I
+; RUN: llc -mtriple=riscv64 < %s | FileCheck %s -check-prefix=RV64I
+; RUN: llc -mtriple=riscv32 -mattr=+save-restore < %s | FileCheck %s -check-prefix=RV32I-SR
+; RUN: llc -mtriple=riscv64 -mattr=+save-restore < %s | FileCheck %s -check-prefix=RV64I-SR
+; RUN: llc -mtriple=riscv32 -mattr=+f,+save-restore -target-abi=ilp32f < %s | FileCheck %s -check-prefix=RV32I-FP-SR
+; RUN: llc -mtriple=riscv64 -mattr=+f,+d,+save-restore -target-abi=lp64d < %s | FileCheck %s -check-prefix=RV64I-FP-SR
+
+; Check that the correct save/restore libcalls are generated.
+
+@var0 = global [18 x i32] zeroinitializer
+@var1 = global [24 x i32] zeroinitializer
+@var2 = global [30 x i32] zeroinitializer
+
+define void @callee_saved0() nounwind {
+; RV32I-LABEL: callee_saved0:
+; RV32I-NOT: call t0, __riscv_save
+; RV32I-NOT: tail __riscv_restore
+;
+; RV64I-LABEL: callee_saved0:
+; RV64I-NOT: call t0, __riscv_save
+; RV64I-NOT: tail __riscv_restore
+;
+; RV32I-SR-LABEL: callee_saved0:
+; RV32I-SR: call t0, __riscv_save_5
+; RV32I-SR: tail __riscv_restore_5
+;
+; RV64I-SR-LABEL: callee_saved0:
+; RV64I-SR: call t0, __riscv_save_5
+; RV64I-SR: tail __riscv_restore_5
+;
+; RV32I-FP-SR-LABEL: callee_saved0:
+; RV32I-FP-SR: call t0, __riscv_save_5
+; RV32I-FP-SR: tail __riscv_restore_5
+;
+; RV64I-FP-SR-LABEL: callee_saved0:
+; RV64I-FP-SR: call t0, __riscv_save_5
+; RV64I-FP-SR: tail __riscv_restore_5
+  %val = load [18 x i32], [18 x i32]* @var0
+  store volatile [18 x i32] %val, [18 x i32]* @var0
+  ret void
+}
+
+define void @callee_saved1() nounwind {
+; RV32I-LABEL: callee_saved1:
+; RV32I-NOT: call t0, __riscv_save
+; RV32I-NOT: tail 

[PATCH] D62686: [RISCV] Add support for save/restore of callee-saved registers via libcalls

[Lewis Revill via Phabricator via cfe-commits]

lewis-revill added a comment.

Since the DebugInfo fix has been accepted, I'm looking to get this patch and 
that fix committed shortly if there are no problems caused by rebasing.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D62686/new/

https://reviews.llvm.org/D62686



___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D73891: [RISCV] Support experimental/unratified extensions

[Lewis Revill via Phabricator via cfe-commits]

lewis-revill added inline comments.



Comment at: clang/lib/Driver/ToolChains/Arch/RISCV.cpp:93
+  // If experimental extension, require use of current version number number
+  if (auto ExperimentalExtension = isExperimentalExtension(Ext)) {
+if (!Args.hasArg(options::OPT_menable_experimental_extensions)) {

Hmm... Not sure it makes sense anymore for the function to be called 
`isExperimentalExtension`, because it's not just returning true or false. Just 
off the top of my head I would call it something like 
`getExperimentalExtensionVersion` or ideally something more concise.



Comment at: clang/lib/Driver/ToolChains/Arch/RISCV.cpp:100
+  return false;
+} else if (Major.empty() && Minor.empty()) {
+  std::string Error =

Is just testing `Major.empty()` not sufficient? We can't have a version with 
just a minor version number.



Comment at: clang/lib/Driver/ToolChains/Arch/RISCV.cpp:125
+  // Allow extensions to declare no version number
+  if (Major.empty() && Minor.empty())
+return true;

Ditto.



Comment at: clang/lib/Driver/ToolChains/Arch/RISCV.cpp:366
 default:
   // Currently LLVM supports only "mafdc".
   D.Diag(diag::err_drv_invalid_riscv_ext_arch_name)

Should this comment be updated?



Comment at: clang/lib/Driver/ToolChains/Arch/RISCV.cpp:102
 
-  // TODO: Handle extensions with version number.
+  // If experimental extension, require use of current version number number
+  if (auto ExperimentalExtension = isExperimentalExtension(Ext)) {

Typo 'number number' ? Also perhaps not accurate to say 'current version 
number', as opposed to something like 'a supported version number'.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D73891/new/

https://reviews.llvm.org/D73891



___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D62686: [RISCV] Add support for save/restore of callee-saved registers via libcalls

[Lewis Revill via Phabricator via cfe-commits]

lewis-revill updated this revision to Diff 242723.
lewis-revill added a comment.

Rebased


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D62686/new/

https://reviews.llvm.org/D62686

Files:
  clang/lib/Driver/ToolChains/Arch/RISCV.cpp
  clang/test/Driver/riscv-features.c
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
  llvm/lib/Target/RISCV/RISCVFrameLowering.h
  llvm/lib/Target/RISCV/RISCVMachineFunctionInfo.h
  llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
  llvm/lib/Target/RISCV/RISCVRegisterInfo.h
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/CodeGen/RISCV/saverestore.ll
  llvm/test/CodeGen/RISCV/shrinkwrap.ll

Index: llvm/test/CodeGen/RISCV/shrinkwrap.ll
===
--- llvm/test/CodeGen/RISCV/shrinkwrap.ll
+++ llvm/test/CodeGen/RISCV/shrinkwrap.ll
@@ -1,6 +1,8 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple riscv32 < %s | FileCheck %s -check-prefix=RV32I-NOSW
 ; RUN: llc -mtriple riscv32 -enable-shrink-wrap < %s | FileCheck %s -check-prefix=RV32I-SW
+; RUN: llc -mtriple riscv32 -enable-shrink-wrap -mattr=+save-restore < %s \
+; RUN: | FileCheck %s -check-prefix=RV32I-SW-SR
 
 
 declare void @abort()
@@ -29,6 +31,16 @@
 ; RV32I-SW-NEXT:addi sp, sp, -16
 ; RV32I-SW-NEXT:sw ra, 12(sp)
 ; RV32I-SW-NEXT:call abort
+;
+; RV32I-SW-SR-LABEL: eliminate_restore:
+; RV32I-SW-SR:   # %bb.0:
+; RV32I-SW-SR-NEXT:addi a1, zero, 32
+; RV32I-SW-SR-NEXT:bgeu a1, a0, .LBB0_2
+; RV32I-SW-SR-NEXT:  # %bb.1: # %if.end
+; RV32I-SW-SR-NEXT:ret
+; RV32I-SW-SR-NEXT:  .LBB0_2: # %if.then
+; RV32I-SW-SR-NEXT:call t0, __riscv_save_0
+; RV32I-SW-SR-NEXT:call abort
   %cmp = icmp ule i32 %n, 32
   br i1 %cmp, label %if.then, label %if.end
 
@@ -84,6 +96,23 @@
 ; RV32I-SW-NEXT:addi sp, sp, 16
 ; RV32I-SW-NEXT:  .LBB1_2: # %if.end
 ; RV32I-SW-NEXT:ret
+;
+; RV32I-SW-SR-LABEL: conditional_alloca:
+; RV32I-SW-SR:   # %bb.0:
+; RV32I-SW-SR-NEXT:addi a1, zero, 32
+; RV32I-SW-SR-NEXT:bltu a1, a0, .LBB1_2
+; RV32I-SW-SR-NEXT:  # %bb.1: # %if.then
+; RV32I-SW-SR-NEXT:call t0, __riscv_save_1
+; RV32I-SW-SR-NEXT:addi s0, sp, 16
+; RV32I-SW-SR-NEXT:addi a0, a0, 15
+; RV32I-SW-SR-NEXT:andi a0, a0, -16
+; RV32I-SW-SR-NEXT:sub a0, sp, a0
+; RV32I-SW-SR-NEXT:mv sp, a0
+; RV32I-SW-SR-NEXT:call notdead
+; RV32I-SW-SR-NEXT:addi sp, s0, -16
+; RV32I-SW-SR-NEXT:tail __riscv_restore_1
+; RV32I-SW-SR-NEXT:  .LBB1_2: # %if.end
+; RV32I-SW-SR-NEXT:ret
   %cmp = icmp ule i32 %n, 32
   br i1 %cmp, label %if.then, label %if.end
 
Index: llvm/test/CodeGen/RISCV/saverestore.ll
===
--- /dev/null
+++ llvm/test/CodeGen/RISCV/saverestore.ll
@@ -0,0 +1,299 @@
+; RUN: llc -mtriple=riscv32 < %s | FileCheck %s -check-prefix=RV32I
+; RUN: llc -mtriple=riscv64 < %s | FileCheck %s -check-prefix=RV64I
+; RUN: llc -mtriple=riscv32 -mattr=+save-restore < %s | FileCheck %s -check-prefix=RV32I-SR
+; RUN: llc -mtriple=riscv64 -mattr=+save-restore < %s | FileCheck %s -check-prefix=RV64I-SR
+; RUN: llc -mtriple=riscv32 -mattr=+f,+save-restore -target-abi=ilp32f < %s | FileCheck %s -check-prefix=RV32I-FP-SR
+; RUN: llc -mtriple=riscv64 -mattr=+f,+d,+save-restore -target-abi=lp64d < %s | FileCheck %s -check-prefix=RV64I-FP-SR
+
+; Check that the correct save/restore libcalls are generated.
+
+@var0 = global [18 x i32] zeroinitializer
+@var1 = global [24 x i32] zeroinitializer
+@var2 = global [30 x i32] zeroinitializer
+
+define void @callee_saved0() nounwind {
+; RV32I-LABEL: callee_saved0:
+; RV32I-NOT: call t0, __riscv_save
+; RV32I-NOT: tail __riscv_restore
+;
+; RV64I-LABEL: callee_saved0:
+; RV64I-NOT: call t0, __riscv_save
+; RV64I-NOT: tail __riscv_restore
+;
+; RV32I-SR-LABEL: callee_saved0:
+; RV32I-SR: call t0, __riscv_save_5
+; RV32I-SR: tail __riscv_restore_5
+;
+; RV64I-SR-LABEL: callee_saved0:
+; RV64I-SR: call t0, __riscv_save_5
+; RV64I-SR: tail __riscv_restore_5
+;
+; RV32I-FP-SR-LABEL: callee_saved0:
+; RV32I-FP-SR: call t0, __riscv_save_5
+; RV32I-FP-SR: tail __riscv_restore_5
+;
+; RV64I-FP-SR-LABEL: callee_saved0:
+; RV64I-FP-SR: call t0, __riscv_save_5
+; RV64I-FP-SR: tail __riscv_restore_5
+  %val = load [18 x i32], [18 x i32]* @var0
+  store volatile [18 x i32] %val, [18 x i32]* @var0
+  ret void
+}
+
+define void @callee_saved1() nounwind {
+; RV32I-LABEL: callee_saved1:
+; RV32I-NOT: call t0, __riscv_save
+; RV32I-NOT: tail __riscv_restore
+;
+; RV64I-LABEL: callee_saved1:
+; RV64I-NOT: call t0, __riscv_save
+; RV64I-NOT: tail __riscv_restore
+;
+; RV32I-SR-LABEL: callee_saved1:
+; RV32I-SR: call t0, __riscv_save_11
+; RV32I-SR: tail __riscv_restore_11
+;
+; RV64I-SR-LABEL: callee_saved1:
+; 

[PATCH] D62686: [RISCV] Add support for save/restore of callee-saved registers via libcalls

[Lewis Revill via Phabricator via cfe-commits]

lewis-revill added a comment.

In D62686#1820816 , @apazos wrote:

> Lewis, your latest patch looks good, we just had another run with no new 
> failures. But we know it will have issues with -g. So I think we should not 
> merge it yet. Do you have a version of the patch that creates the labels for 
> the compiler-generated save/restore lib calls, so that this optimization does 
> not depend on D71593 ? We could merge that 
> version then, and when D71593  is accepted, 
> you just have to rework/remove the label generation part of the patch.


I don't expect that would be possible without making changes to generic code 
anyway. Removing the framesetup flag from the libcalls when generating them 
would allow labels to be produced, but that would require making modifications 
to the logic of this patch which relies on the libcalls being annotated as such.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D62686/new/

https://reviews.llvm.org/D62686



___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D62686: [RISCV] Add support for save/restore of callee-saved registers via libcalls

[Lewis Revill via Phabricator via cfe-commits]

lewis-revill added a comment.

Should I wait for the comments to be resolved on D71593 
 before I commit this patch? Ideally if this 
patch makes it into a release then that bug fix should be there too.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D62686/new/

https://reviews.llvm.org/D62686



___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D62686: [RISCV] Add support for save/restore of callee-saved registers via libcalls

[Lewis Revill via Phabricator via cfe-commits]

lewis-revill added a comment.

In D62686#1808041 , @apazos wrote:

> Lewis, is the patch final? It would be good to merge it before the 10.0 
> release branch creation on Jan 15th


I would say so now.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D62686/new/

https://reviews.llvm.org/D62686



___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D62686: [RISCV] Add support for save/restore of callee-saved registers via libcalls

[Lewis Revill via Phabricator via cfe-commits]

lewis-revill updated this revision to Diff 237620.
lewis-revill added a comment.

Fix .cfi_offset signedness error.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D62686/new/

https://reviews.llvm.org/D62686

Files:
  clang/lib/Driver/ToolChains/Arch/RISCV.cpp
  clang/test/Driver/riscv-features.c
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
  llvm/lib/Target/RISCV/RISCVFrameLowering.h
  llvm/lib/Target/RISCV/RISCVMachineFunctionInfo.h
  llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
  llvm/lib/Target/RISCV/RISCVRegisterInfo.h
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/CodeGen/RISCV/saverestore.ll
  llvm/test/CodeGen/RISCV/shrinkwrap.ll

Index: llvm/test/CodeGen/RISCV/shrinkwrap.ll
===
--- llvm/test/CodeGen/RISCV/shrinkwrap.ll
+++ llvm/test/CodeGen/RISCV/shrinkwrap.ll
@@ -1,6 +1,8 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple riscv32 < %s | FileCheck %s -check-prefix=RV32I-NOSW
 ; RUN: llc -mtriple riscv32 -enable-shrink-wrap < %s | FileCheck %s -check-prefix=RV32I-SW
+; RUN: llc -mtriple riscv32 -enable-shrink-wrap -mattr=+save-restore < %s \
+; RUN: | FileCheck %s -check-prefix=RV32I-SW-SR
 
 
 declare void @abort()
@@ -29,6 +31,16 @@
 ; RV32I-SW-NEXT:addi sp, sp, -16
 ; RV32I-SW-NEXT:sw ra, 12(sp)
 ; RV32I-SW-NEXT:call abort
+;
+; RV32I-SW-SR-LABEL: eliminate_restore:
+; RV32I-SW-SR:   # %bb.0:
+; RV32I-SW-SR-NEXT:addi a1, zero, 32
+; RV32I-SW-SR-NEXT:bgeu a1, a0, .LBB0_2
+; RV32I-SW-SR-NEXT:  # %bb.1: # %if.end
+; RV32I-SW-SR-NEXT:ret
+; RV32I-SW-SR-NEXT:  .LBB0_2: # %if.then
+; RV32I-SW-SR-NEXT:call t0, __riscv_save_0
+; RV32I-SW-SR-NEXT:call abort
   %cmp = icmp ule i32 %n, 32
   br i1 %cmp, label %if.then, label %if.end
 
@@ -84,6 +96,23 @@
 ; RV32I-SW-NEXT:addi sp, sp, 16
 ; RV32I-SW-NEXT:  .LBB1_2: # %if.end
 ; RV32I-SW-NEXT:ret
+;
+; RV32I-SW-SR-LABEL: conditional_alloca:
+; RV32I-SW-SR:   # %bb.0:
+; RV32I-SW-SR-NEXT:addi a1, zero, 32
+; RV32I-SW-SR-NEXT:bltu a1, a0, .LBB1_2
+; RV32I-SW-SR-NEXT:  # %bb.1: # %if.then
+; RV32I-SW-SR-NEXT:call t0, __riscv_save_1
+; RV32I-SW-SR-NEXT:addi s0, sp, 16
+; RV32I-SW-SR-NEXT:addi a0, a0, 15
+; RV32I-SW-SR-NEXT:andi a0, a0, -16
+; RV32I-SW-SR-NEXT:sub a0, sp, a0
+; RV32I-SW-SR-NEXT:mv sp, a0
+; RV32I-SW-SR-NEXT:call notdead
+; RV32I-SW-SR-NEXT:addi sp, s0, -16
+; RV32I-SW-SR-NEXT:tail __riscv_restore_1
+; RV32I-SW-SR-NEXT:  .LBB1_2: # %if.end
+; RV32I-SW-SR-NEXT:ret
   %cmp = icmp ule i32 %n, 32
   br i1 %cmp, label %if.then, label %if.end
 
Index: llvm/test/CodeGen/RISCV/saverestore.ll
===
--- /dev/null
+++ llvm/test/CodeGen/RISCV/saverestore.ll
@@ -0,0 +1,299 @@
+; RUN: llc -mtriple=riscv32 < %s | FileCheck %s -check-prefix=RV32I
+; RUN: llc -mtriple=riscv64 < %s | FileCheck %s -check-prefix=RV64I
+; RUN: llc -mtriple=riscv32 -mattr=+save-restore < %s | FileCheck %s -check-prefix=RV32I-SR
+; RUN: llc -mtriple=riscv64 -mattr=+save-restore < %s | FileCheck %s -check-prefix=RV64I-SR
+; RUN: llc -mtriple=riscv32 -mattr=+f,+save-restore -target-abi=ilp32f < %s | FileCheck %s -check-prefix=RV32I-FP-SR
+; RUN: llc -mtriple=riscv64 -mattr=+f,+d,+save-restore -target-abi=lp64d < %s | FileCheck %s -check-prefix=RV64I-FP-SR
+
+; Check that the correct save/restore libcalls are generated.
+
+@var0 = global [18 x i32] zeroinitializer
+@var1 = global [24 x i32] zeroinitializer
+@var2 = global [30 x i32] zeroinitializer
+
+define void @callee_saved0() nounwind {
+; RV32I-LABEL: callee_saved0:
+; RV32I-NOT: call t0, __riscv_save
+; RV32I-NOT: tail __riscv_restore
+;
+; RV64I-LABEL: callee_saved0:
+; RV64I-NOT: call t0, __riscv_save
+; RV64I-NOT: tail __riscv_restore
+;
+; RV32I-SR-LABEL: callee_saved0:
+; RV32I-SR: call t0, __riscv_save_5
+; RV32I-SR: tail __riscv_restore_5
+;
+; RV64I-SR-LABEL: callee_saved0:
+; RV64I-SR: call t0, __riscv_save_5
+; RV64I-SR: tail __riscv_restore_5
+;
+; RV32I-FP-SR-LABEL: callee_saved0:
+; RV32I-FP-SR: call t0, __riscv_save_5
+; RV32I-FP-SR: tail __riscv_restore_5
+;
+; RV64I-FP-SR-LABEL: callee_saved0:
+; RV64I-FP-SR: call t0, __riscv_save_5
+; RV64I-FP-SR: tail __riscv_restore_5
+  %val = load [18 x i32], [18 x i32]* @var0
+  store volatile [18 x i32] %val, [18 x i32]* @var0
+  ret void
+}
+
+define void @callee_saved1() nounwind {
+; RV32I-LABEL: callee_saved1:
+; RV32I-NOT: call t0, __riscv_save
+; RV32I-NOT: tail __riscv_restore
+;
+; RV64I-LABEL: callee_saved1:
+; RV64I-NOT: call t0, __riscv_save
+; RV64I-NOT: tail __riscv_restore
+;
+; RV32I-SR-LABEL: callee_saved1:
+; RV32I-SR: call t0, __riscv_save_11
+; RV32I-SR: tail __riscv_restore_11
+;
+; 

[PATCH] D62686: [RISCV] Add support for save/restore of callee-saved registers via libcalls

[Lewis Revill via Phabricator via cfe-commits]

lewis-revill added a comment.

In D62686#1815158 , @pzheng wrote:

> I see the following .cfi_offset directives generated using @shiva0217's test 
> case. Any idea why the offset for ra is 536870908?
>
>   callt0, __riscv_save_0
>   .cfi_def_cfa_offset 16
>   .cfi_offset ra, 536870908
>   


Hmm I see this too I'll look into it.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D62686/new/

https://reviews.llvm.org/D62686



___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D62686: [RISCV] Add support for save/restore of callee-saved registers via libcalls

[Lewis Revill via Phabricator via cfe-commits]

lewis-revill updated this revision to Diff 234853.
lewis-revill added a comment.

Added .cfi_offset directives for registers saved by libcalls.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D62686/new/

https://reviews.llvm.org/D62686

Files:
  clang/lib/Driver/ToolChains/Arch/RISCV.cpp
  clang/test/Driver/riscv-features.c
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
  llvm/lib/Target/RISCV/RISCVFrameLowering.h
  llvm/lib/Target/RISCV/RISCVMachineFunctionInfo.h
  llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
  llvm/lib/Target/RISCV/RISCVRegisterInfo.h
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/CodeGen/RISCV/saverestore.ll
  llvm/test/CodeGen/RISCV/shrinkwrap.ll

Index: llvm/test/CodeGen/RISCV/shrinkwrap.ll
===
--- llvm/test/CodeGen/RISCV/shrinkwrap.ll
+++ llvm/test/CodeGen/RISCV/shrinkwrap.ll
@@ -1,6 +1,8 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple riscv32 < %s | FileCheck %s -check-prefix=RV32I-NOSW
 ; RUN: llc -mtriple riscv32 -enable-shrink-wrap < %s | FileCheck %s -check-prefix=RV32I-SW
+; RUN: llc -mtriple riscv32 -enable-shrink-wrap -mattr=+save-restore < %s \
+; RUN: | FileCheck %s -check-prefix=RV32I-SW-SR
 
 
 declare void @abort()
@@ -29,6 +31,16 @@
 ; RV32I-SW-NEXT:addi sp, sp, -16
 ; RV32I-SW-NEXT:sw ra, 12(sp)
 ; RV32I-SW-NEXT:call abort
+;
+; RV32I-SW-SR-LABEL: eliminate_restore:
+; RV32I-SW-SR:   # %bb.0:
+; RV32I-SW-SR-NEXT:addi a1, zero, 32
+; RV32I-SW-SR-NEXT:bgeu a1, a0, .LBB0_2
+; RV32I-SW-SR-NEXT:  # %bb.1: # %if.end
+; RV32I-SW-SR-NEXT:ret
+; RV32I-SW-SR-NEXT:  .LBB0_2: # %if.then
+; RV32I-SW-SR-NEXT:call t0, __riscv_save_0
+; RV32I-SW-SR-NEXT:call abort
   %cmp = icmp ule i32 %n, 32
   br i1 %cmp, label %if.then, label %if.end
 
@@ -84,6 +96,23 @@
 ; RV32I-SW-NEXT:addi sp, sp, 16
 ; RV32I-SW-NEXT:  .LBB1_2: # %if.end
 ; RV32I-SW-NEXT:ret
+;
+; RV32I-SW-SR-LABEL: conditional_alloca:
+; RV32I-SW-SR:   # %bb.0:
+; RV32I-SW-SR-NEXT:addi a1, zero, 32
+; RV32I-SW-SR-NEXT:bltu a1, a0, .LBB1_2
+; RV32I-SW-SR-NEXT:  # %bb.1: # %if.then
+; RV32I-SW-SR-NEXT:call t0, __riscv_save_1
+; RV32I-SW-SR-NEXT:addi s0, sp, 16
+; RV32I-SW-SR-NEXT:addi a0, a0, 15
+; RV32I-SW-SR-NEXT:andi a0, a0, -16
+; RV32I-SW-SR-NEXT:sub a0, sp, a0
+; RV32I-SW-SR-NEXT:mv sp, a0
+; RV32I-SW-SR-NEXT:call notdead
+; RV32I-SW-SR-NEXT:addi sp, s0, -16
+; RV32I-SW-SR-NEXT:tail __riscv_restore_1
+; RV32I-SW-SR-NEXT:  .LBB1_2: # %if.end
+; RV32I-SW-SR-NEXT:ret
   %cmp = icmp ule i32 %n, 32
   br i1 %cmp, label %if.then, label %if.end
 
Index: llvm/test/CodeGen/RISCV/saverestore.ll
===
--- /dev/null
+++ llvm/test/CodeGen/RISCV/saverestore.ll
@@ -0,0 +1,299 @@
+; RUN: llc -mtriple=riscv32 < %s | FileCheck %s -check-prefix=RV32I
+; RUN: llc -mtriple=riscv64 < %s | FileCheck %s -check-prefix=RV64I
+; RUN: llc -mtriple=riscv32 -mattr=+save-restore < %s | FileCheck %s -check-prefix=RV32I-SR
+; RUN: llc -mtriple=riscv64 -mattr=+save-restore < %s | FileCheck %s -check-prefix=RV64I-SR
+; RUN: llc -mtriple=riscv32 -mattr=+f,+save-restore -target-abi=ilp32f < %s | FileCheck %s -check-prefix=RV32I-FP-SR
+; RUN: llc -mtriple=riscv64 -mattr=+f,+d,+save-restore -target-abi=lp64d < %s | FileCheck %s -check-prefix=RV64I-FP-SR
+
+; Check that the correct save/restore libcalls are generated.
+
+@var0 = global [18 x i32] zeroinitializer
+@var1 = global [24 x i32] zeroinitializer
+@var2 = global [30 x i32] zeroinitializer
+
+define void @callee_saved0() nounwind {
+; RV32I-LABEL: callee_saved0:
+; RV32I-NOT: call t0, __riscv_save
+; RV32I-NOT: tail __riscv_restore
+;
+; RV64I-LABEL: callee_saved0:
+; RV64I-NOT: call t0, __riscv_save
+; RV64I-NOT: tail __riscv_restore
+;
+; RV32I-SR-LABEL: callee_saved0:
+; RV32I-SR: call t0, __riscv_save_5
+; RV32I-SR: tail __riscv_restore_5
+;
+; RV64I-SR-LABEL: callee_saved0:
+; RV64I-SR: call t0, __riscv_save_5
+; RV64I-SR: tail __riscv_restore_5
+;
+; RV32I-FP-SR-LABEL: callee_saved0:
+; RV32I-FP-SR: call t0, __riscv_save_5
+; RV32I-FP-SR: tail __riscv_restore_5
+;
+; RV64I-FP-SR-LABEL: callee_saved0:
+; RV64I-FP-SR: call t0, __riscv_save_5
+; RV64I-FP-SR: tail __riscv_restore_5
+  %val = load [18 x i32], [18 x i32]* @var0
+  store volatile [18 x i32] %val, [18 x i32]* @var0
+  ret void
+}
+
+define void @callee_saved1() nounwind {
+; RV32I-LABEL: callee_saved1:
+; RV32I-NOT: call t0, __riscv_save
+; RV32I-NOT: tail __riscv_restore
+;
+; RV64I-LABEL: callee_saved1:
+; RV64I-NOT: call t0, __riscv_save
+; RV64I-NOT: tail __riscv_restore
+;
+; RV32I-SR-LABEL: callee_saved1:
+; RV32I-SR: call t0, __riscv_save_11
+; RV32I-SR: tail 

[PATCH] D62686: [RISCV] Add support for save/restore of callee-saved registers via libcalls

[Lewis Revill via Phabricator via cfe-commits]

lewis-revill updated this revision to Diff 234842.
lewis-revill added a comment.

Fixed existing .cfi_offset offsets. Since these are frame-pointer based they 
also need to account for the libcall stack adjustment.

Currently working on adding .cfi_offset instructions for the registers saved by 
the libcall.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D62686/new/

https://reviews.llvm.org/D62686

Files:
  clang/lib/Driver/ToolChains/Arch/RISCV.cpp
  clang/test/Driver/riscv-features.c
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
  llvm/lib/Target/RISCV/RISCVFrameLowering.h
  llvm/lib/Target/RISCV/RISCVMachineFunctionInfo.h
  llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
  llvm/lib/Target/RISCV/RISCVRegisterInfo.h
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/CodeGen/RISCV/saverestore.ll
  llvm/test/CodeGen/RISCV/shrinkwrap.ll

Index: llvm/test/CodeGen/RISCV/shrinkwrap.ll
===
--- llvm/test/CodeGen/RISCV/shrinkwrap.ll
+++ llvm/test/CodeGen/RISCV/shrinkwrap.ll
@@ -1,6 +1,8 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple riscv32 < %s | FileCheck %s -check-prefix=RV32I-NOSW
 ; RUN: llc -mtriple riscv32 -enable-shrink-wrap < %s | FileCheck %s -check-prefix=RV32I-SW
+; RUN: llc -mtriple riscv32 -enable-shrink-wrap -mattr=+save-restore < %s \
+; RUN: | FileCheck %s -check-prefix=RV32I-SW-SR
 
 
 declare void @abort()
@@ -29,6 +31,16 @@
 ; RV32I-SW-NEXT:addi sp, sp, -16
 ; RV32I-SW-NEXT:sw ra, 12(sp)
 ; RV32I-SW-NEXT:call abort
+;
+; RV32I-SW-SR-LABEL: eliminate_restore:
+; RV32I-SW-SR:   # %bb.0:
+; RV32I-SW-SR-NEXT:addi a1, zero, 32
+; RV32I-SW-SR-NEXT:bgeu a1, a0, .LBB0_2
+; RV32I-SW-SR-NEXT:  # %bb.1: # %if.end
+; RV32I-SW-SR-NEXT:ret
+; RV32I-SW-SR-NEXT:  .LBB0_2: # %if.then
+; RV32I-SW-SR-NEXT:call t0, __riscv_save_0
+; RV32I-SW-SR-NEXT:call abort
   %cmp = icmp ule i32 %n, 32
   br i1 %cmp, label %if.then, label %if.end
 
@@ -84,6 +96,23 @@
 ; RV32I-SW-NEXT:addi sp, sp, 16
 ; RV32I-SW-NEXT:  .LBB1_2: # %if.end
 ; RV32I-SW-NEXT:ret
+;
+; RV32I-SW-SR-LABEL: conditional_alloca:
+; RV32I-SW-SR:   # %bb.0:
+; RV32I-SW-SR-NEXT:addi a1, zero, 32
+; RV32I-SW-SR-NEXT:bltu a1, a0, .LBB1_2
+; RV32I-SW-SR-NEXT:  # %bb.1: # %if.then
+; RV32I-SW-SR-NEXT:call t0, __riscv_save_1
+; RV32I-SW-SR-NEXT:addi s0, sp, 16
+; RV32I-SW-SR-NEXT:addi a0, a0, 15
+; RV32I-SW-SR-NEXT:andi a0, a0, -16
+; RV32I-SW-SR-NEXT:sub a0, sp, a0
+; RV32I-SW-SR-NEXT:mv sp, a0
+; RV32I-SW-SR-NEXT:call notdead
+; RV32I-SW-SR-NEXT:addi sp, s0, -16
+; RV32I-SW-SR-NEXT:tail __riscv_restore_1
+; RV32I-SW-SR-NEXT:  .LBB1_2: # %if.end
+; RV32I-SW-SR-NEXT:ret
   %cmp = icmp ule i32 %n, 32
   br i1 %cmp, label %if.then, label %if.end
 
Index: llvm/test/CodeGen/RISCV/saverestore.ll
===
--- /dev/null
+++ llvm/test/CodeGen/RISCV/saverestore.ll
@@ -0,0 +1,299 @@
+; RUN: llc -mtriple=riscv32 < %s | FileCheck %s -check-prefix=RV32I
+; RUN: llc -mtriple=riscv64 < %s | FileCheck %s -check-prefix=RV64I
+; RUN: llc -mtriple=riscv32 -mattr=+save-restore < %s | FileCheck %s -check-prefix=RV32I-SR
+; RUN: llc -mtriple=riscv64 -mattr=+save-restore < %s | FileCheck %s -check-prefix=RV64I-SR
+; RUN: llc -mtriple=riscv32 -mattr=+f,+save-restore -target-abi=ilp32f < %s | FileCheck %s -check-prefix=RV32I-FP-SR
+; RUN: llc -mtriple=riscv64 -mattr=+f,+d,+save-restore -target-abi=lp64d < %s | FileCheck %s -check-prefix=RV64I-FP-SR
+
+; Check that the correct save/restore libcalls are generated.
+
+@var0 = global [18 x i32] zeroinitializer
+@var1 = global [24 x i32] zeroinitializer
+@var2 = global [30 x i32] zeroinitializer
+
+define void @callee_saved0() nounwind {
+; RV32I-LABEL: callee_saved0:
+; RV32I-NOT: call t0, __riscv_save
+; RV32I-NOT: tail __riscv_restore
+;
+; RV64I-LABEL: callee_saved0:
+; RV64I-NOT: call t0, __riscv_save
+; RV64I-NOT: tail __riscv_restore
+;
+; RV32I-SR-LABEL: callee_saved0:
+; RV32I-SR: call t0, __riscv_save_5
+; RV32I-SR: tail __riscv_restore_5
+;
+; RV64I-SR-LABEL: callee_saved0:
+; RV64I-SR: call t0, __riscv_save_5
+; RV64I-SR: tail __riscv_restore_5
+;
+; RV32I-FP-SR-LABEL: callee_saved0:
+; RV32I-FP-SR: call t0, __riscv_save_5
+; RV32I-FP-SR: tail __riscv_restore_5
+;
+; RV64I-FP-SR-LABEL: callee_saved0:
+; RV64I-FP-SR: call t0, __riscv_save_5
+; RV64I-FP-SR: tail __riscv_restore_5
+  %val = load [18 x i32], [18 x i32]* @var0
+  store volatile [18 x i32] %val, [18 x i32]* @var0
+  ret void
+}
+
+define void @callee_saved1() nounwind {
+; RV32I-LABEL: callee_saved1:
+; RV32I-NOT: call t0, __riscv_save
+; RV32I-NOT: tail __riscv_restore
+;
+; RV64I-LABEL: callee_saved1:
+; RV64I-NOT: call t0, 

[PATCH] D62686: [RISCV] Add support for save/restore of callee-saved registers via libcalls

[Lewis Revill via Phabricator via cfe-commits]

lewis-revill updated this revision to Diff 234091.
lewis-revill added a comment.

Rebased and addressed StackSize vs RealStackSize error.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D62686/new/

https://reviews.llvm.org/D62686

Files:
  clang/lib/Driver/ToolChains/Arch/RISCV.cpp
  clang/test/Driver/riscv-features.c
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
  llvm/lib/Target/RISCV/RISCVFrameLowering.h
  llvm/lib/Target/RISCV/RISCVMachineFunctionInfo.h
  llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
  llvm/lib/Target/RISCV/RISCVRegisterInfo.h
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/CodeGen/RISCV/saverestore.ll
  llvm/test/CodeGen/RISCV/shrinkwrap.ll

Index: llvm/test/CodeGen/RISCV/shrinkwrap.ll
===
--- llvm/test/CodeGen/RISCV/shrinkwrap.ll
+++ llvm/test/CodeGen/RISCV/shrinkwrap.ll
@@ -1,6 +1,8 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple riscv32 < %s | FileCheck %s -check-prefix=RV32I-NOSW
 ; RUN: llc -mtriple riscv32 -enable-shrink-wrap < %s | FileCheck %s -check-prefix=RV32I-SW
+; RUN: llc -mtriple riscv32 -enable-shrink-wrap -mattr=+save-restore < %s \
+; RUN: | FileCheck %s -check-prefix=RV32I-SW-SR
 
 
 declare void @abort()
@@ -29,6 +31,16 @@
 ; RV32I-SW-NEXT:addi sp, sp, -16
 ; RV32I-SW-NEXT:sw ra, 12(sp)
 ; RV32I-SW-NEXT:call abort
+;
+; RV32I-SW-SR-LABEL: eliminate_restore:
+; RV32I-SW-SR:   # %bb.0:
+; RV32I-SW-SR-NEXT:addi a1, zero, 32
+; RV32I-SW-SR-NEXT:bgeu a1, a0, .LBB0_2
+; RV32I-SW-SR-NEXT:  # %bb.1: # %if.end
+; RV32I-SW-SR-NEXT:ret
+; RV32I-SW-SR-NEXT:  .LBB0_2: # %if.then
+; RV32I-SW-SR-NEXT:call t0, __riscv_save_0
+; RV32I-SW-SR-NEXT:call abort
   %cmp = icmp ule i32 %n, 32
   br i1 %cmp, label %if.then, label %if.end
 
@@ -84,6 +96,23 @@
 ; RV32I-SW-NEXT:addi sp, sp, 16
 ; RV32I-SW-NEXT:  .LBB1_2: # %if.end
 ; RV32I-SW-NEXT:ret
+;
+; RV32I-SW-SR-LABEL: conditional_alloca:
+; RV32I-SW-SR:   # %bb.0:
+; RV32I-SW-SR-NEXT:addi a1, zero, 32
+; RV32I-SW-SR-NEXT:bltu a1, a0, .LBB1_2
+; RV32I-SW-SR-NEXT:  # %bb.1: # %if.then
+; RV32I-SW-SR-NEXT:call t0, __riscv_save_1
+; RV32I-SW-SR-NEXT:addi s0, sp, 16
+; RV32I-SW-SR-NEXT:addi a0, a0, 15
+; RV32I-SW-SR-NEXT:andi a0, a0, -16
+; RV32I-SW-SR-NEXT:sub a0, sp, a0
+; RV32I-SW-SR-NEXT:mv sp, a0
+; RV32I-SW-SR-NEXT:call notdead
+; RV32I-SW-SR-NEXT:addi sp, s0, -16
+; RV32I-SW-SR-NEXT:tail __riscv_restore_1
+; RV32I-SW-SR-NEXT:  .LBB1_2: # %if.end
+; RV32I-SW-SR-NEXT:ret
   %cmp = icmp ule i32 %n, 32
   br i1 %cmp, label %if.then, label %if.end
 
Index: llvm/test/CodeGen/RISCV/saverestore.ll
===
--- /dev/null
+++ llvm/test/CodeGen/RISCV/saverestore.ll
@@ -0,0 +1,299 @@
+; RUN: llc -mtriple=riscv32 < %s | FileCheck %s -check-prefix=RV32I
+; RUN: llc -mtriple=riscv64 < %s | FileCheck %s -check-prefix=RV64I
+; RUN: llc -mtriple=riscv32 -mattr=+save-restore < %s | FileCheck %s -check-prefix=RV32I-SR
+; RUN: llc -mtriple=riscv64 -mattr=+save-restore < %s | FileCheck %s -check-prefix=RV64I-SR
+; RUN: llc -mtriple=riscv32 -mattr=+f,+save-restore -target-abi=ilp32f < %s | FileCheck %s -check-prefix=RV32I-FP-SR
+; RUN: llc -mtriple=riscv64 -mattr=+f,+d,+save-restore -target-abi=lp64d < %s | FileCheck %s -check-prefix=RV64I-FP-SR
+
+; Check that the correct save/restore libcalls are generated.
+
+@var0 = global [18 x i32] zeroinitializer
+@var1 = global [24 x i32] zeroinitializer
+@var2 = global [30 x i32] zeroinitializer
+
+define void @callee_saved0() nounwind {
+; RV32I-LABEL: callee_saved0:
+; RV32I-NOT: call t0, __riscv_save
+; RV32I-NOT: tail __riscv_restore
+;
+; RV64I-LABEL: callee_saved0:
+; RV64I-NOT: call t0, __riscv_save
+; RV64I-NOT: tail __riscv_restore
+;
+; RV32I-SR-LABEL: callee_saved0:
+; RV32I-SR: call t0, __riscv_save_5
+; RV32I-SR: tail __riscv_restore_5
+;
+; RV64I-SR-LABEL: callee_saved0:
+; RV64I-SR: call t0, __riscv_save_5
+; RV64I-SR: tail __riscv_restore_5
+;
+; RV32I-FP-SR-LABEL: callee_saved0:
+; RV32I-FP-SR: call t0, __riscv_save_5
+; RV32I-FP-SR: tail __riscv_restore_5
+;
+; RV64I-FP-SR-LABEL: callee_saved0:
+; RV64I-FP-SR: call t0, __riscv_save_5
+; RV64I-FP-SR: tail __riscv_restore_5
+  %val = load [18 x i32], [18 x i32]* @var0
+  store volatile [18 x i32] %val, [18 x i32]* @var0
+  ret void
+}
+
+define void @callee_saved1() nounwind {
+; RV32I-LABEL: callee_saved1:
+; RV32I-NOT: call t0, __riscv_save
+; RV32I-NOT: tail __riscv_restore
+;
+; RV64I-LABEL: callee_saved1:
+; RV64I-NOT: call t0, __riscv_save
+; RV64I-NOT: tail __riscv_restore
+;
+; RV32I-SR-LABEL: callee_saved1:
+; RV32I-SR: call t0, __riscv_save_11
+; RV32I-SR: tail 

[PATCH] D71553: [RISCV] Add Clang frontend support for Bitmanip extension

[Lewis Revill via Phabricator via cfe-commits]

lewis-revill added a comment.

Thanks Scott, it should be relatively easy to add tests for this in 
'clang/test/Preprocessor/riscv-target-features.c' if you could.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D71553/new/

https://reviews.llvm.org/D71553



___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D62686: [RISCV] Add support for save/restore of callee-saved registers via libcalls

[Lewis Revill via Phabricator via cfe-commits]

lewis-revill marked an inline comment as done.
lewis-revill added inline comments.



Comment at: llvm/lib/Target/RISCV/RISCVFrameLowering.cpp:289
   unsigned CFIIndex = MF.addFrameInst(
   MCCFIInstruction::createDefCfaOffset(nullptr, -StackSize));
   BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))

shiva0217 wrote:
> Should the -StackSize be -RealStackSize?
Looks like it, good catch.



Comment at: llvm/lib/Target/RISCV/RISCVFrameLowering.cpp:668
+.setMIFlag(MachineInstr::FrameSetup);
+
+// Add registers spilled in libcall as liveins.

shiva0217 wrote:
> GCC will generate stack adjustment and GPR callee saved CFIs for the save 
> libcalls. Should we do the same?
I'm not familiar with the use of the CFI offset stuff, though just to be sure, 
you're saying that in addition to the manually-added `.cfi_offset`s in the 
libcalls themselves we would want to add them in our frame too?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D62686/new/

https://reviews.llvm.org/D62686



___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D62686: [RISCV] Add support for save/restore of callee-saved registers via libcalls

[Lewis Revill via Phabricator via cfe-commits]

lewis-revill marked an inline comment as done.
lewis-revill added inline comments.



Comment at: llvm/lib/Target/RISCV/RISCVFrameLowering.cpp:667
+.addExternalSymbol(SpillLibCall, RISCVII::MO_CALL)
+.setMIFlag(MachineInstr::FrameSetup);
+

shiva0217 wrote:
> There is a case may trigger an assertion when compile with -O3 -g 
> -msave-restore if the libcall has FrameSetup flag.
>   int main(int a, char* argv[]) {
> exit(0);
> return 0;
>   }
Think I've found the cause of this. When 'DIFlagAllCallsDescribed' is set for 
the module LLVM attempts to provide call entry info DIEs for all calls, 
//including// this one that has been added by us. One detail of this is 
attempting to calculate the return PC value or offset for the call using a 
label that was assumed to be inserted after the call instruction.

However, while the attempt to add the call entry info doesn't check for the 
FrameSetup flag, the label was never inserted, since that code //does// check 
for the flag. Adding the missing check to avoid adding call entry info for 
calls marked as FrameSetup fixed this issue.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D62686/new/

https://reviews.llvm.org/D62686



___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D62686: [RISCV] Add support for save/restore of callee-saved registers via libcalls

[Lewis Revill via Phabricator via cfe-commits]

lewis-revill updated this revision to Diff 232702.
lewis-revill added a comment.

Rebased.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D62686/new/

https://reviews.llvm.org/D62686

Files:
  clang/lib/Driver/ToolChains/Arch/RISCV.cpp
  clang/test/Driver/riscv-features.c
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
  llvm/lib/Target/RISCV/RISCVFrameLowering.h
  llvm/lib/Target/RISCV/RISCVMachineFunctionInfo.h
  llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
  llvm/lib/Target/RISCV/RISCVRegisterInfo.h
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/CodeGen/RISCV/saverestore.ll
  llvm/test/CodeGen/RISCV/shrinkwrap.ll

Index: llvm/test/CodeGen/RISCV/shrinkwrap.ll
===
--- llvm/test/CodeGen/RISCV/shrinkwrap.ll
+++ llvm/test/CodeGen/RISCV/shrinkwrap.ll
@@ -1,6 +1,8 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple riscv32 < %s | FileCheck %s -check-prefix=RV32I-NOSW
 ; RUN: llc -mtriple riscv32 -enable-shrink-wrap < %s | FileCheck %s -check-prefix=RV32I-SW
+; RUN: llc -mtriple riscv32 -enable-shrink-wrap -mattr=+save-restore < %s \
+; RUN: | FileCheck %s -check-prefix=RV32I-SW-SR
 
 
 declare void @abort()
@@ -29,6 +31,16 @@
 ; RV32I-SW-NEXT:addi sp, sp, -16
 ; RV32I-SW-NEXT:sw ra, 12(sp)
 ; RV32I-SW-NEXT:call abort
+;
+; RV32I-SW-SR-LABEL: eliminate_restore:
+; RV32I-SW-SR:   # %bb.0:
+; RV32I-SW-SR-NEXT:addi a1, zero, 32
+; RV32I-SW-SR-NEXT:bgeu a1, a0, .LBB0_2
+; RV32I-SW-SR-NEXT:  # %bb.1: # %if.end
+; RV32I-SW-SR-NEXT:ret
+; RV32I-SW-SR-NEXT:  .LBB0_2: # %if.then
+; RV32I-SW-SR-NEXT:call t0, __riscv_save_0
+; RV32I-SW-SR-NEXT:call abort
   %cmp = icmp ule i32 %n, 32
   br i1 %cmp, label %if.then, label %if.end
 
@@ -84,6 +96,23 @@
 ; RV32I-SW-NEXT:addi sp, sp, 16
 ; RV32I-SW-NEXT:  .LBB1_2: # %if.end
 ; RV32I-SW-NEXT:ret
+;
+; RV32I-SW-SR-LABEL: conditional_alloca:
+; RV32I-SW-SR:   # %bb.0:
+; RV32I-SW-SR-NEXT:addi a1, zero, 32
+; RV32I-SW-SR-NEXT:bltu a1, a0, .LBB1_2
+; RV32I-SW-SR-NEXT:  # %bb.1: # %if.then
+; RV32I-SW-SR-NEXT:call t0, __riscv_save_1
+; RV32I-SW-SR-NEXT:addi s0, sp, 16
+; RV32I-SW-SR-NEXT:addi a0, a0, 15
+; RV32I-SW-SR-NEXT:andi a0, a0, -16
+; RV32I-SW-SR-NEXT:sub a0, sp, a0
+; RV32I-SW-SR-NEXT:mv sp, a0
+; RV32I-SW-SR-NEXT:call notdead
+; RV32I-SW-SR-NEXT:addi sp, s0, -16
+; RV32I-SW-SR-NEXT:tail __riscv_restore_1
+; RV32I-SW-SR-NEXT:  .LBB1_2: # %if.end
+; RV32I-SW-SR-NEXT:ret
   %cmp = icmp ule i32 %n, 32
   br i1 %cmp, label %if.then, label %if.end
 
Index: llvm/test/CodeGen/RISCV/saverestore.ll
===
--- /dev/null
+++ llvm/test/CodeGen/RISCV/saverestore.ll
@@ -0,0 +1,299 @@
+; RUN: llc -mtriple=riscv32 < %s | FileCheck %s -check-prefix=RV32I
+; RUN: llc -mtriple=riscv64 < %s | FileCheck %s -check-prefix=RV64I
+; RUN: llc -mtriple=riscv32 -mattr=+save-restore < %s | FileCheck %s -check-prefix=RV32I-SR
+; RUN: llc -mtriple=riscv64 -mattr=+save-restore < %s | FileCheck %s -check-prefix=RV64I-SR
+; RUN: llc -mtriple=riscv32 -mattr=+f,+save-restore -target-abi=ilp32f < %s | FileCheck %s -check-prefix=RV32I-FP-SR
+; RUN: llc -mtriple=riscv64 -mattr=+f,+d,+save-restore -target-abi=lp64d < %s | FileCheck %s -check-prefix=RV64I-FP-SR
+
+; Check that the correct save/restore libcalls are generated.
+
+@var0 = global [18 x i32] zeroinitializer
+@var1 = global [24 x i32] zeroinitializer
+@var2 = global [30 x i32] zeroinitializer
+
+define void @callee_saved0() nounwind {
+; RV32I-LABEL: callee_saved0:
+; RV32I-NOT: call t0, __riscv_save
+; RV32I-NOT: tail __riscv_restore
+;
+; RV64I-LABEL: callee_saved0:
+; RV64I-NOT: call t0, __riscv_save
+; RV64I-NOT: tail __riscv_restore
+;
+; RV32I-SR-LABEL: callee_saved0:
+; RV32I-SR: call t0, __riscv_save_5
+; RV32I-SR: tail __riscv_restore_5
+;
+; RV64I-SR-LABEL: callee_saved0:
+; RV64I-SR: call t0, __riscv_save_5
+; RV64I-SR: tail __riscv_restore_5
+;
+; RV32I-FP-SR-LABEL: callee_saved0:
+; RV32I-FP-SR: call t0, __riscv_save_5
+; RV32I-FP-SR: tail __riscv_restore_5
+;
+; RV64I-FP-SR-LABEL: callee_saved0:
+; RV64I-FP-SR: call t0, __riscv_save_5
+; RV64I-FP-SR: tail __riscv_restore_5
+  %val = load [18 x i32], [18 x i32]* @var0
+  store volatile [18 x i32] %val, [18 x i32]* @var0
+  ret void
+}
+
+define void @callee_saved1() nounwind {
+; RV32I-LABEL: callee_saved1:
+; RV32I-NOT: call t0, __riscv_save
+; RV32I-NOT: tail __riscv_restore
+;
+; RV64I-LABEL: callee_saved1:
+; RV64I-NOT: call t0, __riscv_save
+; RV64I-NOT: tail __riscv_restore
+;
+; RV32I-SR-LABEL: callee_saved1:
+; RV32I-SR: call t0, __riscv_save_11
+; RV32I-SR: tail __riscv_restore_11
+;
+; RV64I-SR-LABEL: callee_saved1:

[PATCH] D67661: [RISCV] Headers: Add Bitmanip extension Clang header files and rvintrin.h

[Lewis Revill via Phabricator via cfe-commits]

lewis-revill added inline comments.



Comment at: clang/lib/Headers/rv32bintrin-builtins.h:27
+_rv32_clz(const uint_xlen_t rs1) {
+  // Calling these builtins with 0 results in undefined behaviour.
+  if (rs1 == 0) {

Does GCC perform this check before calling the builtin?


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D67661/new/

https://reviews.llvm.org/D67661



___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D67661: [RISCV] Headers: Add Bitmanip extension Clang header files and rvintrin.h

[Lewis Revill via Phabricator via cfe-commits]

lewis-revill added a comment.

So I have a quick comment about this patch, perhaps it might help to get things 
moving again.

I'd like to see the actual frontend changes, IE separate from the header 
implementations, to be split into a separate patch. So we can have things like 
the __riscv_bitmanip macro and the target attribute parsing potentially landed 
sooner?


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D67661/new/

https://reviews.llvm.org/D67661



___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D62686: [RISCV] Add support for save/restore of callee-saved registers via libcalls

[Lewis Revill via Phabricator via cfe-commits]

lewis-revill added inline comments.



Comment at: llvm/lib/Target/RISCV/RISCVFrameLowering.cpp:278
   // Add CFI directives for callee-saved registers.
-  const std::vector  = MFI.getCalleeSavedInfo();
-  // Iterate over list of callee-saved registers and emit .cfi_restore
-  // directives.
-  for (const auto  : CSI) {
-Register Reg = Entry.getReg();
-unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createRestore(
-nullptr, RI->getDwarfRegNum(Reg, true)));
-BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
-.addCFIIndex(CFIIndex);
+  if (!CSI.empty()) {
+// Iterate over list of callee-saved registers and emit .cfi_restore

pzheng wrote:
> lewis-revill wrote:
> > lenary wrote:
> > > Nit: You shouldn't need this `if` statement - the for loop just won't 
> > > execute if CSI is empty, surely.
> > Good catch, thanks!
> Any chance this comment from @lenary is missed?
It appears this CFI code was removed since I last rebased.
But yes, just for posterity I did miss this comment!


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D62686/new/

https://reviews.llvm.org/D62686



___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D62686: [RISCV] Add support for save/restore of callee-saved registers via libcalls

[Lewis Revill via Phabricator via cfe-commits]

lewis-revill updated this revision to Diff 229485.
lewis-revill added a comment.

Rebased


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D62686/new/

https://reviews.llvm.org/D62686

Files:
  clang/lib/Driver/ToolChains/Arch/RISCV.cpp
  clang/test/Driver/riscv-features.c
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
  llvm/lib/Target/RISCV/RISCVFrameLowering.h
  llvm/lib/Target/RISCV/RISCVMachineFunctionInfo.h
  llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
  llvm/lib/Target/RISCV/RISCVRegisterInfo.h
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/CodeGen/RISCV/saverestore.ll
  llvm/test/CodeGen/RISCV/shrinkwrap.ll

Index: llvm/test/CodeGen/RISCV/shrinkwrap.ll
===
--- llvm/test/CodeGen/RISCV/shrinkwrap.ll
+++ llvm/test/CodeGen/RISCV/shrinkwrap.ll
@@ -1,6 +1,8 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple riscv32 < %s | FileCheck %s -check-prefix=RV32I-NOSW
 ; RUN: llc -mtriple riscv32 -enable-shrink-wrap < %s | FileCheck %s -check-prefix=RV32I-SW
+; RUN: llc -mtriple riscv32 -enable-shrink-wrap -mattr=+save-restore < %s \
+; RUN: | FileCheck %s -check-prefix=RV32I-SW-SR
 
 
 declare void @abort()
@@ -29,6 +31,16 @@
 ; RV32I-SW-NEXT:addi sp, sp, -16
 ; RV32I-SW-NEXT:sw ra, 12(sp)
 ; RV32I-SW-NEXT:call abort
+;
+; RV32I-SW-SR-LABEL: eliminate_restore:
+; RV32I-SW-SR:   # %bb.0:
+; RV32I-SW-SR-NEXT:addi a1, zero, 32
+; RV32I-SW-SR-NEXT:bgeu a1, a0, .LBB0_2
+; RV32I-SW-SR-NEXT:  # %bb.1: # %if.end
+; RV32I-SW-SR-NEXT:ret
+; RV32I-SW-SR-NEXT:  .LBB0_2: # %if.then
+; RV32I-SW-SR-NEXT:call t0, __riscv_save_0
+; RV32I-SW-SR-NEXT:call abort
   %cmp = icmp ule i32 %n, 32
   br i1 %cmp, label %if.then, label %if.end
 
@@ -84,6 +96,23 @@
 ; RV32I-SW-NEXT:addi sp, sp, 16
 ; RV32I-SW-NEXT:  .LBB1_2: # %if.end
 ; RV32I-SW-NEXT:ret
+;
+; RV32I-SW-SR-LABEL: conditional_alloca:
+; RV32I-SW-SR:   # %bb.0:
+; RV32I-SW-SR-NEXT:addi a1, zero, 32
+; RV32I-SW-SR-NEXT:bltu a1, a0, .LBB1_2
+; RV32I-SW-SR-NEXT:  # %bb.1: # %if.then
+; RV32I-SW-SR-NEXT:call t0, __riscv_save_1
+; RV32I-SW-SR-NEXT:addi s0, sp, 16
+; RV32I-SW-SR-NEXT:addi a0, a0, 15
+; RV32I-SW-SR-NEXT:andi a0, a0, -16
+; RV32I-SW-SR-NEXT:sub a0, sp, a0
+; RV32I-SW-SR-NEXT:mv sp, a0
+; RV32I-SW-SR-NEXT:call notdead
+; RV32I-SW-SR-NEXT:addi sp, s0, -16
+; RV32I-SW-SR-NEXT:tail __riscv_restore_1
+; RV32I-SW-SR-NEXT:  .LBB1_2: # %if.end
+; RV32I-SW-SR-NEXT:ret
   %cmp = icmp ule i32 %n, 32
   br i1 %cmp, label %if.then, label %if.end
 
Index: llvm/test/CodeGen/RISCV/saverestore.ll
===
--- /dev/null
+++ llvm/test/CodeGen/RISCV/saverestore.ll
@@ -0,0 +1,299 @@
+; RUN: llc -mtriple=riscv32 < %s | FileCheck %s -check-prefix=RV32I
+; RUN: llc -mtriple=riscv64 < %s | FileCheck %s -check-prefix=RV64I
+; RUN: llc -mtriple=riscv32 -mattr=+save-restore < %s | FileCheck %s -check-prefix=RV32I-SR
+; RUN: llc -mtriple=riscv64 -mattr=+save-restore < %s | FileCheck %s -check-prefix=RV64I-SR
+; RUN: llc -mtriple=riscv32 -mattr=+f,+save-restore -target-abi=ilp32f < %s | FileCheck %s -check-prefix=RV32I-FP-SR
+; RUN: llc -mtriple=riscv64 -mattr=+f,+d,+save-restore -target-abi=lp64d < %s | FileCheck %s -check-prefix=RV64I-FP-SR
+
+; Check that the correct save/restore libcalls are generated.
+
+@var0 = global [18 x i32] zeroinitializer
+@var1 = global [24 x i32] zeroinitializer
+@var2 = global [30 x i32] zeroinitializer
+
+define void @callee_saved0() nounwind {
+; RV32I-LABEL: callee_saved0:
+; RV32I-NOT: call t0, __riscv_save
+; RV32I-NOT: tail __riscv_restore
+;
+; RV64I-LABEL: callee_saved0:
+; RV64I-NOT: call t0, __riscv_save
+; RV64I-NOT: tail __riscv_restore
+;
+; RV32I-SR-LABEL: callee_saved0:
+; RV32I-SR: call t0, __riscv_save_5
+; RV32I-SR: tail __riscv_restore_5
+;
+; RV64I-SR-LABEL: callee_saved0:
+; RV64I-SR: call t0, __riscv_save_5
+; RV64I-SR: tail __riscv_restore_5
+;
+; RV32I-FP-SR-LABEL: callee_saved0:
+; RV32I-FP-SR: call t0, __riscv_save_5
+; RV32I-FP-SR: tail __riscv_restore_5
+;
+; RV64I-FP-SR-LABEL: callee_saved0:
+; RV64I-FP-SR: call t0, __riscv_save_5
+; RV64I-FP-SR: tail __riscv_restore_5
+  %val = load [18 x i32], [18 x i32]* @var0
+  store volatile [18 x i32] %val, [18 x i32]* @var0
+  ret void
+}
+
+define void @callee_saved1() nounwind {
+; RV32I-LABEL: callee_saved1:
+; RV32I-NOT: call t0, __riscv_save
+; RV32I-NOT: tail __riscv_restore
+;
+; RV64I-LABEL: callee_saved1:
+; RV64I-NOT: call t0, __riscv_save
+; RV64I-NOT: tail __riscv_restore
+;
+; RV32I-SR-LABEL: callee_saved1:
+; RV32I-SR: call t0, __riscv_save_11
+; RV32I-SR: tail __riscv_restore_11
+;
+; RV64I-SR-LABEL: callee_saved1:
+; 

[PATCH] D62686: [RISCV] Add support for save/restore of callee-saved registers via libcalls

[Lewis Revill via Phabricator via cfe-commits]

lewis-revill updated this revision to Diff 227512.
lewis-revill added a comment.
Herald added a subscriber: sameer.abuasal.

Rebased and merged D68644  into this patch - 
this patch already assumes shrink wrapping support anyway.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D62686/new/

https://reviews.llvm.org/D62686

Files:
  clang/lib/Driver/ToolChains/Arch/RISCV.cpp
  clang/test/Driver/riscv-features.c
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
  llvm/lib/Target/RISCV/RISCVFrameLowering.h
  llvm/lib/Target/RISCV/RISCVMachineFunctionInfo.h
  llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
  llvm/lib/Target/RISCV/RISCVRegisterInfo.h
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/CodeGen/RISCV/saverestore.ll
  llvm/test/CodeGen/RISCV/shrinkwrap.ll

Index: llvm/test/CodeGen/RISCV/shrinkwrap.ll
===
--- llvm/test/CodeGen/RISCV/shrinkwrap.ll
+++ llvm/test/CodeGen/RISCV/shrinkwrap.ll
@@ -1,6 +1,8 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple riscv32 < %s | FileCheck %s -check-prefix=RV32I-NOSW
 ; RUN: llc -mtriple riscv32 -enable-shrink-wrap < %s | FileCheck %s -check-prefix=RV32I-SW
+; RUN: llc -mtriple riscv32 -enable-shrink-wrap -mattr=+save-restore < %s \
+; RUN: | FileCheck %s -check-prefix=RV32I-SW-SR
 
 
 declare void @abort()
@@ -29,6 +31,16 @@
 ; RV32I-SW-NEXT:addi sp, sp, -16
 ; RV32I-SW-NEXT:sw ra, 12(sp)
 ; RV32I-SW-NEXT:call abort
+;
+; RV32I-SW-SR-LABEL: eliminate_restore:
+; RV32I-SW-SR:   # %bb.0:
+; RV32I-SW-SR-NEXT:addi a1, zero, 32
+; RV32I-SW-SR-NEXT:bgeu a1, a0, .LBB0_2
+; RV32I-SW-SR-NEXT:  # %bb.1: # %if.end
+; RV32I-SW-SR-NEXT:ret
+; RV32I-SW-SR-NEXT:  .LBB0_2: # %if.then
+; RV32I-SW-SR-NEXT:call t0, __riscv_save_0
+; RV32I-SW-SR-NEXT:call abort
   %cmp = icmp ule i32 %n, 32
   br i1 %cmp, label %if.then, label %if.end
 
@@ -84,6 +96,23 @@
 ; RV32I-SW-NEXT:addi sp, sp, 16
 ; RV32I-SW-NEXT:  .LBB1_2: # %if.end
 ; RV32I-SW-NEXT:ret
+;
+; RV32I-SW-SR-LABEL: conditional_alloca:
+; RV32I-SW-SR:   # %bb.0:
+; RV32I-SW-SR-NEXT:addi a1, zero, 32
+; RV32I-SW-SR-NEXT:bltu a1, a0, .LBB1_2
+; RV32I-SW-SR-NEXT:  # %bb.1: # %if.then
+; RV32I-SW-SR-NEXT:call t0, __riscv_save_1
+; RV32I-SW-SR-NEXT:addi s0, sp, 16
+; RV32I-SW-SR-NEXT:addi a0, a0, 15
+; RV32I-SW-SR-NEXT:andi a0, a0, -16
+; RV32I-SW-SR-NEXT:sub a0, sp, a0
+; RV32I-SW-SR-NEXT:mv sp, a0
+; RV32I-SW-SR-NEXT:call notdead
+; RV32I-SW-SR-NEXT:addi sp, s0, -16
+; RV32I-SW-SR-NEXT:tail __riscv_restore_1
+; RV32I-SW-SR-NEXT:  .LBB1_2: # %if.end
+; RV32I-SW-SR-NEXT:ret
   %cmp = icmp ule i32 %n, 32
   br i1 %cmp, label %if.then, label %if.end
 
Index: llvm/test/CodeGen/RISCV/saverestore.ll
===
--- /dev/null
+++ llvm/test/CodeGen/RISCV/saverestore.ll
@@ -0,0 +1,299 @@
+; RUN: llc -mtriple=riscv32 < %s | FileCheck %s -check-prefix=RV32I
+; RUN: llc -mtriple=riscv64 < %s | FileCheck %s -check-prefix=RV64I
+; RUN: llc -mtriple=riscv32 -mattr=+save-restore < %s | FileCheck %s -check-prefix=RV32I-SR
+; RUN: llc -mtriple=riscv64 -mattr=+save-restore < %s | FileCheck %s -check-prefix=RV64I-SR
+; RUN: llc -mtriple=riscv32 -mattr=+f,+save-restore -target-abi=ilp32f < %s | FileCheck %s -check-prefix=RV32I-FP-SR
+; RUN: llc -mtriple=riscv64 -mattr=+f,+d,+save-restore -target-abi=lp64d < %s | FileCheck %s -check-prefix=RV64I-FP-SR
+
+; Check that the correct save/restore libcalls are generated.
+
+@var0 = global [18 x i32] zeroinitializer
+@var1 = global [24 x i32] zeroinitializer
+@var2 = global [30 x i32] zeroinitializer
+
+define void @callee_saved0() nounwind {
+; RV32I-LABEL: callee_saved0:
+; RV32I-NOT: call t0, __riscv_save
+; RV32I-NOT: tail __riscv_restore
+;
+; RV64I-LABEL: callee_saved0:
+; RV64I-NOT: call t0, __riscv_save
+; RV64I-NOT: tail __riscv_restore
+;
+; RV32I-SR-LABEL: callee_saved0:
+; RV32I-SR: call t0, __riscv_save_5
+; RV32I-SR: tail __riscv_restore_5
+;
+; RV64I-SR-LABEL: callee_saved0:
+; RV64I-SR: call t0, __riscv_save_5
+; RV64I-SR: tail __riscv_restore_5
+;
+; RV32I-FP-SR-LABEL: callee_saved0:
+; RV32I-FP-SR: call t0, __riscv_save_5
+; RV32I-FP-SR: tail __riscv_restore_5
+;
+; RV64I-FP-SR-LABEL: callee_saved0:
+; RV64I-FP-SR: call t0, __riscv_save_5
+; RV64I-FP-SR: tail __riscv_restore_5
+  %val = load [18 x i32], [18 x i32]* @var0
+  store volatile [18 x i32] %val, [18 x i32]* @var0
+  ret void
+}
+
+define void @callee_saved1() nounwind {
+; RV32I-LABEL: callee_saved1:
+; RV32I-NOT: call t0, __riscv_save
+; RV32I-NOT: tail __riscv_restore
+;
+; RV64I-LABEL: callee_saved1:
+; RV64I-NOT: call t0, __riscv_save
+; RV64I-NOT: tail 

[PATCH] D62686: [RISCV] Add support for save/restore of callee-saved registers via libcalls

[Lewis Revill via Phabricator via cfe-commits]

lewis-revill updated this revision to Diff 226166.
lewis-revill added a comment.

Rebase on top of shrink wrapping patch.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D62686/new/

https://reviews.llvm.org/D62686

Files:
  clang/lib/Driver/ToolChains/Arch/RISCV.cpp
  clang/test/Driver/riscv-features.c
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
  llvm/lib/Target/RISCV/RISCVFrameLowering.h
  llvm/lib/Target/RISCV/RISCVMachineFunctionInfo.h
  llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
  llvm/lib/Target/RISCV/RISCVRegisterInfo.h
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/CodeGen/RISCV/saverestore.ll

Index: llvm/test/CodeGen/RISCV/saverestore.ll
===
--- /dev/null
+++ llvm/test/CodeGen/RISCV/saverestore.ll
@@ -0,0 +1,299 @@
+; RUN: llc -mtriple=riscv32 < %s | FileCheck %s -check-prefix=RV32I
+; RUN: llc -mtriple=riscv64 < %s | FileCheck %s -check-prefix=RV64I
+; RUN: llc -mtriple=riscv32 -mattr=+save-restore < %s | FileCheck %s -check-prefix=RV32I-SR
+; RUN: llc -mtriple=riscv64 -mattr=+save-restore < %s | FileCheck %s -check-prefix=RV64I-SR
+; RUN: llc -mtriple=riscv32 -mattr=+f,+save-restore -target-abi=ilp32f < %s | FileCheck %s -check-prefix=RV32I-FP-SR
+; RUN: llc -mtriple=riscv64 -mattr=+f,+d,+save-restore -target-abi=lp64d < %s | FileCheck %s -check-prefix=RV64I-FP-SR
+
+; Check that the correct save/restore libcalls are generated.
+
+@var0 = global [18 x i32] zeroinitializer
+@var1 = global [24 x i32] zeroinitializer
+@var2 = global [30 x i32] zeroinitializer
+
+define void @callee_saved0() nounwind {
+; RV32I-LABEL: callee_saved0:
+; RV32I-NOT: call t0, __riscv_save
+; RV32I-NOT: tail __riscv_restore
+;
+; RV64I-LABEL: callee_saved0:
+; RV64I-NOT: call t0, __riscv_save
+; RV64I-NOT: tail __riscv_restore
+;
+; RV32I-SR-LABEL: callee_saved0:
+; RV32I-SR: call t0, __riscv_save_5
+; RV32I-SR: tail __riscv_restore_5
+;
+; RV64I-SR-LABEL: callee_saved0:
+; RV64I-SR: call t0, __riscv_save_5
+; RV64I-SR: tail __riscv_restore_5
+;
+; RV32I-FP-SR-LABEL: callee_saved0:
+; RV32I-FP-SR: call t0, __riscv_save_5
+; RV32I-FP-SR: tail __riscv_restore_5
+;
+; RV64I-FP-SR-LABEL: callee_saved0:
+; RV64I-FP-SR: call t0, __riscv_save_5
+; RV64I-FP-SR: tail __riscv_restore_5
+  %val = load [18 x i32], [18 x i32]* @var0
+  store volatile [18 x i32] %val, [18 x i32]* @var0
+  ret void
+}
+
+define void @callee_saved1() nounwind {
+; RV32I-LABEL: callee_saved1:
+; RV32I-NOT: call t0, __riscv_save
+; RV32I-NOT: tail __riscv_restore
+;
+; RV64I-LABEL: callee_saved1:
+; RV64I-NOT: call t0, __riscv_save
+; RV64I-NOT: tail __riscv_restore
+;
+; RV32I-SR-LABEL: callee_saved1:
+; RV32I-SR: call t0, __riscv_save_11
+; RV32I-SR: tail __riscv_restore_11
+;
+; RV64I-SR-LABEL: callee_saved1:
+; RV64I-SR: call t0, __riscv_save_11
+; RV64I-SR: tail __riscv_restore_11
+;
+; RV32I-FP-SR-LABEL: callee_saved1:
+; RV32I-FP-SR: call t0, __riscv_save_11
+; RV32I-FP-SR: tail __riscv_restore_11
+;
+; RV64I-FP-SR-LABEL: callee_saved1:
+; RV64I-FP-SR: call t0, __riscv_save_11
+; RV64I-FP-SR: tail __riscv_restore_11
+  %val = load [24 x i32], [24 x i32]* @var1
+  store volatile [24 x i32] %val, [24 x i32]* @var1
+  ret void
+}
+
+define void @callee_saved2() nounwind {
+; RV32I-LABEL: callee_saved2:
+; RV32I-NOT: call t0, __riscv_save
+; RV32I-NOT: tail __riscv_restore
+;
+; RV64I-LABEL: callee_saved2:
+; RV64I-NOT: call t0, __riscv_save
+; RV64I-NOT: tail __riscv_restore
+;
+; RV32I-SR-LABEL: callee_saved2:
+; RV32I-SR: call t0, __riscv_save_12
+; RV32I-SR: tail __riscv_restore_12
+;
+; RV64I-SR-LABEL: callee_saved2:
+; RV64I-SR: call t0, __riscv_save_12
+; RV64I-SR: tail __riscv_restore_12
+;
+; RV32I-FP-SR-LABEL: callee_saved2:
+; RV32I-FP-SR: call t0, __riscv_save_12
+; RV32I-FP-SR: tail __riscv_restore_12
+;
+; RV64I-FP-SR-LABEL: callee_saved2:
+; RV64I-FP-SR: call t0, __riscv_save_12
+; RV64I-FP-SR: tail __riscv_restore_12
+  %val = load [30 x i32], [30 x i32]* @var2
+  store volatile [30 x i32] %val, [30 x i32]* @var2
+  ret void
+}
+
+; Check that floating point callee saved registers are still manually saved and
+; restored.
+
+define void @callee_saved_fp() nounwind {
+; RV32I-LABEL: callee_saved_fp:
+; RV32I-NOT: call t0, __riscv_save
+; RV32I-NOT: tail __riscv_restore
+;
+; RV64I-LABEL: callee_saved_fp:
+; RV64I-NOT: call t0, __riscv_save
+; RV64I-NOT: tail __riscv_restore
+;
+; RV32I-SR-LABEL: callee_saved_fp:
+; RV32I-SR: call t0, __riscv_save_7
+; RV32I-SR: tail __riscv_restore_7
+;
+; RV64I-SR-LABEL: callee_saved_fp:
+; RV64I-SR: call t0, __riscv_save_7
+; RV64I-SR: tail __riscv_restore_7
+;
+; 

[PATCH] D62686: [RISCV] Add support for save/restore of callee-saved registers via libcalls

[Lewis Revill via Phabricator via cfe-commits]

lewis-revill updated this revision to Diff 225230.
lewis-revill added a comment.

Disable the save/restore optimization when a function contains tail calls. 
Address various miscellaneous concerns with the patch. Update tests to include 
less redundant code when checking cases where save/restore libcalls are not 
used.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D62686/new/

https://reviews.llvm.org/D62686

Files:
  clang/lib/Driver/ToolChains/Arch/RISCV.cpp
  clang/test/Driver/riscv-features.c
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
  llvm/lib/Target/RISCV/RISCVFrameLowering.h
  llvm/lib/Target/RISCV/RISCVMachineFunctionInfo.h
  llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
  llvm/lib/Target/RISCV/RISCVRegisterInfo.h
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/CodeGen/RISCV/saverestore.ll

Index: llvm/test/CodeGen/RISCV/saverestore.ll
===
--- /dev/null
+++ llvm/test/CodeGen/RISCV/saverestore.ll
@@ -0,0 +1,299 @@
+; RUN: llc -mtriple=riscv32 < %s | FileCheck %s -check-prefix=RV32I
+; RUN: llc -mtriple=riscv64 < %s | FileCheck %s -check-prefix=RV64I
+; RUN: llc -mtriple=riscv32 -mattr=+save-restore < %s | FileCheck %s -check-prefix=RV32I-SR
+; RUN: llc -mtriple=riscv64 -mattr=+save-restore < %s | FileCheck %s -check-prefix=RV64I-SR
+; RUN: llc -mtriple=riscv32 -mattr=+f,+save-restore -target-abi=ilp32f < %s | FileCheck %s -check-prefix=RV32I-FP-SR
+; RUN: llc -mtriple=riscv64 -mattr=+f,+d,+save-restore -target-abi=lp64d < %s | FileCheck %s -check-prefix=RV64I-FP-SR
+
+; Check that the correct save/restore libcalls are generated.
+
+@var0 = global [18 x i32] zeroinitializer
+@var1 = global [24 x i32] zeroinitializer
+@var2 = global [30 x i32] zeroinitializer
+
+define void @callee_saved0() nounwind {
+; RV32I-LABEL: callee_saved0:
+; RV32I-NOT: call t0, __riscv_save
+; RV32I-NOT: tail __riscv_restore
+;
+; RV64I-LABEL: callee_saved0:
+; RV64I-NOT: call t0, __riscv_save
+; RV64I-NOT: tail __riscv_restore
+;
+; RV32I-SR-LABEL: callee_saved0:
+; RV32I-SR: call t0, __riscv_save_5
+; RV32I-SR: tail __riscv_restore_5
+;
+; RV64I-SR-LABEL: callee_saved0:
+; RV64I-SR: call t0, __riscv_save_5
+; RV64I-SR: tail __riscv_restore_5
+;
+; RV32I-FP-SR-LABEL: callee_saved0:
+; RV32I-FP-SR: call t0, __riscv_save_5
+; RV32I-FP-SR: tail __riscv_restore_5
+;
+; RV64I-FP-SR-LABEL: callee_saved0:
+; RV64I-FP-SR: call t0, __riscv_save_5
+; RV64I-FP-SR: tail __riscv_restore_5
+  %val = load [18 x i32], [18 x i32]* @var0
+  store volatile [18 x i32] %val, [18 x i32]* @var0
+  ret void
+}
+
+define void @callee_saved1() nounwind {
+; RV32I-LABEL: callee_saved1:
+; RV32I-NOT: call t0, __riscv_save
+; RV32I-NOT: tail __riscv_restore
+;
+; RV64I-LABEL: callee_saved1:
+; RV64I-NOT: call t0, __riscv_save
+; RV64I-NOT: tail __riscv_restore
+;
+; RV32I-SR-LABEL: callee_saved1:
+; RV32I-SR: call t0, __riscv_save_11
+; RV32I-SR: tail __riscv_restore_11
+;
+; RV64I-SR-LABEL: callee_saved1:
+; RV64I-SR: call t0, __riscv_save_11
+; RV64I-SR: tail __riscv_restore_11
+;
+; RV32I-FP-SR-LABEL: callee_saved1:
+; RV32I-FP-SR: call t0, __riscv_save_11
+; RV32I-FP-SR: tail __riscv_restore_11
+;
+; RV64I-FP-SR-LABEL: callee_saved1:
+; RV64I-FP-SR: call t0, __riscv_save_11
+; RV64I-FP-SR: tail __riscv_restore_11
+  %val = load [24 x i32], [24 x i32]* @var1
+  store volatile [24 x i32] %val, [24 x i32]* @var1
+  ret void
+}
+
+define void @callee_saved2() nounwind {
+; RV32I-LABEL: callee_saved2:
+; RV32I-NOT: call t0, __riscv_save
+; RV32I-NOT: tail __riscv_restore
+;
+; RV64I-LABEL: callee_saved2:
+; RV64I-NOT: call t0, __riscv_save
+; RV64I-NOT: tail __riscv_restore
+;
+; RV32I-SR-LABEL: callee_saved2:
+; RV32I-SR: call t0, __riscv_save_12
+; RV32I-SR: tail __riscv_restore_12
+;
+; RV64I-SR-LABEL: callee_saved2:
+; RV64I-SR: call t0, __riscv_save_12
+; RV64I-SR: tail __riscv_restore_12
+;
+; RV32I-FP-SR-LABEL: callee_saved2:
+; RV32I-FP-SR: call t0, __riscv_save_12
+; RV32I-FP-SR: tail __riscv_restore_12
+;
+; RV64I-FP-SR-LABEL: callee_saved2:
+; RV64I-FP-SR: call t0, __riscv_save_12
+; RV64I-FP-SR: tail __riscv_restore_12
+  %val = load [30 x i32], [30 x i32]* @var2
+  store volatile [30 x i32] %val, [30 x i32]* @var2
+  ret void
+}
+
+; Check that floating point callee saved registers are still manually saved and
+; restored.
+
+define void @callee_saved_fp() nounwind {
+; RV32I-LABEL: callee_saved_fp:
+; RV32I-NOT: call t0, __riscv_save
+; RV32I-NOT: tail __riscv_restore
+;
+; RV64I-LABEL: callee_saved_fp:
+; RV64I-NOT: call t0, __riscv_save
+; RV64I-NOT: tail __riscv_restore
+;
+; RV32I-SR-LABEL: callee_saved_fp:
+; RV32I-SR: call 

[PATCH] D62686: [RISCV] Add support for save/restore of callee-saved registers via libcalls

[Lewis Revill via Phabricator via cfe-commits]

lewis-revill added inline comments.



Comment at: llvm/test/CodeGen/RISCV/saverestore.ll:348
+
+; Check that functions with varargs do not use save/restore code
+

luismarques wrote:
> Maybe for these tests just put a -NOT check that __riscv_save_ isn't called?
Thanks, I realise it makes much more sense to do this for all the other 
'non-save-restore' checks too, since they don't actually check any save/restore 
behaviour.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D62686/new/

https://reviews.llvm.org/D62686



___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D62686: [RISCV] Add support for save/restore of callee-saved registers via libcalls

[Lewis Revill via Phabricator via cfe-commits]

lewis-revill added a comment.

In D62686#1708792 , @apazos wrote:

> Yes Eli thanks for pointing out  there are more scenarios that can fail.
>  It looks like the best solution is to permit both flags on, but then bail 
> out from doing this transformation if there is any type of tail call already 
> in the function.
>  This way we avoid messing with reverting tail calls back to regular calls.


Is it worth trying to disallow tail call optimization completely if this flag 
is enabled? I'm not sure what GCC does exactly. but this seems to be the 
behaviour.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D62686/new/

https://reviews.llvm.org/D62686



___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D62686: [RISCV] Add support for save/restore of callee-saved registers via libcalls

[Lewis Revill via Phabricator via cfe-commits]

lewis-revill updated this revision to Diff 223855.
lewis-revill added a comment.

Rebased to fix conflicts with recent split SP adjustments


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D62686/new/

https://reviews.llvm.org/D62686

Files:
  clang/lib/Driver/ToolChains/Arch/RISCV.cpp
  clang/test/Driver/riscv-features.c
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
  llvm/lib/Target/RISCV/RISCVFrameLowering.h
  llvm/lib/Target/RISCV/RISCVMachineFunctionInfo.h
  llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
  llvm/lib/Target/RISCV/RISCVRegisterInfo.h
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/CodeGen/RISCV/saverestore.ll

Index: llvm/test/CodeGen/RISCV/saverestore.ll
===
--- /dev/null
+++ llvm/test/CodeGen/RISCV/saverestore.ll
@@ -0,0 +1,640 @@
+; RUN: llc -mtriple=riscv32 < %s | FileCheck %s -check-prefix=RV32I
+; RUN: llc -mtriple=riscv64 < %s | FileCheck %s -check-prefix=RV64I
+; RUN: llc -mtriple=riscv32 -mattr=+save-restore < %s | FileCheck %s -check-prefix=RV32I-SR
+; RUN: llc -mtriple=riscv64 -mattr=+save-restore < %s | FileCheck %s -check-prefix=RV64I-SR
+; RUN: llc -mtriple=riscv32 -mattr=+f,+save-restore -target-abi=ilp32f < %s | FileCheck %s -check-prefix=RV32I-FP-SR
+; RUN: llc -mtriple=riscv64 -mattr=+f,+d,+save-restore -target-abi=lp64d < %s | FileCheck %s -check-prefix=RV64I-FP-SR
+
+; Check that the correct save/restore libcalls are generated.
+
+@var0 = global [18 x i32] zeroinitializer
+@var1 = global [24 x i32] zeroinitializer
+@var2 = global [30 x i32] zeroinitializer
+
+define void @callee_saved0() nounwind {
+; RV32I-LABEL: callee_saved0:
+; RV32I: addi sp, sp, -32
+; RV32I-NEXT:sw s0, 28(sp)
+; RV32I-NEXT:sw s1, 24(sp)
+; RV32I-NEXT:sw s2, 20(sp)
+; RV32I-NEXT:sw s3, 16(sp)
+; RV32I-NEXT:sw s4, 12(sp)
+; RV32I: lw s4, 12(sp)
+; RV32I-NEXT:lw s3, 16(sp)
+; RV32I-NEXT:lw s2, 20(sp)
+; RV32I-NEXT:lw s1, 24(sp)
+; RV32I-NEXT:lw s0, 28(sp)
+; RV32I-NEXT:addi sp, sp, 32
+; RV32I-NEXT:ret
+;
+; RV64I-LABEL: callee_saved0:
+; RV64I: addi sp, sp, -48
+; RV64I-NEXT:sd s0, 40(sp)
+; RV64I-NEXT:sd s1, 32(sp)
+; RV64I-NEXT:sd s2, 24(sp)
+; RV64I-NEXT:sd s3, 16(sp)
+; RV64I: ld s4, 8(sp)
+; RV64I-NEXT:ld s3, 16(sp)
+; RV64I-NEXT:ld s2, 24(sp)
+; RV64I-NEXT:ld s1, 32(sp)
+; RV64I-NEXT:ld s0, 40(sp)
+; RV64I-NEXT:addi sp, sp, 48
+; RV64I-NEXT:ret
+;
+; RV32I-SR-LABEL: callee_saved0:
+; RV32I-SR: call t0, __riscv_save_5
+; RV32I-SR: tail __riscv_restore_5
+;
+; RV64I-SR-LABEL: callee_saved0:
+; RV64I-SR: call t0, __riscv_save_5
+; RV64I-SR: tail __riscv_restore_5
+;
+; RV32I-FP-SR-LABEL: callee_saved0:
+; RV32I-FP-SR: call t0, __riscv_save_5
+; RV32I-FP-SR: tail __riscv_restore_5
+;
+; RV64I-FP-SR-LABEL: callee_saved0:
+; RV64I-FP-SR: call t0, __riscv_save_5
+; RV64I-FP-SR: tail __riscv_restore_5
+  %val = load [18 x i32], [18 x i32]* @var0
+  store volatile [18 x i32] %val, [18 x i32]* @var0
+  ret void
+}
+
+define void @callee_saved1() nounwind {
+; RV32I-LABEL: callee_saved1:
+; RV32I: addi sp, sp, -48
+; RV32I-NEXT:sw s0, 44(sp)
+; RV32I-NEXT:sw s1, 40(sp)
+; RV32I-NEXT:sw s2, 36(sp)
+; RV32I-NEXT:sw s3, 32(sp)
+; RV32I-NEXT:sw s4, 28(sp)
+; RV32I-NEXT:sw s5, 24(sp)
+; RV32I-NEXT:sw s6, 20(sp)
+; RV32I-NEXT:sw s7, 16(sp)
+; RV32I-NEXT:sw s8, 12(sp)
+; RV32I-NEXT:sw s9, 8(sp)
+; RV32I-NEXT:sw s10, 4(sp)
+; RV32I: lw s10, 4(sp)
+; RV32I-NEXT:lw s9, 8(sp)
+; RV32I-NEXT:lw s8, 12(sp)
+; RV32I-NEXT:lw s7, 16(sp)
+; RV32I-NEXT:lw s6, 20(sp)
+; RV32I-NEXT:lw s5, 24(sp)
+; RV32I-NEXT:lw s4, 28(sp)
+; RV32I-NEXT:lw s3, 32(sp)
+; RV32I-NEXT:lw s2, 36(sp)
+; RV32I-NEXT:lw s1, 40(sp)
+; RV32I-NEXT:lw s0, 44(sp)
+; RV32I-NEXT:addi sp, sp, 48
+; RV32I-NEXT:ret
+;
+; RV64I-LABEL: callee_saved1:
+; RV64I: addi sp, sp, -96
+; RV64I-NEXT:sd s0, 88(sp)
+; RV64I-NEXT:sd s1, 80(sp)
+; RV64I-NEXT:sd s2, 72(sp)
+; RV64I-NEXT:sd s3, 64(sp)
+; RV64I-NEXT:sd s4, 56(sp)
+; RV64I-NEXT:sd s5, 48(sp)
+; RV64I-NEXT:sd s6, 40(sp)
+; RV64I-NEXT:sd s7, 32(sp)
+; RV64I-NEXT:sd s8, 24(sp)
+; RV64I-NEXT:sd s9, 16(sp)
+; RV64I-NEXT:sd s10, 8(sp)
+; RV64I: ld s10, 8(sp)
+; RV64I-NEXT:ld s9, 16(sp)
+; RV64I-NEXT:ld s8, 24(sp)
+; RV64I-NEXT:ld s7, 32(sp)
+; RV64I-NEXT:ld s6, 40(sp)
+; RV64I-NEXT:ld s5, 48(sp)
+; RV64I-NEXT:ld s4, 56(sp)
+; RV64I-NEXT:ld s3, 64(sp)
+; RV64I-NEXT:ld s2, 72(sp)
+; RV64I-NEXT:ld s1, 80(sp)
+; RV64I-NEXT:ld s0, 88(sp)
+; RV64I-NEXT:addi sp, sp, 96
+; RV64I-NEXT:ret
+;
+; RV32I-SR-LABEL: callee_saved1:
+; RV32I-SR: call t0, __riscv_save_11
+; RV32I-SR: 

[PATCH] D62686: [RISCV] Add support for save/restore of callee-saved registers via libcalls

[Lewis Revill via Phabricator via cfe-commits]

lewis-revill updated this revision to Diff 222612.
lewis-revill added a comment.

Rewrote logic to calculate stack sizes, frame indexes and frame pointer 
offsets. This was necessary to take into account the fact that the save/restore 
lib calls are essentially an opaque section of the stack that is inserted at 
the beginning of the frame, after positive offset objects such as fixed stack 
arguments, but before additional callee saved registers (IE FP registers) and 
negative offset (dynamic) objects. So calculations of the actual offsets of 
these objects must be adjusted accordingly for the stack to function correctly.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D62686/new/

https://reviews.llvm.org/D62686

Files:
  clang/lib/Driver/ToolChains/Arch/RISCV.cpp
  clang/test/Driver/riscv-features.c
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
  llvm/lib/Target/RISCV/RISCVFrameLowering.h
  llvm/lib/Target/RISCV/RISCVMachineFunctionInfo.h
  llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
  llvm/lib/Target/RISCV/RISCVRegisterInfo.h
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/CodeGen/RISCV/saverestore.ll

Index: llvm/test/CodeGen/RISCV/saverestore.ll
===
--- /dev/null
+++ llvm/test/CodeGen/RISCV/saverestore.ll
@@ -0,0 +1,640 @@
+; RUN: llc -mtriple=riscv32 < %s | FileCheck %s -check-prefix=RV32I
+; RUN: llc -mtriple=riscv64 < %s | FileCheck %s -check-prefix=RV64I
+; RUN: llc -mtriple=riscv32 -mattr=+save-restore < %s | FileCheck %s -check-prefix=RV32I-SR
+; RUN: llc -mtriple=riscv64 -mattr=+save-restore < %s | FileCheck %s -check-prefix=RV64I-SR
+; RUN: llc -mtriple=riscv32 -mattr=+f,+save-restore -target-abi=ilp32f < %s | FileCheck %s -check-prefix=RV32I-FP-SR
+; RUN: llc -mtriple=riscv64 -mattr=+f,+d,+save-restore -target-abi=lp64d < %s | FileCheck %s -check-prefix=RV64I-FP-SR
+
+; Check that the correct save/restore libcalls are generated.
+
+@var0 = global [18 x i32] zeroinitializer
+@var1 = global [24 x i32] zeroinitializer
+@var2 = global [30 x i32] zeroinitializer
+
+define void @callee_saved0() nounwind {
+; RV32I-LABEL: callee_saved0:
+; RV32I: addi sp, sp, -32
+; RV32I-NEXT:sw s0, 28(sp)
+; RV32I-NEXT:sw s1, 24(sp)
+; RV32I-NEXT:sw s2, 20(sp)
+; RV32I-NEXT:sw s3, 16(sp)
+; RV32I-NEXT:sw s4, 12(sp)
+; RV32I: lw s4, 12(sp)
+; RV32I-NEXT:lw s3, 16(sp)
+; RV32I-NEXT:lw s2, 20(sp)
+; RV32I-NEXT:lw s1, 24(sp)
+; RV32I-NEXT:lw s0, 28(sp)
+; RV32I-NEXT:addi sp, sp, 32
+; RV32I-NEXT:ret
+;
+; RV64I-LABEL: callee_saved0:
+; RV64I: addi sp, sp, -48
+; RV64I-NEXT:sd s0, 40(sp)
+; RV64I-NEXT:sd s1, 32(sp)
+; RV64I-NEXT:sd s2, 24(sp)
+; RV64I-NEXT:sd s3, 16(sp)
+; RV64I: ld s4, 8(sp)
+; RV64I-NEXT:ld s3, 16(sp)
+; RV64I-NEXT:ld s2, 24(sp)
+; RV64I-NEXT:ld s1, 32(sp)
+; RV64I-NEXT:ld s0, 40(sp)
+; RV64I-NEXT:addi sp, sp, 48
+; RV64I-NEXT:ret
+;
+; RV32I-SR-LABEL: callee_saved0:
+; RV32I-SR: call t0, __riscv_save_5
+; RV32I-SR: tail __riscv_restore_5
+;
+; RV64I-SR-LABEL: callee_saved0:
+; RV64I-SR: call t0, __riscv_save_5
+; RV64I-SR: tail __riscv_restore_5
+;
+; RV32I-FP-SR-LABEL: callee_saved0:
+; RV32I-FP-SR: call t0, __riscv_save_5
+; RV32I-FP-SR: tail __riscv_restore_5
+;
+; RV64I-FP-SR-LABEL: callee_saved0:
+; RV64I-FP-SR: call t0, __riscv_save_5
+; RV64I-FP-SR: tail __riscv_restore_5
+  %val = load [18 x i32], [18 x i32]* @var0
+  store volatile [18 x i32] %val, [18 x i32]* @var0
+  ret void
+}
+
+define void @callee_saved1() nounwind {
+; RV32I-LABEL: callee_saved1:
+; RV32I: addi sp, sp, -48
+; RV32I-NEXT:sw s0, 44(sp)
+; RV32I-NEXT:sw s1, 40(sp)
+; RV32I-NEXT:sw s2, 36(sp)
+; RV32I-NEXT:sw s3, 32(sp)
+; RV32I-NEXT:sw s4, 28(sp)
+; RV32I-NEXT:sw s5, 24(sp)
+; RV32I-NEXT:sw s6, 20(sp)
+; RV32I-NEXT:sw s7, 16(sp)
+; RV32I-NEXT:sw s8, 12(sp)
+; RV32I-NEXT:sw s9, 8(sp)
+; RV32I-NEXT:sw s10, 4(sp)
+; RV32I: lw s10, 4(sp)
+; RV32I-NEXT:lw s9, 8(sp)
+; RV32I-NEXT:lw s8, 12(sp)
+; RV32I-NEXT:lw s7, 16(sp)
+; RV32I-NEXT:lw s6, 20(sp)
+; RV32I-NEXT:lw s5, 24(sp)
+; RV32I-NEXT:lw s4, 28(sp)
+; RV32I-NEXT:lw s3, 32(sp)
+; RV32I-NEXT:lw s2, 36(sp)
+; RV32I-NEXT:lw s1, 40(sp)
+; RV32I-NEXT:lw s0, 44(sp)
+; RV32I-NEXT:addi sp, sp, 48
+; RV32I-NEXT:ret
+;
+; RV64I-LABEL: callee_saved1:
+; RV64I: addi sp, sp, -96
+; RV64I-NEXT:sd s0, 88(sp)
+; RV64I-NEXT:sd s1, 80(sp)
+; RV64I-NEXT:sd s2, 72(sp)
+; RV64I-NEXT:sd s3, 64(sp)
+; RV64I-NEXT:sd s4, 56(sp)
+; RV64I-NEXT:sd s5, 48(sp)
+; RV64I-NEXT:sd s6, 40(sp)
+; RV64I-NEXT:sd s7, 32(sp)
+; RV64I-NEXT:sd s8, 24(sp)
+; RV64I-NEXT:sd s9, 16(sp)
+; RV64I-NEXT:sd s10, 8(sp)
+; RV64I: ld 

[PATCH] D62686: [RISCV] Add support for save/restore of callee-saved registers via libcalls

[Lewis Revill via Phabricator via cfe-commits]

lewis-revill planned changes to this revision.
lewis-revill added a comment.

It seems like the regressions I'm seeing are due to the fact that calculating 
offsets for fixed objects at the top of the frame didn't account for extra 
stack size adjustment from the libcalls. I'm trying to find a neat way around 
this without breaking other calculations.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D62686/new/

https://reviews.llvm.org/D62686



___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D62686: [RISCV] Add support for save/restore of callee-saved registers via libcalls

[Lewis Revill via Phabricator via cfe-commits]

lewis-revill marked an inline comment as done.
lewis-revill added a comment.

In D62686#1675347 , @lenary wrote:

> We discussed this in the RISC-V meeting on 19 Sept 2019. @apazos says there 
> are some SPEC failures in both 2006 and 2017, which would be good to triage.


I've uncovered some execution failures in our annotated GCC testsuite as well, 
so I will look into those as a starting point.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D62686/new/

https://reviews.llvm.org/D62686



___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D62686: [RISCV] Add support for save/restore of callee-saved registers via libcalls

[Lewis Revill via Phabricator via cfe-commits]

lewis-revill marked 2 inline comments as done.
lewis-revill added inline comments.



Comment at: llvm/lib/Target/RISCV/RISCV.td:72
 
+def FeatureSaveRestore : SubtargetFeature<"save-restore", "EnableSaveRestore",
+  "true", "Enable save/restore.">;

lenary wrote:
> Given the clang option defaults to false, I think it should here too, to 
> avoid confusion in other frontends.
This is simply a case of a confusing parameter of the SubtargetFeature class.

SubtargetFeature interprets this "true" string as 'Value the attribute to be 
set to by feature'. IE: when the feature is enabled, what value should the 
corresponding RISCVSubtarget variable be set to? Rather than a default value 
for that variable.



Comment at: llvm/lib/Target/RISCV/RISCVFrameLowering.cpp:278
   // Add CFI directives for callee-saved registers.
-  const std::vector  = MFI.getCalleeSavedInfo();
-  // Iterate over list of callee-saved registers and emit .cfi_restore
-  // directives.
-  for (const auto  : CSI) {
-Register Reg = Entry.getReg();
-unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createRestore(
-nullptr, RI->getDwarfRegNum(Reg, true)));
-BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
-.addCFIIndex(CFIIndex);
+  if (!CSI.empty()) {
+// Iterate over list of callee-saved registers and emit .cfi_restore

lenary wrote:
> Nit: You shouldn't need this `if` statement - the for loop just won't execute 
> if CSI is empty, surely.
Good catch, thanks!


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D62686/new/

https://reviews.llvm.org/D62686



___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D62686: [RISCV] Add support for save/restore of callee-saved registers via libcalls

[Lewis Revill via Phabricator via cfe-commits]

lewis-revill updated this revision to Diff 220677.
lewis-revill added a comment.
Herald added a project: clang.
Herald added a subscriber: cfe-commits.

Replace internal -mllvm option with target feature enabled through the clang 
frontend using -msave-restore.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D62686/new/

https://reviews.llvm.org/D62686

Files:
  clang/lib/Driver/ToolChains/Arch/RISCV.cpp
  clang/test/Driver/riscv-features.c
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
  llvm/lib/Target/RISCV/RISCVFrameLowering.h
  llvm/lib/Target/RISCV/RISCVMachineFunctionInfo.h
  llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
  llvm/lib/Target/RISCV/RISCVRegisterInfo.h
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/CodeGen/RISCV/saverestore.ll

Index: llvm/test/CodeGen/RISCV/saverestore.ll
===
--- /dev/null
+++ llvm/test/CodeGen/RISCV/saverestore.ll
@@ -0,0 +1,640 @@
+; RUN: llc -mtriple=riscv32 < %s | FileCheck %s -check-prefix=RV32I
+; RUN: llc -mtriple=riscv64 < %s | FileCheck %s -check-prefix=RV64I
+; RUN: llc -mtriple=riscv32 -mattr=+save-restore < %s | FileCheck %s -check-prefix=RV32I-SR
+; RUN: llc -mtriple=riscv64 -mattr=+save-restore < %s | FileCheck %s -check-prefix=RV64I-SR
+; RUN: llc -mtriple=riscv32 -mattr=+f,+save-restore -target-abi=ilp32f < %s | FileCheck %s -check-prefix=RV32I-FP-SR
+; RUN: llc -mtriple=riscv64 -mattr=+f,+d,+save-restore -target-abi=lp64d < %s | FileCheck %s -check-prefix=RV64I-FP-SR
+
+; Check that the correct save/restore libcalls are generated.
+
+@var0 = global [18 x i32] zeroinitializer
+@var1 = global [24 x i32] zeroinitializer
+@var2 = global [30 x i32] zeroinitializer
+
+define void @callee_saved0() nounwind {
+; RV32I-LABEL: callee_saved0:
+; RV32I: addi sp, sp, -32
+; RV32I-NEXT:sw s0, 28(sp)
+; RV32I-NEXT:sw s1, 24(sp)
+; RV32I-NEXT:sw s2, 20(sp)
+; RV32I-NEXT:sw s3, 16(sp)
+; RV32I-NEXT:sw s4, 12(sp)
+; RV32I: lw s4, 12(sp)
+; RV32I-NEXT:lw s3, 16(sp)
+; RV32I-NEXT:lw s2, 20(sp)
+; RV32I-NEXT:lw s1, 24(sp)
+; RV32I-NEXT:lw s0, 28(sp)
+; RV32I-NEXT:addi sp, sp, 32
+; RV32I-NEXT:ret
+;
+; RV64I-LABEL: callee_saved0:
+; RV64I: addi sp, sp, -48
+; RV64I-NEXT:sd s0, 40(sp)
+; RV64I-NEXT:sd s1, 32(sp)
+; RV64I-NEXT:sd s2, 24(sp)
+; RV64I-NEXT:sd s3, 16(sp)
+; RV64I: ld s4, 8(sp)
+; RV64I-NEXT:ld s3, 16(sp)
+; RV64I-NEXT:ld s2, 24(sp)
+; RV64I-NEXT:ld s1, 32(sp)
+; RV64I-NEXT:ld s0, 40(sp)
+; RV64I-NEXT:addi sp, sp, 48
+; RV64I-NEXT:ret
+;
+; RV32I-SR-LABEL: callee_saved0:
+; RV32I-SR: call t0, __riscv_save_5
+; RV32I-SR: tail __riscv_restore_5
+;
+; RV64I-SR-LABEL: callee_saved0:
+; RV64I-SR: call t0, __riscv_save_5
+; RV64I-SR: tail __riscv_restore_5
+;
+; RV32I-FP-SR-LABEL: callee_saved0:
+; RV32I-FP-SR: call t0, __riscv_save_5
+; RV32I-FP-SR: tail __riscv_restore_5
+;
+; RV64I-FP-SR-LABEL: callee_saved0:
+; RV64I-FP-SR: call t0, __riscv_save_5
+; RV64I-FP-SR: tail __riscv_restore_5
+  %val = load [18 x i32], [18 x i32]* @var0
+  store volatile [18 x i32] %val, [18 x i32]* @var0
+  ret void
+}
+
+define void @callee_saved1() nounwind {
+; RV32I-LABEL: callee_saved1:
+; RV32I: addi sp, sp, -48
+; RV32I-NEXT:sw s0, 44(sp)
+; RV32I-NEXT:sw s1, 40(sp)
+; RV32I-NEXT:sw s2, 36(sp)
+; RV32I-NEXT:sw s3, 32(sp)
+; RV32I-NEXT:sw s4, 28(sp)
+; RV32I-NEXT:sw s5, 24(sp)
+; RV32I-NEXT:sw s6, 20(sp)
+; RV32I-NEXT:sw s7, 16(sp)
+; RV32I-NEXT:sw s8, 12(sp)
+; RV32I-NEXT:sw s9, 8(sp)
+; RV32I-NEXT:sw s10, 4(sp)
+; RV32I: lw s10, 4(sp)
+; RV32I-NEXT:lw s9, 8(sp)
+; RV32I-NEXT:lw s8, 12(sp)
+; RV32I-NEXT:lw s7, 16(sp)
+; RV32I-NEXT:lw s6, 20(sp)
+; RV32I-NEXT:lw s5, 24(sp)
+; RV32I-NEXT:lw s4, 28(sp)
+; RV32I-NEXT:lw s3, 32(sp)
+; RV32I-NEXT:lw s2, 36(sp)
+; RV32I-NEXT:lw s1, 40(sp)
+; RV32I-NEXT:lw s0, 44(sp)
+; RV32I-NEXT:addi sp, sp, 48
+; RV32I-NEXT:ret
+;
+; RV64I-LABEL: callee_saved1:
+; RV64I: addi sp, sp, -96
+; RV64I-NEXT:sd s0, 88(sp)
+; RV64I-NEXT:sd s1, 80(sp)
+; RV64I-NEXT:sd s2, 72(sp)
+; RV64I-NEXT:sd s3, 64(sp)
+; RV64I-NEXT:sd s4, 56(sp)
+; RV64I-NEXT:sd s5, 48(sp)
+; RV64I-NEXT:sd s6, 40(sp)
+; RV64I-NEXT:sd s7, 32(sp)
+; RV64I-NEXT:sd s8, 24(sp)
+; RV64I-NEXT:sd s9, 16(sp)
+; RV64I-NEXT:sd s10, 8(sp)
+; RV64I: ld s10, 8(sp)
+; RV64I-NEXT:ld s9, 16(sp)
+; RV64I-NEXT:ld s8, 24(sp)
+; RV64I-NEXT:ld s7, 32(sp)
+; RV64I-NEXT:ld s6, 40(sp)
+; RV64I-NEXT:ld s5, 48(sp)
+; RV64I-NEXT:ld s4, 56(sp)
+; RV64I-NEXT:ld s3, 64(sp)
+; RV64I-NEXT:ld s2, 72(sp)
+; RV64I-NEXT:ld s1, 80(sp)
+; RV64I-NEXT:ld s0, 88(sp)
+; RV64I-NEXT:addi sp, sp, 96
+; 

[PATCH] D67065: [RISCV] Define __riscv_cmodel_medlow and __riscv_cmodel_medany correctly

[Lewis Revill via Phabricator via cfe-commits]

lewis-revill accepted this revision.
lewis-revill added a comment.
This revision is now accepted and ready to land.

Thanks Kito. This looks good to me.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D67065/new/

https://reviews.llvm.org/D67065



___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D54295: [RISCV] Add inline asm constraint A for RISC-V

[Lewis Revill via Phabricator via cfe-commits]

This revision was not accepted when it landed; it landed in state "Needs 
Review".
This revision was automatically updated to reflect the committed changes.
Closed by commit rL369093: [RISCV] Add inline asm constraint A for RISC-V 
(authored by lewis-revill, committed by ).

Changed prior to commit:
  https://reviews.llvm.org/D54295?vs=215414=215556#toc

Repository:
  rL LLVM

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D54295/new/

https://reviews.llvm.org/D54295

Files:
  cfe/trunk/lib/Basic/Targets/RISCV.cpp
  cfe/trunk/test/CodeGen/riscv-inline-asm.c


Index: cfe/trunk/lib/Basic/Targets/RISCV.cpp
===
--- cfe/trunk/lib/Basic/Targets/RISCV.cpp
+++ cfe/trunk/lib/Basic/Targets/RISCV.cpp
@@ -75,6 +75,10 @@
 // A floating-point register.
 Info.setAllowsRegister();
 return true;
+  case 'A':
+// An address that is held in a general-purpose register.
+Info.setAllowsMemory();
+return true;
   }
 }
 
Index: cfe/trunk/test/CodeGen/riscv-inline-asm.c
===
--- cfe/trunk/test/CodeGen/riscv-inline-asm.c
+++ cfe/trunk/test/CodeGen/riscv-inline-asm.c
@@ -38,3 +38,9 @@
 // CHECK: call void asm sideeffect "", "f"(double [[FLT_ARG]])
   asm volatile ("" :: "f"(d));
 }
+
+void test_A(int *p) {
+// CHECK-LABEL: define void @test_A(i32* %p)
+// CHECK: call void asm sideeffect "", "*A"(i32* %p)
+  asm volatile("" :: "A"(*p));
+}


Index: cfe/trunk/lib/Basic/Targets/RISCV.cpp
===
--- cfe/trunk/lib/Basic/Targets/RISCV.cpp
+++ cfe/trunk/lib/Basic/Targets/RISCV.cpp
@@ -75,6 +75,10 @@
 // A floating-point register.
 Info.setAllowsRegister();
 return true;
+  case 'A':
+// An address that is held in a general-purpose register.
+Info.setAllowsMemory();
+return true;
   }
 }
 
Index: cfe/trunk/test/CodeGen/riscv-inline-asm.c
===
--- cfe/trunk/test/CodeGen/riscv-inline-asm.c
+++ cfe/trunk/test/CodeGen/riscv-inline-asm.c
@@ -38,3 +38,9 @@
 // CHECK: call void asm sideeffect "", "f"(double [[FLT_ARG]])
   asm volatile ("" :: "f"(d));
 }
+
+void test_A(int *p) {
+// CHECK-LABEL: define void @test_A(i32* %p)
+// CHECK: call void asm sideeffect "", "*A"(i32* %p)
+  asm volatile("" :: "A"(*p));
+}
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D54295: [RISCV] Add inline asm constraint A for RISC-V

[Lewis Revill via Phabricator via cfe-commits]

lewis-revill updated this revision to Diff 215414.
lewis-revill edited the summary of this revision.
lewis-revill added a comment.
Herald added subscribers: s.egerton, lenary, MaskRay.

Rebased prior to commit.


Repository:
  rC Clang

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D54295/new/

https://reviews.llvm.org/D54295

Files:
  lib/Basic/Targets/RISCV.cpp
  test/CodeGen/riscv-inline-asm.c


Index: test/CodeGen/riscv-inline-asm.c
===
--- test/CodeGen/riscv-inline-asm.c
+++ test/CodeGen/riscv-inline-asm.c
@@ -38,3 +38,9 @@
 // CHECK: call void asm sideeffect "", "f"(double [[FLT_ARG]])
   asm volatile ("" :: "f"(d));
 }
+
+void test_A(int *p) {
+// CHECK-LABEL: define void @test_A(i32* %p)
+// CHECK: call void asm sideeffect "", "*A"(i32* %p)
+  asm volatile("" :: "A"(*p));
+}
Index: lib/Basic/Targets/RISCV.cpp
===
--- lib/Basic/Targets/RISCV.cpp
+++ lib/Basic/Targets/RISCV.cpp
@@ -75,6 +75,10 @@
 // A floating-point register.
 Info.setAllowsRegister();
 return true;
+  case 'A':
+// An address that is held in a general-purpose register.
+Info.setAllowsMemory();
+return true;
   }
 }
 


Index: test/CodeGen/riscv-inline-asm.c
===
--- test/CodeGen/riscv-inline-asm.c
+++ test/CodeGen/riscv-inline-asm.c
@@ -38,3 +38,9 @@
 // CHECK: call void asm sideeffect "", "f"(double [[FLT_ARG]])
   asm volatile ("" :: "f"(d));
 }
+
+void test_A(int *p) {
+// CHECK-LABEL: define void @test_A(i32* %p)
+// CHECK: call void asm sideeffect "", "*A"(i32* %p)
+  asm volatile("" :: "A"(*p));
+}
Index: lib/Basic/Targets/RISCV.cpp
===
--- lib/Basic/Targets/RISCV.cpp
+++ lib/Basic/Targets/RISCV.cpp
@@ -75,6 +75,10 @@
 // A floating-point register.
 Info.setAllowsRegister();
 return true;
+  case 'A':
+// An address that is held in a general-purpose register.
+Info.setAllowsMemory();
+return true;
   }
 }
 
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D57055: [RISCV] Mark TLS as supported

[Lewis Revill via Phabricator via cfe-commits]

This revision was not accepted when it landed; it landed in state "Needs 
Review".
This revision was automatically updated to reflect the committed changes.
Closed by commit rL363776: [RISCV] Mark TLS as supported (authored by 
lewis-revill, committed by ).
Herald added a project: LLVM.
Herald added a subscriber: llvm-commits.

Changed prior to commit:
  https://reviews.llvm.org/D57055?vs=185283=205523#toc

Repository:
  rL LLVM

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D57055/new/

https://reviews.llvm.org/D57055

Files:
  cfe/trunk/lib/Basic/Targets/RISCV.h
  cfe/trunk/test/CodeGen/thread-specifier.c


Index: cfe/trunk/test/CodeGen/thread-specifier.c
===
--- cfe/trunk/test/CodeGen/thread-specifier.c
+++ cfe/trunk/test/CodeGen/thread-specifier.c
@@ -1,4 +1,6 @@
 // RUN: %clang_cc1 -triple i686-pc-linux-gnu -emit-llvm -o - %s | FileCheck %s
+// RUN: %clang_cc1 -triple riscv32 -emit-llvm -o - %s | FileCheck %s
+// RUN: %clang_cc1 -triple riscv64 -emit-llvm -o - %s | FileCheck %s
 
 // CHECK: @b = external thread_local global
 // CHECK: @d.e = internal thread_local global
Index: cfe/trunk/lib/Basic/Targets/RISCV.h
===
--- cfe/trunk/lib/Basic/Targets/RISCV.h
+++ cfe/trunk/lib/Basic/Targets/RISCV.h
@@ -35,7 +35,6 @@
   RISCVTargetInfo(const llvm::Triple , const TargetOptions &)
   : TargetInfo(Triple), HasM(false), HasA(false), HasF(false),
 HasD(false), HasC(false) {
-TLSSupported = false;
 LongDoubleWidth = 128;
 LongDoubleAlign = 128;
 LongDoubleFormat = ::APFloat::IEEEquad();


Index: cfe/trunk/test/CodeGen/thread-specifier.c
===
--- cfe/trunk/test/CodeGen/thread-specifier.c
+++ cfe/trunk/test/CodeGen/thread-specifier.c
@@ -1,4 +1,6 @@
 // RUN: %clang_cc1 -triple i686-pc-linux-gnu -emit-llvm -o - %s | FileCheck %s
+// RUN: %clang_cc1 -triple riscv32 -emit-llvm -o - %s | FileCheck %s
+// RUN: %clang_cc1 -triple riscv64 -emit-llvm -o - %s | FileCheck %s
 
 // CHECK: @b = external thread_local global
 // CHECK: @d.e = internal thread_local global
Index: cfe/trunk/lib/Basic/Targets/RISCV.h
===
--- cfe/trunk/lib/Basic/Targets/RISCV.h
+++ cfe/trunk/lib/Basic/Targets/RISCV.h
@@ -35,7 +35,6 @@
   RISCVTargetInfo(const llvm::Triple , const TargetOptions &)
   : TargetInfo(Triple), HasM(false), HasA(false), HasF(false),
 HasD(false), HasC(false) {
-TLSSupported = false;
 LongDoubleWidth = 128;
 LongDoubleAlign = 128;
 LongDoubleFormat = ::APFloat::IEEEquad();
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D54295: [RISCV] Add inline asm constraint A for RISC-V

[Lewis Revill via Phabricator via cfe-commits]

lewis-revill updated this revision to Diff 204512.
lewis-revill retitled this revision from "[WIP, RISCV] Add inline asm 
constraint A for RISC-V" to "[RISCV] Add inline asm constraint A for RISC-V".
Herald added subscribers: Jim, benna, psnobl.

Repository:
  rC Clang

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D54295/new/

https://reviews.llvm.org/D54295

Files:
  lib/Basic/Targets/RISCV.cpp
  test/CodeGen/riscv-inline-asm.c


Index: test/CodeGen/riscv-inline-asm.c
===
--- test/CodeGen/riscv-inline-asm.c
+++ test/CodeGen/riscv-inline-asm.c
@@ -26,3 +26,9 @@
 // CHECK: call void asm sideeffect "", "K"(i32 0)
   asm volatile ("" :: "K"(0));
 }
+
+void test_A(int *p) {
+// CHECK-LABEL: define void @test_A(i32* %p)
+// CHECK: call void asm sideeffect "", "*A"(i32* %p)
+  asm volatile("" :: "A"(*p));
+}
Index: lib/Basic/Targets/RISCV.cpp
===
--- lib/Basic/Targets/RISCV.cpp
+++ lib/Basic/Targets/RISCV.cpp
@@ -56,6 +56,10 @@
 // A 5-bit unsigned immediate for CSR access instructions.
 Info.setRequiresImmediate(0, 31);
 return true;
+  case 'A':
+// An address that is held in a general-purpose register.
+Info.setAllowsMemory();
+return true;
   }
 }
 


Index: test/CodeGen/riscv-inline-asm.c
===
--- test/CodeGen/riscv-inline-asm.c
+++ test/CodeGen/riscv-inline-asm.c
@@ -26,3 +26,9 @@
 // CHECK: call void asm sideeffect "", "K"(i32 0)
   asm volatile ("" :: "K"(0));
 }
+
+void test_A(int *p) {
+// CHECK-LABEL: define void @test_A(i32* %p)
+// CHECK: call void asm sideeffect "", "*A"(i32* %p)
+  asm volatile("" :: "A"(*p));
+}
Index: lib/Basic/Targets/RISCV.cpp
===
--- lib/Basic/Targets/RISCV.cpp
+++ lib/Basic/Targets/RISCV.cpp
@@ -56,6 +56,10 @@
 // A 5-bit unsigned immediate for CSR access instructions.
 Info.setRequiresImmediate(0, 31);
 return true;
+  case 'A':
+// An address that is held in a general-purpose register.
+Info.setAllowsMemory();
+return true;
   }
 }
 
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D54091: [RISCV] Add inline asm constraints I, J & K for RISC-V

[Lewis Revill via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL363055: [RISCV] Add inline asm constraints I, J  K for 
RISC-V (authored by lewis-revill, committed by ).

Changed prior to commit:
  https://reviews.llvm.org/D54091?vs=203367=204043#toc

Repository:
  rL LLVM

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D54091/new/

https://reviews.llvm.org/D54091

Files:
  cfe/trunk/lib/Basic/Targets/RISCV.cpp
  cfe/trunk/lib/Basic/Targets/RISCV.h


Index: cfe/trunk/lib/Basic/Targets/RISCV.cpp
===
--- cfe/trunk/lib/Basic/Targets/RISCV.cpp
+++ cfe/trunk/lib/Basic/Targets/RISCV.cpp
@@ -39,6 +39,26 @@
   return llvm::makeArrayRef(GCCRegAliases);
 }
 
+bool RISCVTargetInfo::validateAsmConstraint(
+const char *, TargetInfo::ConstraintInfo ) const {
+  switch (*Name) {
+  default:
+return false;
+  case 'I':
+// A 12-bit signed immediate.
+Info.setRequiresImmediate(-2048, 2047);
+return true;
+  case 'J':
+// Integer zero.
+Info.setRequiresImmediate(0);
+return true;
+  case 'K':
+// A 5-bit unsigned immediate for CSR access instructions.
+Info.setRequiresImmediate(0, 31);
+return true;
+  }
+}
+
 void RISCVTargetInfo::getTargetDefines(const LangOptions ,
MacroBuilder ) const {
   Builder.defineMacro("__ELF__");
Index: cfe/trunk/lib/Basic/Targets/RISCV.h
===
--- cfe/trunk/lib/Basic/Targets/RISCV.h
+++ cfe/trunk/lib/Basic/Targets/RISCV.h
@@ -61,9 +61,7 @@
   ArrayRef getGCCRegAliases() const override;
 
   bool validateAsmConstraint(const char *,
- TargetInfo::ConstraintInfo ) const override {
-return false;
-  }
+ TargetInfo::ConstraintInfo ) const override;
 
   bool hasFeature(StringRef Feature) const override;
 


Index: cfe/trunk/lib/Basic/Targets/RISCV.cpp
===
--- cfe/trunk/lib/Basic/Targets/RISCV.cpp
+++ cfe/trunk/lib/Basic/Targets/RISCV.cpp
@@ -39,6 +39,26 @@
   return llvm::makeArrayRef(GCCRegAliases);
 }
 
+bool RISCVTargetInfo::validateAsmConstraint(
+const char *, TargetInfo::ConstraintInfo ) const {
+  switch (*Name) {
+  default:
+return false;
+  case 'I':
+// A 12-bit signed immediate.
+Info.setRequiresImmediate(-2048, 2047);
+return true;
+  case 'J':
+// Integer zero.
+Info.setRequiresImmediate(0);
+return true;
+  case 'K':
+// A 5-bit unsigned immediate for CSR access instructions.
+Info.setRequiresImmediate(0, 31);
+return true;
+  }
+}
+
 void RISCVTargetInfo::getTargetDefines(const LangOptions ,
MacroBuilder ) const {
   Builder.defineMacro("__ELF__");
Index: cfe/trunk/lib/Basic/Targets/RISCV.h
===
--- cfe/trunk/lib/Basic/Targets/RISCV.h
+++ cfe/trunk/lib/Basic/Targets/RISCV.h
@@ -61,9 +61,7 @@
   ArrayRef getGCCRegAliases() const override;
 
   bool validateAsmConstraint(const char *,
- TargetInfo::ConstraintInfo ) const override {
-return false;
-  }
+ TargetInfo::ConstraintInfo ) const override;
 
   bool hasFeature(StringRef Feature) const override;
 
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D54091: [RISCV] Add inline asm constraints I, J & K for RISC-V

[Lewis Revill via Phabricator via cfe-commits]

lewis-revill updated this revision to Diff 203367.
lewis-revill edited the summary of this revision.
lewis-revill added a comment.
Herald added a project: LLVM.
Herald added a subscriber: llvm-commits.

- Rebased and fixed test run line


Repository:
  rL LLVM

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D54091/new/

https://reviews.llvm.org/D54091

Files:
  lib/Basic/Targets/RISCV.cpp
  lib/Basic/Targets/RISCV.h
  test/CodeGen/riscv-inline-asm.c
  test/Sema/inline-asm-validate-riscv.c

Index: test/Sema/inline-asm-validate-riscv.c
===
--- /dev/null
+++ test/Sema/inline-asm-validate-riscv.c
@@ -0,0 +1,26 @@
+// RUN: %clang_cc1 -triple riscv32 -fsyntax-only -verify %s
+// RUN: %clang_cc1 -triple riscv64 -fsyntax-only -verify %s
+
+void I(int i) {
+  static const int BelowMin = -2049;
+  static const int AboveMax = 2048;
+  asm volatile ("" :: "I"(i)); // expected-error{{constraint 'I' expects an integer constant expression}}
+  asm volatile ("" :: "I"(BelowMin)); // expected-error{{value '-2049' out of range for constraint 'I'}}
+  asm volatile ("" :: "I"(AboveMax)); // expected-error{{value '2048' out of range for constraint 'I'}}
+}
+
+void J(int j) {
+  static const int BelowMin = -1;
+  static const int AboveMax = 1;
+  asm volatile ("" :: "J"(j)); // expected-error{{constraint 'J' expects an integer constant expression}}
+  asm volatile ("" :: "J"(BelowMin)); // expected-error{{value '-1' out of range for constraint 'J'}}
+  asm volatile ("" :: "J"(AboveMax)); // expected-error{{value '1' out of range for constraint 'J'}}
+}
+
+void K(int k) {
+  static const int BelowMin = -1;
+  static const int AboveMax = 32;
+  asm volatile ("" :: "K"(k)); // expected-error{{constraint 'K' expects an integer constant expression}}
+  asm volatile ("" :: "K"(BelowMin)); // expected-error{{value '-1' out of range for constraint 'K'}}
+  asm volatile ("" :: "K"(AboveMax)); // expected-error{{value '32' out of range for constraint 'K'}}
+}
Index: test/CodeGen/riscv-inline-asm.c
===
--- /dev/null
+++ test/CodeGen/riscv-inline-asm.c
@@ -0,0 +1,28 @@
+// RUN: %clang_cc1 -triple riscv32 -O2 -emit-llvm %s -o - \
+// RUN: | FileCheck %s
+// RUN: %clang_cc1 -triple riscv64 -O2 -emit-llvm %s -o - \
+// RUN: | FileCheck %s
+
+// Test RISC-V specific inline assembly constraints.
+
+void test_I() {
+// CHECK-LABEL: define void @test_I()
+// CHECK: call void asm sideeffect "", "I"(i32 2047)
+  asm volatile ("" :: "I"(2047));
+// CHECK: call void asm sideeffect "", "I"(i32 -2048)
+  asm volatile ("" :: "I"(-2048));
+}
+
+void test_J() {
+// CHECK-LABEL: define void @test_J()
+// CHECK: call void asm sideeffect "", "J"(i32 0)
+  asm volatile ("" :: "J"(0));
+}
+
+void test_K() {
+// CHECK-LABEL: define void @test_K()
+// CHECK: call void asm sideeffect "", "K"(i32 31)
+  asm volatile ("" :: "K"(31));
+// CHECK: call void asm sideeffect "", "K"(i32 0)
+  asm volatile ("" :: "K"(0));
+}
Index: lib/Basic/Targets/RISCV.h
===
--- lib/Basic/Targets/RISCV.h
+++ lib/Basic/Targets/RISCV.h
@@ -61,9 +61,7 @@
   ArrayRef getGCCRegAliases() const override;
 
   bool validateAsmConstraint(const char *,
- TargetInfo::ConstraintInfo ) const override {
-return false;
-  }
+ TargetInfo::ConstraintInfo ) const override;
 
   bool hasFeature(StringRef Feature) const override;
 
Index: lib/Basic/Targets/RISCV.cpp
===
--- lib/Basic/Targets/RISCV.cpp
+++ lib/Basic/Targets/RISCV.cpp
@@ -39,6 +39,26 @@
   return llvm::makeArrayRef(GCCRegAliases);
 }
 
+bool RISCVTargetInfo::validateAsmConstraint(
+const char *, TargetInfo::ConstraintInfo ) const {
+  switch (*Name) {
+  default:
+return false;
+  case 'I':
+// A 12-bit signed immediate.
+Info.setRequiresImmediate(-2048, 2047);
+return true;
+  case 'J':
+// Integer zero.
+Info.setRequiresImmediate(0);
+return true;
+  case 'K':
+// A 5-bit unsigned immediate for CSR access instructions.
+Info.setRequiresImmediate(0, 31);
+return true;
+  }
+}
+
 void RISCVTargetInfo::getTargetDefines(const LangOptions ,
MacroBuilder ) const {
   Builder.defineMacro("__ELF__");
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D54295: [WIP, RISCV] Add inline asm constraint A for RISC-V

[Lewis Revill via Phabricator via cfe-commits]

lewis-revill updated this revision to Diff 187335.
lewis-revill added a comment.
Herald added subscribers: llvm-commits, jdoerfert.
Herald added a project: LLVM.

Correct test.


Repository:
  rL LLVM

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D54295/new/

https://reviews.llvm.org/D54295

Files:
  lib/Basic/Targets/RISCV.cpp
  test/CodeGen/riscv-inline-asm.c


Index: test/CodeGen/riscv-inline-asm.c
===
--- test/CodeGen/riscv-inline-asm.c
+++ test/CodeGen/riscv-inline-asm.c
@@ -26,3 +26,9 @@
 // CHECK: call void asm sideeffect "", "K"(i32 0)
   asm volatile ("" :: "K"(0));
 }
+
+void test_A(int *p) {
+// CHECK-LABEL: define void @test_A(i32* %p)
+// CHECK: call void asm sideeffect "", "*A"(i32* %p)
+  asm volatile("" :: "A"(*p));
+}
Index: lib/Basic/Targets/RISCV.cpp
===
--- lib/Basic/Targets/RISCV.cpp
+++ lib/Basic/Targets/RISCV.cpp
@@ -56,6 +56,10 @@
 // A 5-bit unsigned immediate for CSR access instructions.
 Info.setRequiresImmediate(0, 31);
 return true;
+  case 'A':
+// An address that is held in a general-purpose register.
+Info.setAllowsMemory();
+return true;
   }
 }
 


Index: test/CodeGen/riscv-inline-asm.c
===
--- test/CodeGen/riscv-inline-asm.c
+++ test/CodeGen/riscv-inline-asm.c
@@ -26,3 +26,9 @@
 // CHECK: call void asm sideeffect "", "K"(i32 0)
   asm volatile ("" :: "K"(0));
 }
+
+void test_A(int *p) {
+// CHECK-LABEL: define void @test_A(i32* %p)
+// CHECK: call void asm sideeffect "", "*A"(i32* %p)
+  asm volatile("" :: "A"(*p));
+}
Index: lib/Basic/Targets/RISCV.cpp
===
--- lib/Basic/Targets/RISCV.cpp
+++ lib/Basic/Targets/RISCV.cpp
@@ -56,6 +56,10 @@
 // A 5-bit unsigned immediate for CSR access instructions.
 Info.setRequiresImmediate(0, 31);
 return true;
+  case 'A':
+// An address that is held in a general-purpose register.
+Info.setAllowsMemory();
+return true;
   }
 }
 
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D57055: [RISCV] Mark TLS as supported

[Lewis Revill via Phabricator via cfe-commits]

lewis-revill updated this revision to Diff 185283.
lewis-revill added a comment.
Herald added a project: clang.

Added RISC-V to thread specifier test as a means of checking TLS is supported.


Repository:
  rC Clang

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D57055/new/

https://reviews.llvm.org/D57055

Files:
  lib/Basic/Targets/RISCV.h
  test/CodeGen/thread-specifier.c


Index: test/CodeGen/thread-specifier.c
===
--- test/CodeGen/thread-specifier.c
+++ test/CodeGen/thread-specifier.c
@@ -1,4 +1,6 @@
 // RUN: %clang_cc1 -triple i686-pc-linux-gnu -emit-llvm -o - %s | FileCheck %s
+// RUN: %clang_cc1 -triple riscv32 -emit-llvm -o - %s | FileCheck %s
+// RUN: %clang_cc1 -triple riscv64 -emit-llvm -o - %s | FileCheck %s
 
 // CHECK: @b = external thread_local global
 // CHECK: @d.e = internal thread_local global
Index: lib/Basic/Targets/RISCV.h
===
--- lib/Basic/Targets/RISCV.h
+++ lib/Basic/Targets/RISCV.h
@@ -35,7 +35,6 @@
   RISCVTargetInfo(const llvm::Triple , const TargetOptions &)
   : TargetInfo(Triple), HasM(false), HasA(false), HasF(false),
 HasD(false), HasC(false) {
-TLSSupported = false;
 LongDoubleWidth = 128;
 LongDoubleAlign = 128;
 LongDoubleFormat = ::APFloat::IEEEquad();


Index: test/CodeGen/thread-specifier.c
===
--- test/CodeGen/thread-specifier.c
+++ test/CodeGen/thread-specifier.c
@@ -1,4 +1,6 @@
 // RUN: %clang_cc1 -triple i686-pc-linux-gnu -emit-llvm -o - %s | FileCheck %s
+// RUN: %clang_cc1 -triple riscv32 -emit-llvm -o - %s | FileCheck %s
+// RUN: %clang_cc1 -triple riscv64 -emit-llvm -o - %s | FileCheck %s
 
 // CHECK: @b = external thread_local global
 // CHECK: @d.e = internal thread_local global
Index: lib/Basic/Targets/RISCV.h
===
--- lib/Basic/Targets/RISCV.h
+++ lib/Basic/Targets/RISCV.h
@@ -35,7 +35,6 @@
   RISCVTargetInfo(const llvm::Triple , const TargetOptions &)
   : TargetInfo(Triple), HasM(false), HasA(false), HasF(false),
 HasD(false), HasC(false) {
-TLSSupported = false;
 LongDoubleWidth = 128;
 LongDoubleAlign = 128;
 LongDoubleFormat = ::APFloat::IEEEquad();
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D57242: [RISCV] Specify MaxAtomicInlineWidth for RISC-V

[Lewis Revill via Phabricator via cfe-commits]

lewis-revill abandoned this revision.
lewis-revill added a comment.
Herald added a project: clang.

Abandoned in favour of D57450 


Repository:
  rC Clang

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D57242/new/

https://reviews.llvm.org/D57242



___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D57242: [RISCV] Specify MaxAtomicInlineWidth for RISC-V

[Lewis Revill via Phabricator via cfe-commits]

lewis-revill created this revision.
lewis-revill added a reviewer: asb.
Herald added subscribers: cfe-commits, jocewei, PkmX, jfb, rkruppe, the_o, 
brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, shiva0217, 
kito-cheng, niosHD, sabuasal, apazos, simoncook, johnrusso, rbar.

This prevents Clang from generating libcalls which are not necessary when the 
target has atomic support.


Repository:
  rC Clang

https://reviews.llvm.org/D57242

Files:
  lib/Basic/Targets/RISCV.h


Index: lib/Basic/Targets/RISCV.h
===
--- lib/Basic/Targets/RISCV.h
+++ lib/Basic/Targets/RISCV.h
@@ -77,6 +77,7 @@
 IntPtrType = SignedInt;
 PtrDiffType = SignedInt;
 SizeType = UnsignedInt;
+MaxAtomicInlineWidth = 32;
 resetDataLayout("e-m:e-p:32:32-i64:64-n32-S128");
   }
 
@@ -95,6 +96,7 @@
   : RISCVTargetInfo(Triple, Opts) {
 LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
 IntMaxType = Int64Type = SignedLong;
+MaxAtomicInlineWidth = 64;
 resetDataLayout("e-m:e-p:64:64-i64:64-i128:128-n64-S128");
   }
 


Index: lib/Basic/Targets/RISCV.h
===
--- lib/Basic/Targets/RISCV.h
+++ lib/Basic/Targets/RISCV.h
@@ -77,6 +77,7 @@
 IntPtrType = SignedInt;
 PtrDiffType = SignedInt;
 SizeType = UnsignedInt;
+MaxAtomicInlineWidth = 32;
 resetDataLayout("e-m:e-p:32:32-i64:64-n32-S128");
   }
 
@@ -95,6 +96,7 @@
   : RISCVTargetInfo(Triple, Opts) {
 LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
 IntMaxType = Int64Type = SignedLong;
+MaxAtomicInlineWidth = 64;
 resetDataLayout("e-m:e-p:64:64-i64:64-i128:128-n64-S128");
   }
 
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D57055: [RISCV] Mark TLS as supported

[Lewis Revill via Phabricator via cfe-commits]

lewis-revill updated this revision to Diff 182920.
lewis-revill added a comment.

Rely on default value rather than explicitly marking `TLSSupported` as true.


Repository:
  rC Clang

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D57055/new/

https://reviews.llvm.org/D57055

Files:
  lib/Basic/Targets/RISCV.h


Index: lib/Basic/Targets/RISCV.h
===
--- lib/Basic/Targets/RISCV.h
+++ lib/Basic/Targets/RISCV.h
@@ -36,7 +36,6 @@
   RISCVTargetInfo(const llvm::Triple , const TargetOptions &)
   : TargetInfo(Triple), HasM(false), HasA(false), HasF(false),
 HasD(false), HasC(false) {
-TLSSupported = false;
 LongDoubleWidth = 128;
 LongDoubleAlign = 128;
 LongDoubleFormat = ::APFloat::IEEEquad();


Index: lib/Basic/Targets/RISCV.h
===
--- lib/Basic/Targets/RISCV.h
+++ lib/Basic/Targets/RISCV.h
@@ -36,7 +36,6 @@
   RISCVTargetInfo(const llvm::Triple , const TargetOptions &)
   : TargetInfo(Triple), HasM(false), HasA(false), HasF(false),
 HasD(false), HasC(false) {
-TLSSupported = false;
 LongDoubleWidth = 128;
 LongDoubleAlign = 128;
 LongDoubleFormat = ::APFloat::IEEEquad();
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D57055: [RISCV] Mark TLS as supported

[Lewis Revill via Phabricator via cfe-commits]

lewis-revill created this revision.
lewis-revill added a reviewer: asb.
Herald added subscribers: cfe-commits, jocewei, PkmX, rkruppe, the_o, 
brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, shiva0217, 
kito-cheng, niosHD, sabuasal, apazos, simoncook, johnrusso, rbar.

Inform Clang that TLS is implemented by LLVM for RISC-V


Repository:
  rC Clang

https://reviews.llvm.org/D57055

Files:
  lib/Basic/Targets/RISCV.h


Index: lib/Basic/Targets/RISCV.h
===
--- lib/Basic/Targets/RISCV.h
+++ lib/Basic/Targets/RISCV.h
@@ -36,7 +36,7 @@
   RISCVTargetInfo(const llvm::Triple , const TargetOptions &)
   : TargetInfo(Triple), HasM(false), HasA(false), HasF(false),
 HasD(false), HasC(false) {
-TLSSupported = false;
+TLSSupported = true;
 LongDoubleWidth = 128;
 LongDoubleAlign = 128;
 LongDoubleFormat = ::APFloat::IEEEquad();


Index: lib/Basic/Targets/RISCV.h
===
--- lib/Basic/Targets/RISCV.h
+++ lib/Basic/Targets/RISCV.h
@@ -36,7 +36,7 @@
   RISCVTargetInfo(const llvm::Triple , const TargetOptions &)
   : TargetInfo(Triple), HasM(false), HasA(false), HasF(false),
 HasD(false), HasC(false) {
-TLSSupported = false;
+TLSSupported = true;
 LongDoubleWidth = 128;
 LongDoubleAlign = 128;
 LongDoubleFormat = ::APFloat::IEEEquad();
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D54091: [RISCV] Add inline asm constraints I, J & K for RISC-V

[Lewis Revill via Phabricator via cfe-commits]

lewis-revill updated this revision to Diff 174360.
lewis-revill edited the summary of this revision.
lewis-revill added a comment.

Updated to reflect desired changes (and fix an incorrect boundary). I didn't 
add r & m to riscv-inline-asm.c as I wasn't clear what exactly was desired.


Repository:
  rC Clang

https://reviews.llvm.org/D54091

Files:
  lib/Basic/Targets/RISCV.cpp
  lib/Basic/Targets/RISCV.h
  test/CodeGen/riscv-inline-asm.c
  test/Sema/inline-asm-validate-riscv.c

Index: test/Sema/inline-asm-validate-riscv.c
===
--- /dev/null
+++ test/Sema/inline-asm-validate-riscv.c
@@ -0,0 +1,26 @@
+// RUN: %clang_cc1 -triple riscv32 -fsyntax-only -verify %s
+// RUN: %clang_cc1 -triple riscv64 -fsyntax-only -verify %s
+
+void I(int i) {
+  static const int BelowMin = -2049;
+  static const int AboveMax = 2048;
+  asm volatile ("" :: "I"(i)); // expected-error{{constraint 'I' expects an integer constant expression}}
+  asm volatile ("" :: "I"(BelowMin)); // expected-error{{value '-2049' out of range for constraint 'I'}}
+  asm volatile ("" :: "I"(AboveMax)); // expected-error{{value '2048' out of range for constraint 'I'}}
+}
+
+void J(int j) {
+  static const int BelowMin = -1;
+  static const int AboveMax = 1;
+  asm volatile ("" :: "J"(j)); // expected-error{{constraint 'J' expects an integer constant expression}}
+  asm volatile ("" :: "J"(BelowMin)); // expected-error{{value '-1' out of range for constraint 'J'}}
+  asm volatile ("" :: "J"(AboveMax)); // expected-error{{value '1' out of range for constraint 'J'}}
+}
+
+void K(int k) {
+  static const int BelowMin = -1;
+  static const int AboveMax = 32;
+  asm volatile ("" :: "K"(k)); // expected-error{{constraint 'K' expects an integer constant expression}}
+  asm volatile ("" :: "K"(BelowMin)); // expected-error{{value '-1' out of range for constraint 'K'}}
+  asm volatile ("" :: "K"(AboveMax)); // expected-error{{value '32' out of range for constraint 'K'}}
+}
Index: test/CodeGen/riscv-inline-asm.c
===
--- /dev/null
+++ test/CodeGen/riscv-inline-asm.c
@@ -0,0 +1,28 @@
+// RUN: %clang_cc1 -triple riscv32 -target-feature +f -O2 -emit-llvm %s -o - \
+// RUN: | FileCheck %s
+// RUN: %clang_cc1 -triple riscv64 -target-feature +f -O2 -emit-llvm %s -o - \
+// RUN: | FileCheck %s
+
+// Test RISC-V specific inline assembly constraints.
+
+void test_I() {
+// CHECK-LABEL: define void @test_I()
+// CHECK: call void asm sideeffect "", "I"(i32 2047)
+  asm volatile ("" :: "I"(2047));
+// CHECK: call void asm sideeffect "", "I"(i32 -2048)
+  asm volatile ("" :: "I"(-2048));
+}
+
+void test_J() {
+// CHECK-LABEL: define void @test_J()
+// CHECK: call void asm sideeffect "", "J"(i32 0)
+  asm volatile ("" :: "J"(0));
+}
+
+void test_K() {
+// CHECK-LABEL: define void @test_K()
+// CHECK: call void asm sideeffect "", "K"(i32 31)
+  asm volatile ("" :: "K"(31));
+// CHECK: call void asm sideeffect "", "K"(i32 0)
+  asm volatile ("" :: "K"(0));
+}
Index: lib/Basic/Targets/RISCV.h
===
--- lib/Basic/Targets/RISCV.h
+++ lib/Basic/Targets/RISCV.h
@@ -62,9 +62,7 @@
   ArrayRef getGCCRegAliases() const override;
 
   bool validateAsmConstraint(const char *,
- TargetInfo::ConstraintInfo ) const override {
-return false;
-  }
+ TargetInfo::ConstraintInfo ) const override;
 
   bool hasFeature(StringRef Feature) const override;
 
Index: lib/Basic/Targets/RISCV.cpp
===
--- lib/Basic/Targets/RISCV.cpp
+++ lib/Basic/Targets/RISCV.cpp
@@ -40,6 +40,26 @@
   return llvm::makeArrayRef(GCCRegAliases);
 }
 
+bool RISCVTargetInfo::validateAsmConstraint(
+const char *, TargetInfo::ConstraintInfo ) const {
+  switch (*Name) {
+  default:
+return false;
+  case 'I':
+// A 12-bit signed immediate.
+Info.setRequiresImmediate(-2048, 2047);
+return true;
+  case 'J':
+// Integer zero.
+Info.setRequiresImmediate(0);
+return true;
+  case 'K':
+// A 5-bit unsigned immediate for CSR access instructions.
+Info.setRequiresImmediate(0, 31);
+return true;
+  }
+}
+
 void RISCVTargetInfo::getTargetDefines(const LangOptions ,
MacroBuilder ) const {
   Builder.defineMacro("__ELF__");
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D54295: [WIP, RISCV] Add inline asm constraint A for RISC-V

[Lewis Revill via Phabricator via cfe-commits]

lewis-revill created this revision.
lewis-revill added a reviewer: asb.
Herald added subscribers: cfe-commits, jocewei, PkmX, rkruppe, the_o, 
brucehoult, MartinMosbeck, rogfer01, mgrang, edward-jones, zzheng, jrtc27, 
shiva0217, kito-cheng, niosHD, sabuasal, apazos, simoncook, johnrusso, rbar, 
eraman.

This allows the constraint A to be used in inline asm for RISC-V, which allows 
an address held in a register to be used.

This patch adds the minimal amount of code required to get operands with the 
right constraints to compile. Semantically it would be nice to be able to use 
`setAllowsRegister` rather than `setAllowsMemory` and fall through to the 
backend to verify and lower the register as a memory operand.


Repository:
  rC Clang

https://reviews.llvm.org/D54295

Files:
  lib/Basic/Targets/RISCV.cpp
  test/CodeGen/riscv-inline-asm.c


Index: test/CodeGen/riscv-inline-asm.c
===
--- test/CodeGen/riscv-inline-asm.c
+++ test/CodeGen/riscv-inline-asm.c
@@ -26,3 +26,9 @@
 // CHECK: call void asm sideeffect "", "K"(i32 0)
   asm volatile ("" :: "K"(0));
 }
+
+void test_A(int *p) {
+// CHECK-LABEL: define void @test_A(i32* %p)
+// CHECK: call void asm volatile "", "*A"(i32* %p)
+  asm volatile("" :: "A"(*p));
+}
Index: lib/Basic/Targets/RISCV.cpp
===
--- lib/Basic/Targets/RISCV.cpp
+++ lib/Basic/Targets/RISCV.cpp
@@ -57,6 +57,10 @@
 // A 5-bit unsigned immediate for CSR access instructions.
 Info.setRequiresImmediate(0, 31);
 return true;
+  case 'A':
+// An address that is held in a general-purpose register.
+Info.setAllowsMemory();
+return true;
   }
 }
 


Index: test/CodeGen/riscv-inline-asm.c
===
--- test/CodeGen/riscv-inline-asm.c
+++ test/CodeGen/riscv-inline-asm.c
@@ -26,3 +26,9 @@
 // CHECK: call void asm sideeffect "", "K"(i32 0)
   asm volatile ("" :: "K"(0));
 }
+
+void test_A(int *p) {
+// CHECK-LABEL: define void @test_A(i32* %p)
+// CHECK: call void asm volatile "", "*A"(i32* %p)
+  asm volatile("" :: "A"(*p));
+}
Index: lib/Basic/Targets/RISCV.cpp
===
--- lib/Basic/Targets/RISCV.cpp
+++ lib/Basic/Targets/RISCV.cpp
@@ -57,6 +57,10 @@
 // A 5-bit unsigned immediate for CSR access instructions.
 Info.setRequiresImmediate(0, 31);
 return true;
+  case 'A':
+// An address that is held in a general-purpose register.
+Info.setAllowsMemory();
+return true;
   }
 }
 
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D54091: [RISCV] Add inline asm constraints I, J & K for RISC-V

[Lewis Revill via Phabricator via cfe-commits]

lewis-revill created this revision.
lewis-revill added a reviewer: asb.
Herald added subscribers: cfe-commits, jocewei, PkmX, rkruppe, the_o, 
brucehoult, MartinMosbeck, rogfer01, mgrang, edward-jones, zzheng, jrtc27, 
shiva0217, kito-cheng, niosHD, sabuasal, apazos, simoncook, johnrusso, rbar, 
eraman.

This allows the constraints I, J & K to be used in inline asm for RISC-V, with 
the following semantics (equivalent to GCC):

I: Any 12-bit signed immediate.
J: Immediate integer zero only.
K: Any 5-bit unsigned immediate.

Note that GCC also implements 'f' for floating point register and 'A' for 
address-only operand. These are not implemented here because:

1. It appears trivial to implement the floating point register constraint, 
however since floating point registers are not recognised by the calling 
convention the call to the inline asm node cannot be lowered.
2. I'm not yet certain how to implement an 'address-only' operand and I'd 
rather get the above constraints done first and add it later.


Repository:
  rC Clang

https://reviews.llvm.org/D54091

Files:
  lib/Basic/Targets/RISCV.cpp
  lib/Basic/Targets/RISCV.h
  test/CodeGen/riscv-inline-asm.c


Index: test/CodeGen/riscv-inline-asm.c
===
--- /dev/null
+++ test/CodeGen/riscv-inline-asm.c
@@ -0,0 +1,28 @@
+// RUN: %clang_cc1 -triple riscv32 -target-feature +f -O2 -emit-llvm %s -o - \
+// RUN: | FileCheck %s
+// RUN: %clang_cc1 -triple riscv64 -target-feature +f -O2 -emit-llvm %s -o - \
+// RUN: | FileCheck %s
+
+// Test RISC-V specific inline assembly constraints.
+
+void test_I() {
+// CHECK-LABEL: define void @test_I()
+// CHECK: call void asm sideeffect "", "I"(i32 2047)
+  asm volatile ("" :: "I"(2047));
+// CHECK: call void asm sideeffect "", "I"(i32 -2048)
+  asm volatile ("" :: "I"(-2048));
+}
+
+void test_J() {
+// CHECK-LABEL: define void @test_J()
+// CHECK: call void asm sideeffect "", "J"(i32 0)
+  asm volatile ("" :: "J"(0));
+}
+
+void test_K() {
+// CHECK-LABEL: define void @test_K()
+// CHECK: call void asm sideeffect "", "K"(i32 31)
+  asm volatile ("" :: "K"(31));
+// CHECK: call void asm sideeffect "", "K"(i32 0)
+  asm volatile ("" :: "K"(0));
+}
Index: lib/Basic/Targets/RISCV.h
===
--- lib/Basic/Targets/RISCV.h
+++ lib/Basic/Targets/RISCV.h
@@ -62,9 +62,7 @@
   ArrayRef getGCCRegAliases() const override;
 
   bool validateAsmConstraint(const char *,
- TargetInfo::ConstraintInfo ) const override {
-return false;
-  }
+ TargetInfo::ConstraintInfo ) const override;
 
   bool hasFeature(StringRef Feature) const override;
 
Index: lib/Basic/Targets/RISCV.cpp
===
--- lib/Basic/Targets/RISCV.cpp
+++ lib/Basic/Targets/RISCV.cpp
@@ -40,6 +40,26 @@
   return llvm::makeArrayRef(GCCRegAliases);
 }
 
+bool RISCVTargetInfo::validateAsmConstraint(
+const char *, TargetInfo::ConstraintInfo ) const {
+  switch (*Name) {
+  default:
+return false;
+  case 'I':
+// A 12-bit signed immediate.
+Info.setRequiresImmediate(-2048, 2048);
+return true;
+  case 'J':
+// Integer zero.
+Info.setRequiresImmediate(0);
+return true;
+  case 'K':
+// A 5-bit unsigned immediate for CSR access instructions.
+Info.setRequiresImmediate(0, 31);
+return true;
+  }
+}
+
 void RISCVTargetInfo::getTargetDefines(const LangOptions ,
MacroBuilder ) const {
   Builder.defineMacro("__ELF__");


Index: test/CodeGen/riscv-inline-asm.c
===
--- /dev/null
+++ test/CodeGen/riscv-inline-asm.c
@@ -0,0 +1,28 @@
+// RUN: %clang_cc1 -triple riscv32 -target-feature +f -O2 -emit-llvm %s -o - \
+// RUN: | FileCheck %s
+// RUN: %clang_cc1 -triple riscv64 -target-feature +f -O2 -emit-llvm %s -o - \
+// RUN: | FileCheck %s
+
+// Test RISC-V specific inline assembly constraints.
+
+void test_I() {
+// CHECK-LABEL: define void @test_I()
+// CHECK: call void asm sideeffect "", "I"(i32 2047)
+  asm volatile ("" :: "I"(2047));
+// CHECK: call void asm sideeffect "", "I"(i32 -2048)
+  asm volatile ("" :: "I"(-2048));
+}
+
+void test_J() {
+// CHECK-LABEL: define void @test_J()
+// CHECK: call void asm sideeffect "", "J"(i32 0)
+  asm volatile ("" :: "J"(0));
+}
+
+void test_K() {
+// CHECK-LABEL: define void @test_K()
+// CHECK: call void asm sideeffect "", "K"(i32 31)
+  asm volatile ("" :: "K"(31));
+// CHECK: call void asm sideeffect "", "K"(i32 0)
+  asm volatile ("" :: "K"(0));
+}
Index: lib/Basic/Targets/RISCV.h
===
--- lib/Basic/Targets/RISCV.h
+++ lib/Basic/Targets/RISCV.h
@@ -62,9 +62,7 @@
   ArrayRef getGCCRegAliases() const override;
 
   bool validateAsmConstraint(const char *,
- 

[PATCH] D51972: [RISCV] Explicitly set an empty --sysroot in the test

[Lewis Revill via Phabricator via cfe-commits]

lewis-revill added a comment.

Great, go ahead.


https://reviews.llvm.org/D51972



___
cfe-commits mailing list
cfe-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D51972: [RISCV] Explicitly set an empty --sysroot in the test

[Lewis Revill via Phabricator via cfe-commits]

lewis-revill added a comment.

@asb @kristina can we get this committed?


https://reviews.llvm.org/D51972



___
cfe-commits mailing list
cfe-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D51972: [RISCV] Explicitly set an empty --sysroot in the test

[Lewis Revill via Phabricator via cfe-commits]

lewis-revill accepted this revision.
lewis-revill added a comment.
This revision is now accepted and ready to land.

The reasoning seems sound for this testcase change. I think the behaviour of 
`computeSysRoot()` makes sense under this condition since it follows what the 
user specified, it's just not something I thought of when writing the tests for 
the previous patch.

Thanks


https://reviews.llvm.org/D51972



___
cfe-commits mailing list
cfe-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D50246: [RISCV] Add support for computing sysroot for riscv32-unknown-elf

[Lewis Revill via Phabricator via cfe-commits]

lewis-revill added a comment.

@asb can we get this committed?


Repository:
  rC Clang

https://reviews.llvm.org/D50246



___
cfe-commits mailing list
cfe-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D50246: [RISCV] Add support for computing sysroot for riscv32-unknown-elf

[Lewis Revill via Phabricator via cfe-commits]

lewis-revill updated this revision to Diff 163339.
lewis-revill added a comment.

Rebased and ensured that -fuse-init-array is always used (as intended in 
https://reviews.llvm.org/D50043), since addClangTargetOptions is overidden for 
this patch.


Repository:
  rC Clang

https://reviews.llvm.org/D50246

Files:
  lib/Driver/ToolChains/RISCV.cpp
  lib/Driver/ToolChains/RISCV.h
  test/Driver/riscv32-toolchain.c

Index: test/Driver/riscv32-toolchain.c
===
--- test/Driver/riscv32-toolchain.c
+++ test/Driver/riscv32-toolchain.c
@@ -19,14 +19,28 @@
 // C-RV32-BAREMETAL-ILP32: "--start-group" "-lc" "-lgloss" "--end-group" "-lgcc"
 // C-RV32-BAREMETAL-ILP32: "{{.*}}/Inputs/basic_riscv32_tree/lib/gcc/riscv32-unknown-elf/8.0.1{{/|}}crtend.o"
 
+// RUN: %clang %s -### -no-canonical-prefixes \
+// RUN:   -target riscv32-unknown-elf \
+// RUN:   --gcc-toolchain=%S/Inputs/basic_riscv32_tree 2>&1 \
+// RUN:   | FileCheck -check-prefix=C-RV32-BAREMETAL-NOSYSROOT-ILP32 %s
+
+// C-RV32-BAREMETAL-NOSYSROOT-ILP32: "-fuse-init-array"
+// C-RV32-BAREMETAL-NOSYSROOT-ILP32: "{{.*}}Inputs/basic_riscv32_tree/lib/gcc/riscv32-unknown-elf/8.0.1/../../../../bin{{/|}}riscv32-unknown-elf-ld"
+// C-RV32-BAREMETAL-NOSYSROOT-ILP32: "{{.*}}/Inputs/basic_riscv32_tree/lib/gcc/riscv32-unknown-elf/8.0.1/../../../../riscv32-unknown-elf/lib{{/|}}crt0.o"
+// C-RV32-BAREMETAL-NOSYSROOT-ILP32: "{{.*}}/Inputs/basic_riscv32_tree/lib/gcc/riscv32-unknown-elf/8.0.1{{/|}}crtbegin.o"
+// C-RV32-BAREMETAL-NOSYSROOT-ILP32: "-L{{.*}}/Inputs/basic_riscv32_tree/lib/gcc/riscv32-unknown-elf/8.0.1/../../../../riscv32-unknown-elf{{/|}}lib"
+// C-RV32-BAREMETAL-NOSYSROOT-ILP32: "-L{{.*}}/Inputs/basic_riscv32_tree/lib/gcc/riscv32-unknown-elf/8.0.1"
+// C-RV32-BAREMETAL-NOSYSROOT-ILP32: "--start-group" "-lc" "-lgloss" "--end-group" "-lgcc"
+// C-RV32-BAREMETAL-NOSYSROOT-ILP32: "{{.*}}/Inputs/basic_riscv32_tree/lib/gcc/riscv32-unknown-elf/8.0.1{{/|}}crtend.o"
+
 // RUN: %clangxx %s -### -no-canonical-prefixes \
 // RUN:   -target riscv32-unknown-elf -stdlib=libstdc++ \
 // RUN:   --gcc-toolchain=%S/Inputs/basic_riscv32_tree \
 // RUN:   --sysroot=%S/Inputs/basic_riscv32_tree/riscv32-unknown-elf 2>&1 \
 // RUN:   | FileCheck -check-prefix=CXX-RV32-BAREMETAL-ILP32 %s
 
 // CXX-RV32-BAREMETAL-ILP32: "-fuse-init-array"
-// CXX-RV32-BAREMETAL-ILP32: "-internal-isystem" "{{.*}}Inputs/basic_riscv32_tree/lib/gcc/riscv32-unknown-elf/8.0.1/../../../../riscv32-unknown-elf/include/c++{{/|}}8.0.1"
+// CXX-RV32-BAREMETAL-ILP32: "-internal-isystem" "{{.*}}Inputs/basic_riscv32_tree/riscv32-unknown-elf/include/c++{{/|}}8.0.1"
 // CXX-RV32-BAREMETAL-ILP32: "{{.*}}Inputs/basic_riscv32_tree/lib/gcc/riscv32-unknown-elf/8.0.1/../../../../bin{{/|}}riscv32-unknown-elf-ld"
 // CXX-RV32-BAREMETAL-ILP32: "--sysroot={{.*}}/Inputs/basic_riscv32_tree/riscv32-unknown-elf"
 // CXX-RV32-BAREMETAL-ILP32: "{{.*}}/Inputs/basic_riscv32_tree/riscv32-unknown-elf/lib{{/|}}crt0.o"
@@ -36,6 +50,21 @@
 // CXX-RV32-BAREMETAL-ILP32: "-lstdc++" "--start-group" "-lc" "-lgloss" "--end-group" "-lgcc"
 // CXX-RV32-BAREMETAL-ILP32: "{{.*}}/Inputs/basic_riscv32_tree/lib/gcc/riscv32-unknown-elf/8.0.1{{/|}}crtend.o"
 
+// RUN: %clangxx %s -### -no-canonical-prefixes \
+// RUN:   -target riscv32-unknown-elf -stdlib=libstdc++ \
+// RUN:   --gcc-toolchain=%S/Inputs/basic_riscv32_tree 2>&1 \
+// RUN:   | FileCheck -check-prefix=CXX-RV32-BAREMETAL-NOSYSROOT-ILP32 %s
+
+// CXX-RV32-BAREMETAL-NOSYSROOT-ILP32: "-fuse-init-array"
+// CXX-RV32-BAREMETAL-NOSYSROOT-ILP32: "-internal-isystem" "{{.*}}Inputs/basic_riscv32_tree/lib/gcc/riscv32-unknown-elf/8.0.1/../../../../riscv32-unknown-elf/include/c++{{/|}}8.0.1"
+// CXX-RV32-BAREMETAL-NOSYSROOT-ILP32: "{{.*}}Inputs/basic_riscv32_tree/lib/gcc/riscv32-unknown-elf/8.0.1/../../../../bin{{/|}}riscv32-unknown-elf-ld"
+// CXX-RV32-BAREMETAL-NOSYSROOT-ILP32: "{{.*}}/Inputs/basic_riscv32_tree/lib/gcc/riscv32-unknown-elf/8.0.1/../../../../riscv32-unknown-elf/lib{{/|}}crt0.o"
+// CXX-RV32-BAREMETAL-NOSYSROOT-ILP32: "{{.*}}/Inputs/basic_riscv32_tree/lib/gcc/riscv32-unknown-elf/8.0.1{{/|}}crtbegin.o"
+// CXX-RV32-BAREMETAL-NOSYSROOT-ILP32: "-L{{.*}}/Inputs/basic_riscv32_tree/lib/gcc/riscv32-unknown-elf/8.0.1/../../../../riscv32-unknown-elf/lib"
+// CXX-RV32-BAREMETAL-NOSYSROOT-ILP32: "-L{{.*}}/Inputs/basic_riscv32_tree/lib/gcc/riscv32-unknown-elf/8.0.1"
+// CXX-RV32-BAREMETAL-NOSYSROOT-ILP32: "-lstdc++" "--start-group" "-lc" "-lgloss" "--end-group" "-lgcc"
+// CXX-RV32-BAREMETAL-NOSYSROOT-ILP32: "{{.*}}/Inputs/basic_riscv32_tree/lib/gcc/riscv32-unknown-elf/8.0.1{{/|}}crtend.o"
+
 // RUN: %clang %s -### -no-canonical-prefixes -fuse-ld=ld \
 // RUN:   -target riscv32-linux-unknown-elf \
 // RUN:   --gcc-toolchain=%S/Inputs/multilib_riscv_linux_sdk \
Index: lib/Driver/ToolChains/RISCV.h
===
--- 

[PATCH] D50246: [RISCV] Add support for computing sysroot for riscv32-unknown-elf

[Lewis Revill via Phabricator via cfe-commits]

lewis-revill updated this revision to Diff 162179.
lewis-revill added a comment.

Added tests for the case where `--sysroot` is not provided.


Repository:
  rC Clang

https://reviews.llvm.org/D50246

Files:
  lib/Driver/ToolChains/RISCV.cpp
  lib/Driver/ToolChains/RISCV.h
  test/Driver/riscv32-toolchain.c

Index: test/Driver/riscv32-toolchain.c
===
--- test/Driver/riscv32-toolchain.c
+++ test/Driver/riscv32-toolchain.c
@@ -18,13 +18,26 @@
 // C-RV32-BAREMETAL-ILP32: "--start-group" "-lc" "-lgloss" "--end-group" "-lgcc"
 // C-RV32-BAREMETAL-ILP32: "{{.*}}/Inputs/basic_riscv32_tree/lib/gcc/riscv32-unknown-elf/8.0.1{{/|}}crtend.o"
 
+// RUN: %clang %s -### -no-canonical-prefixes \
+// RUN:   -target riscv32-unknown-elf \
+// RUN:   --gcc-toolchain=%S/Inputs/basic_riscv32_tree 2>&1 \
+// RUN:   | FileCheck -check-prefix=C-RV32-BAREMETAL-NOSYSROOT-ILP32 %s
+
+// C-RV32-BAREMETAL-NOSYSROOT-ILP32: "{{.*}}Inputs/basic_riscv32_tree/lib/gcc/riscv32-unknown-elf/8.0.1/../../../../bin{{/|}}riscv32-unknown-elf-ld"
+// C-RV32-BAREMETAL-NOSYSROOT-ILP32: "{{.*}}/Inputs/basic_riscv32_tree/lib/gcc/riscv32-unknown-elf/8.0.1/../../../../riscv32-unknown-elf/lib{{/|}}crt0.o"
+// C-RV32-BAREMETAL-NOSYSROOT-ILP32: "{{.*}}/Inputs/basic_riscv32_tree/lib/gcc/riscv32-unknown-elf/8.0.1{{/|}}crtbegin.o"
+// C-RV32-BAREMETAL-NOSYSROOT-ILP32: "-L{{.*}}/Inputs/basic_riscv32_tree/lib/gcc/riscv32-unknown-elf/8.0.1/../../../../riscv32-unknown-elf{{/|}}lib"
+// C-RV32-BAREMETAL-NOSYSROOT-ILP32: "-L{{.*}}/Inputs/basic_riscv32_tree/lib/gcc/riscv32-unknown-elf/8.0.1"
+// C-RV32-BAREMETAL-NOSYSROOT-ILP32: "--start-group" "-lc" "-lgloss" "--end-group" "-lgcc"
+// C-RV32-BAREMETAL-NOSYSROOT-ILP32: "{{.*}}/Inputs/basic_riscv32_tree/lib/gcc/riscv32-unknown-elf/8.0.1{{/|}}crtend.o"
+
 // RUN: %clangxx %s -### -no-canonical-prefixes \
 // RUN:   -target riscv32-unknown-elf -stdlib=libstdc++ \
 // RUN:   --gcc-toolchain=%S/Inputs/basic_riscv32_tree \
 // RUN:   --sysroot=%S/Inputs/basic_riscv32_tree/riscv32-unknown-elf 2>&1 \
 // RUN:   | FileCheck -check-prefix=CXX-RV32-BAREMETAL-ILP32 %s
 
-// CXX-RV32-BAREMETAL-ILP32: "-internal-isystem" "{{.*}}Inputs/basic_riscv32_tree/lib/gcc/riscv32-unknown-elf/8.0.1/../../../../riscv32-unknown-elf/include/c++{{/|}}8.0.1"
+// CXX-RV32-BAREMETAL-ILP32: "-internal-isystem" "{{.*}}Inputs/basic_riscv32_tree/riscv32-unknown-elf/include/c++{{/|}}8.0.1"
 // CXX-RV32-BAREMETAL-ILP32: "{{.*}}Inputs/basic_riscv32_tree/lib/gcc/riscv32-unknown-elf/8.0.1/../../../../bin{{/|}}riscv32-unknown-elf-ld"
 // CXX-RV32-BAREMETAL-ILP32: "--sysroot={{.*}}/Inputs/basic_riscv32_tree/riscv32-unknown-elf"
 // CXX-RV32-BAREMETAL-ILP32: "{{.*}}/Inputs/basic_riscv32_tree/riscv32-unknown-elf/lib{{/|}}crt0.o"
@@ -34,6 +47,20 @@
 // CXX-RV32-BAREMETAL-ILP32: "-lstdc++" "--start-group" "-lc" "-lgloss" "--end-group" "-lgcc"
 // CXX-RV32-BAREMETAL-ILP32: "{{.*}}/Inputs/basic_riscv32_tree/lib/gcc/riscv32-unknown-elf/8.0.1{{/|}}crtend.o"
 
+// RUN: %clangxx %s -### -no-canonical-prefixes \
+// RUN:   -target riscv32-unknown-elf -stdlib=libstdc++ \
+// RUN:   --gcc-toolchain=%S/Inputs/basic_riscv32_tree 2>&1 \
+// RUN:   | FileCheck -check-prefix=CXX-RV32-BAREMETAL-NOSYSROOT-ILP32 %s
+
+// CXX-RV32-BAREMETAL-NOSYSROOT-ILP32: "-internal-isystem" "{{.*}}Inputs/basic_riscv32_tree/lib/gcc/riscv32-unknown-elf/8.0.1/../../../../riscv32-unknown-elf/include/c++{{/|}}8.0.1"
+// CXX-RV32-BAREMETAL-NOSYSROOT-ILP32: "{{.*}}Inputs/basic_riscv32_tree/lib/gcc/riscv32-unknown-elf/8.0.1/../../../../bin{{/|}}riscv32-unknown-elf-ld"
+// CXX-RV32-BAREMETAL-NOSYSROOT-ILP32: "{{.*}}/Inputs/basic_riscv32_tree/lib/gcc/riscv32-unknown-elf/8.0.1/../../../../riscv32-unknown-elf/lib{{/|}}crt0.o"
+// CXX-RV32-BAREMETAL-NOSYSROOT-ILP32: "{{.*}}/Inputs/basic_riscv32_tree/lib/gcc/riscv32-unknown-elf/8.0.1{{/|}}crtbegin.o"
+// CXX-RV32-BAREMETAL-NOSYSROOT-ILP32: "-L{{.*}}/Inputs/basic_riscv32_tree/lib/gcc/riscv32-unknown-elf/8.0.1/../../../../riscv32-unknown-elf/lib"
+// CXX-RV32-BAREMETAL-NOSYSROOT-ILP32: "-L{{.*}}/Inputs/basic_riscv32_tree/lib/gcc/riscv32-unknown-elf/8.0.1"
+// CXX-RV32-BAREMETAL-NOSYSROOT-ILP32: "-lstdc++" "--start-group" "-lc" "-lgloss" "--end-group" "-lgcc"
+// CXX-RV32-BAREMETAL-NOSYSROOT-ILP32: "{{.*}}/Inputs/basic_riscv32_tree/lib/gcc/riscv32-unknown-elf/8.0.1{{/|}}crtend.o"
+
 // RUN: %clang %s -### -no-canonical-prefixes -fuse-ld=ld \
 // RUN:   -target riscv32-linux-unknown-elf \
 // RUN:   --gcc-toolchain=%S/Inputs/multilib_riscv_linux_sdk \
Index: lib/Driver/ToolChains/RISCV.h
===
--- lib/Driver/ToolChains/RISCV.h
+++ lib/Driver/ToolChains/RISCV.h
@@ -23,6 +23,9 @@
  const llvm::opt::ArgList );
 
   bool IsIntegratedAssemblerDefault() const override { return true; }
+  void addClangTargetOptions(const llvm::opt::ArgList ,
+

[PATCH] D50246: [RISCV] Add support for computing sysroot for riscv32-unknown-elf

[Lewis Revill via Phabricator via cfe-commits]

lewis-revill updated this revision to Diff 160602.
lewis-revill added a comment.

Fixed this issue by adding -nostdsysteminc to the Clang target options, 
preventing the frontend from generating additional include paths.


Repository:
  rC Clang

https://reviews.llvm.org/D50246

Files:
  lib/Driver/ToolChains/RISCV.cpp
  lib/Driver/ToolChains/RISCV.h
  test/Driver/riscv32-toolchain.c

Index: test/Driver/riscv32-toolchain.c
===
--- test/Driver/riscv32-toolchain.c
+++ test/Driver/riscv32-toolchain.c
@@ -24,7 +24,7 @@
 // RUN:   --sysroot=%S/Inputs/basic_riscv32_tree/riscv32-unknown-elf 2>&1 \
 // RUN:   | FileCheck -check-prefix=CXX-RV32-BAREMETAL-ILP32 %s
 
-// CXX-RV32-BAREMETAL-ILP32: "-internal-isystem" "{{.*}}Inputs/basic_riscv32_tree/lib/gcc/riscv32-unknown-elf/8.0.1/../../../../riscv32-unknown-elf/include/c++{{/|}}8.0.1"
+// CXX-RV32-BAREMETAL-ILP32: "-internal-isystem" "{{.*}}Inputs/basic_riscv32_tree/riscv32-unknown-elf/include/c++{{/|}}8.0.1"
 // CXX-RV32-BAREMETAL-ILP32: "{{.*}}Inputs/basic_riscv32_tree/lib/gcc/riscv32-unknown-elf/8.0.1/../../../../bin{{/|}}riscv32-unknown-elf-ld"
 // CXX-RV32-BAREMETAL-ILP32: "--sysroot={{.*}}/Inputs/basic_riscv32_tree/riscv32-unknown-elf"
 // CXX-RV32-BAREMETAL-ILP32: "{{.*}}/Inputs/basic_riscv32_tree/riscv32-unknown-elf/lib{{/|}}crt0.o"
Index: lib/Driver/ToolChains/RISCV.h
===
--- lib/Driver/ToolChains/RISCV.h
+++ lib/Driver/ToolChains/RISCV.h
@@ -23,6 +23,9 @@
  const llvm::opt::ArgList );
 
   bool IsIntegratedAssemblerDefault() const override { return true; }
+  void addClangTargetOptions(const llvm::opt::ArgList ,
+ llvm::opt::ArgStringList ,
+ Action::OffloadKind) const override;
   void
   AddClangSystemIncludeArgs(const llvm::opt::ArgList ,
 llvm::opt::ArgStringList ) const override;
@@ -32,6 +35,9 @@
 
 protected:
   Tool *buildLinker() const override;
+
+private:
+  std::string computeSysRoot() const;
 };
 
 } // end namespace toolchains
Index: lib/Driver/ToolChains/RISCV.cpp
===
--- lib/Driver/ToolChains/RISCV.cpp
+++ lib/Driver/ToolChains/RISCV.cpp
@@ -13,6 +13,7 @@
 #include "clang/Driver/Compilation.h"
 #include "clang/Driver/Options.h"
 #include "llvm/Option/ArgList.h"
+#include "llvm/Support/FileSystem.h"
 #include "llvm/Support/Path.h"
 #include "llvm/Support/raw_ostream.h"
 
@@ -27,7 +28,7 @@
const ArgList )
 : Generic_ELF(D, Triple, Args) {
   GCCInstallation.init(Triple, Args);
-  getFilePaths().push_back(D.SysRoot + "/lib");
+  getFilePaths().push_back(computeSysRoot() + "/lib");
   if (GCCInstallation.isValid()) {
 getFilePaths().push_back(GCCInstallation.getInstallPath().str());
 getProgramPaths().push_back(
@@ -39,30 +40,52 @@
   return new tools::RISCV::Linker(*this);
 }
 
+void RISCVToolChain::addClangTargetOptions(
+const llvm::opt::ArgList ,
+llvm::opt::ArgStringList ,
+Action::OffloadKind) const {
+  CC1Args.push_back("-nostdsysteminc");
+}
+
 void RISCVToolChain::AddClangSystemIncludeArgs(const ArgList ,
ArgStringList ) const {
   if (DriverArgs.hasArg(options::OPT_nostdinc))
 return;
 
   if (!DriverArgs.hasArg(options::OPT_nostdlibinc)) {
-SmallString<128> Dir(getDriver().SysRoot);
+SmallString<128> Dir(computeSysRoot());
 llvm::sys::path::append(Dir, "include");
 addSystemInclude(DriverArgs, CC1Args, Dir.str());
   }
 }
 
 void RISCVToolChain::addLibStdCxxIncludePaths(
 const llvm::opt::ArgList ,
 llvm::opt::ArgStringList ) const {
-  StringRef LibDir = GCCInstallation.getParentLibPath();
   const GCCVersion  = GCCInstallation.getVersion();
   StringRef TripleStr = GCCInstallation.getTriple().str();
   const Multilib  = GCCInstallation.getMultilib();
-  addLibStdCXXIncludePaths(
-  LibDir.str() + "/../" + TripleStr.str() + "/include/c++/" + Version.Text,
+  addLibStdCXXIncludePaths(computeSysRoot() + "/include/c++/" + Version.Text,
   "", TripleStr, "", "", Multilib.includeSuffix(), DriverArgs, CC1Args);
 }
 
+std::string RISCVToolChain::computeSysRoot() const {
+  if (!getDriver().SysRoot.empty())
+return getDriver().SysRoot;
+
+  if (!GCCInstallation.isValid())
+return std::string();
+
+  StringRef LibDir = GCCInstallation.getParentLibPath();
+  StringRef TripleStr = GCCInstallation.getTriple().str();
+  std::string SysRootDir = LibDir.str() + "/../" + TripleStr.str();
+
+  if (!llvm::sys::fs::exists(SysRootDir))
+return std::string();
+
+  return SysRootDir;
+}
+
 void RISCV::Linker::ConstructJob(Compilation , const JobAction ,
  const InputInfo ,
  const InputInfoList ,

[PATCH] D50246: [RISCV] Add support for computing sysroot for riscv32-unknown-elf

[Lewis Revill via Phabricator via cfe-commits]

lewis-revill added a comment.

@xbolva00 In my opinion this is an issue for another revision. Personally I 
would choose to rename/move the other RISCV driver file to something along the 
lines of RISCVLinux, however I think it is best for @asb to decide since he is 
the code owner for the RISC-V backend.


Repository:
  rC Clang

https://reviews.llvm.org/D50246



___
cfe-commits mailing list
cfe-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D50246: [RISCV] Add support for computing sysroot for riscv32-unknown-elf

[Lewis Revill via Phabricator via cfe-commits]

lewis-revill updated this revision to Diff 158994.
lewis-revill added a comment.

Modified test which assumed the path to C++ includes was determined without use 
of the sysroot path.


Repository:
  rC Clang

https://reviews.llvm.org/D50246

Files:
  lib/Driver/ToolChains/RISCV.cpp
  lib/Driver/ToolChains/RISCV.h
  test/Driver/riscv32-toolchain.c


Index: test/Driver/riscv32-toolchain.c
===
--- test/Driver/riscv32-toolchain.c
+++ test/Driver/riscv32-toolchain.c
@@ -24,7 +24,7 @@
 // RUN:   --sysroot=%S/Inputs/basic_riscv32_tree/riscv32-unknown-elf 2>&1 \
 // RUN:   | FileCheck -check-prefix=CXX-RV32-BAREMETAL-ILP32 %s
 
-// CXX-RV32-BAREMETAL-ILP32: "-internal-isystem" 
"{{.*}}Inputs/basic_riscv32_tree/lib/gcc/riscv32-unknown-elf/8.0.1/../../../../riscv32-unknown-elf/include/c++{{/|}}8.0.1"
+// CXX-RV32-BAREMETAL-ILP32: "-internal-isystem" 
"{{.*}}Inputs/basic_riscv32_tree/riscv32-unknown-elf/include/c++{{/|}}8.0.1"
 // CXX-RV32-BAREMETAL-ILP32: 
"{{.*}}Inputs/basic_riscv32_tree/lib/gcc/riscv32-unknown-elf/8.0.1/../../../../bin{{/|}}riscv32-unknown-elf-ld"
 // CXX-RV32-BAREMETAL-ILP32: 
"--sysroot={{.*}}/Inputs/basic_riscv32_tree/riscv32-unknown-elf"
 // CXX-RV32-BAREMETAL-ILP32: 
"{{.*}}/Inputs/basic_riscv32_tree/riscv32-unknown-elf/lib{{/|}}crt0.o"
Index: lib/Driver/ToolChains/RISCV.h
===
--- lib/Driver/ToolChains/RISCV.h
+++ lib/Driver/ToolChains/RISCV.h
@@ -32,6 +32,9 @@
 
 protected:
   Tool *buildLinker() const override;
+
+private:
+  std::string computeSysRoot() const;
 };
 
 } // end namespace toolchains
Index: lib/Driver/ToolChains/RISCV.cpp
===
--- lib/Driver/ToolChains/RISCV.cpp
+++ lib/Driver/ToolChains/RISCV.cpp
@@ -13,6 +13,7 @@
 #include "clang/Driver/Compilation.h"
 #include "clang/Driver/Options.h"
 #include "llvm/Option/ArgList.h"
+#include "llvm/Support/FileSystem.h"
 #include "llvm/Support/Path.h"
 #include "llvm/Support/raw_ostream.h"
 
@@ -27,7 +28,7 @@
const ArgList )
 : Generic_ELF(D, Triple, Args) {
   GCCInstallation.init(Triple, Args);
-  getFilePaths().push_back(D.SysRoot + "/lib");
+  getFilePaths().push_back(computeSysRoot() + "/lib");
   if (GCCInstallation.isValid()) {
 getFilePaths().push_back(GCCInstallation.getInstallPath().str());
 getProgramPaths().push_back(
@@ -45,24 +46,39 @@
 return;
 
   if (!DriverArgs.hasArg(options::OPT_nostdlibinc)) {
-SmallString<128> Dir(getDriver().SysRoot);
+SmallString<128> Dir(computeSysRoot());
 llvm::sys::path::append(Dir, "include");
 addSystemInclude(DriverArgs, CC1Args, Dir.str());
   }
 }
 
 void RISCVToolChain::addLibStdCxxIncludePaths(
 const llvm::opt::ArgList ,
 llvm::opt::ArgStringList ) const {
-  StringRef LibDir = GCCInstallation.getParentLibPath();
   const GCCVersion  = GCCInstallation.getVersion();
   StringRef TripleStr = GCCInstallation.getTriple().str();
   const Multilib  = GCCInstallation.getMultilib();
-  addLibStdCXXIncludePaths(
-  LibDir.str() + "/../" + TripleStr.str() + "/include/c++/" + Version.Text,
+  addLibStdCXXIncludePaths(computeSysRoot() + "/include/c++/" + Version.Text,
   "", TripleStr, "", "", Multilib.includeSuffix(), DriverArgs, CC1Args);
 }
 
+std::string RISCVToolChain::computeSysRoot() const {
+  if (!getDriver().SysRoot.empty())
+return getDriver().SysRoot;
+
+  if (!GCCInstallation.isValid())
+return std::string();
+
+  StringRef LibDir = GCCInstallation.getParentLibPath();
+  StringRef TripleStr = GCCInstallation.getTriple().str();
+  std::string SysRootDir = LibDir.str() + "/../" + TripleStr.str();
+
+  if (!llvm::sys::fs::exists(SysRootDir))
+return std::string();
+
+  return SysRootDir;
+}
+
 void RISCV::Linker::ConstructJob(Compilation , const JobAction ,
  const InputInfo ,
  const InputInfoList ,


Index: test/Driver/riscv32-toolchain.c
===
--- test/Driver/riscv32-toolchain.c
+++ test/Driver/riscv32-toolchain.c
@@ -24,7 +24,7 @@
 // RUN:   --sysroot=%S/Inputs/basic_riscv32_tree/riscv32-unknown-elf 2>&1 \
 // RUN:   | FileCheck -check-prefix=CXX-RV32-BAREMETAL-ILP32 %s
 
-// CXX-RV32-BAREMETAL-ILP32: "-internal-isystem" "{{.*}}Inputs/basic_riscv32_tree/lib/gcc/riscv32-unknown-elf/8.0.1/../../../../riscv32-unknown-elf/include/c++{{/|}}8.0.1"
+// CXX-RV32-BAREMETAL-ILP32: "-internal-isystem" "{{.*}}Inputs/basic_riscv32_tree/riscv32-unknown-elf/include/c++{{/|}}8.0.1"
 // CXX-RV32-BAREMETAL-ILP32: "{{.*}}Inputs/basic_riscv32_tree/lib/gcc/riscv32-unknown-elf/8.0.1/../../../../bin{{/|}}riscv32-unknown-elf-ld"
 // CXX-RV32-BAREMETAL-ILP32: "--sysroot={{.*}}/Inputs/basic_riscv32_tree/riscv32-unknown-elf"
 // CXX-RV32-BAREMETAL-ILP32: 

[PATCH] D46822: [RISCV] Add driver for riscv32-unknown-elf baremetal target

[Lewis Revill via Phabricator via cfe-commits]

lewis-revill added a comment.

I've submitted a patch to address Simon's issues in 
https://reviews.llvm.org/D50246


Repository:
  rC Clang

https://reviews.llvm.org/D46822



___
cfe-commits mailing list
cfe-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D50246: [RISCV] Add support for computing sysroot for riscv32-unknown-elf

[Lewis Revill via Phabricator via cfe-commits]

lewis-revill created this revision.
lewis-revill added reviewers: asb, simoncook, edward-jones.
Herald added subscribers: cfe-commits, rkruppe, the_o, brucehoult, 
MartinMosbeck, rogfer01, mgrang, zzheng, jrtc27, shiva0217, kito-cheng, niosHD, 
sabuasal, apazos, johnrusso, rbar.

Extends r338385 to allow the driver to compute the sysroot when an explicit 
path is not provided. This allows the linker to find C runtime files and the 
correct include directory for header files.


Repository:
  rC Clang

https://reviews.llvm.org/D50246

Files:
  lib/Driver/ToolChains/RISCV.cpp
  lib/Driver/ToolChains/RISCV.h


Index: lib/Driver/ToolChains/RISCV.h
===
--- lib/Driver/ToolChains/RISCV.h
+++ lib/Driver/ToolChains/RISCV.h
@@ -32,6 +32,9 @@
 
 protected:
   Tool *buildLinker() const override;
+
+private:
+  std::string computeSysRoot() const;
 };
 
 } // end namespace toolchains
Index: lib/Driver/ToolChains/RISCV.cpp
===
--- lib/Driver/ToolChains/RISCV.cpp
+++ lib/Driver/ToolChains/RISCV.cpp
@@ -13,6 +13,7 @@
 #include "clang/Driver/Compilation.h"
 #include "clang/Driver/Options.h"
 #include "llvm/Option/ArgList.h"
+#include "llvm/Support/FileSystem.h"
 #include "llvm/Support/Path.h"
 #include "llvm/Support/raw_ostream.h"
 
@@ -27,7 +28,7 @@
const ArgList )
 : Generic_ELF(D, Triple, Args) {
   GCCInstallation.init(Triple, Args);
-  getFilePaths().push_back(D.SysRoot + "/lib");
+  getFilePaths().push_back(computeSysRoot() + "/lib");
   if (GCCInstallation.isValid()) {
 getFilePaths().push_back(GCCInstallation.getInstallPath().str());
 getProgramPaths().push_back(
@@ -45,24 +46,39 @@
 return;
 
   if (!DriverArgs.hasArg(options::OPT_nostdlibinc)) {
-SmallString<128> Dir(getDriver().SysRoot);
+SmallString<128> Dir(computeSysRoot());
 llvm::sys::path::append(Dir, "include");
 addSystemInclude(DriverArgs, CC1Args, Dir.str());
   }
 }
 
 void RISCVToolChain::addLibStdCxxIncludePaths(
 const llvm::opt::ArgList ,
 llvm::opt::ArgStringList ) const {
-  StringRef LibDir = GCCInstallation.getParentLibPath();
   const GCCVersion  = GCCInstallation.getVersion();
   StringRef TripleStr = GCCInstallation.getTriple().str();
   const Multilib  = GCCInstallation.getMultilib();
-  addLibStdCXXIncludePaths(
-  LibDir.str() + "/../" + TripleStr.str() + "/include/c++/" + Version.Text,
+  addLibStdCXXIncludePaths(computeSysRoot() + "/include/c++/" + Version.Text,
   "", TripleStr, "", "", Multilib.includeSuffix(), DriverArgs, CC1Args);
 }
 
+std::string RISCVToolChain::computeSysRoot() const {
+  if (!getDriver().SysRoot.empty())
+return getDriver().SysRoot;
+
+  if (!GCCInstallation.isValid())
+return std::string();
+
+  StringRef LibDir = GCCInstallation.getParentLibPath();
+  StringRef TripleStr = GCCInstallation.getTriple().str();
+  std::string SysRootDir = LibDir.str() + "/../" + TripleStr.str();
+
+  if (!llvm::sys::fs::exists(SysRootDir))
+return std::string();
+
+  return SysRootDir;
+}
+
 void RISCV::Linker::ConstructJob(Compilation , const JobAction ,
  const InputInfo ,
  const InputInfoList ,


Index: lib/Driver/ToolChains/RISCV.h
===
--- lib/Driver/ToolChains/RISCV.h
+++ lib/Driver/ToolChains/RISCV.h
@@ -32,6 +32,9 @@
 
 protected:
   Tool *buildLinker() const override;
+
+private:
+  std::string computeSysRoot() const;
 };
 
 } // end namespace toolchains
Index: lib/Driver/ToolChains/RISCV.cpp
===
--- lib/Driver/ToolChains/RISCV.cpp
+++ lib/Driver/ToolChains/RISCV.cpp
@@ -13,6 +13,7 @@
 #include "clang/Driver/Compilation.h"
 #include "clang/Driver/Options.h"
 #include "llvm/Option/ArgList.h"
+#include "llvm/Support/FileSystem.h"
 #include "llvm/Support/Path.h"
 #include "llvm/Support/raw_ostream.h"
 
@@ -27,7 +28,7 @@
const ArgList )
 : Generic_ELF(D, Triple, Args) {
   GCCInstallation.init(Triple, Args);
-  getFilePaths().push_back(D.SysRoot + "/lib");
+  getFilePaths().push_back(computeSysRoot() + "/lib");
   if (GCCInstallation.isValid()) {
 getFilePaths().push_back(GCCInstallation.getInstallPath().str());
 getProgramPaths().push_back(
@@ -45,24 +46,39 @@
 return;
 
   if (!DriverArgs.hasArg(options::OPT_nostdlibinc)) {
-SmallString<128> Dir(getDriver().SysRoot);
+SmallString<128> Dir(computeSysRoot());
 llvm::sys::path::append(Dir, "include");
 addSystemInclude(DriverArgs, CC1Args, Dir.str());
   }
 }
 
 void RISCVToolChain::addLibStdCxxIncludePaths(
 const llvm::opt::ArgList ,
 llvm::opt::ArgStringList ) const {
-  StringRef LibDir = GCCInstallation.getParentLibPath();
   const GCCVersion  = GCCInstallation.getVersion();
   StringRef TripleStr