[clang] 024bb62 - [Driver] Pass --target2= to linker from baremetal toolchain

[Mikhail Maltsev via cfe-commits]

Author: Mikhail Maltsev
Date: 2023-04-28T18:30:49+01:00
New Revision: 024bb62ffd072e9a90343e88c92e40b5849c2632

URL: 
https://github.com/llvm/llvm-project/commit/024bb62ffd072e9a90343e88c92e40b5849c2632
DIFF: 
https://github.com/llvm/llvm-project/commit/024bb62ffd072e9a90343e88c92e40b5849c2632.diff

LOG: [Driver] Pass --target2= to linker from baremetal toolchain

According to the GNU ld manual
https://sourceware.org/binutils/docs/ld/ARM.html#ARM the R_ARM_TARGET2
relocation (used in exception handling tables) is treated differently
depending on the target. By default, LLD treats R_ARM_TARGET2 as
R_ARM_GOT_PREL (--target2=got-rel), which is correct for Linux but not
for embedded targets.

This patch adds --target2=rel to linker options in the baremetal
toolchain driver so that on baremetal targets, R_ARM_TARGET2 is
treated as R_ARM_REL32. Such behavior is compatible with GNU ld and
unwinding libraries (e.g., libuwind).

Reviewed By: peter.smith, phosek

Differential Revision: https://reviews.llvm.org/D149458

Added: 


Modified: 
clang/lib/Driver/ToolChains/BareMetal.cpp
clang/test/Driver/baremetal.cpp

Removed: 




diff  --git a/clang/lib/Driver/ToolChains/BareMetal.cpp 
b/clang/lib/Driver/ToolChains/BareMetal.cpp
index 38f26d0176471..3232394007bc3 100644
--- a/clang/lib/Driver/ToolChains/BareMetal.cpp
+++ b/clang/lib/Driver/ToolChains/BareMetal.cpp
@@ -342,6 +342,12 @@ void baremetal::Linker::ConstructJob(Compilation , const 
JobAction ,
   if (TC.getTriple().isRISCV())
 CmdArgs.push_back("-X");
 
+  // The R_ARM_TARGET2 relocation must be treated as R_ARM_REL32 on arm*-*-elf
+  // and arm*-*-eabi (the default is R_ARM_GOT_PREL, used on arm*-*-linux and
+  // arm*-*-*bsd).
+  if (isARMBareMetal(TC.getTriple()))
+CmdArgs.push_back("--target2=rel");
+
   CmdArgs.push_back("-o");
   CmdArgs.push_back(Output.getFilename());
 

diff  --git a/clang/test/Driver/baremetal.cpp b/clang/test/Driver/baremetal.cpp
index 7f2334493c529..c00713a5d30fb 100644
--- a/clang/test/Driver/baremetal.cpp
+++ b/clang/test/Driver/baremetal.cpp
@@ -15,7 +15,7 @@
 // CHECK-V6M-C-SAME: "-T" "semihosted.lds" 
"-Lsome{{[/\\]+}}directory{{[/\\]+}}user{{[/\\]+}}asked{{[/\\]+}}for"
 // CHECK-V6M-C-SAME: "-L[[SYSROOT:[^"]+]]{{[/\\]+}}lib"
 // CHECK-V6M-C-SAME: "-L[[RESOURCE_DIR:[^"]+]]{{[/\\]+}}lib{{[/\\]+}}baremetal"
-// CHECK-V6M-C-SAME: "-lc" "-lm" "-lclang_rt.builtins-armv6m" "-o" 
"{{.*}}.tmp.out"
+// CHECK-V6M-C-SAME: "-lc" "-lm" "-lclang_rt.builtins-armv6m" "--target2=rel" 
"-o" "{{.*}}.tmp.out"
 
 // RUN: %clang %s -### --target=armv6m-none-eabi -nostdlibinc -nobuiltininc 
2>&1 \
 // RUN: --sysroot=%S/Inputs/baremetal_arm | FileCheck 
--check-prefix=CHECK-V6M-LIBINC %s
@@ -42,7 +42,7 @@
 // CHECK-V6M-DEFAULTCXX-SAME: 
"-L{{[^"]*}}{{[/\\]+}}Inputs{{[/\\]+}}baremetal_arm{{[/\\]+}}lib"
 // CHECK-V6M-DEFAULTCXX-SAME: 
"-L[[RESOURCE_DIR]]{{[/\\]+}}lib{{[/\\]+}}baremetal"
 // CHECK-V6M-DEFAULTCXX-SAME: "-lc++" "-lc++abi" "-lunwind"
-// CHECK-V6M-DEFAULTCXX-SAME: "-lc" "-lm" "-lclang_rt.builtins-armv6m" "-o" 
"a.out"
+// CHECK-V6M-DEFAULTCXX-SAME: "-lc" "-lm" "-lclang_rt.builtins-armv6m" 
"--target2=rel" "-o" "a.out"
 
 // RUN: %clangxx %s -### --target=armv6m-none-eabi -stdlib=libc++ 2>&1 \
 // RUN: --sysroot=%S/Inputs/baremetal_arm | FileCheck 
--check-prefix=CHECK-V6M-LIBCXX %s
@@ -53,7 +53,7 @@
 // CHECK-V6M-LIBCXX-SAME: 
"-L{{[^"]*}}{{[/\\]+}}Inputs{{[/\\]+}}baremetal_arm{{[/\\]+}}lib"
 // CHECK-V6M-LIBCXX-SAME: "-L[[RESOURCE_DIR]]{{[/\\]+}}lib{{[/\\]+}}baremetal"
 // CHECK-V6M-LIBCXX-SAME: "-lc++" "-lc++abi" "-lunwind"
-// CHECK-V6M-LIBCXX-SAME: "-lc" "-lm" "-lclang_rt.builtins-armv6m" "-o" "a.out"
+// CHECK-V6M-LIBCXX-SAME: "-lc" "-lm" "-lclang_rt.builtins-armv6m" 
"--target2=rel" "-o" "a.out"
 
 // RUN: %clangxx %s -### --target=armv6m-none-eabi 2>&1 \
 // RUN: --sysroot=%S/Inputs/baremetal_arm \
@@ -66,7 +66,7 @@
 // CHECK-V6M-LIBSTDCXX-SAME: 
"-L{{[^"]*}}{{[/\\]+}}Inputs{{[/\\]+}}baremetal_arm{{[/\\]+}}lib"
 // CHECK-V6M-LIBSTDCXX-SAME: 
"-L[[RESOURCE_DIR]]{{[/\\]+}}lib{{[/\\]+}}baremetal"
 // CHECK-V6M-LIBSTDCXX-SAME: "-lstdc++" "-lsupc++" "-lunwind"
-// CHECK-V6M-LIBSTDCXX-SAME: "-lc" "-lm" "-lclang_rt.builtins-armv6m" "-o" 
"a.out"
+// CHECK-V6M-LIBSTDCXX-SAME: "-lc" "-lm" "-lclang_rt.builtins-armv6m" 
"--target2=rel" "-o" "a.out"
 
 // RUN: %clangxx %s -### --target=armv6m-none-eabi 2>&1 \
 // RUN: --sysroot=%S/Inputs/baremetal_arm \



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[clang] a0e3091 - [clang][Tooling] Get rid of a hack in SymbolOccurrences, NFCI

[Mikhail Maltsev via cfe-commits]

Author: Mikhail Maltsev
Date: 2021-01-22T13:01:41Z
New Revision: a0e30914f8c8bb60795a008ce2d9e3c0a4f9b7a2

URL: 
https://github.com/llvm/llvm-project/commit/a0e30914f8c8bb60795a008ce2d9e3c0a4f9b7a2
DIFF: 
https://github.com/llvm/llvm-project/commit/a0e30914f8c8bb60795a008ce2d9e3c0a4f9b7a2.diff

LOG: [clang][Tooling] Get rid of a hack in SymbolOccurrences, NFCI

The class `SymbolOccurrences` can store either a single `SourceRange`
in-place or multiple `SourceRanges` on the heap. In the latter case
the number of source ranges is stored in the internal representation
of the beginning `SourceLocation` of the in-place `SourceRange`
object.

This change gets rid of such hack by placing `SourceRange` in a union
which holds either a valid `SourceRange` or an `unsigned int` (a number
of ranges).

The change also adds `static_assert`s that check that `SourceRange` and
`SourceLocation` are trivially destructible (this is required for the
current patch and for D94237 which has already been committed).

Reviewed By: MarkMurrayARM, simon_tatham

Differential Revision: https://reviews.llvm.org/D94599

Added: 


Modified: 
clang/include/clang/Tooling/Refactoring/Rename/SymbolOccurrences.h
clang/lib/Basic/SourceLocation.cpp
clang/lib/Tooling/Refactoring/Rename/SymbolOccurrences.cpp

Removed: 




diff  --git 
a/clang/include/clang/Tooling/Refactoring/Rename/SymbolOccurrences.h 
b/clang/include/clang/Tooling/Refactoring/Rename/SymbolOccurrences.h
index 3b903cb822f3..c4bfaa9cc377 100644
--- a/clang/include/clang/Tooling/Refactoring/Rename/SymbolOccurrences.h
+++ b/clang/include/clang/Tooling/Refactoring/Rename/SymbolOccurrences.h
@@ -69,17 +69,18 @@ class SymbolOccurrence {
   OccurrenceKind getKind() const { return Kind; }
 
   ArrayRef getNameRanges() const {
-if (MultipleRanges) {
-  return llvm::makeArrayRef(MultipleRanges.get(),
-RangeOrNumRanges.getBegin().getRawEncoding());
-}
-return RangeOrNumRanges;
+if (MultipleRanges)
+  return llvm::makeArrayRef(MultipleRanges.get(), NumRanges);
+return SingleRange;
   }
 
 private:
   OccurrenceKind Kind;
   std::unique_ptr MultipleRanges;
-  SourceRange RangeOrNumRanges;
+  union {
+SourceRange SingleRange;
+unsigned NumRanges;
+  };
 };
 
 using SymbolOccurrences = std::vector;

diff  --git a/clang/lib/Basic/SourceLocation.cpp 
b/clang/lib/Basic/SourceLocation.cpp
index fde139932c40..6f6412028d77 100644
--- a/clang/lib/Basic/SourceLocation.cpp
+++ b/clang/lib/Basic/SourceLocation.cpp
@@ -42,6 +42,14 @@ void PrettyStackTraceLoc::print(raw_ostream ) const {
 // SourceLocation
 
//===--===//
 
+static_assert(std::is_trivially_destructible::value,
+  "SourceLocation must be trivially destructible because it is "
+  "used in unions");
+
+static_assert(std::is_trivially_destructible::value,
+  "SourceRange must be trivially destructible because it is "
+  "used in unions");
+
 unsigned SourceLocation::getHashValue() const {
   return llvm::DenseMapInfo::getHashValue(ID);
 }

diff  --git a/clang/lib/Tooling/Refactoring/Rename/SymbolOccurrences.cpp 
b/clang/lib/Tooling/Refactoring/Rename/SymbolOccurrences.cpp
index 9e69d37e81ad..762864c953d8 100644
--- a/clang/lib/Tooling/Refactoring/Rename/SymbolOccurrences.cpp
+++ b/clang/lib/Tooling/Refactoring/Rename/SymbolOccurrences.cpp
@@ -21,13 +21,12 @@ SymbolOccurrence::SymbolOccurrence(const SymbolName , 
OccurrenceKind Kind,
  "mismatching number of locations and lengths");
   assert(!Locations.empty() && "no locations");
   if (Locations.size() == 1) {
-RangeOrNumRanges = SourceRange(
+new () SourceRange(
 Locations[0], Locations[0].getLocWithOffset(NamePieces[0].size()));
 return;
   }
   MultipleRanges = std::make_unique(Locations.size());
-  RangeOrNumRanges.setBegin(
-  SourceLocation::getFromRawEncoding(Locations.size()));
+  NumRanges = Locations.size();
   for (const auto  : llvm::enumerate(Locations)) {
 MultipleRanges[Loc.index()] = SourceRange(
 Loc.value(),



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[clang-tools-extra] 176f5e9 - [clang-tidy] Use DenseSet in UpgradeDurationConversionsCheck, NFCI

[Mikhail Maltsev via cfe-commits]

Author: Mikhail Maltsev
Date: 2021-01-14T13:50:16Z
New Revision: 176f5e95e1afad75ff045a00f0fa9c781bd5f54a

URL: 
https://github.com/llvm/llvm-project/commit/176f5e95e1afad75ff045a00f0fa9c781bd5f54a
DIFF: 
https://github.com/llvm/llvm-project/commit/176f5e95e1afad75ff045a00f0fa9c781bd5f54a.diff

LOG: [clang-tidy] Use DenseSet in 
UpgradeDurationConversionsCheck, NFCI

This change replaces `unordered_set` (which used to store
internal representation of `SourceLocation`-s) with
`DenseSet` (which stores `SourceLocation`-s directly).

Reviewed By: aaron.ballman, njames93

Differential Revision: https://reviews.llvm.org/D94601

Added: 


Modified: 
clang-tools-extra/clang-tidy/abseil/UpgradeDurationConversionsCheck.cpp
clang-tools-extra/clang-tidy/abseil/UpgradeDurationConversionsCheck.h

Removed: 




diff  --git 
a/clang-tools-extra/clang-tidy/abseil/UpgradeDurationConversionsCheck.cpp 
b/clang-tools-extra/clang-tidy/abseil/UpgradeDurationConversionsCheck.cpp
index 208d1df27763..539b575d1880 100644
--- a/clang-tools-extra/clang-tidy/abseil/UpgradeDurationConversionsCheck.cpp
+++ b/clang-tools-extra/clang-tidy/abseil/UpgradeDurationConversionsCheck.cpp
@@ -128,7 +128,7 @@ void UpgradeDurationConversionsCheck::check(
 
   if (!match(isInTemplateInstantiation(), *OuterExpr, *Result.Context)
.empty()) {
-if (MatchedTemplateLocations.count(Loc.getRawEncoding()) == 0) {
+if (MatchedTemplateLocations.count(Loc) == 0) {
   // For each location matched in a template instantiation, we check if the
   // location can also be found in `MatchedTemplateLocations`. If it is not
   // found, that means the expression did not create a match without the
@@ -144,7 +144,7 @@ void UpgradeDurationConversionsCheck::check(
   internal::Matcher IsInsideTemplate =
   hasAncestor(decl(anyOf(classTemplateDecl(), functionTemplateDecl(;
   if (!match(IsInsideTemplate, *ArgExpr, *Result.Context).empty())
-MatchedTemplateLocations.insert(Loc.getRawEncoding());
+MatchedTemplateLocations.insert(Loc);
 
   DiagnosticBuilder Diag = diag(Loc, Message);
   CharSourceRange SourceRange = Lexer::makeFileCharRange(

diff  --git 
a/clang-tools-extra/clang-tidy/abseil/UpgradeDurationConversionsCheck.h 
b/clang-tools-extra/clang-tidy/abseil/UpgradeDurationConversionsCheck.h
index 7a450a8e9249..23af29299f78 100644
--- a/clang-tools-extra/clang-tidy/abseil/UpgradeDurationConversionsCheck.h
+++ b/clang-tools-extra/clang-tidy/abseil/UpgradeDurationConversionsCheck.h
@@ -11,7 +11,8 @@
 
 #include "../ClangTidyCheck.h"
 
-#include 
+#include "clang/Basic/SourceLocation.h"
+#include "llvm/ADT/DenseSet.h"
 
 namespace clang {
 namespace tidy {
@@ -32,7 +33,7 @@ class UpgradeDurationConversionsCheck : public ClangTidyCheck 
{
   void check(const ast_matchers::MatchFinder::MatchResult ) override;
 
 private:
-  std::unordered_set MatchedTemplateLocations;
+  llvm::DenseSet MatchedTemplateLocations;
 };
 
 } // namespace abseil



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[clang] 17f8c45 - [clang] Use SourceLocations in unions [NFCI]

[Mikhail Maltsev via cfe-commits]

Author: Mikhail Maltsev
Date: 2021-01-14T10:56:53Z
New Revision: 17f8c458de631c0311828931a5bdf72b1a13c29d

URL: 
https://github.com/llvm/llvm-project/commit/17f8c458de631c0311828931a5bdf72b1a13c29d
DIFF: 
https://github.com/llvm/llvm-project/commit/17f8c458de631c0311828931a5bdf72b1a13c29d.diff

LOG: [clang] Use SourceLocations in unions [NFCI]

Currently, there are many instances where `SourceLocation` objects are
converted to raw representation to be stored in structs that are
used as fields of tagged unions.

This is done to make the corresponding structs trivial.
Triviality allows avoiding undefined behavior when implicitly changing
the active member of the union.

However, in most cases, we can explicitly construct an active member
using placement new. This patch adds the required active member
selections and replaces `SourceLocation`-s represented as
`unsigned int` with proper `SourceLocation`-s.

One notable exception is `DeclarationNameLoc`: the objects of this class
are often not properly initialized (so the code currently relies on
its default constructor which uses memset). This class will be fixed
in a separate patch.

Reviewed By: dblaikie

Differential Revision: https://reviews.llvm.org/D94237

Added: 


Modified: 
clang/include/clang/AST/DependentDiagnostic.h
clang/include/clang/AST/Expr.h
clang/include/clang/AST/TemplateBase.h
clang/include/clang/Basic/SourceManager.h
clang/include/clang/Sema/DeclSpec.h
clang/include/clang/Sema/Designator.h
clang/include/clang/Sema/Initialization.h
clang/lib/AST/Expr.cpp
clang/lib/AST/TemplateBase.cpp
clang/lib/Parse/ParseDeclCXX.cpp
clang/lib/Sema/DeclSpec.cpp
clang/lib/Sema/SemaDecl.cpp
clang/lib/Sema/SemaExpr.cpp
clang/lib/Sema/SemaType.cpp

Removed: 




diff  --git a/clang/include/clang/AST/DependentDiagnostic.h 
b/clang/include/clang/AST/DependentDiagnostic.h
index 5a8624608e74..18276d54d540 100644
--- a/clang/include/clang/AST/DependentDiagnostic.h
+++ b/clang/include/clang/AST/DependentDiagnostic.h
@@ -48,7 +48,7 @@ class DependentDiagnostic {
  QualType BaseObjectType,
  const PartialDiagnostic ) {
 DependentDiagnostic *DD = Create(Context, Parent, PDiag);
-DD->AccessData.Loc = Loc.getRawEncoding();
+DD->AccessData.Loc = Loc;
 DD->AccessData.IsMember = IsMemberAccess;
 DD->AccessData.Access = AS;
 DD->AccessData.TargetDecl = TargetDecl;
@@ -73,7 +73,7 @@ class DependentDiagnostic {
 
   SourceLocation getAccessLoc() const {
 assert(getKind() == Access);
-return SourceLocation::getFromRawEncoding(AccessData.Loc);
+return AccessData.Loc;
   }
 
   NamedDecl *getAccessTarget() const {
@@ -112,7 +112,7 @@ class DependentDiagnostic {
   PartialDiagnostic Diag;
 
   struct {
-unsigned Loc;
+SourceLocation Loc;
 unsigned Access : 2;
 unsigned IsMember : 1;
 NamedDecl *TargetDecl;

diff  --git a/clang/include/clang/AST/Expr.h b/clang/include/clang/AST/Expr.h
index c8d87ec48a3f..a44d06967431 100644
--- a/clang/include/clang/AST/Expr.h
+++ b/clang/include/clang/AST/Expr.h
@@ -4994,10 +4994,10 @@ class DesignatedInitExpr final
 uintptr_t NameOrField;
 
 /// The location of the '.' in the designated initializer.
-unsigned DotLoc;
+SourceLocation DotLoc;
 
 /// The location of the field name in the designated initializer.
-unsigned FieldLoc;
+SourceLocation FieldLoc;
   };
 
   /// An array or GNU array-range designator, e.g., "[9]" or "[10..15]".
@@ -5006,12 +5006,12 @@ class DesignatedInitExpr final
 /// initializer expression's list of subexpressions.
 unsigned Index;
 /// The location of the '[' starting the array range designator.
-unsigned LBracketLoc;
+SourceLocation LBracketLoc;
 /// The location of the ellipsis separating the start and end
 /// indices. Only valid for GNU array-range designators.
-unsigned EllipsisLoc;
+SourceLocation EllipsisLoc;
 /// The location of the ']' terminating the array range designator.
-unsigned RBracketLoc;
+SourceLocation RBracketLoc;
   };
 
   /// Represents a single C99 designator.
@@ -5043,29 +5043,32 @@ class DesignatedInitExpr final
 Designator(const IdentifierInfo *FieldName, SourceLocation DotLoc,
SourceLocation FieldLoc)
   : Kind(FieldDesignator) {
+  new () DesignatedInitExpr::FieldDesignator;
   Field.NameOrField = reinterpret_cast(FieldName) | 0x01;
-  Field.DotLoc = DotLoc.getRawEncoding();
-  Field.FieldLoc = FieldLoc.getRawEncoding();
+  Field.DotLoc = DotLoc;
+  Field.FieldLoc = FieldLoc;
 }
 
 /// Initializes an array designator.
 Designator(unsigned Index, SourceLocation LBracketLoc,
SourceLocation RBracketLoc)
   : Kind(ArrayDesignator) {
+  new () 

[clang] c1e08f0 - [clang][AST] Get rid of an alignment hack in DeclObjC.h [NFCI]

[Mikhail Maltsev via cfe-commits]

Author: Mikhail Maltsev
Date: 2021-01-12T10:22:35Z
New Revision: c1e08f0073e35cf17c0a0343cf7efff914dbd66d

URL: 
https://github.com/llvm/llvm-project/commit/c1e08f0073e35cf17c0a0343cf7efff914dbd66d
DIFF: 
https://github.com/llvm/llvm-project/commit/c1e08f0073e35cf17c0a0343cf7efff914dbd66d.diff

LOG: [clang][AST] Get rid of an alignment hack in DeclObjC.h [NFCI]

This code currently uses a union object to increase the
alignment of the type ObjCTypeParamList. The original intent of this
trick was to be able to use the expression `this + 1` to access the
beginning of a tail-allocated array of `ObjCTypeParamDecl *` pointers.

The code has since been refactored and uses `llvm::TrailingObjects` to
manage the tail-allocated array. This template takes care of
alignment, so the hack is no longer necessary.

This patch removes the union so that the `SourceRange` class can be
used directly instead of being re-implemented with raw representations
of source locations.

Reviewed By: aprantl

Differential Revision: https://reviews.llvm.org/D94224

Added: 


Modified: 
clang/include/clang/AST/DeclObjC.h
clang/lib/AST/DeclObjC.cpp

Removed: 




diff  --git a/clang/include/clang/AST/DeclObjC.h 
b/clang/include/clang/AST/DeclObjC.h
index 88cedbd91b6d..b1bce069920c 100644
--- a/clang/include/clang/AST/DeclObjC.h
+++ b/clang/include/clang/AST/DeclObjC.h
@@ -656,20 +656,8 @@ class ObjCTypeParamDecl : public TypedefNameDecl {
 /// \endcode
 class ObjCTypeParamList final
 : private llvm::TrailingObjects {
-  /// Stores the components of a SourceRange as a POD.
-  struct PODSourceRange {
-unsigned Begin;
-unsigned End;
-  };
-
-  union {
-/// Location of the left and right angle brackets.
-PODSourceRange Brackets;
-
-// Used only for alignment.
-ObjCTypeParamDecl *AlignmentHack;
-  };
-
+  /// Location of the left and right angle brackets.
+  SourceRange Brackets;
   /// The number of parameters in the list, which are tail-allocated.
   unsigned NumParams;
 
@@ -717,17 +705,9 @@ class ObjCTypeParamList final
 return *(end() - 1);
   }
 
-  SourceLocation getLAngleLoc() const {
-return SourceLocation::getFromRawEncoding(Brackets.Begin);
-  }
-
-  SourceLocation getRAngleLoc() const {
-return SourceLocation::getFromRawEncoding(Brackets.End);
-  }
-
-  SourceRange getSourceRange() const {
-return SourceRange(getLAngleLoc(), getRAngleLoc());
-  }
+  SourceLocation getLAngleLoc() const { return Brackets.getBegin(); }
+  SourceLocation getRAngleLoc() const { return Brackets.getEnd(); }
+  SourceRange getSourceRange() const { return Brackets; }
 
   /// Gather the default set of type arguments to be substituted for
   /// these type parameters when dealing with an unspecialized type.

diff  --git a/clang/lib/AST/DeclObjC.cpp b/clang/lib/AST/DeclObjC.cpp
index 961230fb54ce..5f82fcec90e3 100644
--- a/clang/lib/AST/DeclObjC.cpp
+++ b/clang/lib/AST/DeclObjC.cpp
@@ -1461,9 +1461,7 @@ SourceRange ObjCTypeParamDecl::getSourceRange() const {
 ObjCTypeParamList::ObjCTypeParamList(SourceLocation lAngleLoc,
  ArrayRef typeParams,
  SourceLocation rAngleLoc)
-: NumParams(typeParams.size()) {
-  Brackets.Begin = lAngleLoc.getRawEncoding();
-  Brackets.End = rAngleLoc.getRawEncoding();
+: Brackets(lAngleLoc, rAngleLoc), NumParams(typeParams.size()) {
   std::copy(typeParams.begin(), typeParams.end(), begin());
 }
 



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[clang] 9f76788 - [clang][Sema] Compare SourceLocations directly [NFCI]

[Mikhail Maltsev via cfe-commits]

Author: Mikhail Maltsev
Date: 2021-01-09T14:13:18Z
New Revision: 9f76788b0930ed48f5f20a25f1b30d63c8486531

URL: 
https://github.com/llvm/llvm-project/commit/9f76788b0930ed48f5f20a25f1b30d63c8486531
DIFF: 
https://github.com/llvm/llvm-project/commit/9f76788b0930ed48f5f20a25f1b30d63c8486531.diff

LOG: [clang][Sema] Compare SourceLocations directly [NFCI]

The ordered comparison operators are defined for the SourceLocation
class, so SourceLocation objects can be compared directly. There is no
need to extract the internal representation for comparison.

Reviewed By: aprantl

Differential Revision: https://reviews.llvm.org/D94231

Added: 


Modified: 
clang/lib/Sema/SemaDecl.cpp
clang/lib/Sema/SemaStmt.cpp

Removed: 




diff  --git a/clang/lib/Sema/SemaDecl.cpp b/clang/lib/Sema/SemaDecl.cpp
index 3a1294ce431f..dd31f3f98487 100644
--- a/clang/lib/Sema/SemaDecl.cpp
+++ b/clang/lib/Sema/SemaDecl.cpp
@@ -436,9 +436,7 @@ ParsedType Sema::getTypeName(const IdentifierInfo , 
SourceLocation NameLoc,
  Res != ResEnd; ++Res) {
   if (isa(*Res) || isa(*Res) ||
   (AllowDeducedTemplate && getAsTypeTemplateDecl(*Res))) {
-if (!IIDecl ||
-(*Res)->getLocation().getRawEncoding() <
-  IIDecl->getLocation().getRawEncoding())
+if (!IIDecl || (*Res)->getLocation() < IIDecl->getLocation())
   IIDecl = *Res;
   }
 }

diff  --git a/clang/lib/Sema/SemaStmt.cpp b/clang/lib/Sema/SemaStmt.cpp
index a47fdf625bba..b24a8ab110b2 100644
--- a/clang/lib/Sema/SemaStmt.cpp
+++ b/clang/lib/Sema/SemaStmt.cpp
@@ -672,8 +672,7 @@ static bool CmpCaseVals(const std::pair& lhs,
 return true;
 
   if (lhs.first == rhs.first &&
-  lhs.second->getCaseLoc().getRawEncoding()
-   < rhs.second->getCaseLoc().getRawEncoding())
+  lhs.second->getCaseLoc() < rhs.second->getCaseLoc())
 return true;
   return false;
 }



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[clang] 443ab4d - [clang][Basic] Integrate SourceLocation with FoldingSet, NFCI

[Mikhail Maltsev via cfe-commits]

Author: Mikhail Maltsev
Date: 2020-10-27T10:43:39Z
New Revision: 443ab4d2e01246bf93cd410db945dc9ab6adf1b3

URL: 
https://github.com/llvm/llvm-project/commit/443ab4d2e01246bf93cd410db945dc9ab6adf1b3
DIFF: 
https://github.com/llvm/llvm-project/commit/443ab4d2e01246bf93cd410db945dc9ab6adf1b3.diff

LOG: [clang][Basic] Integrate SourceLocation with FoldingSet, NFCI

This patch removes the necessity to access the SourceLocation internal
representation in several places that use FoldingSet objects.

Reviewed By: dexonsmith

Differential Revision: https://reviews.llvm.org/D69844

Added: 


Modified: 
clang/include/clang/Basic/SourceLocation.h
clang/lib/Analysis/PathDiagnostic.cpp
clang/lib/Basic/SourceLocation.cpp
clang/lib/StaticAnalyzer/Core/BugReporter.cpp

Removed: 




diff  --git a/clang/include/clang/Basic/SourceLocation.h 
b/clang/include/clang/Basic/SourceLocation.h
index 88ecb7c586d9..fc722b1d563d 100644
--- a/clang/include/clang/Basic/SourceLocation.h
+++ b/clang/include/clang/Basic/SourceLocation.h
@@ -26,6 +26,9 @@ namespace llvm {
 
 template  struct DenseMapInfo;
 
+class FoldingSetNodeID;
+template  struct FoldingSetTrait;
+
 } // namespace llvm
 
 namespace clang {
@@ -87,6 +90,7 @@ class SourceLocation {
   friend class ASTReader;
   friend class ASTWriter;
   friend class SourceManager;
+  friend struct llvm::FoldingSetTrait;
 
   unsigned ID = 0;
 
@@ -501,6 +505,11 @@ namespace llvm {
 }
   };
 
+  // Allow calling FoldingSetNodeID::Add with SourceLocation object as 
parameter
+  template <> struct FoldingSetTrait {
+static void Profile(const clang::SourceLocation , FoldingSetNodeID );
+  };
+
   // Teach SmallPtrSet how to handle SourceLocation.
   template<>
   struct PointerLikeTypeTraits {

diff  --git a/clang/lib/Analysis/PathDiagnostic.cpp 
b/clang/lib/Analysis/PathDiagnostic.cpp
index f80b99b99806..b42f47fb68c5 100644
--- a/clang/lib/Analysis/PathDiagnostic.cpp
+++ b/clang/lib/Analysis/PathDiagnostic.cpp
@@ -1083,9 +1083,9 @@ unsigned PathDiagnostic::full_size() {
 
//===--===//
 
 void PathDiagnosticLocation::Profile(llvm::FoldingSetNodeID ) const {
-  ID.AddInteger(Range.getBegin().getRawEncoding());
-  ID.AddInteger(Range.getEnd().getRawEncoding());
-  ID.AddInteger(Loc.getRawEncoding());
+  ID.Add(Range.getBegin());
+  ID.Add(Range.getEnd());
+  ID.Add(static_cast(Loc));
 }
 
 void PathDiagnosticPiece::Profile(llvm::FoldingSetNodeID ) const {
@@ -1095,8 +1095,8 @@ void PathDiagnosticPiece::Profile(llvm::FoldingSetNodeID 
) const {
   ID.AddInteger((unsigned) getDisplayHint());
   ArrayRef Ranges = getRanges();
   for (const auto  : Ranges) {
-ID.AddInteger(I.getBegin().getRawEncoding());
-ID.AddInteger(I.getEnd().getRawEncoding());
+ID.Add(I.getBegin());
+ID.Add(I.getEnd());
   }
 }
 

diff  --git a/clang/lib/Basic/SourceLocation.cpp 
b/clang/lib/Basic/SourceLocation.cpp
index 2ff17973323e..fde139932c40 100644
--- a/clang/lib/Basic/SourceLocation.cpp
+++ b/clang/lib/Basic/SourceLocation.cpp
@@ -15,6 +15,7 @@
 #include "clang/Basic/PrettyStackTrace.h"
 #include "clang/Basic/SourceManager.h"
 #include "llvm/ADT/DenseMapInfo.h"
+#include "llvm/ADT/FoldingSet.h"
 #include "llvm/ADT/StringRef.h"
 #include "llvm/Support/Compiler.h"
 #include "llvm/Support/MemoryBuffer.h"
@@ -45,6 +46,11 @@ unsigned SourceLocation::getHashValue() const {
   return llvm::DenseMapInfo::getHashValue(ID);
 }
 
+void llvm::FoldingSetTrait::Profile(
+const SourceLocation , llvm::FoldingSetNodeID ) {
+  ID.AddInteger(X.ID);
+}
+
 void SourceLocation::print(raw_ostream , const SourceManager )const{
   if (!isValid()) {
 OS << "";

diff  --git a/clang/lib/StaticAnalyzer/Core/BugReporter.cpp 
b/clang/lib/StaticAnalyzer/Core/BugReporter.cpp
index ebad1d1b67b4..bf38891b370a 100644
--- a/clang/lib/StaticAnalyzer/Core/BugReporter.cpp
+++ b/clang/lib/StaticAnalyzer/Core/BugReporter.cpp
@@ -2193,8 +2193,8 @@ void BasicBugReport::Profile(llvm::FoldingSetNodeID& 
hash) const {
   for (SourceRange range : Ranges) {
 if (!range.isValid())
   continue;
-hash.AddInteger(range.getBegin().getRawEncoding());
-hash.AddInteger(range.getEnd().getRawEncoding());
+hash.Add(range.getBegin());
+hash.Add(range.getEnd());
   }
 }
 
@@ -2216,8 +2216,8 @@ void 
PathSensitiveBugReport::Profile(llvm::FoldingSetNodeID ) const {
   for (SourceRange range : Ranges) {
 if (!range.isValid())
   continue;
-hash.AddInteger(range.getBegin().getRawEncoding());
-hash.AddInteger(range.getEnd().getRawEncoding());
+hash.Add(range.getBegin());
+hash.Add(range.getEnd());
   }
 }
 



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[clang-tools-extra] 7819411 - [clang] Use SourceLocation as key in hash maps, NFCI

[Mikhail Maltsev via cfe-commits]

Author: Mikhail Maltsev
Date: 2020-10-20T16:24:09+01:00
New Revision: 781941183700b52d11b27227e3341385447610fa

URL: 
https://github.com/llvm/llvm-project/commit/781941183700b52d11b27227e3341385447610fa
DIFF: 
https://github.com/llvm/llvm-project/commit/781941183700b52d11b27227e3341385447610fa.diff

LOG: [clang] Use SourceLocation as key in hash maps, NFCI

The patch adjusts the existing `llvm::DenseMap` and
`llvm::DenseSet` objects that store source locations, so
that they use `SourceLocation` directly instead of `unsigned`.

This patch relies on the `DenseMapInfo` trait added in D89719.

It also replaces the construction of `SourceLocation` objects from
the constants -1 and -2 with calls to the trait's methods `getEmptyKey`
and `getTombstoneKey` where appropriate.

Reviewed By: dexonsmith

Differential Revision: https://reviews.llvm.org/D69840

Added: 


Modified: 
clang-tools-extra/clang-tidy/cppcoreguidelines/SpecialMemberFunctionsCheck.h
clang-tools-extra/clang-tidy/utils/RenamerClangTidyCheck.cpp
clang-tools-extra/clang-tidy/utils/RenamerClangTidyCheck.h
clang-tools-extra/clangd/FindTarget.cpp
clang/include/clang/Edit/EditedSource.h
clang/include/clang/Sema/Sema.h
clang/include/clang/Tooling/Syntax/Tokens.h
clang/lib/ARCMigrate/TransGCAttrs.cpp
clang/lib/ARCMigrate/TransProperties.cpp
clang/lib/ARCMigrate/Transforms.h
clang/lib/CodeGen/CGOpenMPRuntime.h
clang/lib/Edit/EditedSource.cpp
clang/lib/Tooling/Syntax/BuildTree.cpp
clang/lib/Tooling/Syntax/Tokens.cpp

Removed: 




diff  --git 
a/clang-tools-extra/clang-tidy/cppcoreguidelines/SpecialMemberFunctionsCheck.h 
b/clang-tools-extra/clang-tidy/cppcoreguidelines/SpecialMemberFunctionsCheck.h
index 83fca3d5799b0..f232a0a09fbb7 100644
--- 
a/clang-tools-extra/clang-tidy/cppcoreguidelines/SpecialMemberFunctionsCheck.h
+++ 
b/clang-tools-extra/clang-tidy/cppcoreguidelines/SpecialMemberFunctionsCheck.h
@@ -85,15 +85,13 @@ struct DenseMapInfo<
   clang::tidy::cppcoreguidelines::SpecialMemberFunctionsCheck::ClassDefId;
 
   static inline ClassDefId getEmptyKey() {
-return ClassDefId(
-clang::SourceLocation::getFromRawEncoding(static_cast(-1)),
-"EMPTY");
+return ClassDefId(DenseMapInfo::getEmptyKey(),
+  "EMPTY");
   }
 
   static inline ClassDefId getTombstoneKey() {
-return ClassDefId(
-clang::SourceLocation::getFromRawEncoding(static_cast(-2)),
-"TOMBSTONE");
+return ClassDefId(DenseMapInfo::getTombstoneKey(),
+  "TOMBSTONE");
   }
 
   static unsigned getHashValue(ClassDefId Val) {
@@ -101,7 +99,7 @@ struct DenseMapInfo<
 assert(Val != getTombstoneKey() && "Cannot hash the tombstone key!");
 
 std::hash SecondHash;
-return Val.first.getRawEncoding() + SecondHash(Val.second);
+return Val.first.getHashValue() + SecondHash(Val.second);
   }
 
   static bool isEqual(const ClassDefId , const ClassDefId ) {

diff  --git a/clang-tools-extra/clang-tidy/utils/RenamerClangTidyCheck.cpp 
b/clang-tools-extra/clang-tidy/utils/RenamerClangTidyCheck.cpp
index bb8caf1d84e2e..6a25813eb7480 100644
--- a/clang-tools-extra/clang-tidy/utils/RenamerClangTidyCheck.cpp
+++ b/clang-tools-extra/clang-tidy/utils/RenamerClangTidyCheck.cpp
@@ -28,15 +28,13 @@ struct 
DenseMapInfo {
   using NamingCheckId = clang::tidy::RenamerClangTidyCheck::NamingCheckId;
 
   static inline NamingCheckId getEmptyKey() {
-return NamingCheckId(
-clang::SourceLocation::getFromRawEncoding(static_cast(-1)),
-"EMPTY");
+return NamingCheckId(DenseMapInfo::getEmptyKey(),
+ "EMPTY");
   }
 
   static inline NamingCheckId getTombstoneKey() {
-return NamingCheckId(
-clang::SourceLocation::getFromRawEncoding(static_cast(-2)),
-"TOMBSTONE");
+return 
NamingCheckId(DenseMapInfo::getTombstoneKey(),
+ "TOMBSTONE");
   }
 
   static unsigned getHashValue(NamingCheckId Val) {
@@ -44,7 +42,8 @@ struct 
DenseMapInfo {
 assert(Val != getTombstoneKey() && "Cannot hash the tombstone key!");
 
 std::hash SecondHash;
-return Val.first.getRawEncoding() + SecondHash(Val.second);
+return DenseMapInfo::getHashValue(Val.first) +
+   SecondHash(Val.second);
   }
 
   static bool isEqual(const NamingCheckId , const NamingCheckId ) {
@@ -173,8 +172,7 @@ void RenamerClangTidyCheck::addUsage(
   // is already in there
   RenamerClangTidyCheck::NamingCheckFailure  =
   NamingCheckFailures[Decl];
-
-  if (!Failure.RawUsageLocs.insert(FixLocation.getRawEncoding()).second)
+  if (!Failure.RawUsageLocs.insert(FixLocation).second)
 return;
 
   if (!Failure.ShouldFix())
@@ -550,9 +548,8 @@ void RenamerClangTidyCheck::onEndOfTranslationUnit() {
   //
   // Other multi-token identifiers, such as operators are not checked 
at
   // all.
- 

[clang] 234c47a - [clang][Basic] Make SourceLocation usable as key in hash maps, NFCI

[Mikhail Maltsev via cfe-commits]

Author: Mikhail Maltsev
Date: 2020-10-20T15:52:59+01:00
New Revision: 234c47ae2a8e1877de8c661d5bb862ba952eabf9

URL: 
https://github.com/llvm/llvm-project/commit/234c47ae2a8e1877de8c661d5bb862ba952eabf9
DIFF: 
https://github.com/llvm/llvm-project/commit/234c47ae2a8e1877de8c661d5bb862ba952eabf9.diff

LOG: [clang][Basic] Make SourceLocation usable as key in hash maps, NFCI

This change creates a `DenseMapInfo` trait specialization for the
SourceLocation class. The empty key, the tombstone key, and the hash
function are identical to `DenseMapInfo`, because we already
have hash maps that use raw the representation of `SourceLocation` as
a key.

The update of existing `DenseMap`s containing raw representation of
`SourceLocation`s will be done in a follow-up patch. As an example
the patch makes use of the new trait in one instance:
clang-tidy/google/UpgradeGoogletestCaseCheck.{h,cpp}

Reviewed By: dexonsmith

Differential Revision: https://reviews.llvm.org/D89719

Added: 


Modified: 
clang-tools-extra/clang-tidy/google/UpgradeGoogletestCaseCheck.cpp
clang-tools-extra/clang-tidy/google/UpgradeGoogletestCaseCheck.h
clang/include/clang/Basic/SourceLocation.h
clang/lib/Basic/SourceLocation.cpp

Removed: 




diff  --git 
a/clang-tools-extra/clang-tidy/google/UpgradeGoogletestCaseCheck.cpp 
b/clang-tools-extra/clang-tidy/google/UpgradeGoogletestCaseCheck.cpp
index b2261ca7f507..d943b7a1a270 100644
--- a/clang-tools-extra/clang-tidy/google/UpgradeGoogletestCaseCheck.cpp
+++ b/clang-tools-extra/clang-tidy/google/UpgradeGoogletestCaseCheck.cpp
@@ -298,8 +298,7 @@ void UpgradeGoogletestCaseCheck::check(const 
MatchFinder::MatchResult ) {
 }
 
 if (IsInInstantiation) {
-  if (MatchedTemplateLocations.count(
-  ReplacementRange.getBegin().getRawEncoding()) == 0) {
+  if (MatchedTemplateLocations.count(ReplacementRange.getBegin()) == 0) {
 // For each location matched in a template instantiation, we check if
 // the location can also be found in `MatchedTemplateLocations`. If it
 // is not found, that means the expression did not create a match
@@ -313,8 +312,7 @@ void UpgradeGoogletestCaseCheck::check(const 
MatchFinder::MatchResult ) {
 if (IsInTemplate) {
   // We gather source locations from template matches not in template
   // instantiations for future matches.
-  MatchedTemplateLocations.insert(
-  ReplacementRange.getBegin().getRawEncoding());
+  MatchedTemplateLocations.insert(ReplacementRange.getBegin());
 }
 
 if (!AddFix) {

diff  --git a/clang-tools-extra/clang-tidy/google/UpgradeGoogletestCaseCheck.h 
b/clang-tools-extra/clang-tidy/google/UpgradeGoogletestCaseCheck.h
index 367498b16a97..a05bedf60b23 100644
--- a/clang-tools-extra/clang-tidy/google/UpgradeGoogletestCaseCheck.h
+++ b/clang-tools-extra/clang-tidy/google/UpgradeGoogletestCaseCheck.h
@@ -33,7 +33,7 @@ class UpgradeGoogletestCaseCheck : public ClangTidyCheck {
   void check(const ast_matchers::MatchFinder::MatchResult ) override;
 
 private:
-  llvm::DenseSet MatchedTemplateLocations;
+  llvm::DenseSet MatchedTemplateLocations;
 };
 
 } // namespace google

diff  --git a/clang/include/clang/Basic/SourceLocation.h 
b/clang/include/clang/Basic/SourceLocation.h
index 3735b904ef47..88ecb7c586d9 100644
--- a/clang/include/clang/Basic/SourceLocation.h
+++ b/clang/include/clang/Basic/SourceLocation.h
@@ -175,6 +175,7 @@ class SourceLocation {
End.isFileID();
   }
 
+  unsigned getHashValue() const;
   void print(raw_ostream , const SourceManager ) const;
   std::string printToString(const SourceManager ) const;
   void dump(const SourceManager ) const;
@@ -479,6 +480,27 @@ namespace llvm {
 }
   };
 
+  /// Define DenseMapInfo so that SourceLocation's can be used as keys in
+  /// DenseMap and DenseSet. This trait class is eqivalent to
+  /// DenseMapInfo which uses SourceLocation::ID is used as a key.
+  template <> struct DenseMapInfo {
+static clang::SourceLocation getEmptyKey() {
+  return clang::SourceLocation::getFromRawEncoding(~0U);
+}
+
+static clang::SourceLocation getTombstoneKey() {
+  return clang::SourceLocation::getFromRawEncoding(~0U - 1);
+}
+
+static unsigned getHashValue(clang::SourceLocation Loc) {
+  return Loc.getHashValue();
+}
+
+static bool isEqual(clang::SourceLocation LHS, clang::SourceLocation RHS) {
+  return LHS == RHS;
+}
+  };
+
   // Teach SmallPtrSet how to handle SourceLocation.
   template<>
   struct PointerLikeTypeTraits {

diff  --git a/clang/lib/Basic/SourceLocation.cpp 
b/clang/lib/Basic/SourceLocation.cpp
index 8cb0899ea39d..2ff17973323e 100644
--- a/clang/lib/Basic/SourceLocation.cpp
+++ b/clang/lib/Basic/SourceLocation.cpp
@@ -14,6 +14,7 @@
 #include "clang/Basic/LLVM.h"
 #include "clang/Basic/PrettyStackTrace.h"
 #include "clang/Basic/SourceManager.h"

[clang] a3c1603 - [clang] Use SourceLocation as key in std::map, NFCI

[Mikhail Maltsev via cfe-commits]

Author: Mikhail Maltsev
Date: 2020-10-19T18:31:05+01:00
New Revision: a3c16039b3f119cd83d872f256c45599ae6ac60c

URL: 
https://github.com/llvm/llvm-project/commit/a3c16039b3f119cd83d872f256c45599ae6ac60c
DIFF: 
https://github.com/llvm/llvm-project/commit/a3c16039b3f119cd83d872f256c45599ae6ac60c.diff

LOG: [clang] Use SourceLocation as key in std::map, NFCI

SourceLocation implements `operator<`, so `SourceLocation`-s can be used
as keys in `std::map` directly, there is no need to extract the internal
representation.

Since the `operator<` simply compares the internal representations of
its operands, this patch does not introduce any functional changes.

Reviewed By: dexonsmith

Differential Revision: https://reviews.llvm.org/D89705

Added: 


Modified: 
clang/lib/ARCMigrate/TransProperties.cpp
clang/lib/Frontend/Rewrite/InclusionRewriter.cpp

Removed: 




diff  --git a/clang/lib/ARCMigrate/TransProperties.cpp 
b/clang/lib/ARCMigrate/TransProperties.cpp
index cba2256ef97b..db0e6acafc66 100644
--- a/clang/lib/ARCMigrate/TransProperties.cpp
+++ b/clang/lib/ARCMigrate/TransProperties.cpp
@@ -65,7 +65,7 @@ class PropertiesRewriter {
   };
 
   typedef SmallVector PropsTy;
-  typedef std::map AtPropDeclsTy;
+  typedef std::map AtPropDeclsTy;
   AtPropDeclsTy AtProps;
   llvm::DenseMap ActionOnProp;
 
@@ -76,13 +76,13 @@ class PropertiesRewriter {
   static void collectProperties(ObjCContainerDecl *D, AtPropDeclsTy ,
 AtPropDeclsTy *PrevAtProps = nullptr) {
 for (auto *Prop : D->instance_properties()) {
-  if (Prop->getAtLoc().isInvalid())
+  SourceLocation Loc = Prop->getAtLoc();
+  if (Loc.isInvalid())
 continue;
-  unsigned RawLoc = Prop->getAtLoc().getRawEncoding();
   if (PrevAtProps)
-if (PrevAtProps->find(RawLoc) != PrevAtProps->end())
+if (PrevAtProps->find(Loc) != PrevAtProps->end())
   continue;
-  PropsTy  = AtProps[RawLoc];
+  PropsTy  = AtProps[Loc];
   props.push_back(Prop);
 }
   }
@@ -113,8 +113,7 @@ class PropertiesRewriter {
   ObjCIvarDecl *ivarD = implD->getPropertyIvarDecl();
   if (!ivarD || ivarD->isInvalidDecl())
 continue;
-  unsigned rawAtLoc = propD->getAtLoc().getRawEncoding();
-  AtPropDeclsTy::iterator findAtLoc = AtProps.find(rawAtLoc);
+  AtPropDeclsTy::iterator findAtLoc = AtProps.find(propD->getAtLoc());
   if (findAtLoc == AtProps.end())
 continue;
 
@@ -130,7 +129,7 @@ class PropertiesRewriter {
 
 for (AtPropDeclsTy::iterator
I = AtProps.begin(), E = AtProps.end(); I != E; ++I) {
-  SourceLocation atLoc = SourceLocation::getFromRawEncoding(I->first);
+  SourceLocation atLoc = I->first;
   PropsTy  = I->second;
   if (!getPropertyType(props)->isObjCRetainableType())
 continue;

diff  --git a/clang/lib/Frontend/Rewrite/InclusionRewriter.cpp 
b/clang/lib/Frontend/Rewrite/InclusionRewriter.cpp
index dcf645f67f2f..4b5447ccda89 100644
--- a/clang/lib/Frontend/Rewrite/InclusionRewriter.cpp
+++ b/clang/lib/Frontend/Rewrite/InclusionRewriter.cpp
@@ -44,13 +44,13 @@ class InclusionRewriter : public PPCallbacks {
   bool ShowLineMarkers; ///< Show #line markers.
   bool UseLineDirectives; ///< Use of line directives or line markers.
   /// Tracks where inclusions that change the file are found.
-  std::map FileIncludes;
+  std::map FileIncludes;
   /// Tracks where inclusions that import modules are found.
-  std::map ModuleIncludes;
+  std::map ModuleIncludes;
   /// Tracks where inclusions that enter modules (in a module build) are found.
-  std::map ModuleEntryIncludes;
+  std::map ModuleEntryIncludes;
   /// Tracks where #if and #elif directives get evaluated and whether to true.
-  std::map IfConditions;
+  std::map IfConditions;
   /// Used transitively for building up the FileIncludes mapping over the
   /// various \c PPCallbacks callbacks.
   SourceLocation LastInclusionLocation;
@@ -65,8 +65,8 @@ class InclusionRewriter : public PPCallbacks {
   void detectMainFileEOL();
   void handleModuleBegin(Token ) {
 assert(Tok.getKind() == tok::annot_module_begin);
-ModuleEntryIncludes.insert({Tok.getLocation().getRawEncoding(),
-(Module *)Tok.getAnnotationValue()});
+ModuleEntryIncludes.insert(
+{Tok.getLocation(), (Module *)Tok.getAnnotationValue()});
   }
 private:
   void FileChanged(SourceLocation Loc, FileChangeReason Reason,
@@ -164,7 +164,7 @@ void InclusionRewriter::FileChanged(SourceLocation Loc,
 return;
   FileID Id = FullSourceLoc(Loc, SM).getFileID();
   auto P = FileIncludes.insert(
-  std::make_pair(LastInclusionLocation.getRawEncoding(),
+  std::make_pair(LastInclusionLocation,
  IncludedFile(Id, NewFileType, PP.GetCurDirLookup(;
   (void)P;
   assert(P.second && "Unexpected revisitation of the same include 

[clang] 8cc842a - [clang][Sema] Use enumerator instead of hard-coded constant

[Mikhail Maltsev via cfe-commits]

Author: Mikhail Maltsev
Date: 2020-09-24T10:24:22+01:00
New Revision: 8cc842a95072aaa87b5067a12aa9ef5b3ac8e592

URL: 
https://github.com/llvm/llvm-project/commit/8cc842a95072aaa87b5067a12aa9ef5b3ac8e592
DIFF: 
https://github.com/llvm/llvm-project/commit/8cc842a95072aaa87b5067a12aa9ef5b3ac8e592.diff

LOG: [clang][Sema] Use enumerator instead of hard-coded constant

Sema::DiagnoseSwiftName uses the constant 12 instead of the
corresponding enumerator ExpectedFunctionWithProtoType. This is
fragile and will fail if a new value gets added in the middle of the
enum.

Reviewed By: aaron.ballman

Differential Revision: https://reviews.llvm.org/D88164

Added: 


Modified: 
clang/lib/Sema/SemaDeclAttr.cpp

Removed: 




diff  --git a/clang/lib/Sema/SemaDeclAttr.cpp b/clang/lib/Sema/SemaDeclAttr.cpp
index 3babbe05ca8f..d15ef232a5fb 100644
--- a/clang/lib/Sema/SemaDeclAttr.cpp
+++ b/clang/lib/Sema/SemaDeclAttr.cpp
@@ -5868,7 +5868,7 @@ bool Sema::DiagnoseSwiftName(Decl *D, StringRef Name, 
SourceLocation Loc,
 
   if (!F->hasWrittenPrototype()) {
 Diag(Loc, diag::warn_attribute_wrong_decl_type) << AL
-<< /* non-K functions */12;
+<< ExpectedFunctionWithProtoType;
 return false;
   }
 }



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[clang] ae1396c - [ARM][BFloat16] Change types of some Arm and AArch64 bf16 intrinsics

[Mikhail Maltsev via cfe-commits]

Author: Mikhail Maltsev
Date: 2020-08-27T18:43:16+01:00
New Revision: ae1396c7d4d83366695137f69f046719fd199408

URL: 
https://github.com/llvm/llvm-project/commit/ae1396c7d4d83366695137f69f046719fd199408
DIFF: 
https://github.com/llvm/llvm-project/commit/ae1396c7d4d83366695137f69f046719fd199408.diff

LOG: [ARM][BFloat16] Change types of some Arm and AArch64 bf16 intrinsics

This patch adjusts the following ARM/AArch64 LLVM IR intrinsics:
- neon_bfmmla
- neon_bfmlalb
- neon_bfmlalt
so that they take and return bf16 and float types. Previously these
intrinsics used <8 x i8> and <4 x i8> vectors (a rudiment from
implementation lacking bf16 IR type).

The neon_vbfdot[q] intrinsics are adjusted similarly. This change
required some additional selection patterns for vbfdot itself and
also for vector shuffles (in a previous patch) because of SelectionDAG
transformations kicking in and mangling the original code.

This patch makes the generated IR cleaner (less useless bitcasts are
produced), but it does not affect the final assembly.

Reviewed By: dmgreen

Differential Revision: https://reviews.llvm.org/D86146

Added: 
llvm/test/Bitcode/aarch64-bf16-upgrade.ll
llvm/test/Bitcode/aarch64-bf16-upgrade.ll.bc
llvm/test/Bitcode/arm-bf16-upgrade.ll
llvm/test/Bitcode/arm-bf16-upgrade.ll.bc

Modified: 
clang/lib/CodeGen/CGBuiltin.cpp
clang/test/CodeGen/aarch64-bf16-dotprod-intrinsics.c
clang/test/CodeGen/arm-bf16-dotprod-intrinsics.c
llvm/include/llvm/IR/IntrinsicsAArch64.td
llvm/include/llvm/IR/IntrinsicsARM.td
llvm/lib/IR/AutoUpgrade.cpp
llvm/lib/Target/AArch64/AArch64InstrFormats.td
llvm/lib/Target/AArch64/AArch64InstrInfo.td
llvm/lib/Target/ARM/ARMInstrNEON.td
llvm/test/CodeGen/AArch64/aarch64-bf16-dotprod-intrinsics.ll
llvm/test/CodeGen/ARM/arm-bf16-dotprod-intrinsics.ll

Removed: 




diff  --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
index 24e33c164009..69899fd8e668 100644
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -6241,28 +6241,10 @@ Value *CodeGenFunction::EmitCommonNeonBuiltinExpr(
   case NEON::BI__builtin_neon_vbfdot_v:
   case NEON::BI__builtin_neon_vbfdotq_v: {
 llvm::Type *InputTy =
-llvm::FixedVectorType::get(Int8Ty, Ty->getPrimitiveSizeInBits() / 8);
+llvm::FixedVectorType::get(BFloatTy, Ty->getPrimitiveSizeInBits() / 
16);
 llvm::Type *Tys[2] = { Ty, InputTy };
 return EmitNeonCall(CGM.getIntrinsic(Int, Tys), Ops, "vbfdot");
   }
-  case NEON::BI__builtin_neon_vbfmmlaq_v: {
-llvm::Type *InputTy =
-llvm::FixedVectorType::get(Int8Ty, Ty->getPrimitiveSizeInBits() / 8);
-llvm::Type *Tys[2] = { Ty, InputTy };
-return EmitNeonCall(CGM.getIntrinsic(Int, Tys), Ops, "vbfmmla");
-  }
-  case NEON::BI__builtin_neon_vbfmlalbq_v: {
-llvm::Type *InputTy =
-llvm::FixedVectorType::get(Int8Ty, Ty->getPrimitiveSizeInBits() / 8);
-llvm::Type *Tys[2] = { Ty, InputTy };
-return EmitNeonCall(CGM.getIntrinsic(Int, Tys), Ops, "vbfmlalb");
-  }
-  case NEON::BI__builtin_neon_vbfmlaltq_v: {
-llvm::Type *InputTy =
-llvm::FixedVectorType::get(Int8Ty, Ty->getPrimitiveSizeInBits() / 8);
-llvm::Type *Tys[2] = { Ty, InputTy };
-return EmitNeonCall(CGM.getIntrinsic(Int, Tys), Ops, "vbfmlalt");
-  }
   case NEON::BI__builtin_neon___a32_vcvt_bf16_v: {
 llvm::Type *Tys[1] = { Ty };
 Function *F = CGM.getIntrinsic(Int, Tys);

diff  --git a/clang/test/CodeGen/aarch64-bf16-dotprod-intrinsics.c 
b/clang/test/CodeGen/aarch64-bf16-dotprod-intrinsics.c
index 22e1396787ce..b9b5013bf6bd 100644
--- a/clang/test/CodeGen/aarch64-bf16-dotprod-intrinsics.c
+++ b/clang/test/CodeGen/aarch64-bf16-dotprod-intrinsics.c
@@ -1,146 +1,138 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
 // RUN: %clang_cc1 -triple aarch64-arm-none-eabi -target-feature +neon 
-target-feature +bf16 \
 // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg -instcombine 
| FileCheck %s
 
 #include 
 
-// CHECK-LABEL: test_vbfdot_f32
-// CHECK-NEXT: entry:
-// CHECK-NEXT  %0 = bitcast <4 x bfloat> %a to <8 x i8>
-// CHECK-NEXT  %1 = bitcast <4 x bfloat> %b to <8 x i8>
-// CHECK-NEXT  %vbfdot1.i = tail call <2 x float> 
@llvm.aarch64.neon.bfdot.v2f32.v8i8(<2 x float> %r, <8 x i8> %0, <8 x i8> %1)
-// CHECK-NEXT  ret <2 x float> %vbfdot1.i
+// CHECK-LABEL: @test_vbfdot_f32(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[VBFDOT3_I:%.*]] = call <2 x float> 
@llvm.aarch64.neon.bfdot.v2f32.v4bf16(<2 x float> [[R:%.*]], <4 x bfloat> 
[[A:%.*]], <4 x bfloat> [[B:%.*]]) [[ATTR3:#.*]]
+// CHECK-NEXT:ret <2 x float> [[VBFDOT3_I]]
+//
 float32x2_t test_vbfdot_f32(float32x2_t r, bfloat16x4_t a, bfloat16x4_t b) {
   return vbfdot_f32(r, a, b);
 }
 
-// CHECK-LABEL: test_vbfdotq_f32
-// CHECK-NEXT: entry:
-// CHECK-NEXT  %0 = bitcast <8 x bfloat> %a to 

[clang] 3f353a2 - [BFloat] Add convert/copy instrinsic support

[Mikhail Maltsev via cfe-commits]

Author: Mikhail Maltsev
Date: 2020-06-23T14:27:05Z
New Revision: 3f353a2e5a98d19be2a4d7414b8eb258c32965fd

URL: 
https://github.com/llvm/llvm-project/commit/3f353a2e5a98d19be2a4d7414b8eb258c32965fd
DIFF: 
https://github.com/llvm/llvm-project/commit/3f353a2e5a98d19be2a4d7414b8eb258c32965fd.diff

LOG: [BFloat] Add convert/copy instrinsic support

This patch is part of a series implementing the Bfloat16 extension of the 
Armv8.6-a architecture, as detailed here:

https://community.arm.com/developer/ip-products/processors/b/processors-ip-blog/posts/arm-architecture-developments-armv8-6-a

Specifically it adds intrinsic support in clang and llvm for Arm and AArch64.

The bfloat type, and its properties are specified in the Arm Architecture 
Reference Manual:

https://developer.arm.com/docs/ddi0487/latest/arm-architecture-reference-manual-armv8-for-armv8-a-architecture-profile

The following people contributed to this patch:
  - Alexandros Lamprineas
  - Luke Cheeseman
  - Mikhail Maltsev
  - Momchil Velikov
  - Luke Geeson

Differential Revision: https://reviews.llvm.org/D80928

Added: 
clang/test/CodeGen/aarch64-bf16-lane-intrinsics.c
clang/test/CodeGen/arm-bf16-convert-intrinsics.c
clang/test/Sema/aarch64-neon-bf16-ranges.c
llvm/test/CodeGen/AArch64/bf16-convert-intrinsics.ll
llvm/test/CodeGen/ARM/bf16-convert-intrinsics.ll

Modified: 
clang/include/clang/Basic/arm_neon.td
clang/lib/CodeGen/CGBuiltin.cpp
clang/utils/TableGen/NeonEmitter.cpp
llvm/include/llvm/IR/IntrinsicsAArch64.td
llvm/include/llvm/IR/IntrinsicsARM.td
llvm/lib/Target/AArch64/AArch64InstrFormats.td
llvm/lib/Target/AArch64/AArch64InstrInfo.td
llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
llvm/test/CodeGen/AArch64/bf16-vector-shuffle.ll

Removed: 




diff  --git a/clang/include/clang/Basic/arm_neon.td 
b/clang/include/clang/Basic/arm_neon.td
index 42d50f726393..d0269f31c32d 100644
--- a/clang/include/clang/Basic/arm_neon.td
+++ b/clang/include/clang/Basic/arm_neon.td
@@ -252,6 +252,34 @@ def OP_BFMLALT_LN
 : Op<(call "vbfmlalt", $p0, $p1,
   (dup_typed $p1, (call "vget_lane", $p2, $p3)))>;
 
+def OP_VCVT_F32_BF16
+: Op<(bitcast "R",
+  (call "vshll_n", (bitcast "int16x4_t", $p0),
+   (literal "int32_t", "16")))>;
+def OP_VCVT_F32_BF16_LO
+: Op<(call "vcvt_f32_bf16", (call "vget_low", $p0))>;
+def OP_VCVT_F32_BF16_HI
+: Op<(call "vcvt_f32_bf16", (call "vget_high", $p0))>;
+
+def OP_VCVT_BF16_F32_LO_A64
+: Op<(call "__a64_vcvtq_low_bf16", $p0)>;
+def OP_VCVT_BF16_F32_A64
+: Op<(call "vget_low", (call "__a64_vcvtq_low_bf16", $p0))>;
+
+def OP_VCVT_BF16_F32_A32
+: Op<(call "__a32_vcvt_bf16", $p0)>;
+
+def OP_VCVT_BF16_F32_LO_A32
+: Op<(call "vcombine", (cast "bfloat16x4_t", (literal "uint64_t", "0ULL")),
+   (call "__a32_vcvt_bf16", $p0))>;
+def OP_VCVT_BF16_F32_HI_A32
+: Op<(call "vcombine", (call "__a32_vcvt_bf16", $p1),
+   (call "vget_low", $p0))>;
+
+def OP_CVT_F32_BF16
+: Op<(bitcast "R", (op "<<", (bitcast "int32_t", $p0),
+ (literal "int32_t", "16")))>;
+
 
//===--===//
 // Auxiliary Instructions
 
//===--===//
@@ -1949,6 +1977,31 @@ let ArchGuard = 
"defined(__ARM_FEATURE_BF16_VECTOR_ARITHMETIC)" in {
   def VLD3_DUP_BF : WInst<"vld3_dup", "3(c*!)", "bQb">;
   def VLD4_DUP_BF : WInst<"vld4_dup", "4(c*!)", "bQb">;
 
+  def VCVT_F32_BF16 : SOpInst<"vcvt_f32_bf16", "(F>)(Bq!)",  "Qb", 
OP_VCVT_F32_BF16>;
+  def VCVT_LOW_F32_BF16 : SOpInst<"vcvt_low_f32", "(F>)(BQ!)",  "Qb", 
OP_VCVT_F32_BF16_LO>;
+  def VCVT_HIGH_F32_BF16 : SOpInst<"vcvt_high_f32", "(F>)(BQ!)", "Qb", 
OP_VCVT_F32_BF16_HI>;
+
+  def SCALAR_CVT_BF16_F32 : SInst<"vcvth_bf16", "(1B)1", "f">;
+  def SCALAR_CVT_F32_BF16 : SOpInst<"vcvtah_f32", "(1F>)(1!)", "b", 
OP_CVT_F32_BF16>;
+}
+
+let ArchGuard = "defined(__ARM_FEATURE_BF16_VECTOR_ARITHMETIC) && 
!defined(__aarch64__)" in {
+  def VCVT_BF16_F32_A32_INTERNAL : WInst<"__a32_vcvt_bf16", "BQ", "f">;
+  def VCVT_BF16_F32_A32 : SOpInst<"vcvt_bf16", "BQ", "f", 
OP_VCVT_BF16_F32_A32>;
+  def VCVT_LOW_BF16_F32_A32 : SOpInst<"vcvt_low_bf16",  "BQ", "Qf", 
OP_VCVT_BF16_F32_LO_A32>;
+  def VCVT_HIGH_BF16_F32_A32 : SOpInst<"vcvt_high_bf16", "BBQ", "Qf", 
OP_VCVT_BF16_F32_HI_A32>;
+}
+
+let ArchGuard = "defined(__ARM_FEATURE_BF16_VECTOR_ARITHMETIC) && 
defined(__aarch64__)" in {
+  def VCVT_LOW_BF16_F32_A64_INTERNAL : WInst<"__a64_vcvtq_low_bf16", "BQ", 
"Hf">;
+  def VCVT_LOW_BF16_F32_A64 : SOpInst<"vcvt_low_bf16", "BQ", "Qf", 
OP_VCVT_BF16_F32_LO_A64>;
+  def VCVT_HIGH_BF16_F32_A64 : SInst<"vcvt_high_bf16", "BBQ", "Qf">;
+  def VCVT_BF16_F32 : SOpInst<"vcvt_bf16","BQ", "f", OP_VCVT_BF16_F32_A64>;
+
+  def 

[clang] 9c57954 - [ARM] BFloat MatMul Intrinsics

[Mikhail Maltsev via cfe-commits]

Author: Mikhail Maltsev
Date: 2020-06-23T12:06:37Z
New Revision: 9c579540ff6945d126a680d01db38548db9a972d

URL: 
https://github.com/llvm/llvm-project/commit/9c579540ff6945d126a680d01db38548db9a972d
DIFF: 
https://github.com/llvm/llvm-project/commit/9c579540ff6945d126a680d01db38548db9a972d.diff

LOG: [ARM] BFloat MatMul Intrinsics

Summary:
This patch adds support for BFloat Matrix Multiplication Intrinsics
and Code Generation from __bf16 to AArch32. This includes IR intrinsics. Tests 
are
provided as needed.

This patch is part of a series implementing the Bfloat16 extension of
the
Armv8.6-a architecture, as detailed here:

https://community.arm.com/developer/ip-products/processors/b/processors-ip-blog/posts/arm-architecture-developments-armv8-6-a

The bfloat type and its properties are specified in the Arm
Architecture
Reference Manual:

https://developer.arm.com/docs/ddi0487/latest/arm-architecture-reference-manual-armv8-for-armv8-a-architecture-profile

The following people contributed to this patch:

 - Luke Geeson
 - Momchil Velikov
 - Mikhail Maltsev
 - Luke Cheeseman
 - Simon Tatham

Reviewers: stuij, t.p.northover, SjoerdMeijer, sdesmalen, fpetrogalli, 
LukeGeeson, simon_tatham, dmgreen, MarkMurrayARM

Reviewed By: MarkMurrayARM

Subscribers: MarkMurrayARM, danielkiss, kristof.beyls, hiraditya, cfe-commits, 
llvm-commits, chill, miyuki

Tags: #clang, #llvm

Differential Revision: https://reviews.llvm.org/D81740

Added: 
clang/test/CodeGen/arm-bf16-dotprod-intrinsics.c
llvm/test/CodeGen/ARM/arm-bf16-dotprod-intrinsics.ll

Modified: 
clang/lib/CodeGen/CGBuiltin.cpp
llvm/include/llvm/IR/IntrinsicsARM.td
llvm/lib/Target/ARM/ARMInstrNEON.td

Removed: 




diff  --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
index 32e43c295d23..6cbc5c20ad36 100644
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -4748,6 +4748,11 @@ static const ARMVectorIntrinsicInfo ARMSIMDIntrinsicMap 
[] = {
   NEONMAP1(vaeseq_v, arm_neon_aese, 0),
   NEONMAP1(vaesimcq_v, arm_neon_aesimc, 0),
   NEONMAP1(vaesmcq_v, arm_neon_aesmc, 0),
+  NEONMAP1(vbfdot_v, arm_neon_bfdot, 0),
+  NEONMAP1(vbfdotq_v, arm_neon_bfdot, 0),
+  NEONMAP1(vbfmlalbq_v, arm_neon_bfmlalb, 0),
+  NEONMAP1(vbfmlaltq_v, arm_neon_bfmlalt, 0),
+  NEONMAP1(vbfmmlaq_v, arm_neon_bfmmla, 0),
   NEONMAP1(vbsl_v, arm_neon_vbsl, AddRetType),
   NEONMAP1(vbslq_v, arm_neon_vbsl, AddRetType),
   NEONMAP1(vcadd_rot270_v, arm_neon_vcadd_rot270, Add1ArgType),

diff  --git a/clang/test/CodeGen/arm-bf16-dotprod-intrinsics.c 
b/clang/test/CodeGen/arm-bf16-dotprod-intrinsics.c
new file mode 100644
index ..0eb130a377bd
--- /dev/null
+++ b/clang/test/CodeGen/arm-bf16-dotprod-intrinsics.c
@@ -0,0 +1,166 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -triple armv8-arm-none-eabi \
+// RUN:   -target-feature +neon -target-feature +bf16 -mfloat-abi soft \
+// RUN:   -disable-O0-optnone -S -emit-llvm -o - %s \
+// RUN: | opt -S -mem2reg -instcombine | FileCheck %s
+// RUN: %clang_cc1 -triple armv8-arm-none-eabi \
+// RUN:   -target-feature +neon -target-feature +bf16 -mfloat-abi hard \
+// RUN:   -disable-O0-optnone -S -emit-llvm -o - %s \
+// RUN: | opt -S -mem2reg -instcombine | FileCheck %s
+
+#include 
+
+// CHECK-LABEL: @test_vbfdot_f32(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = bitcast <4 x bfloat> [[A:%.*]] to <8 x i8>
+// CHECK-NEXT:[[TMP1:%.*]] = bitcast <4 x bfloat> [[B:%.*]] to <8 x i8>
+// CHECK-NEXT:[[VBFDOT1_I:%.*]] = call <2 x float> 
@llvm.arm.neon.bfdot.v2f32.v8i8(<2 x float> [[R:%.*]], <8 x i8> [[TMP0]], <8 x 
i8> [[TMP1]]) #3
+// CHECK-NEXT:ret <2 x float> [[VBFDOT1_I]]
+//
+float32x2_t test_vbfdot_f32(float32x2_t r, bfloat16x4_t a, bfloat16x4_t b) {
+  return vbfdot_f32(r, a, b);
+}
+
+// CHECK-LABEL: @test_vbfdotq_f32(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = bitcast <8 x bfloat> [[A:%.*]] to <16 x i8>
+// CHECK-NEXT:[[TMP1:%.*]] = bitcast <8 x bfloat> [[B:%.*]] to <16 x i8>
+// CHECK-NEXT:[[VBFDOT1_I:%.*]] = call <4 x float> 
@llvm.arm.neon.bfdot.v4f32.v16i8(<4 x float> [[R:%.*]], <16 x i8> [[TMP0]], <16 
x i8> [[TMP1]]) #3
+// CHECK-NEXT:ret <4 x float> [[VBFDOT1_I]]
+//
+float32x4_t test_vbfdotq_f32(float32x4_t r, bfloat16x8_t a, bfloat16x8_t b){
+  return vbfdotq_f32(r, a, b);
+}
+
+// CHECK-LABEL: @test_vbfdot_lane_f32(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[DOTCAST:%.*]] = bitcast <4 x bfloat> [[B:%.*]] to <2 x 
float>
+// CHECK-NEXT:[[LANE:%.*]] = shufflevector <2 x float> [[DOTCAST]], <2 x 
float> undef, <2 x i32> zeroinitializer
+// CHECK-NEXT:[[DOTCAST1:%.*]] = bitcast <2 x float> [[LANE]] to <8 x i8>
+// CHECK-NEXT:[[TMP0:%.*]] = bitcast <4 x bfloat> [[A:%.*]] to <8 x i8>
+// CHECK-NEXT:[[VBFDOT1_I:%.*]] = call <2 x float> 
@llvm.arm.neon.bfdot.v2f32.v8i8(<2 

[clang] 3a4feb1 - [ARM][BFloat] Implement bf16 get/set_lane without casts to i16 vectors

[Mikhail Maltsev via cfe-commits]

Author: Mikhail Maltsev
Date: 2020-06-22T17:35:43Z
New Revision: 3a4feb1d53df68bed7748a0625b593ba4b5dae32

URL: 
https://github.com/llvm/llvm-project/commit/3a4feb1d53df68bed7748a0625b593ba4b5dae32
DIFF: 
https://github.com/llvm/llvm-project/commit/3a4feb1d53df68bed7748a0625b593ba4b5dae32.diff

LOG: [ARM][BFloat] Implement bf16 get/set_lane without casts to i16 vectors

Currently, in order to extract an element from a bf16 vector, we cast
the vector to an i16 vector, perform the extraction, and cast the result to
bfloat. This behavior was copied from the old fp16 implementation.

The goal of this patch is to achieve optimal code generation for lane
copying intrinsics in a subsequent patch (LLVM fails to fold certain
combinations of bitcast, insertelement, extractelement and
shufflevector instructions leading to the generation of suboptimal code).

Differential Revision: https://reviews.llvm.org/D82206

Added: 


Modified: 
clang/include/clang/Basic/arm_neon.td
clang/lib/CodeGen/CGBuiltin.cpp
clang/test/CodeGen/arm-bf16-getset-intrinsics.c

Removed: 




diff  --git a/clang/include/clang/Basic/arm_neon.td 
b/clang/include/clang/Basic/arm_neon.td
index 289f5ea47b92..42d50f726393 100644
--- a/clang/include/clang/Basic/arm_neon.td
+++ b/clang/include/clang/Basic/arm_neon.td
@@ -190,28 +190,20 @@ def OP_SCALAR_QRDMLAH_LN : Op<(call "vqadd", $p0, (call 
"vqrdmulh", $p1,
 def OP_SCALAR_QRDMLSH_LN : Op<(call "vqsub", $p0, (call "vqrdmulh", $p1,
   (call "vget_lane", $p2, $p3)))>;
 
-multiclass ScalarGetSetLaneOpsF16 {
-  def _GET_LN  : Op<(bitcast scalarTy,
-(call "vget_lane",
-(bitcast "int16x4_t", $p0), $p1))>;
-  def _GET_LNQ : Op<(bitcast scalarTy,
-(call "vget_lane",
-(bitcast "int16x8_t", $p0), $p1))>;
-  def _SET_LN  : Op<(bitcast vectorTy4,
-(call "vset_lane",
-(bitcast "int16_t", $p0),
-(bitcast "int16x4_t", $p1), $p2))>;
-  def _SET_LNQ : Op<(bitcast vectorTy8,
-(call "vset_lane",
-(bitcast "int16_t", $p0),
-(bitcast "int16x8_t", $p1), $p2))>;
-}
-
-defm OP_SCALAR_HALF: ScalarGetSetLaneOpsF16<"float16_t",
-"float16x4_t", "float16x8_t">;
-defm OP_SCALAR_BF16: ScalarGetSetLaneOpsF16<"bfloat16_t",
-"bfloat16x4_t", "bfloat16x8_t">;
+def OP_SCALAR_HALF_GET_LN : Op<(bitcast "float16_t",
+   (call "vget_lane",
+ (bitcast "int16x4_t", $p0), $p1))>;
+def OP_SCALAR_HALF_GET_LNQ : Op<(bitcast "float16_t",
+(call "vget_lane",
+  (bitcast "int16x8_t", $p0), $p1))>;
+def OP_SCALAR_HALF_SET_LN : Op<(bitcast "float16x4_t",
+   (call "vset_lane",
+ (bitcast "int16_t", $p0),
+ (bitcast "int16x4_t", $p1), $p2))>;
+def OP_SCALAR_HALF_SET_LNQ : Op<(bitcast "float16x8_t",
+(call "vset_lane",
+  (bitcast "int16_t", $p0),
+  (bitcast "int16x8_t", $p1), $p2))>;
 
 def OP_DOT_LN
 : Op<(call "vdot", $p0, $p1,
@@ -1918,10 +1910,12 @@ let ArchGuard = 
"defined(__ARM_FEATURE_BF16_VECTOR_ARITHMETIC)" in {
   def VGET_HIGH_BF : NoTestOpInst<"vget_high", ".Q", "b", OP_HI>;
   def VGET_LOW_BF  : NoTestOpInst<"vget_low", ".Q", "b", OP_LO>;
 
-  def VGET_LANE_BF : IOpInst<"vget_lane", "1.I", "b", OP_SCALAR_BF16_GET_LN>;
-  def VSET_LANE_BF : IOpInst<"vset_lane", ".1.I", "b", OP_SCALAR_BF16_SET_LN>;
-  def VGET_LANEQ_BF : IOpInst<"vget_lane", "1.I", "Qb", 
OP_SCALAR_BF16_GET_LNQ>;
-  def VSET_LANEQ_BF : IOpInst<"vset_lane", ".1.I", "Qb", 
OP_SCALAR_BF16_SET_LNQ>;
+  def VGET_LANE_BF : IInst<"vget_lane", "1.I", "bQb">;
+  def VSET_LANE_BF : IInst<"vset_lane", ".1.I", "bQb">;
+  def SCALAR_VDUP_LANE_BF : IInst<"vdup_lane", "1.I", "Sb">;
+  def SCALAR_VDUP_LANEQ_BF : IInst<"vdup_laneq", "1QI", "Sb"> {
+let isLaneQ = 1;
+  }
 
   def VLD1_BF : WInst<"vld1", ".(c*!)", "bQb">;
   def VLD2_BF : WInst<"vld2", "2(c*!)", "bQb">;
@@ -1957,18 +1951,6 @@ let ArchGuard = 
"defined(__ARM_FEATURE_BF16_VECTOR_ARITHMETIC)" in {
 
 }
 
-let ArchGuard = "defined(__ARM_FEATURE_BF16_VECTOR_ARITHMETIC) && 
!defined(__aarch64__)" in {
-  def SCALAR_VDUP_LANE_BF_A32 : IOpInst<"vduph_lane", "1.I", "b", 
OP_SCALAR_BF16_GET_LN>;
-  def SCALAR_VDUP_LANEQ_BF_A32 : IOpInst<"vduph_laneq", "1.I", "Hb", 
OP_SCALAR_BF16_GET_LNQ>;
-}
-
-let ArchGuard = "defined(__ARM_FEATURE_BF16_VECTOR_ARITHMETIC) && 
defined(__aarch64__)" in 

[clang] 089fbe6 - [Docs] Fixed formatting in release notes, NFC

[Mikhail Maltsev via cfe-commits]

Author: Mikhail Maltsev
Date: 2020-04-22T18:25:22+01:00
New Revision: 089fbe69193364fee14ed94a58c530d8417dc391

URL: 
https://github.com/llvm/llvm-project/commit/089fbe69193364fee14ed94a58c530d8417dc391
DIFF: 
https://github.com/llvm/llvm-project/commit/089fbe69193364fee14ed94a58c530d8417dc391.diff

LOG: [Docs] Fixed formatting in release notes, NFC

Added: 


Modified: 
clang/docs/ReleaseNotes.rst
llvm/docs/ReleaseNotes.rst

Removed: 




diff  --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst
index 1f4bc0f0d0da..88edf0092dc5 100644
--- a/clang/docs/ReleaseNotes.rst
+++ b/clang/docs/ReleaseNotes.rst
@@ -61,8 +61,8 @@ Non-comprehensive list of changes in this release
   v8.1-M MVE instruction set.  supports the complete API defined
   in the Arm C Language Extensions.
 
-- For the ARM target, C-language intrinsics  for the CDE instruction
-  set are now provided.
+- For the ARM target, C-language intrinsics  for the CDE
+  instruction set are now provided.
 
 * clang adds support for a set of  extended integer types (``_ExtInt(N)``) that
   permit non-power of 2 integers, exposing the LLVM integer types. Since a 
major

diff  --git a/llvm/docs/ReleaseNotes.rst b/llvm/docs/ReleaseNotes.rst
index 3afdce296fcd..e0ff25622704 100644
--- a/llvm/docs/ReleaseNotes.rst
+++ b/llvm/docs/ReleaseNotes.rst
@@ -79,7 +79,7 @@ During this release ...
 * Added support for assembly for the optional Custom Datapath Extension (CDE)
   for Arm M-profile targets.
 
-* Implemented C-language intrinsics  for the CDE instruction set.
+* Implemented C-language intrinsics  for the CDE instruction 
set.
 
 Changes to the MIPS Target
 --



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[clang] d7ab9e7 - [ARM] Release notes for the Custom Datapath Extension (CDE)

[Mikhail Maltsev via cfe-commits]

Author: Mikhail Maltsev
Date: 2020-04-22T16:34:19+01:00
New Revision: d7ab9e7c9b309ebac094bba209f7c15ad5f01768

URL: 
https://github.com/llvm/llvm-project/commit/d7ab9e7c9b309ebac094bba209f7c15ad5f01768
DIFF: 
https://github.com/llvm/llvm-project/commit/d7ab9e7c9b309ebac094bba209f7c15ad5f01768.diff

LOG: [ARM] Release notes for the Custom Datapath Extension (CDE)

Summary:
This change mentions CDE assembly in the LLVM release notes and CDE
intrinsics in both Clang and LLVM release notes.

Reviewers: kristof.beyls, simon_tatham

Reviewed By: kristof.beyls

Subscribers: danielkiss, cfe-commits

Tags: #clang

Differential Revision: https://reviews.llvm.org/D78481

Added: 


Modified: 
clang/docs/ReleaseNotes.rst
llvm/docs/ReleaseNotes.rst

Removed: 




diff  --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst
index 6ed00a5be936..1f4bc0f0d0da 100644
--- a/clang/docs/ReleaseNotes.rst
+++ b/clang/docs/ReleaseNotes.rst
@@ -61,6 +61,8 @@ Non-comprehensive list of changes in this release
   v8.1-M MVE instruction set.  supports the complete API defined
   in the Arm C Language Extensions.
 
+- For the ARM target, C-language intrinsics  for the CDE instruction
+  set are now provided.
 
 * clang adds support for a set of  extended integer types (``_ExtInt(N)``) that
   permit non-power of 2 integers, exposing the LLVM integer types. Since a 
major

diff  --git a/llvm/docs/ReleaseNotes.rst b/llvm/docs/ReleaseNotes.rst
index aad4ea88da1e..3afdce296fcd 100644
--- a/llvm/docs/ReleaseNotes.rst
+++ b/llvm/docs/ReleaseNotes.rst
@@ -76,6 +76,11 @@ During this release ...
   set.  now supports the complete API defined in the Arm C
   Language Extensions.
 
+* Added support for assembly for the optional Custom Datapath Extension (CDE)
+  for Arm M-profile targets.
+
+* Implemented C-language intrinsics  for the CDE instruction set.
+
 Changes to the MIPS Target
 --
 



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[clang] bd722ef - [ARM,CDE] Improve CDE intrinsics testing

[Mikhail Maltsev via cfe-commits]

Author: Mikhail Maltsev
Date: 2020-03-27T16:05:18Z
New Revision: bd722ef63f18ee672d60358113431f9bb5c55380

URL: 
https://github.com/llvm/llvm-project/commit/bd722ef63f18ee672d60358113431f9bb5c55380
DIFF: 
https://github.com/llvm/llvm-project/commit/bd722ef63f18ee672d60358113431f9bb5c55380.diff

LOG: [ARM,CDE] Improve CDE intrinsics testing

Summary:
This patch:
* adds tests for vreinterpret intinsics in big-endian mode
* adds C++ runs to the CDE+MVE header compatibility test

Reviewers: simon_tatham, MarkMurrayARM, ostannard, dmgreen

Reviewed By: simon_tatham

Subscribers: kristof.beyls, cfe-commits

Tags: #clang

Differential Revision: https://reviews.llvm.org/D76927

Added: 


Modified: 
clang/test/CodeGen/arm-cde-reinterpret.c
clang/test/Headers/arm-cde-header.c

Removed: 




diff  --git a/clang/test/CodeGen/arm-cde-reinterpret.c 
b/clang/test/CodeGen/arm-cde-reinterpret.c
index 569b51bdfdbe..c169a88bc4e3 100644
--- a/clang/test/CodeGen/arm-cde-reinterpret.c
+++ b/clang/test/CodeGen/arm-cde-reinterpret.c
@@ -1,8 +1,11 @@
-// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
 // RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi \
 // RUN:   -target-feature +cdecp0 -target-feature +mve.fp \
 // RUN:   -mfloat-abi hard -O0 -disable-O0-optnone \
-// RUN:   -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s
+// RUN:   -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s 
--check-prefixes=CHECK,CHECK-LE
+// RUN: %clang_cc1 -triple thumbebv8.1m.main-arm-none-eabi \
+// RUN:   -target-feature +cdecp0 -target-feature +mve.fp \
+// RUN:   -mfloat-abi hard -O0 -disable-O0-optnone \
+// RUN:   -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s 
--check-prefixes=CHECK,CHECK-BE
 
 #include 
 
@@ -16,7 +19,8 @@ int8x16_t test_s8(uint8x16_t x) {
 
 // CHECK-LABEL: @test_u16(
 // CHECK-NEXT:  entry:
-// CHECK-NEXT:[[TMP0:%.*]] = bitcast <16 x i8> [[X:%.*]] to <8 x i16>
+// CHECK-LE-NEXT: [[TMP0:%.*]] = bitcast <16 x i8> [[X:%.*]] to <8 x i16>
+// CHECK-BE-NEXT: [[TMP0:%.*]] = call <8 x i16> 
@llvm.arm.mve.vreinterpretq.v8i16.v16i8(<16 x i8> [[X:%.*]])
 // CHECK-NEXT:ret <8 x i16> [[TMP0]]
 //
 uint16x8_t test_u16(uint8x16_t x) {
@@ -25,7 +29,8 @@ uint16x8_t test_u16(uint8x16_t x) {
 
 // CHECK-LABEL: @test_s32(
 // CHECK-NEXT:  entry:
-// CHECK-NEXT:[[TMP0:%.*]] = bitcast <16 x i8> [[X:%.*]] to <4 x i32>
+// CHECK-LE-NEXT: [[TMP0:%.*]] = bitcast <16 x i8> [[X:%.*]] to <4 x i32>
+// CHECK-BE-NEXT: [[TMP0:%.*]] = call <4 x i32> 
@llvm.arm.mve.vreinterpretq.v4i32.v16i8(<16 x i8> [[X:%.*]])
 // CHECK-NEXT:ret <4 x i32> [[TMP0]]
 //
 int32x4_t test_s32(uint8x16_t x) {
@@ -34,7 +39,8 @@ int32x4_t test_s32(uint8x16_t x) {
 
 // CHECK-LABEL: @test_u32(
 // CHECK-NEXT:  entry:
-// CHECK-NEXT:[[TMP0:%.*]] = bitcast <16 x i8> [[X:%.*]] to <4 x i32>
+// CHECK-LE-NEXT: [[TMP0:%.*]] = bitcast <16 x i8> [[X:%.*]] to <4 x i32>
+// CHECK-BE-NEXT: [[TMP0:%.*]] = call <4 x i32> 
@llvm.arm.mve.vreinterpretq.v4i32.v16i8(<16 x i8> [[X:%.*]])
 // CHECK-NEXT:ret <4 x i32> [[TMP0]]
 //
 uint32x4_t test_u32(uint8x16_t x) {
@@ -43,7 +49,8 @@ uint32x4_t test_u32(uint8x16_t x) {
 
 // CHECK-LABEL: @test_s64(
 // CHECK-NEXT:  entry:
-// CHECK-NEXT:[[TMP0:%.*]] = bitcast <16 x i8> [[X:%.*]] to <2 x i64>
+// CHECK-LE-NEXT: [[TMP0:%.*]] = bitcast <16 x i8> [[X:%.*]] to <2 x i64>
+// CHECK-BE-NEXT: [[TMP0:%.*]] = call <2 x i64> 
@llvm.arm.mve.vreinterpretq.v2i64.v16i8(<16 x i8> [[X:%.*]])
 // CHECK-NEXT:ret <2 x i64> [[TMP0]]
 //
 int64x2_t test_s64(uint8x16_t x) {
@@ -52,7 +59,8 @@ int64x2_t test_s64(uint8x16_t x) {
 
 // CHECK-LABEL: @test_u64(
 // CHECK-NEXT:  entry:
-// CHECK-NEXT:[[TMP0:%.*]] = bitcast <16 x i8> [[X:%.*]] to <2 x i64>
+// CHECK-LE-NEXT: [[TMP0:%.*]] = bitcast <16 x i8> [[X:%.*]] to <2 x i64>
+// CHECK-BE-NEXT: [[TMP0:%.*]] = call <2 x i64> 
@llvm.arm.mve.vreinterpretq.v2i64.v16i8(<16 x i8> [[X:%.*]])
 // CHECK-NEXT:ret <2 x i64> [[TMP0]]
 //
 uint64x2_t test_u64(uint8x16_t x) {
@@ -61,7 +69,8 @@ uint64x2_t test_u64(uint8x16_t x) {
 
 // CHECK-LABEL: @test_f16(
 // CHECK-NEXT:  entry:
-// CHECK-NEXT:[[TMP0:%.*]] = bitcast <16 x i8> [[X:%.*]] to <8 x half>
+// CHECK-LE-NEXT: [[TMP0:%.*]] = bitcast <16 x i8> [[X:%.*]] to <8 x half>
+// CHECK-BE-NEXT: [[TMP0:%.*]] = call <8 x half> 
@llvm.arm.mve.vreinterpretq.v8f16.v16i8(<16 x i8> [[X:%.*]])
 // CHECK-NEXT:ret <8 x half> [[TMP0]]
 //
 float16x8_t test_f16(uint8x16_t x) {
@@ -70,7 +79,8 @@ float16x8_t test_f16(uint8x16_t x) {
 
 // CHECK-LABEL: @test_f32(
 // CHECK-NEXT:  entry:
-// CHECK-NEXT:[[TMP0:%.*]] = bitcast <16 x i8> [[X:%.*]] to <4 x float>
+// CHECK-LE-NEXT: [[TMP0:%.*]] = bitcast <16 x i8> [[X:%.*]] to <4 x float>
+// CHECK-BE-NEXT: [[TMP0:%.*]] = call <4 x float> 
@llvm.arm.mve.vreinterpretq.v4f32.v16i8(<16 x i8> [[X:%.*]])
 // CHECK-NEXT:ret <4 x float> [[TMP0]]
 //
 float32x4_t 

[clang] bb4da94 - [ARM, CDE] Implement predicated Q-register CDE intrinsics

[Mikhail Maltsev via cfe-commits]

Author: Mikhail Maltsev
Date: 2020-03-25T17:08:19Z
New Revision: bb4da94e5b5f64ea68197de9be44c7c5a4c91ce7

URL: 
https://github.com/llvm/llvm-project/commit/bb4da94e5b5f64ea68197de9be44c7c5a4c91ce7
DIFF: 
https://github.com/llvm/llvm-project/commit/bb4da94e5b5f64ea68197de9be44c7c5a4c91ce7.diff

LOG: [ARM,CDE] Implement predicated Q-register CDE intrinsics

Summary:
This patch implements the following CDE intrinsics:

  T __arm_vcx1q_m(int coproc, T inactive, uint32_t imm, mve_pred_t p);
  T __arm_vcx2q_m(int coproc, T inactive, U n, uint32_t imm, mve_pred_t p);
  T __arm_vcx3q_m(int coproc, T inactive, U n, V m, uint32_t imm, mve_pred_t p);

  T __arm_vcx1qa_m(int coproc, T acc, uint32_t imm, mve_pred_t p);
  T __arm_vcx2qa_m(int coproc, T acc, U n, uint32_t imm, mve_pred_t p);
  T __arm_vcx3qa_m(int coproc, T acc, U n, V m, uint32_t imm, mve_pred_t p);

The intrinsics are not part of the released ACLE spec, but internally at
Arm we have reached consensus to add them to the next ACLE release.

Reviewers: simon_tatham, MarkMurrayARM, ostannard, dmgreen

Reviewed By: simon_tatham

Subscribers: kristof.beyls, hiraditya, danielkiss, cfe-commits

Tags: #clang

Differential Revision: https://reviews.llvm.org/D76610

Added: 


Modified: 
clang/include/clang/Basic/arm_cde.td
clang/test/CodeGen/arm-cde-vec.c
llvm/include/llvm/IR/IntrinsicsARM.td
llvm/lib/Target/ARM/ARMInstrCDE.td
llvm/test/CodeGen/Thumb2/cde-vec.ll

Removed: 




diff  --git a/clang/include/clang/Basic/arm_cde.td 
b/clang/include/clang/Basic/arm_cde.td
index e258bf5ee83e..6a00e669864c 100644
--- a/clang/include/clang/Basic/arm_cde.td
+++ b/clang/include/clang/Basic/arm_cde.td
@@ -189,6 +189,40 @@ def vcx3qa : FunctionMacro<
   "__arm_vcx3qa_impl((cp), (acc), __arm_vreinterpretq_u8(n), "
  "__arm_vreinterpretq_u8(m), (imm))">;
 
+class CDEIntrinsicMasked
+  : CDEIntrinsic
+$cp, $inactive_or_acc), cgArgs, (? $imm, $pred))> {
+  let params = T.All;
+  let polymorphicOnly = 1;
+}
+
+def vcx1q_m : CDEIntrinsicMasked<"vcx1q", (args), (args imm_12b:$imm), (?)>;
+def vcx1qa_m : CDEIntrinsicMasked<"vcx1qa", (args), (args imm_12b:$imm), (?)>;
+
+multiclass VCXPredicated macroArgs, string macro> {
+  def _m_impl : CDEIntrinsicMasked;
+  def a_m_impl : CDEIntrinsicMasked;
+
+  def _m: FunctionMacro<
+!listconcat(["cp", "inactive"], macroArgs, ["imm", "pred"]),
+"__arm_"#NAME#"_m_impl((cp), (inactive), "#macro#" (imm), (pred))">;
+  def a_m: FunctionMacro<
+!listconcat(["cp", "acc"], macroArgs, ["imm", "pred"]),
+"__arm_"#NAME#"a_m_impl((cp), (acc), "#macro#" (imm), (pred))">;
+}
+
+defm vcx2q :
+  VCXPredicated<(args v16u8:$n), (args imm_7b:$imm), (? $n), ["n"],
+"__arm_vreinterpretq_u8(n),">;
+defm vcx3q :
+  VCXPredicated<(args v16u8:$n, v16u8:$m), (args imm_4b:$imm), (? $n, $m),
+["n", "m"], "__arm_vreinterpretq_u8(n), "
+"__arm_vreinterpretq_u8(m),">;
+
 // vreinterpretq intrinsics required by the ACLE CDE specification
 
 foreach desttype = [/* no u8 */ s8, u16, s16, u32, s32, u64, s64, f16, f32] in 
{

diff  --git a/clang/test/CodeGen/arm-cde-vec.c 
b/clang/test/CodeGen/arm-cde-vec.c
index fcf9270d87f0..ea186a46be00 100644
--- a/clang/test/CodeGen/arm-cde-vec.c
+++ b/clang/test/CodeGen/arm-cde-vec.c
@@ -102,3 +102,75 @@ uint64x2_t test_vcx3q(uint64x2_t n, float32x4_t m) {
 int8x16_t test_vcx3qa(int8x16_t acc, uint16x8_t n, float32x4_t m) {
   return __arm_vcx3qa(1, acc, n, m, 13);
 }
+
+// CHECK-LABEL: @test_vcx1q_m(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
+// CHECK-NEXT:[[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 
[[TMP0]])
+// CHECK-NEXT:[[TMP2:%.*]] = call <8 x i16> 
@llvm.arm.cde.vcx1q.predicated.v8i16.v8i1(i32 0, <8 x i16> [[INACTIVE:%.*]], 
i32 , <8 x i1> [[TMP1]])
+// CHECK-NEXT:ret <8 x i16> [[TMP2]]
+//
+uint16x8_t test_vcx1q_m(uint16x8_t inactive, mve_pred16_t p) {
+  return __arm_vcx1q_m(0, inactive, , p);
+}
+
+// CHECK-LABEL: @test_vcx1qa_m(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
+// CHECK-NEXT:[[TMP1:%.*]] = call <16 x i1> 
@llvm.arm.mve.pred.i2v.v16i1(i32 [[TMP0]])
+// CHECK-NEXT:[[TMP2:%.*]] = call <16 x i8> 
@llvm.arm.cde.vcx1qa.predicated.v16i8.v16i1(i32 1, <16 x i8> [[ACC:%.*]], i32 
1112, <16 x i1> [[TMP1]])
+// CHECK-NEXT:ret <16 x i8> [[TMP2]]
+//
+uint8x16_t test_vcx1qa_m(uint8x16_t acc, mve_pred16_t p) {
+  return __arm_vcx1qa_m(1, acc, 1112, p);
+}
+
+// CHECK-LABEL: @test_vcx2q_m(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = bitcast <4 x float> [[N:%.*]] to <16 x i8>
+// CHECK-NEXT:[[TMP1:%.*]] = zext i16 [[P:%.*]] to i32
+// CHECK-NEXT:[[TMP2:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 
[[TMP1]])
+// CHECK-NEXT:[[TMP3:%.*]] = call <4 x i32> 

Re: [clang] 43606ef - Suppress an "unused variable" warning in release build

[Mikhail Maltsev via cfe-commits]

Yes, it does. isIntegerConstantExpr assigns a value to CoprocNoAP.

--
Regards,
   Mikhail Maltsev


From: David Blaikie 
Sent: Sunday, March 22, 2020 03:32
To: Mikhail Maltsev; Mikhail Maltsev
Cc: cfe-commits
Subject: Re: [clang] 43606ef - Suppress an "unused variable" warning in release 
build

Does "isIntegerConstantExpr" have side effects that are desired/necessary? 
Otherwise please change this to roll the isIntegerConstantExpr into the assert 
(so that it is only executed when asserts are enabled)

On Tue, Mar 10, 2020 at 10:11 AM Mikhail Maltsev via cfe-commits 
mailto:cfe-commits@lists.llvm.org>> wrote:

Author: Mikhail Maltsev
Date: 2020-03-10T17:10:52Z
New Revision: 43606efb6847fc9c79e7d93760a2a6191e8a8539

URL: 
https://github.com/llvm/llvm-project/commit/43606efb6847fc9c79e7d93760a2a6191e8a8539
DIFF: 
https://github.com/llvm/llvm-project/commit/43606efb6847fc9c79e7d93760a2a6191e8a8539.diff

LOG: Suppress an "unused variable" warning in release build

Added:


Modified:
clang/lib/Sema/SemaChecking.cpp

Removed:




diff  --git a/clang/lib/Sema/SemaChecking.cpp b/clang/lib/Sema/SemaChecking.cpp
index 24d0d9209a1d..8a2b4b019663 100644
--- a/clang/lib/Sema/SemaChecking.cpp
+++ b/clang/lib/Sema/SemaChecking.cpp
@@ -2094,6 +2094,7 @@ bool Sema::CheckARMCoprocessorImmediate(const Expr 
*CoprocArg, bool WantCDE) {

   llvm::APSInt CoprocNoAP;
   bool IsICE = CoprocArg->isIntegerConstantExpr(CoprocNoAP, Context);
+  (void)IsICE;
   assert(IsICE && "Coprocossor immediate is not a constant expression");
   int64_t CoprocNo = CoprocNoAP.getExtValue();
   assert(CoprocNo >= 0 && "Coprocessor immediate must be non-negative");



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[clang] 6ae3eff - [ARM,CDE] Implement CDE vreinterpret intrinsics

[Mikhail Maltsev via cfe-commits]

Author: Mikhail Maltsev
Date: 2020-03-20T14:01:57Z
New Revision: 6ae3eff8baaca95752b1ec9732c605b3d4e8d630

URL: 
https://github.com/llvm/llvm-project/commit/6ae3eff8baaca95752b1ec9732c605b3d4e8d630
DIFF: 
https://github.com/llvm/llvm-project/commit/6ae3eff8baaca95752b1ec9732c605b3d4e8d630.diff

LOG: [ARM,CDE] Implement CDE vreinterpret intrinsics

Summary:
This patch implements the following CDE intrinsics:

  int8x16_t __arm_vreinterpretq_s8_u8 (uint8x16_t in);
  uint16x8_t __arm_vreinterpretq_u16_u8 (uint8x16_t in);
  int16x8_t __arm_vreinterpretq_s16_u8 (uint8x16_t in);
  uint32x4_t __arm_vreinterpretq_u32_u8 (uint8x16_t in);
  int32x4_t __arm_vreinterpretq_s32_u8 (uint8x16_t in);
  uint64x2_t __arm_vreinterpretq_u64_u8 (uint8x16_t in);
  int64x2_t __arm_vreinterpretq_s64_u8 (uint8x16_t in);
  float16x8_t __arm_vreinterpretq_f16_u8 (uint8x16_t in);
  float32x4_t __arm_vreinterpretq_f32_u8 (uint8x16_t in);

These intrinsics are header-only because they reuse the existing
MVE vreinterpret clang built-ins.

This set is slightly different from the published specification
(see https://static.docs.arm.com/101028/0010/ACLE_2019Q4_release-0010.pdf):
it includes

  int8x16_t __arm_vreinterpretq_s8_u8 (uint8x16_t in);

which was unintentionally ommitted from the spec, and
does not include

  float64x2_t __arm_vreinterpretq_f64_u8 (uint8x16_t in);

The float64x2_t type requires additional implementation
effort, and we are not including it yet.

Reviewers: simon_tatham, MarkMurrayARM, dmgreen, ostannard

Reviewed By: MarkMurrayARM

Subscribers: kristof.beyls, danielkiss, cfe-commits

Tags: #clang

Differential Revision: https://reviews.llvm.org/D76300

Added: 
clang/test/CodeGen/arm-cde-reinterpret.c

Modified: 
clang/include/clang/Basic/arm_cde.td

Removed: 




diff  --git a/clang/include/clang/Basic/arm_cde.td 
b/clang/include/clang/Basic/arm_cde.td
index 2d48cbf21d8c..e258bf5ee83e 100644
--- a/clang/include/clang/Basic/arm_cde.td
+++ b/clang/include/clang/Basic/arm_cde.td
@@ -188,3 +188,11 @@ def vcx3qa : FunctionMacro<
   ["cp", "acc", "n", "m", "imm"],
   "__arm_vcx3qa_impl((cp), (acc), __arm_vreinterpretq_u8(n), "
  "__arm_vreinterpretq_u8(m), (imm))">;
+
+// vreinterpretq intrinsics required by the ACLE CDE specification
+
+foreach desttype = [/* no u8 */ s8, u16, s16, u32, s32, u64, s64, f16, f32] in 
{
+  let params = [u8], headerOnly = 1, pnt = PNT_None in
+  def "vreinterpretq_" # desttype : Intrinsic<
+VecOf, (args Vector:$x), (vreinterpret $x, VecOf)>;
+}

diff  --git a/clang/test/CodeGen/arm-cde-reinterpret.c 
b/clang/test/CodeGen/arm-cde-reinterpret.c
new file mode 100644
index ..569b51bdfdbe
--- /dev/null
+++ b/clang/test/CodeGen/arm-cde-reinterpret.c
@@ -0,0 +1,78 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi \
+// RUN:   -target-feature +cdecp0 -target-feature +mve.fp \
+// RUN:   -mfloat-abi hard -O0 -disable-O0-optnone \
+// RUN:   -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s
+
+#include 
+
+// CHECK-LABEL: @test_s8(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:ret <16 x i8> [[X:%.*]]
+//
+int8x16_t test_s8(uint8x16_t x) {
+  return __arm_vreinterpretq_s8_u8(x);
+}
+
+// CHECK-LABEL: @test_u16(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = bitcast <16 x i8> [[X:%.*]] to <8 x i16>
+// CHECK-NEXT:ret <8 x i16> [[TMP0]]
+//
+uint16x8_t test_u16(uint8x16_t x) {
+  return __arm_vreinterpretq_u16_u8(x);
+}
+
+// CHECK-LABEL: @test_s32(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = bitcast <16 x i8> [[X:%.*]] to <4 x i32>
+// CHECK-NEXT:ret <4 x i32> [[TMP0]]
+//
+int32x4_t test_s32(uint8x16_t x) {
+  return __arm_vreinterpretq_s32_u8(x);
+}
+
+// CHECK-LABEL: @test_u32(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = bitcast <16 x i8> [[X:%.*]] to <4 x i32>
+// CHECK-NEXT:ret <4 x i32> [[TMP0]]
+//
+uint32x4_t test_u32(uint8x16_t x) {
+  return __arm_vreinterpretq_u32_u8(x);
+}
+
+// CHECK-LABEL: @test_s64(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = bitcast <16 x i8> [[X:%.*]] to <2 x i64>
+// CHECK-NEXT:ret <2 x i64> [[TMP0]]
+//
+int64x2_t test_s64(uint8x16_t x) {
+  return __arm_vreinterpretq_s64_u8(x);
+}
+
+// CHECK-LABEL: @test_u64(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = bitcast <16 x i8> [[X:%.*]] to <2 x i64>
+// CHECK-NEXT:ret <2 x i64> [[TMP0]]
+//
+uint64x2_t test_u64(uint8x16_t x) {
+  return __arm_vreinterpretq_u64_u8(x);
+}
+
+// CHECK-LABEL: @test_f16(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = bitcast <16 x i8> [[X:%.*]] to <8 x half>
+// CHECK-NEXT:ret <8 x half> [[TMP0]]
+//
+float16x8_t test_f16(uint8x16_t x) {
+  return __arm_vreinterpretq_f16_u8(x);
+}
+
+// CHECK-LABEL: @test_f32(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = bitcast 

[clang] 969034b - [ARM, CDE] Implement CDE unpredicated Q-register intrinsics

[Mikhail Maltsev via cfe-commits]

Author: Mikhail Maltsev
Date: 2020-03-20T14:01:56Z
New Revision: 969034b86037d3c1daf725aef13ba16424f92fe1

URL: 
https://github.com/llvm/llvm-project/commit/969034b86037d3c1daf725aef13ba16424f92fe1
DIFF: 
https://github.com/llvm/llvm-project/commit/969034b86037d3c1daf725aef13ba16424f92fe1.diff

LOG: [ARM,CDE] Implement CDE unpredicated Q-register intrinsics

Summary:
This patch implements the following intrinsics:

  uint8x16_t __arm_vcx1q_u8 (int coproc, uint32_t imm);
  T __arm_vcx1qa(int coproc, T acc, uint32_t imm);
  T __arm_vcx2q(int coproc, T n, uint32_t imm);
  uint8x16_t __arm_vcx2q_u8(int coproc, T n, uint32_t imm);
  T __arm_vcx2qa(int coproc, T acc, U n, uint32_t imm);
  T __arm_vcx3q(int coproc, T n, U m, uint32_t imm);
  uint8x16_t __arm_vcx3q_u8(int coproc, T n, U m, uint32_t imm);
  T __arm_vcx3qa(int coproc, T acc, U n, V m, uint32_t imm);

Most of them are polymorphic. Furthermore, some intrinsics are
polymorphic by 2 or 3 parameter types, such polymorphism is not
supported by the existing MVE/CDE tablegen backends, also we don't
really want to have a combinatorial explosion caused by 1000 different
combinations of 3 vector types. Because of this some intrinsics are
implemented as macros involving a cast of the polymorphic arguments to
uint8x16_t.

The IR intrinsics are even more restricted in terms of types: all MVE
vectors are cast to v16i8.

Reviewers: simon_tatham, MarkMurrayARM, dmgreen, ostannard

Reviewed By: MarkMurrayARM

Subscribers: kristof.beyls, hiraditya, danielkiss, cfe-commits

Tags: #clang

Differential Revision: https://reviews.llvm.org/D76299

Added: 
clang/test/CodeGen/arm-cde-vec.c
llvm/test/CodeGen/Thumb2/cde-vec.ll

Modified: 
clang/include/clang/Basic/arm_cde.td
clang/test/Sema/arm-cde-immediates.c
clang/utils/TableGen/MveEmitter.cpp
llvm/include/llvm/IR/IntrinsicsARM.td
llvm/lib/Target/ARM/ARMInstrCDE.td

Removed: 




diff  --git a/clang/include/clang/Basic/arm_cde.td 
b/clang/include/clang/Basic/arm_cde.td
index 9cd0af8987c9..2d48cbf21d8c 100644
--- a/clang/include/clang/Basic/arm_cde.td
+++ b/clang/include/clang/Basic/arm_cde.td
@@ -37,6 +37,13 @@ class CDEImmediateBits : Immediate>;
 class CDEIRInt params = [], bit appendKind = 0>
   : IRIntBase<"arm_cde_" # name, params, appendKind>;
 
+// Class for generating function macros in arm_cde.h:
+// "#define () "
+class FunctionMacro params_, string definition_> {
+  list params = params_;
+  string definition = definition_;
+}
+
 // Coprocessor immediate
 def imm_coproc : Immediate>;
 
@@ -107,3 +114,77 @@ defm vcx2: CDE_VCXFP_m<(args imm_6b:$imm), (args u32:$n), 
(args u64:$n),
 defm vcx3: CDE_VCXFP_m<(args imm_3b:$imm),
(args u32:$n, u32:$m), (args u64:$n, u64:$m),
(? (bitcast $n, FScalar), (bitcast $m, FScalar))>;
+
+// VCX* instructions operating on Q vector registers
+
+def v16u8 : VecOf;
+
+let pnt = PNT_None, params = [u8] in
+def vcx1q : CDEIntrinsic $cp, $imm)>;
+
+let pnt = PNT_Type, params = T.All, polymorphicOnly = 1 in {
+  def vcx1qa :
+CDEIntrinsic $cp, (bitcast $acc, v16u8), $imm),
+ Vector)>;
+
+  def vcx2q :
+CDEIntrinsic $cp, (bitcast $n, VecOf), $imm),
+  Vector)>;
+  def vcx2q_u8 :
+CDEIntrinsic $cp, (bitcast $n, VecOf), $imm)>;
+
+  def vcx2qa_impl :
+CDEIntrinsic $cp, (bitcast $acc, v16u8), $n, $imm),
+ Vector)>;
+
+  def vcx3q_impl :
+CDEIntrinsic $cp, (bitcast $n, v16u8), $m, $imm),
+ Vector)>;
+  def vcx3q_u8_impl :
+CDEIntrinsic $cp, (bitcast $n, v16u8), $m, $imm)>;
+  def vcx3qa_impl :
+CDEIntrinsic $cp, (bitcast $acc, v16u8), $n, $m,
+ $imm),
+ Vector)>;
+}
+
+// Reinterpret intrinsics required to implement __arm_vcx*q with 2 or 3
+// polymorphic paramters.
+let params = [/* no u8 */ s8, u16, s16, u32, s32, u64, s64, f16, f32],
+headerOnly = 1, polymorphicOnly = 1 in
+def vreinterpretq_u8 :
+Intrinsic;
+
+// We need vreinterpretq_u8_u8 to avoid doing smart tricks in the macros
+let params = [u8], polymorphicOnly = 1 in
+def vreinterpretq_u8_cde :
+CDEIntrinsic,
+NameOverride<"vreinterpretq_u8">;
+
+
+def vcx2qa : FunctionMacro<
+  ["cp", "acc", "n", "imm"],
+  "__arm_vcx2qa_impl((cp), (acc), __arm_vreinterpretq_u8(n), (imm))">;
+
+def vcx3q : FunctionMacro<
+  ["cp", "n", "m", "imm"],
+  "__arm_vcx3q_impl((cp), (n), __arm_vreinterpretq_u8(m), (imm))">;
+def vcx3q_u8 : FunctionMacro<
+  ["cp", "n", "m", "imm"],
+  "__arm_vcx3q_u8_impl((cp), (n), __arm_vreinterpretq_u8(m), (imm))">;
+def vcx3qa : FunctionMacro<
+  ["cp", "acc", "n", "m", "imm"],
+  "__arm_vcx3qa_impl((cp), (acc), __arm_vreinterpretq_u8(n), "
+ "__arm_vreinterpretq_u8(m), (imm))">;

diff  --git a/clang/test/CodeGen/arm-cde-vec.c 

[clang] 7a85e35 - [ARM,CDE] Implement GPR CDE intrinsics

[Mikhail Maltsev via cfe-commits]

Author: Mikhail Maltsev
Date: 2020-03-20T14:01:51Z
New Revision: 7a85e3585ec59b1bfe3b08072ff042af80d07f22

URL: 
https://github.com/llvm/llvm-project/commit/7a85e3585ec59b1bfe3b08072ff042af80d07f22
DIFF: 
https://github.com/llvm/llvm-project/commit/7a85e3585ec59b1bfe3b08072ff042af80d07f22.diff

LOG: [ARM,CDE] Implement GPR CDE intrinsics

Summary:
This change implements ACLE CDE intrinsics that translate to
instructions working with general-purpose registers.

The specification is available at
https://static.docs.arm.com/101028/0010/ACLE_2019Q4_release-0010.pdf

Each ACLE intrinsic gets a corresponding LLVM IR intrinsic (because
they have distinct function prototypes). Dual-register operands are
represented as pairs of i32 values. Because of this the instruction
selection for these intrinsics cannot be represented as TableGen
patterns and requires custom C++ code.

Reviewers: simon_tatham, MarkMurrayARM, dmgreen, ostannard

Reviewed By: MarkMurrayARM

Subscribers: kristof.beyls, hiraditya, danielkiss, cfe-commits

Tags: #clang

Differential Revision: https://reviews.llvm.org/D76296

Added: 
llvm/test/CodeGen/Thumb2/cde-gpr.ll

Modified: 
clang/include/clang/Basic/arm_cde.td
clang/test/CodeGen/arm-cde-gpr.c
clang/test/Sema/arm-cde-immediates.c
llvm/include/llvm/IR/IntrinsicsARM.td
llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
llvm/lib/Target/ARM/ARMInstrCDE.td

Removed: 




diff  --git a/clang/include/clang/Basic/arm_cde.td 
b/clang/include/clang/Basic/arm_cde.td
index 222b63966a38..139007d387a0 100644
--- a/clang/include/clang/Basic/arm_cde.td
+++ b/clang/include/clang/Basic/arm_cde.td
@@ -13,6 +13,7 @@
 
 include "arm_mve_defs.td"
 
+// ACLE CDE intrinsic
 class CDEIntrinsic
   : Intrinsic {
   let builtinExtension = "cde";
@@ -40,6 +41,32 @@ def imm_11b : CDEImmediateBits<11>;
 def imm_12b : CDEImmediateBits<12>;
 def imm_13b : CDEImmediateBits<13>;
 
-let pnt = PNT_None, params = T.None in
-def cx1 : CDEIntrinsic $cp, $imm)>;
+// CX* instructions operating on GPRs
+multiclass CDE_CX_m {
+  defvar cp = (args imm_coproc:$cp);
+  let pnt = PNT_None, params = T.None in {
+def "" : CDEIntrinsic $cp), cgArgs, (? $imm))>;
+def a  : CDEIntrinsic $cp, $acc),
+cgArgs, (? $imm))>;
+
+def d :
+  CDEIntrinsic $cp), cgArgs, (? $imm)):$pair,
+ (or (shl (u64 (xval $pair, 1)), (u64 32)),
+  (u64 (xval $pair, 0>;
+def da :
+  CDEIntrinsic $cp, $acc_lo, $acc_hi), cgArgs,
+   (? $imm)):$pair,
+ (or (shl (u64 (xval $pair, 1)), (u64 32)),
+  (u64 (xval $pair, 0>;
+  }
+}
+
+defm cx1 : CDE_CX_m<(args imm_13b:$imm), (args), (?)>;
+defm cx2 : CDE_CX_m<(args imm_9b:$imm), (args u32:$n), (? $n)>;
+defm cx3 : CDE_CX_m<(args imm_6b:$imm), (args u32:$n, u32:$m), (? $n, $m)>;

diff  --git a/clang/test/CodeGen/arm-cde-gpr.c 
b/clang/test/CodeGen/arm-cde-gpr.c
index 9a24b1540b67..1e6893d7d2f8 100644
--- a/clang/test/CodeGen/arm-cde-gpr.c
+++ b/clang/test/CodeGen/arm-cde-gpr.c
@@ -11,6 +11,150 @@
 // CHECK-NEXT:[[TMP0:%.*]] = call i32 @llvm.arm.cde.cx1(i32 0, i32 123)
 // CHECK-NEXT:ret i32 [[TMP0]]
 //
-uint32_t test_cx1() {
+uint32_t test_cx1(void) {
   return __arm_cx1(0, 123);
 }
+
+// CHECK-LABEL: @test_cx1a(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = call i32 @llvm.arm.cde.cx1a(i32 0, i32 
[[ACC:%.*]], i32 345)
+// CHECK-NEXT:ret i32 [[TMP0]]
+//
+uint32_t test_cx1a(uint32_t acc) {
+  return __arm_cx1a(0, acc, 345);
+}
+
+// CHECK-LABEL: @test_cx1d(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = call { i32, i32 } @llvm.arm.cde.cx1d(i32 1, 
i32 567)
+// CHECK-NEXT:[[TMP1:%.*]] = extractvalue { i32, i32 } [[TMP0]], 1
+// CHECK-NEXT:[[TMP2:%.*]] = zext i32 [[TMP1]] to i64
+// CHECK-NEXT:[[TMP3:%.*]] = shl i64 [[TMP2]], 32
+// CHECK-NEXT:[[TMP4:%.*]] = extractvalue { i32, i32 } [[TMP0]], 0
+// CHECK-NEXT:[[TMP5:%.*]] = zext i32 [[TMP4]] to i64
+// CHECK-NEXT:[[TMP6:%.*]] = or i64 [[TMP3]], [[TMP5]]
+// CHECK-NEXT:ret i64 [[TMP6]]
+//
+uint64_t test_cx1d(void) {
+  return __arm_cx1d(1, 567);
+}
+
+// CHECK-LABEL: @test_cx1da(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = lshr i64 [[ACC:%.*]], 32
+// CHECK-NEXT:[[TMP1:%.*]] = trunc i64 [[TMP0]] to i32
+// CHECK-NEXT:[[TMP2:%.*]] = trunc i64 [[ACC]] to i32
+// CHECK-NEXT:[[TMP3:%.*]] = call { i32, i32 } @llvm.arm.cde.cx1da(i32 0, 
i32 [[TMP2]], i32 [[TMP1]], i32 789)
+// CHECK-NEXT:[[TMP4:%.*]] = extractvalue { i32, i32 } [[TMP3]], 1
+// CHECK-NEXT:[[TMP5:%.*]] = zext i32 [[TMP4]] to i64
+// CHECK-NEXT:[[TMP6:%.*]] = shl i64 [[TMP5]], 32
+// CHECK-NEXT:[[TMP7:%.*]] = extractvalue { i32, i32 } [[TMP3]], 0
+// CHECK-NEXT:[[TMP8:%.*]] = zext i32 [[TMP7]] to i64
+// CHECK-NEXT:[[TMP9:%.*]] = or i64 [[TMP6]], 

[clang] d22e661 - [ARM, CDE] Implement CDE S and D-register intrinsics

[Mikhail Maltsev via cfe-commits]

Author: Mikhail Maltsev
Date: 2020-03-20T14:01:53Z
New Revision: d22e66171251cd3dd07507912189aa814a419678

URL: 
https://github.com/llvm/llvm-project/commit/d22e66171251cd3dd07507912189aa814a419678
DIFF: 
https://github.com/llvm/llvm-project/commit/d22e66171251cd3dd07507912189aa814a419678.diff

LOG: [ARM,CDE] Implement CDE S and D-register intrinsics

Summary:
This patch implements the following ACLE intrinsics:

  uint32_t __arm_vcx1_u32(int coproc, uint32_t imm);
  uint32_t __arm_vcx1a_u32(int coproc, uint32_t acc, uint32_t imm);
  uint32_t __arm_vcx2_u32(int coproc, uint32_t n, uint32_t imm);
  uint32_t __arm_vcx2a_u32(int coproc, uint32_t acc, uint32_t n, uint32_t imm);
  uint32_t __arm_vcx3_u32(int coproc, uint32_t n, uint32_t m, uint32_t imm);
  uint32_t __arm_vcx3a_u32(int coproc, uint32_t acc, uint32_t n, uint32_t m, 
uint32_t imm);

  uint64_t __arm_vcx1d_u64(int coproc, uint32_t imm);
  uint64_t __arm_vcx1da_u64(int coproc, uint64_t acc, uint32_t imm);
  uint64_t __arm_vcx2d_u64(int coproc, uint64_t m, uint32_t imm);
  uint64_t __arm_vcx2da_u64(int coproc, uint64_t acc, uint64_t m, uint32_t imm);
  uint64_t __arm_vcx3d_u64(int coproc, uint64_t n, uint64_t m, uint32_t imm);
  uint64_t __arm_vcx3da_u64(int coproc, uint64_t acc, uint64_t n, uint64_t m, 
uint32_t imm);

Since the semantics of CDE instructions is opaque to the compiler, the
ACLE intrinsics require dedicated LLVM IR intrinsics. The 64-bit and
32-bit variants share the same IR intrinsic.

Reviewers: simon_tatham, MarkMurrayARM, ostannard, dmgreen

Reviewed By: MarkMurrayARM

Subscribers: kristof.beyls, hiraditya, danielkiss, cfe-commits

Tags: #clang

Differential Revision: https://reviews.llvm.org/D76298

Added: 
clang/test/CodeGen/arm-cde-vfp.c
llvm/test/CodeGen/Thumb2/cde-vfp.ll

Modified: 
clang/include/clang/Basic/arm_cde.td
clang/test/Sema/arm-cde-immediates.c
clang/utils/TableGen/MveEmitter.cpp
llvm/include/llvm/IR/IntrinsicsARM.td
llvm/lib/Target/ARM/ARMInstrCDE.td

Removed: 




diff  --git a/clang/include/clang/Basic/arm_cde.td 
b/clang/include/clang/Basic/arm_cde.td
index 139007d387a0..9cd0af8987c9 100644
--- a/clang/include/clang/Basic/arm_cde.td
+++ b/clang/include/clang/Basic/arm_cde.td
@@ -13,6 +13,15 @@
 
 include "arm_mve_defs.td"
 
+// f64 is not defined in arm_mve_defs.td because MVE instructions only work 
with
+// f16 and f32
+def f64: PrimitiveType<"f", 64>;
+
+// Float expects t to be a scalar type, and expands to the floating-point
+// type of the same width.
+class Float: ComplexType<(CTO_CopyKind t, f32)>;
+def FScalar: Float;
+
 // ACLE CDE intrinsic
 class CDEIntrinsic
   : Intrinsic {
@@ -70,3 +79,31 @@ multiclass CDE_CX_m {
 defm cx1 : CDE_CX_m<(args imm_13b:$imm), (args), (?)>;
 defm cx2 : CDE_CX_m<(args imm_9b:$imm), (args u32:$n), (? $n)>;
 defm cx3 : CDE_CX_m<(args imm_6b:$imm), (args u32:$n, u32:$m), (? $n, $m)>;
+
+// VCX* instructions operating on VFP registers
+multiclass CDE_VCXFP_m {
+  defvar cp = (args imm_coproc:$cp);
+  let pnt = PNT_None, params = [u32] in {
+def "" : CDEIntrinsic $cp), cgArgs, (? $imm)),
+   Scalar)>;
+def a  : CDEIntrinsic $cp,
+ (bitcast $acc, FScalar)), cgArgs, (? $imm)), Scalar)>;
+  }
+  let pnt = PNT_None, params = [u64] in {
+def d  : CDEIntrinsic $cp), cgArgs, (? $imm)),
+   Scalar)>;
+def da : CDEIntrinsic $cp,
+ (bitcast $acc, FScalar)), cgArgs, (? $imm)), Scalar)>;
+  }
+}
+
+defm vcx1: CDE_VCXFP_m<(args imm_11b:$imm), (args), (args), (?)>;
+defm vcx2: CDE_VCXFP_m<(args imm_6b:$imm), (args u32:$n), (args u64:$n),
+   (? (bitcast $n, FScalar))>;
+defm vcx3: CDE_VCXFP_m<(args imm_3b:$imm),
+   (args u32:$n, u32:$m), (args u64:$n, u64:$m),
+   (? (bitcast $n, FScalar), (bitcast $m, FScalar))>;

diff  --git a/clang/test/CodeGen/arm-cde-vfp.c 
b/clang/test/CodeGen/arm-cde-vfp.c
new file mode 100644
index ..fffcb716359d
--- /dev/null
+++ b/clang/test/CodeGen/arm-cde-vfp.c
@@ -0,0 +1,145 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi \
+// RUN:   -target-feature +cdecp0 -target-feature +cdecp1 \
+// RUN:   -mfloat-abi hard -O0 -disable-O0-optnone \
+// RUN:   -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s
+
+#include 
+
+// CHECK-LABEL: @test_vcx1_u32(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = call float @llvm.arm.cde.vcx1.f32(i32 0, i32 
11)
+// CHECK-NEXT:[[TMP1:%.*]] = bitcast float [[TMP0]] to i32
+// CHECK-NEXT:ret i32 [[TMP1]]
+//
+uint32_t test_vcx1_u32(void) {
+  return __arm_vcx1_u32(0, 11);
+}
+
+// CHECK-LABEL: @test_vcx1a_u32(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = bitcast i32 [[ACC:%.*]] to float
+// CHECK-NEXT:[[TMP1:%.*]] = call float 

[clang] 43606ef - Suppress an "unused variable" warning in release build

[Mikhail Maltsev via cfe-commits]

Author: Mikhail Maltsev
Date: 2020-03-10T17:10:52Z
New Revision: 43606efb6847fc9c79e7d93760a2a6191e8a8539

URL: 
https://github.com/llvm/llvm-project/commit/43606efb6847fc9c79e7d93760a2a6191e8a8539
DIFF: 
https://github.com/llvm/llvm-project/commit/43606efb6847fc9c79e7d93760a2a6191e8a8539.diff

LOG: Suppress an "unused variable" warning in release build

Added: 


Modified: 
clang/lib/Sema/SemaChecking.cpp

Removed: 




diff  --git a/clang/lib/Sema/SemaChecking.cpp b/clang/lib/Sema/SemaChecking.cpp
index 24d0d9209a1d..8a2b4b019663 100644
--- a/clang/lib/Sema/SemaChecking.cpp
+++ b/clang/lib/Sema/SemaChecking.cpp
@@ -2094,6 +2094,7 @@ bool Sema::CheckARMCoprocessorImmediate(const Expr 
*CoprocArg, bool WantCDE) {
 
   llvm::APSInt CoprocNoAP;
   bool IsICE = CoprocArg->isIntegerConstantExpr(CoprocNoAP, Context);
+  (void)IsICE;
   assert(IsICE && "Coprocossor immediate is not a constant expression");
   int64_t CoprocNo = CoprocNoAP.getExtValue();
   assert(CoprocNo >= 0 && "Coprocessor immediate must be non-negative");



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[clang] 47edf5b - [ARM, CDE] Generalize MVE intrinsics infrastructure to support CDE

[Mikhail Maltsev via cfe-commits]

Author: Mikhail Maltsev
Date: 2020-03-10T14:03:16Z
New Revision: 47edf5bafb8ede52dca836eac770efffbf657d30

URL: 
https://github.com/llvm/llvm-project/commit/47edf5bafb8ede52dca836eac770efffbf657d30
DIFF: 
https://github.com/llvm/llvm-project/commit/47edf5bafb8ede52dca836eac770efffbf657d30.diff

LOG: [ARM,CDE] Generalize MVE intrinsics infrastructure to support CDE

Summary:
This patch generalizes the existing code to support CDE intrinsics
which will share some properties with existing MVE intrinsics
(some of the intrinsics will be polymorphic and accept/return values
of MVE vector types).
Specifically the patch:
* Adds new tablegen backends -gen-arm-cde-builtin-def,
  -gen-arm-cde-builtin-codegen, -gen-arm-cde-builtin-sema,
  -gen-arm-cde-builtin-aliases, -gen-arm-cde-builtin-header based on
  existing MVE backends.
* Renames the '__clang_arm_mve_alias' attribute into
  '__clang_arm_builtin_alias' (it will be used with CDE intrinsics as
  well as MVE intrinsics)
* Implements semantic checks for the coprocessor argument of the CDE
  intrinsics as well as the existing coprocessor intrinsics.
* Adds one CDE intrinsic __arm_cx1 to test the above changes

Reviewers: simon_tatham, MarkMurrayARM, ostannard, dmgreen

Reviewed By: simon_tatham

Subscribers: sdesmalen, mgorny, kristof.beyls, danielkiss, cfe-commits, 
llvm-commits

Tags: #clang, #llvm

Differential Revision: https://reviews.llvm.org/D75850

Added: 
clang/include/clang/Basic/arm_cde.td
clang/test/CodeGen/arm-cde-gpr.c
clang/test/Headers/arm-cde-header.c
clang/test/Sema/arm-cde-immediates.c

Modified: 
clang/include/clang/Basic/Attr.td
clang/include/clang/Basic/AttrDocs.td
clang/include/clang/Basic/BuiltinsARM.def
clang/include/clang/Basic/CMakeLists.txt
clang/include/clang/Basic/DiagnosticSemaKinds.td
clang/include/clang/Basic/arm_mve_defs.td
clang/include/clang/Sema/Sema.h
clang/lib/AST/Decl.cpp
clang/lib/CodeGen/CGBuiltin.cpp
clang/lib/CodeGen/CodeGenFunction.h
clang/lib/Headers/CMakeLists.txt
clang/lib/Sema/SemaChecking.cpp
clang/lib/Sema/SemaDeclAttr.cpp
clang/test/Misc/pragma-attribute-supported-attributes-list.test
clang/test/Sema/arm-mve-alias-attribute.c
clang/utils/TableGen/MveEmitter.cpp
clang/utils/TableGen/TableGen.cpp
clang/utils/TableGen/TableGenBackends.h
llvm/include/llvm/IR/IntrinsicsARM.td

Removed: 




diff  --git a/clang/include/clang/Basic/Attr.td 
b/clang/include/clang/Basic/Attr.td
index a5b053209866..b18cfef33fba 100644
--- a/clang/include/clang/Basic/Attr.td
+++ b/clang/include/clang/Basic/Attr.td
@@ -622,11 +622,11 @@ def Alias : Attr {
   let Documentation = [Undocumented];
 }
 
-def ArmMveAlias : InheritableAttr, TargetSpecificAttr {
-  let Spellings = [Clang<"__clang_arm_mve_alias">];
+def ArmBuiltinAlias : InheritableAttr, TargetSpecificAttr {
+  let Spellings = [Clang<"__clang_arm_builtin_alias">];
   let Args = [IdentifierArgument<"BuiltinName">];
   let Subjects = SubjectList<[Function], ErrorDiag>;
-  let Documentation = [ArmMveAliasDocs];
+  let Documentation = [ArmBuiltinAliasDocs];
 }
 
 def Aligned : InheritableAttr {

diff  --git a/clang/include/clang/Basic/AttrDocs.td 
b/clang/include/clang/Basic/AttrDocs.td
index cc9d3c80c0da..aea574995c8e 100644
--- a/clang/include/clang/Basic/AttrDocs.td
+++ b/clang/include/clang/Basic/AttrDocs.td
@@ -4669,11 +4669,11 @@ When the Owner's lifetime ends, it will consider the 
Pointer to be dangling.
 }];
 }
 
-def ArmMveAliasDocs : Documentation {
+def ArmBuiltinAliasDocs : Documentation {
   let Category = DocCatFunction;
   let Content = [{
-This attribute is used in the implementation of the ACLE intrinsics
-for the Arm MVE instruction set. It allows the intrinsic functions to
+This attribute is used in the implementation of the ACLE intrinsics.
+It allows the intrinsic functions to
 be declared using the names defined in ACLE, and still be recognized
 as clang builtins equivalent to the underlying name. For example,
 ``arm_mve.h`` declares the function ``vaddq_u32`` with
@@ -4684,8 +4684,8 @@ recognized as that clang builtin, and in the latter case, 
the choice
 of which builtin to identify the function as can be deferred until
 after overload resolution.
 
-This attribute can only be used to set up the aliases for the MVE
-intrinsic functions; it is intended for use only inside ``arm_mve.h``,
+This attribute can only be used to set up the aliases for certain Arm
+intrinsic functions; it is intended for use only inside ``arm_*.h``
 and is not a general mechanism for declaring arbitrary aliases for
 clang builtin functions.
   }];

diff  --git a/clang/include/clang/Basic/BuiltinsARM.def 
b/clang/include/clang/Basic/BuiltinsARM.def
index 848abb44ad36..be20c24aa28a 100644
--- a/clang/include/clang/Basic/BuiltinsARM.def
+++ b/clang/include/clang/Basic/BuiltinsARM.def
@@ -202,6 +202,8 @@ 

[clang] cdeeb54 - [ARM,CDE] Implement CDE feature test macros

[Mikhail Maltsev via cfe-commits]

Author: Mikhail Maltsev
Date: 2020-03-09T16:14:06Z
New Revision: cdeeb548bbebdff7661fb20b72839b920be0adbe

URL: 
https://github.com/llvm/llvm-project/commit/cdeeb548bbebdff7661fb20b72839b920be0adbe
DIFF: 
https://github.com/llvm/llvm-project/commit/cdeeb548bbebdff7661fb20b72839b920be0adbe.diff

LOG: [ARM,CDE] Implement CDE feature test macros

Summary:
This patch implements feature test macros for the CDE extension
according to the upcoming ACLE specification.

The following 2 macros are being added:
- __ARM_FEATURE_CDE - defined as '1' when any coprocessor is
  configured as a CDE coprocessor
- __ARM_FEATURE_CDE_COPROC - defined as an 8-bit mask, each bit of the
  mask corresponds to a coprocessor and is set when the corresponding
  coprocessor is configured as CDE (and cleared otherwise).

The patch also exposes the value of __ARM_FEATURE_CDE_COPROC in the
target-independent method TargetInfo::getARMCDECorpocMask, the method
will be used in follow-up patches implementing semantic checks of CDE
intrinsics (we want to diagnose the cases when CDE intrinsics are used
with coprocessors that are not configured as CDE).

Reviewers: simon_tatham, dmgreen, ostannard, MarkMurrayARM

Reviewed By: simon_tatham

Subscribers: kristof.beyls, danielkiss, cfe-commits

Tags: #clang

Differential Revision: https://reviews.llvm.org/D75843

Added: 


Modified: 
clang/include/clang/Basic/TargetInfo.h
clang/lib/Basic/TargetInfo.cpp
clang/lib/Basic/Targets/ARM.cpp
clang/lib/Basic/Targets/ARM.h
clang/test/Preprocessor/arm-target-features.c

Removed: 




diff  --git a/clang/include/clang/Basic/TargetInfo.h 
b/clang/include/clang/Basic/TargetInfo.h
index 80581eabe1b7..cbfcece1b666 100644
--- a/clang/include/clang/Basic/TargetInfo.h
+++ b/clang/include/clang/Basic/TargetInfo.h
@@ -210,6 +210,8 @@ class TargetInfo : public virtual TransferrableTargetInfo,
 
   unsigned HasAArch64SVETypes : 1;
 
+  unsigned ARMCDECoprocMask : 8;
+
   // TargetInfo Constructor.  Default initializes all fields.
   TargetInfo(const llvm::Triple );
 
@@ -808,6 +810,10 @@ class TargetInfo : public virtual TransferrableTargetInfo,
   /// available on this target.
   bool hasAArch64SVETypes() const { return HasAArch64SVETypes; }
 
+  /// For ARM targets returns a mask defining which coprocessors are configured
+  /// as Custom Datapath.
+  uint32_t getARMCDECoprocMask() const { return ARMCDECoprocMask; }
+
   /// Returns whether the passed in string is a valid clobber in an
   /// inline asm statement.
   ///

diff  --git a/clang/lib/Basic/TargetInfo.cpp b/clang/lib/Basic/TargetInfo.cpp
index 3a21a19e1f19..58d018c5bd3e 100644
--- a/clang/lib/Basic/TargetInfo.cpp
+++ b/clang/lib/Basic/TargetInfo.cpp
@@ -113,6 +113,7 @@ TargetInfo::TargetInfo(const llvm::Triple ) : 
TargetOpts(), Triple(T) {
   HasBuiltinMSVaList = false;
   IsRenderScriptTarget = false;
   HasAArch64SVETypes = false;
+  ARMCDECoprocMask = 0;
 
   // Default to no types using fpret.
   RealTypeUsesObjCFPRet = 0;

diff  --git a/clang/lib/Basic/Targets/ARM.cpp b/clang/lib/Basic/Targets/ARM.cpp
index 02144c6ebe85..4ab794ef3c09 100644
--- a/clang/lib/Basic/Targets/ARM.cpp
+++ b/clang/lib/Basic/Targets/ARM.cpp
@@ -154,6 +154,8 @@ bool ARMTargetInfo::hasMVEFloat() const {
   return hasMVE() && (MVE & MVE_FP);
 }
 
+bool ARMTargetInfo::hasCDE() const { return getARMCDECoprocMask() != 0; }
+
 bool ARMTargetInfo::isThumb() const {
   return ArchISA == llvm::ARM::ISAKind::THUMB;
 }
@@ -422,6 +424,7 @@ bool 
ARMTargetInfo::handleTargetFeatures(std::vector ,
   HWDiv = 0;
   DotProd = 0;
   HasFloat16 = true;
+  ARMCDECoprocMask = 0;
 
   // This does not diagnose illegal cases like having both
   // "+vfpv2" and "+vfpv3" or having "+neon" and "-fp64".
@@ -486,6 +489,10 @@ bool 
ARMTargetInfo::handleTargetFeatures(std::vector ,
   FPU |= FPARMV8;
   MVE |= MVE_INT | MVE_FP;
   HW_FP |= HW_FP_SP | HW_FP_HP;
+} else if (Feature.size() == strlen("+cdecp0") && Feature >= "+cdecp0" &&
+   Feature <= "+cdecp7") {
+  unsigned Coproc = Feature.back() - '0';
+  ARMCDECoprocMask |= (1U << Coproc);
 }
   }
 
@@ -758,6 +765,12 @@ void ARMTargetInfo::getTargetDefines(const LangOptions 
,
 Builder.defineMacro("__ARM_FEATURE_MVE", hasMVEFloat() ? "3" : "1");
   }
 
+  if (hasCDE()) {
+Builder.defineMacro("__ARM_FEATURE_CDE", "1");
+Builder.defineMacro("__ARM_FEATURE_CDE_COPROC",
+"0x" + Twine::utohexstr(getARMCDECoprocMask()));
+  }
+
   Builder.defineMacro("__ARM_SIZEOF_WCHAR_T",
   Twine(Opts.WCharSize ? Opts.WCharSize : 4));
 

diff  --git a/clang/lib/Basic/Targets/ARM.h b/clang/lib/Basic/Targets/ARM.h
index 9696a4404589..725954038602 100644
--- a/clang/lib/Basic/Targets/ARM.h
+++ b/clang/lib/Basic/Targets/ARM.h
@@ -108,6 +108,7 @@ class LLVM_LIBRARY_VISIBILITY ARMTargetInfo : public 
TargetInfo {
   bool 

[libunwind] 00c5793 - Revert "Promote nameless lambda used by dl_iterate_phdr to named function to clean up control flow inside findUnwindSections. Also, expose the data structure"

[Mikhail Maltsev via cfe-commits]

Author: Mikhail Maltsev
Date: 2020-03-04T14:54:24Z
New Revision: 00c5793edefdb465db6cff06b3b50706c31b25c1

URL: 
https://github.com/llvm/llvm-project/commit/00c5793edefdb465db6cff06b3b50706c31b25c1
DIFF: 
https://github.com/llvm/llvm-project/commit/00c5793edefdb465db6cff06b3b50706c31b25c1.diff

LOG: Revert "Promote nameless lambda used by dl_iterate_phdr to named function 
to clean up control flow inside findUnwindSections. Also, expose the data 
structure"

This reverts commit d93371238e7f5d5f9c506a88cf4f05f8dea9d008.

The commit broke the build in several configurations (including
Windows and bare-metal). For details see comments in
https://reviews.llvm.org/D75480

Added: 


Modified: 
libunwind/src/AddressSpace.hpp

Removed: 




diff  --git a/libunwind/src/AddressSpace.hpp b/libunwind/src/AddressSpace.hpp
index 63c20412ef54..7433476f9117 100644
--- a/libunwind/src/AddressSpace.hpp
+++ b/libunwind/src/AddressSpace.hpp
@@ -392,111 +392,6 @@ LocalAddressSpace::getEncodedP(pint_t , pint_t end, 
uint8_t encoding,
   return result;
 }
 
-#if defined(_LIBUNWIND_ARM_EHABI) || defined(_LIBUNWIND_SUPPORT_DWARF_UNWIND)
-struct _LIBUNWIND_HIDDEN dl_iterate_cb_data {
-  LocalAddressSpace *addressSpace;
-  UnwindInfoSections *sects;
-  uintptr_t targetAddr;
-};
-
-static int findUnwindSectionByPhdr(struct dl_phdr_info *pinfo, size_t, void 
*data) {
-  auto cbdata = static_cast(data);
-  bool found_obj = false;
-  bool found_hdr = false;
-
-  assert(cbdata);
-  assert(cbdata->sects);
-
-  if (cbdata->targetAddr < pinfo->dlpi_addr) {
-return false;
-  }
-
-#if !defined(Elf_Half)
-  typedef ElfW(Half) Elf_Half;
-#endif
-#if !defined(Elf_Phdr)
-  typedef ElfW(Phdr) Elf_Phdr;
-#endif
-#if !defined(Elf_Addr)
-  typedef ElfW(Addr) Elf_Addr;
-#endif
-
-  Elf_Addr image_base = pinfo->dlpi_addr;
-
-#if defined(__ANDROID__) && __ANDROID_API__ < 18
-  if (image_base == 0) {
-// Normally, an image base of 0 indicates a non-PIE executable. On
-// versions of Android prior to API 18, the dynamic linker reported a
-// dlpi_addr of 0 for PIE executables. Compute the true image base
-// using the PT_PHDR segment.
-// See https://github.com/android/ndk/issues/505.
-for (Elf_Half i = 0; i < pinfo->dlpi_phnum; i++) {
-  const Elf_Phdr *phdr = >dlpi_phdr[i];
-  if (phdr->p_type == PT_PHDR) {
-image_base = reinterpret_cast(pinfo->dlpi_phdr) -
-  phdr->p_vaddr;
-break;
-  }
-}
-  }
-#endif
-
-  #if defined(_LIBUNWIND_SUPPORT_DWARF_UNWIND)
-#if !defined(_LIBUNWIND_SUPPORT_DWARF_INDEX)
- #error "_LIBUNWIND_SUPPORT_DWARF_UNWIND requires 
_LIBUNWIND_SUPPORT_DWARF_INDEX on this platform."
-   #endif
-  size_t object_length;
-
-  for (Elf_Half i = 0; i < pinfo->dlpi_phnum; i++) {
-const Elf_Phdr *phdr = >dlpi_phdr[i];
-if (phdr->p_type == PT_LOAD) {
-  uintptr_t begin = image_base + phdr->p_vaddr;
-  uintptr_t end = begin + phdr->p_memsz;
-  if (cbdata->targetAddr >= begin && cbdata->targetAddr < end) {
-cbdata->sects->dso_base = begin;
-object_length = phdr->p_memsz;
-found_obj = true;
-  }
-} else if (phdr->p_type == PT_GNU_EH_FRAME) {
-  EHHeaderParser::EHHeaderInfo hdrInfo;
-  uintptr_t eh_frame_hdr_start = image_base + phdr->p_vaddr;
-  cbdata->sects->dwarf_index_section = eh_frame_hdr_start;
-  cbdata->sects->dwarf_index_section_length = phdr->p_memsz;
-  found_hdr = EHHeaderParser::decodeEHHdr(
-  *cbdata->addressSpace, eh_frame_hdr_start, phdr->p_memsz,
-  hdrInfo);
-  if (found_hdr)
-cbdata->sects->dwarf_section = hdrInfo.eh_frame_ptr;
-}
-  }
-
-  if (found_obj && found_hdr) {
-cbdata->sects->dwarf_section_length = object_length;
-return true;
-  } else {
-return false;
-  }
- #else // defined(_LIBUNWIND_ARM_EHABI)
-  for (Elf_Half i = 0; i < pinfo->dlpi_phnum; i++) {
-const Elf_Phdr *phdr = >dlpi_phdr[i];
-if (phdr->p_type == PT_LOAD) {
-  uintptr_t begin = image_base + phdr->p_vaddr;
-  uintptr_t end = begin + phdr->p_memsz;
-  if (cbdata->targetAddr >= begin && cbdata->targetAddr < end)
-found_obj = true;
-} else if (phdr->p_type == PT_ARM_EXIDX) {
-  uintptr_t exidx_start = image_base + phdr->p_vaddr;
-  cbdata->sects->arm_section = exidx_start;
-  cbdata->sects->arm_section_length = phdr->p_memsz;
-  found_hdr = true;
-}
-  }
-  return found_obj && found_hdr;
-  #endif
-}
-
-#endif  // defined(_LIBUNWIND_ARM_EHABI) || 
defined(_LIBUNWIND_SUPPORT_DWARF_UNWIND)
-
 inline bool LocalAddressSpace::findUnwindSections(pint_t targetAddr,
   UnwindInfoSections ) {
 #ifdef __APPLE__
@@ -588,8 +483,110 @@ inline bool LocalAddressSpace::findUnwindSections(pint_t 
targetAddr,
   if (info.arm_section && info.arm_section_length)
 return true;
 #elif 

[clang] 12fed51 - [ARM, MVE] Remove 64-bit variants of vbrsrq* intrinsics

[Mikhail Maltsev via cfe-commits]

Author: Mikhail Maltsev
Date: 2020-02-24T12:49:20Z
New Revision: 12fed51c0807b0727f9eecdd3dcf774a82fa7ecd

URL: 
https://github.com/llvm/llvm-project/commit/12fed51c0807b0727f9eecdd3dcf774a82fa7ecd
DIFF: 
https://github.com/llvm/llvm-project/commit/12fed51c0807b0727f9eecdd3dcf774a82fa7ecd.diff

LOG: [ARM,MVE] Remove 64-bit variants of vbrsrq* intrinsics

Summary:
According to the ACLE the vbrsrq* intrinsics don't accept vectors
with 64-bit elements (and neither does the corresponding VBRSR
instruction).

Reviewers: simon_tatham, dmgreen, MarkMurrayARM, ostannard

Reviewed By: simon_tatham

Subscribers: kristof.beyls, cfe-commits

Tags: #clang

Differential Revision: https://reviews.llvm.org/D75038

Added: 


Modified: 
clang/include/clang/Basic/arm_mve.td

Removed: 




diff  --git a/clang/include/clang/Basic/arm_mve.td 
b/clang/include/clang/Basic/arm_mve.td
index ca7246d78bd6..7150852d7004 100644
--- a/clang/include/clang/Basic/arm_mve.td
+++ b/clang/include/clang/Basic/arm_mve.td
@@ -1310,7 +1310,7 @@ foreach desttype = !listconcat(T.Int16, T.Int32, T.Float) 
in {
   }
 }
 
-let params = T.All in {
+let params = T.Usual in {
 let pnt = PNT_NType in
 def vbrsrq_n: Intrinsic $a, $b)>;



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[clang] f4fd7db - [ARM,MVE] Add vqdmull[b,t]q intrinsic families

[Mikhail Maltsev via cfe-commits]

Author: Mikhail Maltsev
Date: 2020-02-20T10:51:19Z
New Revision: f4fd7dbf85e278eff303514760bff4773a87e601

URL: 
https://github.com/llvm/llvm-project/commit/f4fd7dbf85e278eff303514760bff4773a87e601
DIFF: 
https://github.com/llvm/llvm-project/commit/f4fd7dbf85e278eff303514760bff4773a87e601.diff

LOG: [ARM,MVE] Add vqdmull[b,t]q intrinsic families

Summary:
This patch adds two families of ACLE intrinsics: vqdmullbq and
vqdmulltq (including vector-vector and vector-scalar variants) and the
corresponding LLVM IR intrinsics llvm.arm.mve.vqdmull and
llvm.arm.mve.vqdmull.predicated.

Reviewers: simon_tatham, MarkMurrayARM, dmgreen, ostannard

Reviewed By: MarkMurrayARM

Subscribers: kristof.beyls, hiraditya, cfe-commits, llvm-commits

Tags: #clang, #llvm

Differential Revision: https://reviews.llvm.org/D74845

Added: 
clang/test/CodeGen/arm-mve-intrinsics/vqdmullbq.c
clang/test/CodeGen/arm-mve-intrinsics/vqdmulltq.c
llvm/test/CodeGen/Thumb2/mve-intrinsics/vqdmull.ll

Modified: 
clang/include/clang/Basic/arm_mve.td
llvm/include/llvm/IR/IntrinsicsARM.td
llvm/lib/Target/ARM/ARMInstrMVE.td

Removed: 




diff  --git a/clang/include/clang/Basic/arm_mve.td 
b/clang/include/clang/Basic/arm_mve.td
index bfb49864922f..ca7246d78bd6 100644
--- a/clang/include/clang/Basic/arm_mve.td
+++ b/clang/include/clang/Basic/arm_mve.td
@@ -330,11 +330,22 @@ let params = T.Usual in {
   defm : VectorScalarArithmetic<"mul_predicated", "vmulq">;
 }
 
-multiclass DblVectorVectorArithmetic {
+multiclass DblVectorVectorArithmetic {
   defm "" : IntrinsicMX<
   DblVector, (args Vector:$a, Vector:$b, DblPredicate:$pred),
   !con((IRInt $a, $b),
-   extraArgs, (? $pred, $inactive))>;
+   extraArgs, (? $pred, $inactive)), wantXVariant>;
+}
+
+multiclass DblVectorScalarArithmetic {
+  defm "" : IntrinsicMXNameOverride<
+  DblVector, (args Vector:$a, unpromoted:$b, DblPredicate:$pred),
+  !con((IRInt $a, (splat 
$b)),
+   extraArgs, (? $pred, $inactive)), basename, wantXVariant, "_n",
+   PNT_NType, PNT_NType>;
 }
 
 // Predicated intrinsics - Int types only
@@ -373,6 +384,28 @@ let params = T.Poly, overrideKindLetter = "p" in {
   defm vmulltq_poly : DblVectorVectorArithmetic<"mull_poly_predicated", (? 
(u32 1))>;
 }
 
+let params = [s16, s32] in {
+  def  vqdmullbq:  Intrinsic $a, $b, 
0)>;
+  def  vqdmulltq:  Intrinsic $a, $b, 
1)>;
+  defm vqdmullbq:  DblVectorVectorArithmetic<"vqdmull_predicated", (? (u32 
0)), 0>;
+  defm vqdmulltq:  DblVectorVectorArithmetic<"vqdmull_predicated", (? (u32 
1)), 0>;
+
+  let pnt = PNT_NType in {
+def vqdmullbq_n: Intrinsic:$b),
+   (IRInt<"vqdmull", [DblVector, Vector]>
+$a, (splat $b), 0)>;
+def vqdmulltq_n: Intrinsic:$b),
+   (IRInt<"vqdmull", [DblVector, Vector]>
+$a, (splat $b), 1)>;
+  }
+  defm vqdmullbq_n: DblVectorScalarArithmetic<"vqdmull_predicated",
+  "vqdmullbq", (? (u32 0)), 0>;
+  defm vqdmulltq_n: DblVectorScalarArithmetic<"vqdmull_predicated",
+  "vqdmulltq", (? (u32 1)), 0>;
+}
+
 // Predicated intrinsics - Float types only
 let params = T.Float in {
   defm vminnmq : VectorVectorArithmetic<"min_predicated", (? (u32 0))>;

diff  --git a/clang/test/CodeGen/arm-mve-intrinsics/vqdmullbq.c 
b/clang/test/CodeGen/arm-mve-intrinsics/vqdmullbq.c
new file mode 100644
index ..c7aa5a3c17b5
--- /dev/null
+++ b/clang/test/CodeGen/arm-mve-intrinsics/vqdmullbq.c
@@ -0,0 +1,125 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature 
+mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 
-disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s
+// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature 
+mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 
-disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg | 
FileCheck %s
+
+#include 
+
+// CHECK-LABEL: @test_vqdmullbq_s16(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = call <4 x i32> 
@llvm.arm.mve.vqdmull.v4i32.v8i16(<8 x i16> [[A:%.*]], <8 x i16> [[B:%.*]], i32 
0)
+// CHECK-NEXT:ret <4 x i32> [[TMP0]]
+//
+int32x4_t test_vqdmullbq_s16(int16x8_t a, int16x8_t b) {
+#ifdef POLYMORPHIC
+  return vqdmullbq(a, b);
+#else  /* POLYMORPHIC */
+  return vqdmullbq_s16(a, b);
+#endif /* POLYMORPHIC */
+}
+
+// CHECK-LABEL: @test_vqdmullbq_s32(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = call <2 x i64> 
@llvm.arm.mve.vqdmull.v2i64.v4i32(<4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]], i32 
0)
+// CHECK-NEXT:ret <2 x i64> [[TMP0]]
+//
+int64x2_t test_vqdmullbq_s32(int32x4_t a, int32x4_t b) 

[clang] 461fd94 - [ARM,MVE] Fix predicate types of some intrinsics

[Mikhail Maltsev via cfe-commits]

Author: Mikhail Maltsev
Date: 2020-02-19T16:24:54Z
New Revision: 461fd94f004c78374fc7b0338d018f9610f2e5f5

URL: 
https://github.com/llvm/llvm-project/commit/461fd94f004c78374fc7b0338d018f9610f2e5f5
DIFF: 
https://github.com/llvm/llvm-project/commit/461fd94f004c78374fc7b0338d018f9610f2e5f5.diff

LOG: [ARM,MVE] Fix predicate types of some intrinsics

Summary:
Some predicated MVE intrinsics return a vector with element size
different from the input vector element size. In this case the
predicate must type correspond to the output vector type.

The following intrinsics use the incorrect predicate type:
* llvm.arm.mve.mull.int.predicated
* llvm.arm.mve.mull.poly.predicated
* llvm.arm.mve.vshll.imm.predicated

This patch fixes the issue.

Reviewers: simon_tatham, dmgreen, ostannard, MarkMurrayARM

Reviewed By: MarkMurrayARM

Subscribers: kristof.beyls, hiraditya, cfe-commits, llvm-commits

Tags: #clang, #llvm

Differential Revision: https://reviews.llvm.org/D74838

Added: 


Modified: 
clang/include/clang/Basic/arm_mve.td
clang/include/clang/Basic/arm_mve_defs.td
clang/test/CodeGen/arm-mve-intrinsics/vector-shift-imm.c
clang/test/CodeGen/arm-mve-intrinsics/vmullbq.c
clang/test/CodeGen/arm-mve-intrinsics/vmulltq.c
llvm/lib/Target/ARM/ARMInstrMVE.td
llvm/test/CodeGen/Thumb2/mve-intrinsics/vector-shift-imm.ll
llvm/test/CodeGen/Thumb2/mve-intrinsics/vmullbq.ll
llvm/test/CodeGen/Thumb2/mve-intrinsics/vmulltq.ll

Removed: 




diff  --git a/clang/include/clang/Basic/arm_mve.td 
b/clang/include/clang/Basic/arm_mve.td
index 45cd1fb28605..bfb49864922f 100644
--- a/clang/include/clang/Basic/arm_mve.td
+++ b/clang/include/clang/Basic/arm_mve.td
@@ -332,8 +332,8 @@ let params = T.Usual in {
 
 multiclass DblVectorVectorArithmetic {
   defm "" : IntrinsicMX<
-  DblVector, (args Vector:$a, Vector:$b, Predicate:$pred),
-  !con((IRInt $a, $b),
+  DblVector, (args Vector:$a, Vector:$b, DblPredicate:$pred),
+  !con((IRInt $a, $b),
extraArgs, (? $pred, $inactive))>;
 }
 
@@ -881,8 +881,8 @@ multiclass vshll_imm {
 (IRInt<"vshll_imm", [DblVector, Vector]>
 $v, $sh, (unsignedflag Scalar), top)>;
 defm "": IntrinsicMX
+  DblPredicate:$pred),
+(IRInt<"vshll_imm_predicated", [DblVector, Vector, DblPredicate]>
 $v, $sh, (unsignedflag Scalar), top, $pred, $inactive), 1, "_n">;
   }
 }

diff  --git a/clang/include/clang/Basic/arm_mve_defs.td 
b/clang/include/clang/Basic/arm_mve_defs.td
index 7f8f717e8163..776dc9c73da4 100644
--- a/clang/include/clang/Basic/arm_mve_defs.td
+++ b/clang/include/clang/Basic/arm_mve_defs.td
@@ -318,9 +318,11 @@ def SScalar: Signed;
 def SVector: VecOf;
 
 // DblVector expands to a vector of scalars of size twice the size of Scalar.
+// DblPredicate expands to a predicate corresponding to DblVector
 // HalfVector, similarly, expands to a vector of half-sized scalars. And
 // UHalfVector is a vector of half-sized _unsigned integers_.
 def DblVector: VecOf>;
+def DblPredicate: PredOf>;
 def HalfVector: VecOf>;
 def UHalfVector: VecOf>>;
 

diff  --git a/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-imm.c 
b/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-imm.c
index 2128d0801c6a..e86f78b659c0 100644
--- a/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-imm.c
+++ b/clang/test/CodeGen/arm-mve-intrinsics/vector-shift-imm.c
@@ -1382,8 +1382,8 @@ uint32x4_t test_vshlltq_n_u16(uint16x8_t a)
 // CHECK-LABEL: @test_vshllbq_m_n_s8(
 // CHECK-NEXT:  entry:
 // CHECK-NEXT:[[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
-// CHECK-NEXT:[[TMP1:%.*]] = call <16 x i1> 
@llvm.arm.mve.pred.i2v.v16i1(i32 [[TMP0]])
-// CHECK-NEXT:[[TMP2:%.*]] = call <8 x i16> 
@llvm.arm.mve.vshll.imm.predicated.v8i16.v16i8.v16i1(<16 x i8> [[A:%.*]], i32 
6, i32 0, i32 0, <16 x i1> [[TMP1]], <8 x i16> [[INACTIVE:%.*]])
+// CHECK-NEXT:[[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 
[[TMP0]])
+// CHECK-NEXT:[[TMP2:%.*]] = call <8 x i16> 
@llvm.arm.mve.vshll.imm.predicated.v8i16.v16i8.v8i1(<16 x i8> [[A:%.*]], i32 6, 
i32 0, i32 0, <8 x i1> [[TMP1]], <8 x i16> [[INACTIVE:%.*]])
 // CHECK-NEXT:ret <8 x i16> [[TMP2]]
 //
 int16x8_t test_vshllbq_m_n_s8(int16x8_t inactive, int8x16_t a, mve_pred16_t p)
@@ -1398,8 +1398,8 @@ int16x8_t test_vshllbq_m_n_s8(int16x8_t inactive, 
int8x16_t a, mve_pred16_t p)
 // CHECK-LABEL: @test_vshllbq_m_n_s16(
 // CHECK-NEXT:  entry:
 // CHECK-NEXT:[[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
-// CHECK-NEXT:[[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 
[[TMP0]])
-// CHECK-NEXT:[[TMP2:%.*]] = call <4 x i32> 
@llvm.arm.mve.vshll.imm.predicated.v4i32.v8i16.v8i1(<8 x i16> [[A:%.*]], i32 
10, i32 0, i32 0, <8 x i1> [[TMP1]], <4 x i32> [[INACTIVE:%.*]])
+// CHECK-NEXT:[[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 

[clang] 63809d3 - [ARM,MVE] Add vbrsrq intrinsics family

[Mikhail Maltsev via cfe-commits]

Author: Mikhail Maltsev
Date: 2020-02-18T17:31:21Z
New Revision: 63809d365e56512b1b6eac6065547f523d10dbf0

URL: 
https://github.com/llvm/llvm-project/commit/63809d365e56512b1b6eac6065547f523d10dbf0
DIFF: 
https://github.com/llvm/llvm-project/commit/63809d365e56512b1b6eac6065547f523d10dbf0.diff

LOG: [ARM,MVE] Add vbrsrq intrinsics family

Summary:
This patch adds a new MVE intrinsics family, `vbrsrq`: vector bit
reverse and shift right. The intrinsics are compiled into the VBRSR
instruction. Two new LLVM IR intrinsics were also added: arm.mve.vbrsr
and arm.mve.vbrsr.predicated.

Reviewers: simon_tatham, dmgreen, ostannard, MarkMurrayARM

Reviewed By: simon_tatham

Subscribers: kristof.beyls, hiraditya, cfe-commits, llvm-commits

Tags: #clang, #llvm

Differential Revision: https://reviews.llvm.org/D74721

Added: 
clang/test/CodeGen/arm-mve-intrinsics/vbrsrq.c
llvm/test/CodeGen/Thumb2/mve-intrinsics/vbrsrq.ll

Modified: 
clang/include/clang/Basic/arm_mve.td
llvm/include/llvm/IR/IntrinsicsARM.td
llvm/lib/Target/ARM/ARMInstrMVE.td

Removed: 




diff  --git a/clang/include/clang/Basic/arm_mve.td 
b/clang/include/clang/Basic/arm_mve.td
index 3a6b63199e39..45cd1fb28605 100644
--- a/clang/include/clang/Basic/arm_mve.td
+++ b/clang/include/clang/Basic/arm_mve.td
@@ -1276,3 +1276,13 @@ foreach desttype = !listconcat(T.Int16, T.Int32, 
T.Float) in {
   1, "_n_"#desttype, PNT_2Type, pnt_nx>;
   }
 }
+
+let params = T.All in {
+let pnt = PNT_NType in
+def vbrsrq_n: Intrinsic $a, $b)>;
+defm vbrsrq : IntrinsicMX
+ $inactive, $a, $b, $pred), 1, "_n",
+ PNT_NType, PNT_NType>;
+}

diff  --git a/clang/test/CodeGen/arm-mve-intrinsics/vbrsrq.c 
b/clang/test/CodeGen/arm-mve-intrinsics/vbrsrq.c
new file mode 100644
index ..e1fd5993cc74
--- /dev/null
+++ b/clang/test/CodeGen/arm-mve-intrinsics/vbrsrq.c
@@ -0,0 +1,92 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature 
+mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 
-disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s
+// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature 
+mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 
-disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg | 
FileCheck %s
+
+#include 
+
+// CHECK-LABEL: @test_vbrsrq_n_u32(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = call <4 x i32> @llvm.arm.mve.vbrsr.v4i32(<4 x 
i32> [[A:%.*]], i32 [[B:%.*]])
+// CHECK-NEXT:ret <4 x i32> [[TMP0]]
+//
+uint32x4_t test_vbrsrq_n_u32(uint32x4_t a, int32_t b) {
+#ifdef POLYMORPHIC
+  return vbrsrq(a, b);
+#else  /* POLYMORPHIC */
+  return vbrsrq_n_u32(a, b);
+#endif /* POLYMORPHIC */
+}
+
+// CHECK-LABEL: @test_vbrsrq_n_f16(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = call <8 x half> @llvm.arm.mve.vbrsr.v8f16(<8 
x half> [[A:%.*]], i32 [[B:%.*]])
+// CHECK-NEXT:ret <8 x half> [[TMP0]]
+//
+float16x8_t test_vbrsrq_n_f16(float16x8_t a, int32_t b) {
+#ifdef POLYMORPHIC
+  return vbrsrq(a, b);
+#else  /* POLYMORPHIC */
+  return vbrsrq_n_f16(a, b);
+#endif /* POLYMORPHIC */
+}
+
+// CHECK-LABEL: @test_vbrsrq_m_n_s8(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
+// CHECK-NEXT:[[TMP1:%.*]] = call <16 x i1> 
@llvm.arm.mve.pred.i2v.v16i1(i32 [[TMP0]])
+// CHECK-NEXT:[[TMP2:%.*]] = call <16 x i8> 
@llvm.arm.mve.vbrsr.predicated.v16i8.v16i1(<16 x i8> [[INACTIVE:%.*]], <16 x 
i8> [[A:%.*]], i32 [[B:%.*]], <16 x i1> [[TMP1]])
+// CHECK-NEXT:ret <16 x i8> [[TMP2]]
+//
+int8x16_t test_vbrsrq_m_n_s8(int8x16_t inactive, int8x16_t a, int32_t b, 
mve_pred16_t p) {
+#ifdef POLYMORPHIC
+  return vbrsrq_m(inactive, a, b, p);
+#else  /* POLYMORPHIC */
+  return vbrsrq_m_n_s8(inactive, a, b, p);
+#endif /* POLYMORPHIC */
+}
+
+// CHECK-LABEL: @test_vbrsrq_m_n_f32(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
+// CHECK-NEXT:[[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 
[[TMP0]])
+// CHECK-NEXT:[[TMP2:%.*]] = call <4 x float> 
@llvm.arm.mve.vbrsr.predicated.v4f32.v4i1(<4 x float> [[INACTIVE:%.*]], <4 x 
float> [[A:%.*]], i32 [[B:%.*]], <4 x i1> [[TMP1]])
+// CHECK-NEXT:ret <4 x float> [[TMP2]]
+//
+float32x4_t test_vbrsrq_m_n_f32(float32x4_t inactive, float32x4_t a, int32_t 
b, mve_pred16_t p) {
+#ifdef POLYMORPHIC
+  return vbrsrq_m(inactive, a, b, p);
+#else  /* POLYMORPHIC */
+  return vbrsrq_m_n_f32(inactive, a, b, p);
+#endif /* POLYMORPHIC */
+}
+
+// CHECK-LABEL: @test_vbrsrq_x_n_u16(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
+// CHECK-NEXT:[[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 
[[TMP0]])
+// CHECK-NEXT:[[TMP2:%.*]] 

[clang] 58f66f8 - [ARM,CDE] Cosmetic changes, additonal driver tests

[Mikhail Maltsev via cfe-commits]

Author: Mikhail Maltsev
Date: 2020-02-18T10:23:09Z
New Revision: 58f66f8af01db7f7f349654793a2b88376644122

URL: 
https://github.com/llvm/llvm-project/commit/58f66f8af01db7f7f349654793a2b88376644122
DIFF: 
https://github.com/llvm/llvm-project/commit/58f66f8af01db7f7f349654793a2b88376644122.diff

LOG: [ARM,CDE] Cosmetic changes, additonal driver tests

Summary:
This is a follow-up patch addressing post-commit comments in
https://reviews.llvm.org/D74044:
* Add more Clang driver tests (-march=armv8.1m.main and 
-march=armv8.1m.main+mve.fp)
* Clang-format a chunk in ARMAsmParser.cpp
* Add a missing copyright header to ARMInstrCDE.td

Reviewers: SjoerdMeijer, simon_tatham, dmgreen

Reviewed By: SjoerdMeijer

Subscribers: kristof.beyls, hiraditya, cfe-commits, llvm-commits

Tags: #clang, #llvm

Differential Revision: https://reviews.llvm.org/D74732

Added: 


Modified: 
clang/test/Driver/arm-cde.c
llvm/lib/Target/ARM/ARMInstrCDE.td
llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp

Removed: 




diff  --git a/clang/test/Driver/arm-cde.c b/clang/test/Driver/arm-cde.c
index 696bee46cc34..8dfa130da3fb 100644
--- a/clang/test/Driver/arm-cde.c
+++ b/clang/test/Driver/arm-cde.c
@@ -1,5 +1,7 @@
-// RUN: %clang -target arm-none-none-eabi -march=armv8m.main %s -### -c 2>&1 | 
FileCheck %s --check-prefix=CHECK-NOCDE
-// CHECK-NOCDE: "-triple" "thumbv8m.main-none-none-eabi"
+// RUN: %clang -target arm-none-none-eabi -march=armv8m.main %s -### -c 2>&1 | 
FileCheck %s --check-prefixes=CHECK-NOCDE,CHECK-NOCDE-V8
+// RUN: %clang -target arm-none-none-eabi -march=armv8.1m.main %s -### -c 2>&1 
| FileCheck %s --check-prefixes=CHECK-NOCDE,CHECK-NOCDE-V81
+// CHECK-NOCDE-V8: "-triple" "thumbv8m.main-none-none-eabi"
+// CHECK-NOCDE-V81: "-triple" "thumbv8.1m.main-none-none-eabi"
 // CHECK-NOCDE-NOT: "-target-feature" "+cdecp0"
 // CHECK-NOCDE-NOT: "-target-feature" "+cdecp1"
 // CHECK-NOCDE-NOT: "-target-feature" "+cdecp2"
@@ -9,13 +11,20 @@
 // CHECK-NOCDE-NOT: "-target-feature" "+cdecp6"
 // CHECK-NOCDE-NOT: "-target-feature" "+cdecp7"
 
-// RUN: %clang -target arm-none-none-eabi -march=armv8m.main+cdecp0+cdecp3 %s 
-### -c 2>&1 | FileCheck %s --check-prefix=CHECK-CDE1
-// CHECK-CDE1: "-triple" "thumbv8m.main-none-none-eabi"
+// RUN: %clang -target arm-none-none-eabi -march=armv8m.main+cdecp0+cdecp3 %s 
-### -c 2>&1 | FileCheck %s --check-prefixes=CHECK-CDE1,CHECK-CDE1-V8
+// RUN: %clang -target arm-none-none-eabi -march=armv8.1m.main+cdecp0+cdecp3 
%s -### -c 2>&1 | FileCheck %s --check-prefixes=CHECK-CDE1,CHECK-CDE1-V81
+// RUN: %clang -target arm-none-none-eabi 
-march=armv8.1m.main+mve.fp+cdecp0+cdecp3 %s -### -c 2>&1 | FileCheck %s 
--check-prefixes=CHECK-CDE1,CHECK-CDE1-V81MVE
+// CHECK-CDE1-V8: "-triple" "thumbv8m.main-none-none-eabi"
+// CHECK-CDE1-V81: "-triple" "thumbv8.1m.main-none-none-eabi"
+// CHECK-CDE1-V81MVE: "-triple" "thumbv8.1m.main-none-none-eabi"
+// CHECK-CDE1-V81MVE-DAG: "-target-feature" "+mve.fp"
 // CHECK-CDE1-DAG: "-target-feature" "+cdecp0"
 // CHECK-CDE1-DAG: "-target-feature" "+cdecp3"
 
-// RUN: %clang -target arm-none-none-eabi -march=armv8m.main+cdecp0+cdecp3 %s 
-### -c 2>&1 | FileCheck %s --check-prefix=CHECK-CDE2
-// CHECK-CDE2: "-triple" "thumbv8m.main-none-none-eabi"
+// RUN: %clang -target arm-none-none-eabi -march=armv8m.main+cdecp0+cdecp3 %s 
-### -c 2>&1 | FileCheck %s --check-prefixes=CHECK-CDE2,CHECK-CDE2-V8
+// RUN: %clang -target arm-none-none-eabi -march=armv8.1m.main+cdecp0+cdecp3 
%s -### -c 2>&1 | FileCheck %s --check-prefixes=CHECK-CDE2,CHECK-CDE2-V81
+// CHECK-CDE2-V8: "-triple" "thumbv8m.main-none-none-eabi"
+// CHECK-CDE2-V81: "-triple" "thumbv8.1m.main-none-none-eabi"
 // CHECK-CDE2-NOT: "-target-feature" "+cdecp1"
 // CHECK-CDE2-NOT: "-target-feature" "+cdecp2"
 // CHECK-CDE2-NOT: "-target-feature" "+cdecp4"

diff  --git a/llvm/lib/Target/ARM/ARMInstrCDE.td 
b/llvm/lib/Target/ARM/ARMInstrCDE.td
index 4e73ea819473..fb02e9fefd8c 100644
--- a/llvm/lib/Target/ARM/ARMInstrCDE.td
+++ b/llvm/lib/Target/ARM/ARMInstrCDE.td
@@ -1,3 +1,15 @@
+//===-- ARMInstrCDE.td - CDE support for ARM ---*- tablegen 
-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM 
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+//
+// This file describes the Arm CDE (Custom Datapath Extension) instruction set.
+//
+//===--===//
+
 // Immediate operand of arbitrary bit width
 class BitWidthImmOperand
   : ImmAsmOperand<0, !add(!shl(1, width), -1)> {

diff  --git a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp 
b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
index 65c2d4790633..3ffee6804b3c 100644
--- 

[clang] dd4d093 - [ARM] Add initial support for Custom Datapath Extension (CDE)

[Mikhail Maltsev via cfe-commits]

Author: Mikhail Maltsev
Date: 2020-02-17T15:39:16Z
New Revision: dd4d09376209cdc5615097a5be92105f55d06f5d

URL: 
https://github.com/llvm/llvm-project/commit/dd4d09376209cdc5615097a5be92105f55d06f5d
DIFF: 
https://github.com/llvm/llvm-project/commit/dd4d09376209cdc5615097a5be92105f55d06f5d.diff

LOG: [ARM] Add initial support for Custom Datapath Extension (CDE)

Summary:
This patch adds assembly-level support for a new Arm M-profile
architecture extension, Custom Datapath Extension (CDE).

A brief description of the extension is available at
https://developer.arm.com/architectures/instruction-sets/custom-instructions

The latest specification for CDE is currently a beta release and is
available at
https://static.docs.arm.com/ddi0607/aa/DDI0607A_a_armv8m_arm_supplement_cde.pdf

CDE allows chip vendors to add custom CPU instructions.  The CDE
instructions re-use the same encoding space as existing coprocessor
instructions (such as MRC, MCR, CDP etc.). Each coprocessor in range
cp0-cp7 can be configured as either general purpose (GCP) or custom
datapath (CDEv1).  This configuration is defined by the CPU vendor and
is provided to LLVM using 8 subtarget features: cdecp0 ... cdecp7.

The semantics of CDE instructions are implementation-defined, but the
instructions are guaranteed to be pure (that is, they are stateless,
they do not access memory or any registers except their explicit
inputs/outputs).

CDE requires the CPU to support at least Armv8.0-M mainline
architecture. CDE includes 3 sets of instructions:
* Instructions that operate on general purpose registers and NZCV
  flags
* Instructions that operate on the S or D register file (require
  either FP or MVE extension)
* Instructions that operate on the Q register file, require MVE

The user-facing names that can be specified on the command line are
the same as the 8 subtarget feature names. For example:

$ clang -target arm-none-none-eabi -march=armv8m.main+cdecp0+cdecp3

tells the compiler that the coprocessors 0 and 3 are configured as
CDEv1 and the remaining coprocessors are configured as GCP (which is
the default).

Reviewers: simon_tatham, ostannard, dmgreen, eli.friedman

Reviewed By: simon_tatham

Subscribers: kristof.beyls, hiraditya, cfe-commits, llvm-commits

Tags: #clang, #llvm

Differential Revision: https://reviews.llvm.org/D74044

Added: 
clang/test/Driver/arm-cde.c
llvm/lib/Target/ARM/ARMInstrCDE.td
llvm/test/MC/ARM/cde-fp-vec.s
llvm/test/MC/ARM/cde-integer.s
llvm/test/MC/ARM/cde-vec-pred.s
llvm/test/MC/Disassembler/ARM/cde-fp-vec.txt
llvm/test/MC/Disassembler/ARM/cde-integer.txt
llvm/test/MC/Disassembler/ARM/cde-vec-pred.txt

Modified: 
llvm/include/llvm/Support/ARMTargetParser.def
llvm/include/llvm/Support/ARMTargetParser.h
llvm/lib/Target/ARM/ARM.td
llvm/lib/Target/ARM/ARMInstrInfo.td
llvm/lib/Target/ARM/ARMPredicates.td
llvm/lib/Target/ARM/ARMRegisterInfo.td
llvm/lib/Target/ARM/ARMSubtarget.h
llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h

Removed: 




diff  --git a/clang/test/Driver/arm-cde.c b/clang/test/Driver/arm-cde.c
new file mode 100644
index ..696bee46cc34
--- /dev/null
+++ b/clang/test/Driver/arm-cde.c
@@ -0,0 +1,24 @@
+// RUN: %clang -target arm-none-none-eabi -march=armv8m.main %s -### -c 2>&1 | 
FileCheck %s --check-prefix=CHECK-NOCDE
+// CHECK-NOCDE: "-triple" "thumbv8m.main-none-none-eabi"
+// CHECK-NOCDE-NOT: "-target-feature" "+cdecp0"
+// CHECK-NOCDE-NOT: "-target-feature" "+cdecp1"
+// CHECK-NOCDE-NOT: "-target-feature" "+cdecp2"
+// CHECK-NOCDE-NOT: "-target-feature" "+cdecp3"
+// CHECK-NOCDE-NOT: "-target-feature" "+cdecp4"
+// CHECK-NOCDE-NOT: "-target-feature" "+cdecp5"
+// CHECK-NOCDE-NOT: "-target-feature" "+cdecp6"
+// CHECK-NOCDE-NOT: "-target-feature" "+cdecp7"
+
+// RUN: %clang -target arm-none-none-eabi -march=armv8m.main+cdecp0+cdecp3 %s 
-### -c 2>&1 | FileCheck %s --check-prefix=CHECK-CDE1
+// CHECK-CDE1: "-triple" "thumbv8m.main-none-none-eabi"
+// CHECK-CDE1-DAG: "-target-feature" "+cdecp0"
+// CHECK-CDE1-DAG: "-target-feature" "+cdecp3"
+
+// RUN: %clang -target arm-none-none-eabi -march=armv8m.main+cdecp0+cdecp3 %s 
-### -c 2>&1 | FileCheck %s --check-prefix=CHECK-CDE2
+// CHECK-CDE2: "-triple" "thumbv8m.main-none-none-eabi"
+// CHECK-CDE2-NOT: "-target-feature" "+cdecp1"
+// CHECK-CDE2-NOT: "-target-feature" "+cdecp2"
+// CHECK-CDE2-NOT: "-target-feature" "+cdecp4"
+// CHECK-CDE2-NOT: "-target-feature" "+cdecp5"
+// CHECK-CDE2-NOT: "-target-feature" "+cdecp6"
+// CHECK-CDE2-NOT: "-target-feature" "+cdecp7"

diff  --git a/llvm/include/llvm/Support/ARMTargetParser.def 
b/llvm/include/llvm/Support/ARMTargetParser.def
index 7f03d9a1320a..c3d8c894db85 100644
--- 

[clang] 2694cc3 - [ARM][MVE] Add fixed point vector conversion intrinsics

[Mikhail Maltsev via cfe-commits]

Author: Mikhail Maltsev
Date: 2020-02-06T16:49:45Z
New Revision: 2694cc3dca94dbaec15eea40bf69872e0b0d8a5c

URL: 
https://github.com/llvm/llvm-project/commit/2694cc3dca94dbaec15eea40bf69872e0b0d8a5c
DIFF: 
https://github.com/llvm/llvm-project/commit/2694cc3dca94dbaec15eea40bf69872e0b0d8a5c.diff

LOG: [ARM][MVE] Add fixed point vector conversion intrinsics

Summary:
This patch implements the following Arm ACLE MVE intrinsics:
* vcvtq_n_*
* vcvtq_m_n_*
* vcvtq_x_n_*

and two corresponding LLVM IR intrinsics:
* int_arm_mve_vcvt_fix (vcvtq_n_*)
* int_arm_mve_vcvt_fix_predicated (vcvtq_m_n_*, vcvtq_x_n_*)

Reviewers: simon_tatham, ostannard, MarkMurrayARM, dmgreen

Reviewed By: MarkMurrayARM

Subscribers: kristof.beyls, hiraditya, cfe-commits, llvm-commits

Tags: #clang, #llvm

Differential Revision: https://reviews.llvm.org/D74134

Added: 


Modified: 
clang/include/clang/Basic/arm_mve.td
clang/test/CodeGen/arm-mve-intrinsics/vcvt.c
clang/test/Sema/arm-mve-immediates.c
llvm/include/llvm/IR/IntrinsicsARM.td
llvm/lib/Target/ARM/ARMInstrMVE.td
llvm/test/CodeGen/Thumb2/mve-intrinsics/vcvt.ll

Removed: 




diff  --git a/clang/include/clang/Basic/arm_mve.td 
b/clang/include/clang/Basic/arm_mve.td
index 9c82050be1ce..4edef930f3b4 100644
--- a/clang/include/clang/Basic/arm_mve.td
+++ b/clang/include/clang/Basic/arm_mve.td
@@ -1098,3 +1098,29 @@ let params = T.All in {
   def vsetq_lane: Intrinsic:$e, Vector:$v, 
imm_lane:$lane),
 (ielt_var $v, $e, $lane)>;
 }
+
+foreach desttype = !listconcat(T.Int16, T.Int32, T.Float) in {
+  defvar is_dest_float = !eq(desttype.kind, "f");
+  defvar is_dest_unsigned = !eq(desttype.kind, "u");
+  // First immediate operand of the LLVM intrinsic
+  defvar unsigned_flag = !if(is_dest_float, (unsignedflag Scalar),
+ !if(is_dest_unsigned, V.True, V.False));
+  // For float->int conversions _n and _x_n intrinsics are not polymorphic
+  // because the signedness of the destination type cannot be inferred.
+  defvar pnt_nx = !if(is_dest_float, PNT_2Type, PNT_None);
+
+  let params = !if(is_dest_float,
+   !if(!eq(desttype.size, 16), T.Int16, T.Int32),
+   !if(!eq(desttype.size, 16), [f16], [f32])) in {
+let pnt = pnt_nx in
+  def "vcvtq_n_"#desttype : Intrinsic,
+(args Vector:$a, imm_1toN:$b),
+(IRInt<"vcvt_fix", [VecOf, Vector]> unsigned_flag, $a, $b)>;
+
+defm "vcvtq" : IntrinsicMX,
+  (args Vector:$a, imm_1toN:$b, Predicate:$p),
+  (IRInt<"vcvt_fix_predicated", [VecOf, Vector, Predicate]>
+ unsigned_flag, $inactive, $a, $b, $p),
+  1, "_n_"#desttype, PNT_2Type, pnt_nx>;
+  }
+}

diff  --git a/clang/test/CodeGen/arm-mve-intrinsics/vcvt.c 
b/clang/test/CodeGen/arm-mve-intrinsics/vcvt.c
index ccee9fd76c7c..a1c99de62ebb 100644
--- a/clang/test/CodeGen/arm-mve-intrinsics/vcvt.c
+++ b/clang/test/CodeGen/arm-mve-intrinsics/vcvt.c
@@ -1,5 +1,6 @@
 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
 // RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature 
+mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 
-disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s
+// RUN: %clang_cc1 -DPOLYMORPHIC -triple thumbv8.1m.main-arm-none-eabi 
-target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 
-disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s
 
 #include 
 
@@ -24,3 +25,339 @@ float16x8_t test_vcvttq_m_f16_f32(float16x8_t a, 
float32x4_t b, mve_pred16_t p)
 {
 return vcvttq_m_f16_f32(a, b, p);
 }
+
+// CHECK-LABEL: @test_vcvtq_n_f16_s16(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = call <8 x half> 
@llvm.arm.mve.vcvt.fix.v8f16.v8i16(i32 0, <8 x i16> [[A:%.*]], i32 1)
+// CHECK-NEXT:ret <8 x half> [[TMP0]]
+//
+float16x8_t test_vcvtq_n_f16_s16(int16x8_t a)
+{
+#ifdef POLYMORPHIC
+return vcvtq_n(a, 1);
+#else
+return vcvtq_n_f16_s16(a, 1);
+#endif
+}
+
+// CHECK-LABEL: @test_vcvtq_n_f16_u16(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = call <8 x half> 
@llvm.arm.mve.vcvt.fix.v8f16.v8i16(i32 1, <8 x i16> [[A:%.*]], i32 2)
+// CHECK-NEXT:ret <8 x half> [[TMP0]]
+//
+float16x8_t test_vcvtq_n_f16_u16(uint16x8_t a)
+{
+#ifdef POLYMORPHIC
+return vcvtq_n(a, 2);
+#else
+return vcvtq_n_f16_u16(a, 2);
+#endif
+}
+
+// CHECK-LABEL: @test_vcvtq_n_f32_s32(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = call <4 x float> 
@llvm.arm.mve.vcvt.fix.v4f32.v4i32(i32 0, <4 x i32> [[A:%.*]], i32 3)
+// CHECK-NEXT:ret <4 x float> [[TMP0]]
+//
+float32x4_t test_vcvtq_n_f32_s32(int32x4_t a)
+{
+#ifdef POLYMORPHIC
+return vcvtq_n(a, 3);
+#else
+return vcvtq_n_f32_s32(a, 3);
+#endif
+}
+
+// CHECK-LABEL: @test_vcvtq_n_f32_u32(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = 

[clang] 7128aac - [ARM] Make ARM::ArchExtKind use 64-bit underlying type, NFCI

[Mikhail Maltsev via cfe-commits]

Author: Mikhail Maltsev
Date: 2020-02-04T11:24:18Z
New Revision: 7128aace600f29c81f735c3b1d3f5f51464c4630

URL: 
https://github.com/llvm/llvm-project/commit/7128aace600f29c81f735c3b1d3f5f51464c4630
DIFF: 
https://github.com/llvm/llvm-project/commit/7128aace600f29c81f735c3b1d3f5f51464c4630.diff

LOG: [ARM] Make ARM::ArchExtKind use 64-bit underlying type, NFCI

Summary:
This patch changes the underlying type of the ARM::ArchExtKind
enumeration to uint64_t and adjusts the related code.

The goal of the patch is to prepare the code base for a new
architecture extension.

Reviewers: simon_tatham, eli.friedman, ostannard, dmgreen

Reviewed By: dmgreen

Subscribers: merge_guards_bot, kristof.beyls, hiraditya, cfe-commits, 
llvm-commits, pbarrio

Tags: #clang, #llvm

Differential Revision: https://reviews.llvm.org/D73906

Added: 


Modified: 
clang/lib/Basic/Targets/ARM.cpp
clang/lib/Driver/ToolChains/Arch/ARM.cpp
llvm/include/llvm/Support/ARMTargetParser.h
llvm/lib/Support/ARMTargetParser.cpp
llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
llvm/unittests/Support/TargetParserTest.cpp

Removed: 




diff  --git a/clang/lib/Basic/Targets/ARM.cpp b/clang/lib/Basic/Targets/ARM.cpp
index c51a18216b83..c6f661fdec99 100644
--- a/clang/lib/Basic/Targets/ARM.cpp
+++ b/clang/lib/Basic/Targets/ARM.cpp
@@ -372,7 +372,7 @@ bool ARMTargetInfo::initFeatureMap(
   llvm::ARM::getFPUFeatures(FPUKind, TargetFeatures);
 
   // get default Extension features
-  unsigned Extensions = llvm::ARM::getDefaultExtensions(CPU, Arch);
+  uint64_t Extensions = llvm::ARM::getDefaultExtensions(CPU, Arch);
   llvm::ARM::getExtensionFeatures(Extensions, TargetFeatures);
 
   for (auto Feature : TargetFeatures)

diff  --git a/clang/lib/Driver/ToolChains/Arch/ARM.cpp 
b/clang/lib/Driver/ToolChains/Arch/ARM.cpp
index e7133607aedb..ce3990038a4b 100644
--- a/clang/lib/Driver/ToolChains/Arch/ARM.cpp
+++ b/clang/lib/Driver/ToolChains/Arch/ARM.cpp
@@ -57,7 +57,7 @@ void arm::getARMArchCPUFromArgs(const ArgList , 
llvm::StringRef ,
 static void getARMHWDivFeatures(const Driver , const Arg *A,
 const ArgList , StringRef HWDiv,
 std::vector ) {
-  unsigned HWDivID = llvm::ARM::parseHWDiv(HWDiv);
+  uint64_t HWDivID = llvm::ARM::parseHWDiv(HWDiv);
   if (!llvm::ARM::getHWDivFeatures(HWDivID, Features))
 D.Diag(clang::diag::err_drv_clang_unsupported) << A->getAsString(Args);
 }
@@ -91,7 +91,7 @@ static void DecodeARMFeaturesFromCPU(const Driver , 
StringRef CPU,
   CPU = CPU.split("+").first;
   if (CPU != "generic") {
 llvm::ARM::ArchKind ArchKind = llvm::ARM::parseCPUArch(CPU);
-unsigned Extension = llvm::ARM::getDefaultExtensions(CPU, ArchKind);
+uint64_t Extension = llvm::ARM::getDefaultExtensions(CPU, ArchKind);
 llvm::ARM::getExtensionFeatures(Extension, Features);
   }
 }

diff  --git a/llvm/include/llvm/Support/ARMTargetParser.h 
b/llvm/include/llvm/Support/ARMTargetParser.h
index 02d4c975129f..ac2cd259826d 100644
--- a/llvm/include/llvm/Support/ARMTargetParser.h
+++ b/llvm/include/llvm/Support/ARMTargetParser.h
@@ -24,7 +24,7 @@ namespace ARM {
 
 // Arch extension modifiers for CPUs.
 // Note that this is not the same as the AArch64 list
-enum ArchExtKind : unsigned {
+enum ArchExtKind : uint64_t {
   AEK_INVALID = 0,
   AEK_NONE =1,
   AEK_CRC = 1 << 1,
@@ -47,11 +47,11 @@ enum ArchExtKind : unsigned {
   AEK_FP_DP   = 1 << 18,
   AEK_LOB = 1 << 19,
   // Unsupported extensions.
-  AEK_OS = 0x800,
-  AEK_IWMMXT = 0x1000,
-  AEK_IWMMXT2 = 0x2000,
-  AEK_MAVERICK = 0x4000,
-  AEK_XSCALE = 0x8000,
+  AEK_OS   =1ULL << 59,
+  AEK_IWMMXT   =1ULL << 60,
+  AEK_IWMMXT2  =1ULL << 61,
+  AEK_MAVERICK =1ULL << 62,
+  AEK_XSCALE   =1ULL << 63,
 };
 
 // List of Arch Extension names.
@@ -59,7 +59,7 @@ enum ArchExtKind : unsigned {
 struct ExtName {
   const char *NameCStr;
   size_t NameLength;
-  unsigned ID;
+  uint64_t ID;
   const char *Feature;
   const char *NegFeature;
 
@@ -102,7 +102,7 @@ template  struct CpuNames {
   size_t NameLength;
   T ArchID;
   bool Default; // is $Name the default CPU for $ArchID ?
-  unsigned DefaultExtensions;
+  uint64_t DefaultExtensions;
 
   StringRef getName() const { return StringRef(NameCStr, NameLength); }
 };
@@ -193,7 +193,7 @@ template  struct ArchNames {
   const char *SubArchCStr;
   size_t SubArchLength;
   unsigned DefaultFPU;
-  unsigned ArchBaseExtensions;
+  uint64_t ArchBaseExtensions;
   T ID;
   ARMBuildAttrs::CPUArch ArchAttr; // Arch ID in build attributes.
 
@@ -225,33 +225,33 @@ FPURestriction getFPURestriction(unsigned FPUKind);
 
 // FIXME: These should be moved to TargetTuple once it exists
 bool getFPUFeatures(unsigned FPUKind, std::vector );
-bool getHWDivFeatures(unsigned HWDivKind, std::vector );
-bool 

[clang] e6d3261 - [ARM][MVE] Refactor complex vector intrinsics [NFCI]

[Mikhail Maltsev via cfe-commits]

Author: Mikhail Maltsev
Date: 2019-12-10T16:21:52Z
New Revision: e6d3261c67ecade5d959ee3094eb2bd1cd7ec447

URL: 
https://github.com/llvm/llvm-project/commit/e6d3261c67ecade5d959ee3094eb2bd1cd7ec447
DIFF: 
https://github.com/llvm/llvm-project/commit/e6d3261c67ecade5d959ee3094eb2bd1cd7ec447.diff

LOG: [ARM][MVE] Refactor complex vector intrinsics [NFCI]

Summary:
This patch refactors instruction selection of the complex vector
addition, multiplication and multiply-add intrinsics, so that it is
now based on TableGen patterns rather than C++ code.

It also changes the first parameter (halving vs non-halving) of the
arm_mve_vcaddq IR intrinsic to match the corresponding instruction
encoding, hence it requires some changes in the tests.

The patch addresses David's comment in https://reviews.llvm.org/D71190

Reviewers: dmgreen, ostannard, simon_tatham, MarkMurrayARM

Reviewed By: dmgreen

Subscribers: merge_guards_bot, kristof.beyls, hiraditya, cfe-commits, 
llvm-commits

Tags: #clang, #llvm

Differential Revision: https://reviews.llvm.org/D71245

Added: 


Modified: 
clang/include/clang/Basic/arm_mve.td
clang/test/CodeGen/arm-mve-intrinsics/vcaddq.c
clang/test/CodeGen/arm-mve-intrinsics/vhcaddq.c
llvm/include/llvm/IR/IntrinsicsARM.td
llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
llvm/lib/Target/ARM/ARMInstrMVE.td
llvm/test/CodeGen/Thumb2/mve-intrinsics/vcaddq.ll

Removed: 




diff  --git a/clang/include/clang/Basic/arm_mve.td 
b/clang/include/clang/Basic/arm_mve.td
index f3d3f4124101..618a087d6275 100644
--- a/clang/include/clang/Basic/arm_mve.td
+++ b/clang/include/clang/Basic/arm_mve.td
@@ -683,16 +683,16 @@ def vadciq_m: Intrinsic;
 }
 
-multiclass VectorComplexAddPred {
+multiclass VectorComplexAddPred {
   def "" : Intrinsic halving, angle, $a, $b)>;
+ (IRInt<"vcaddq", [Vector]> not_halving, angle, $a, $b)>;
   def _m : Intrinsic
-   halving, angle, $inactive, $a, $b, $pred)>;
+   not_halving, angle, $inactive, $a, $b, $pred)>;
   def _x : Intrinsic
-   halving, angle, (undef Vector), $a, $b, $pred)>;
+   not_halving, angle, (undef Vector), $a, $b, $pred)>;
 }
 
 multiclass VectorComplexMulPred {
@@ -715,9 +715,9 @@ multiclass VectorComplexMLAPred {
 (IRInt<"vcmlaq_predicated", [Vector, Predicate]> angle, $a, $b, $c, 
$pred)>;
 }
 
-multiclass VectorComplexAddAngle {
-  defm _rot90 : VectorComplexAddPred;
-  defm _rot270 : VectorComplexAddPred;
+multiclass VectorComplexAddAngle {
+  defm _rot90 : VectorComplexAddPred;
+  defm _rot270 : VectorComplexAddPred;
 }
 
 multiclass VectorComplexMulAngle {
@@ -735,10 +735,10 @@ multiclass VectorComplexMLAAngle {
 }
 
 let params = T.Usual in
-defm vcaddq : VectorComplexAddAngle<(u32 0)>;
+defm vcaddq : VectorComplexAddAngle<(u32 1)>;
 
 let params = T.Signed in
-defm vhcaddq : VectorComplexAddAngle<(u32 1)>;
+defm vhcaddq : VectorComplexAddAngle<(u32 0)>;
 
 let params = T.Float in {
 defm vcmulq : VectorComplexMulAngle;

diff  --git a/clang/test/CodeGen/arm-mve-intrinsics/vcaddq.c 
b/clang/test/CodeGen/arm-mve-intrinsics/vcaddq.c
index 3e00384eeb61..f23751a3526a 100644
--- a/clang/test/CodeGen/arm-mve-intrinsics/vcaddq.c
+++ b/clang/test/CodeGen/arm-mve-intrinsics/vcaddq.c
@@ -6,7 +6,7 @@
 
 // CHECK-LABEL: @test_vcaddq_rot90_u8(
 // CHECK-NEXT:  entry:
-// CHECK-NEXT:[[TMP0:%.*]] = call <16 x i8> @llvm.arm.mve.vcaddq.v16i8(i32 
0, i32 0, <16 x i8> [[A:%.*]], <16 x i8> [[B:%.*]])
+// CHECK-NEXT:[[TMP0:%.*]] = call <16 x i8> @llvm.arm.mve.vcaddq.v16i8(i32 
1, i32 0, <16 x i8> [[A:%.*]], <16 x i8> [[B:%.*]])
 // CHECK-NEXT:ret <16 x i8> [[TMP0]]
 //
 uint8x16_t test_vcaddq_rot90_u8(uint8x16_t a, uint8x16_t b)
@@ -20,7 +20,7 @@ uint8x16_t test_vcaddq_rot90_u8(uint8x16_t a, uint8x16_t b)
 
 // CHECK-LABEL: @test_vcaddq_rot90_u16(
 // CHECK-NEXT:  entry:
-// CHECK-NEXT:[[TMP0:%.*]] = call <8 x i16> @llvm.arm.mve.vcaddq.v8i16(i32 
0, i32 0, <8 x i16> [[A:%.*]], <8 x i16> [[B:%.*]])
+// CHECK-NEXT:[[TMP0:%.*]] = call <8 x i16> @llvm.arm.mve.vcaddq.v8i16(i32 
1, i32 0, <8 x i16> [[A:%.*]], <8 x i16> [[B:%.*]])
 // CHECK-NEXT:ret <8 x i16> [[TMP0]]
 //
 uint16x8_t test_vcaddq_rot90_u16(uint16x8_t a, uint16x8_t b)
@@ -34,7 +34,7 @@ uint16x8_t test_vcaddq_rot90_u16(uint16x8_t a, uint16x8_t b)
 
 // CHECK-LABEL: @test_vcaddq_rot90_u32(
 // CHECK-NEXT:  entry:
-// CHECK-NEXT:[[TMP0:%.*]] = call <4 x i32> @llvm.arm.mve.vcaddq.v4i32(i32 
0, i32 0, <4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]])
+// CHECK-NEXT:[[TMP0:%.*]] = call <4 x i32> @llvm.arm.mve.vcaddq.v4i32(i32 
1, i32 0, <4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]])
 // CHECK-NEXT:ret <4 x i32> [[TMP0]]
 //
 uint32x4_t test_vcaddq_rot90_u32(uint32x4_t a, uint32x4_t b)
@@ -48,7 +48,7 @@ uint32x4_t test_vcaddq_rot90_u32(uint32x4_t a, uint32x4_t b)
 
 // CHECK-LABEL: @test_vcaddq_rot90_s8(
 // CHECK-NEXT:  entry:
-// CHECK-NEXT:[[TMP0:%.*]] = call <16 x i8> 

[libunwind] 4fb8ecd - [libunwind] Adjust the signal_frame test for Arm

[Mikhail Maltsev via cfe-commits]

Author: Mikhail Maltsev
Date: 2019-11-19T09:58:46Z
New Revision: 4fb8ecdef4c9b19563e428a151c376a4103d65fc

URL: 
https://github.com/llvm/llvm-project/commit/4fb8ecdef4c9b19563e428a151c376a4103d65fc
DIFF: 
https://github.com/llvm/llvm-project/commit/4fb8ecdef4c9b19563e428a151c376a4103d65fc.diff

LOG: [libunwind] Adjust the signal_frame test for Arm

Summary:
This patch adjusts the signal_frame.pass.cpp to pass on Arm targets:
* When Arm EHABI is used the unwinder does not use DWARF, hence the
  DWARF-specific check unw_is_signal_frame() must be disabled.
* Certain C libraries don't include EH tables, so the unwinder must
  not try to step out of main(). The patch moves the test code out of
  main() into a separate function to avoid this.

Reviewers: saugustine, ostannard, phosek, jfb, mclow.lists

Reviewed By: saugustine

Subscribers: dexonsmith, aprantl, kristof.beyls, christof, libcxx-commits, 
pbarrio, labrinea

Tags: #libc

Differential Revision: https://reviews.llvm.org/D70397

Added: 


Modified: 
libunwind/test/signal_frame.pass.cpp

Removed: 




diff  --git a/libunwind/test/signal_frame.pass.cpp 
b/libunwind/test/signal_frame.pass.cpp
index b14e95a51528..a6f3f483bea5 100644
--- a/libunwind/test/signal_frame.pass.cpp
+++ b/libunwind/test/signal_frame.pass.cpp
@@ -13,13 +13,19 @@
 #include 
 #include 
 
-int main(void) {
+void test() {
   asm(".cfi_signal_frame");
   unw_cursor_t cursor;
   unw_context_t uc;
   unw_getcontext();
   unw_init_local(, );
   assert(unw_step() > 0);
+#if !defined(_LIBUNWIND_ARM_EHABI)
   assert(unw_is_signal_frame());
+#endif
+}
+
+int main() {
+  test();
   return 0;
 }



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[libunwind] r366701 - [libunwind][ARM] Fix types in _Unwind_VRS_Get.

[Mikhail Maltsev via cfe-commits]

Author: miyuki
Date: Mon Jul 22 09:43:03 2019
New Revision: 366701

URL: http://llvm.org/viewvc/llvm-project?rev=366701=rev
Log:
[libunwind][ARM] Fix types in _Unwind_VRS_Get.

This is a small fix for https://reviews.llvm.org/D64996. The types of
w0 and w1 in _Unwind_VRS_Get must be uint64_t, not uint32_t.

Committing as obvious.

Modified:
libunwind/trunk/src/Unwind-EHABI.cpp

Modified: libunwind/trunk/src/Unwind-EHABI.cpp
URL: 
http://llvm.org/viewvc/llvm-project/libunwind/trunk/src/Unwind-EHABI.cpp?rev=366701=366700=366701=diff
==
--- libunwind/trunk/src/Unwind-EHABI.cpp (original)
+++ libunwind/trunk/src/Unwind-EHABI.cpp Mon Jul 22 09:43:03 2019
@@ -941,8 +941,8 @@ _Unwind_VRS_Pop(_Unwind_Context *context
   // format 1", which is equivalent to FSTMD + a padding word.
   for (uint32_t i = first; i < end; ++i) {
 // SP is only 32-bit aligned so don't copy 64-bit at a time.
-uint32_t w0 = *sp++;
-uint32_t w1 = *sp++;
+uint64_t w0 = *sp++;
+uint64_t w1 = *sp++;
 #ifdef __LITTLE_ENDIAN__
 uint64_t value = (w1 << 32) | w0;
 #else


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[libunwind] r366587 - [libunwind][ARM] Fix loading FP registers on big-endian targets

[Mikhail Maltsev via cfe-commits]

Author: miyuki
Date: Fri Jul 19 08:20:32 2019
New Revision: 366587

URL: http://llvm.org/viewvc/llvm-project?rev=366587=rev
Log:
[libunwind][ARM] Fix loading FP registers on big-endian targets

Summary:
The function Unwind-EHABI.cpp:_Unwind_VRS_Pop loads the saved values of
64-bit FP registers as two 32-bit words because they might not be
8-byte aligned. Combining these words into a 64-bit value has to be
done differently on big-endian platforms.

Reviewers: ostannard, john.brawn, dmgreen

Reviewed By: ostannard

Subscribers: kristof.beyls, christof, libcxx-commits

Tags: #libc

Differential Revision: https://reviews.llvm.org/D64996

Modified:
libunwind/trunk/src/Unwind-EHABI.cpp

Modified: libunwind/trunk/src/Unwind-EHABI.cpp
URL: 
http://llvm.org/viewvc/llvm-project/libunwind/trunk/src/Unwind-EHABI.cpp?rev=366587=366586=366587=diff
==
--- libunwind/trunk/src/Unwind-EHABI.cpp (original)
+++ libunwind/trunk/src/Unwind-EHABI.cpp Fri Jul 19 08:20:32 2019
@@ -941,8 +941,13 @@ _Unwind_VRS_Pop(_Unwind_Context *context
   // format 1", which is equivalent to FSTMD + a padding word.
   for (uint32_t i = first; i < end; ++i) {
 // SP is only 32-bit aligned so don't copy 64-bit at a time.
-uint64_t value = *sp++;
-value |= ((uint64_t)(*sp++)) << 32;
+uint32_t w0 = *sp++;
+uint32_t w1 = *sp++;
+#ifdef __LITTLE_ENDIAN__
+uint64_t value = (w1 << 32) | w0;
+#else
+uint64_t value = (w0 << 32) | w1;
+#endif
 if (_Unwind_VRS_Set(context, regclass, i, representation, ) !=
 _UVRSR_OK)
   return _UVRSR_FAILED;


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[libunwind] r365505 - [libunwind] Fix Unwind-EHABI.cpp:getByte on big-endian targets

[Mikhail Maltsev via cfe-commits]

Author: miyuki
Date: Tue Jul  9 08:29:06 2019
New Revision: 365505

URL: http://llvm.org/viewvc/llvm-project?rev=365505=rev
Log:
[libunwind] Fix Unwind-EHABI.cpp:getByte on big-endian targets

Summary:
The function getByte is dependent on endianness and the current
behavior is incorrect on big-endian targets.

This patch fixes the issue.

Reviewers: phosek, ostannard, dmgreen, christof, chill

Reviewed By: ostannard, chill

Subscribers: chill, christof, libcxx-commits

Tags: #libc

Differential Revision: https://reviews.llvm.org/D64402

Modified:
libunwind/trunk/src/Unwind-EHABI.cpp

Modified: libunwind/trunk/src/Unwind-EHABI.cpp
URL: 
http://llvm.org/viewvc/llvm-project/libunwind/trunk/src/Unwind-EHABI.cpp?rev=365505=365504=365505=diff
==
--- libunwind/trunk/src/Unwind-EHABI.cpp (original)
+++ libunwind/trunk/src/Unwind-EHABI.cpp Tue Jul  9 08:29:06 2019
@@ -31,7 +31,11 @@ namespace {
 // signinficant byte.
 uint8_t getByte(const uint32_t* data, size_t offset) {
   const uint8_t* byteData = reinterpret_cast(data);
+#ifdef __LITTLE_ENDIAN__
   return byteData[(offset & ~(size_t)0x03) + (3 - (offset & (size_t)0x03))];
+#else
+  return byteData[offset];
+#endif
 }
 
 const char* getNextWord(const char* data, uint32_t* out) {


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r363687 - [CodeGen][ARM] Fix FP16 vector coercion

[Mikhail Maltsev via cfe-commits]

Author: miyuki
Date: Tue Jun 18 07:34:27 2019
New Revision: 363687

URL: http://llvm.org/viewvc/llvm-project?rev=363687=rev
Log:
[CodeGen][ARM] Fix FP16 vector coercion

Summary:
When a function argument or return type is a homogeneous aggregate
which contains an FP16 vector but the target does not support FP16
operations natively, the type must be converted into an array of
integer vectors by then front end (otherwise LLVM will handle FP16
vectors incorrectly by scalarizing them and promoting FP16 to float,
see https://reviews.llvm.org/D50507).

Currently the logic for checking whether or not a given homogeneous
aggregate contains FP16 vectors is incorrect: it only looks at the
type of the first vector.

This patch fixes the issue by adding a new method
ARMABIInfo::containsAnyFP16Vectors and using it. The traversal logic
of this method is largely the same as in
ABIInfo::isHomogeneousAggregate.

Reviewers: eli.friedman, olista01, ostannard

Reviewed By: ostannard

Subscribers: ostannard, john.brawn, javed.absar, kristof.beyls, pbarrio, 
cfe-commits

Tags: #clang

Differential Revision: https://reviews.llvm.org/D63437

Added:
cfe/trunk/test/CodeGen/arm-vfp16-arguments2.cpp
Modified:
cfe/trunk/lib/CodeGen/TargetInfo.cpp

Modified: cfe/trunk/lib/CodeGen/TargetInfo.cpp
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/CodeGen/TargetInfo.cpp?rev=363687=363686=363687=diff
==
--- cfe/trunk/lib/CodeGen/TargetInfo.cpp (original)
+++ cfe/trunk/lib/CodeGen/TargetInfo.cpp Tue Jun 18 07:34:27 2019
@@ -5607,6 +5607,7 @@ private:
   uint64_t Members) const;
   ABIArgInfo coerceIllegalVector(QualType Ty) const;
   bool isIllegalVectorType(QualType Ty) const;
+  bool containsAnyFP16Vectors(QualType Ty) const;
 
   bool isHomogeneousAggregateBaseType(QualType Ty) const override;
   bool isHomogeneousAggregateSmallEnough(const Type *Ty,
@@ -5806,9 +5807,7 @@ ABIArgInfo ARMABIInfo::classifyHomogeneo
   // Base can be a floating-point or a vector.
   if (const VectorType *VT = Base->getAs()) {
 // FP16 vectors should be converted to integer vectors
-if (!getTarget().hasLegalHalfType() &&
-(VT->getElementType()->isFloat16Type() ||
-  VT->getElementType()->isHalfType())) {
+if (!getTarget().hasLegalHalfType() && containsAnyFP16Vectors(Ty)) {
   uint64_t Size = getContext().getTypeSize(VT);
   llvm::Type *NewVecTy = llvm::VectorType::get(
   llvm::Type::getInt32Ty(getVMContext()), Size / 32);
@@ -6169,6 +6168,37 @@ bool ARMABIInfo::isIllegalVectorType(Qua
   return false;
 }
 
+/// Return true if a type contains any 16-bit floating point vectors
+bool ARMABIInfo::containsAnyFP16Vectors(QualType Ty) const {
+  if (const ConstantArrayType *AT = getContext().getAsConstantArrayType(Ty)) {
+uint64_t NElements = AT->getSize().getZExtValue();
+if (NElements == 0)
+  return false;
+return containsAnyFP16Vectors(AT->getElementType());
+  } else if (const RecordType *RT = Ty->getAs()) {
+const RecordDecl *RD = RT->getDecl();
+
+// If this is a C++ record, check the bases first.
+if (const CXXRecordDecl *CXXRD = dyn_cast(RD))
+  if (llvm::any_of(CXXRD->bases(), [this](const CXXBaseSpecifier ) {
+return containsAnyFP16Vectors(B.getType());
+  }))
+return true;
+
+if (llvm::any_of(RD->fields(), [this](FieldDecl *FD) {
+  return FD && containsAnyFP16Vectors(FD->getType());
+}))
+  return true;
+
+return false;
+  } else {
+if (const VectorType *VT = Ty->getAs())
+  return (VT->getElementType()->isFloat16Type() ||
+  VT->getElementType()->isHalfType());
+return false;
+  }
+}
+
 bool ARMABIInfo::isLegalVectorTypeForSwift(CharUnits vectorSize,
llvm::Type *eltTy,
unsigned numElts) const {

Added: cfe/trunk/test/CodeGen/arm-vfp16-arguments2.cpp
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGen/arm-vfp16-arguments2.cpp?rev=363687=auto
==
--- cfe/trunk/test/CodeGen/arm-vfp16-arguments2.cpp (added)
+++ cfe/trunk/test/CodeGen/arm-vfp16-arguments2.cpp Tue Jun 18 07:34:27 2019
@@ -0,0 +1,63 @@
+// RUN: %clang_cc1 -triple armv7a--none-eabi -target-abi aapcs \
+// RUN:   -mfloat-abi soft -target-feature +neon -emit-llvm -o - -O1 %s \
+// RUN:   | FileCheck %s --check-prefix=CHECK-SOFT
+// RUN: %clang_cc1 -triple armv7a--none-eabi -target-abi aapcs \
+// RUN:   -mfloat-abi hard -target-feature +neon -emit-llvm -o - -O1 %s \
+// RUN:   | FileCheck %s --check-prefix=CHECK-HARD
+// RUN: %clang_cc1 -triple armv7a--none-eabi -target-abi aapcs \
+// RUN:   -mfloat-abi hard -target-feature +neon -target-feature +fullfp16 \
+// RUN:   -emit-llvm -o - -O1 %s \
+// RUN:   | FileCheck %s 

[libunwind] r363545 - [libunwind][AArch64] Fix libunwind::Registers_arm64::jumpto

[Mikhail Maltsev via cfe-commits]

Author: miyuki
Date: Mon Jun 17 04:00:21 2019
New Revision: 363545

URL: http://llvm.org/viewvc/llvm-project?rev=363545=rev
Log:
[libunwind][AArch64] Fix libunwind::Registers_arm64::jumpto

Summary:
The AArch64 version of the libunwind function which restores the
CPU state and resumes execution is not interrupt-safe. It restores
the target value of SP before loading the floating-point registers
from the context struct, but that struct is allocated on the stack
which is being deallocated. This means that if an interrupt occurs
during this function, and uses a lot of stack space, it could
overwrite the values about to be loaded into the floating-point
registers.

This patch fixes the issue.

Patch by Oliver Stannard.

Reviewers: phosek, chill

Reviewed By: chill

Subscribers: chill, javed.absar, kristof.beyls, christof, LukeCheeseman, 
pbarrio, olista01, libcxx-commits

Tags: #libc

Differential Revision: https://reviews.llvm.org/D63006

Modified:
libunwind/trunk/src/UnwindRegistersRestore.S

Modified: libunwind/trunk/src/UnwindRegistersRestore.S
URL: 
http://llvm.org/viewvc/llvm-project/libunwind/trunk/src/UnwindRegistersRestore.S?rev=363545=363544=363545=diff
==
--- libunwind/trunk/src/UnwindRegistersRestore.S (original)
+++ libunwind/trunk/src/UnwindRegistersRestore.S Mon Jun 17 04:00:21 2019
@@ -575,7 +575,8 @@ DEFINE_LIBUNWIND_FUNCTION(_ZN9libunwind1
   ldpx10,x11, [x0, #0x050]
   ldpx12,x13, [x0, #0x060]
   ldpx14,x15, [x0, #0x070]
-  ldpx16,x17, [x0, #0x080]
+  // x16 and x17 were clobbered by the call into the unwinder, so no point in
+  // restoring them.
   ldpx18,x19, [x0, #0x090]
   ldpx20,x21, [x0, #0x0A0]
   ldpx22,x23, [x0, #0x0B0]
@@ -583,8 +584,6 @@ DEFINE_LIBUNWIND_FUNCTION(_ZN9libunwind1
   ldpx26,x27, [x0, #0x0D0]
   ldpx28,x29, [x0, #0x0E0]
   ldrx30, [x0, #0x100]  // restore pc into lr
-  ldrx1,  [x0, #0x0F8]
-  movsp,x1  // restore sp
 
   ldpd0, d1,  [x0, #0x110]
   ldpd2, d3,  [x0, #0x120]
@@ -604,7 +603,13 @@ DEFINE_LIBUNWIND_FUNCTION(_ZN9libunwind1
   ldrd30, [x0, #0x200]
   ldrd31, [x0, #0x208]
 
+  // Finally, restore sp. This must be done after the the last read from the
+  // context struct, because it is allocated on the stack, and an exception
+  // could clobber the de-allocated portion of the stack after sp has been
+  // restored.
+  ldrx16, [x0, #0x0F8]
   ldpx0, x1,  [x0, #0x000]  // restore x0,x1
+  movsp,x16 // restore sp
   retx30// jump to pc
 
 #elif defined(__arm__) && !defined(__APPLE__)


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r342365 - [Analyzer] Define and use diff_plist in tests, NFC

[Mikhail Maltsev via cfe-commits]

Author: miyuki
Date: Mon Sep 17 03:19:46 2018
New Revision: 342365

URL: http://llvm.org/viewvc/llvm-project?rev=342365=rev
Log:
[Analyzer] Define and use diff_plist in tests, NFC

This patch defines a new substitution and uses it to reduce
duplication in the Clang Analyzer test cases.

Differential Revision: https://reviews.llvm.org/D52036

Modified:
cfe/trunk/test/Analysis/NewDelete-path-notes.cpp
cfe/trunk/test/Analysis/conditional-path-notes.c
cfe/trunk/test/Analysis/copypaste/plist-diagnostics-notes-as-events.cpp
cfe/trunk/test/Analysis/copypaste/plist-diagnostics.cpp
cfe/trunk/test/Analysis/cxx-for-range.cpp
cfe/trunk/test/Analysis/diagnostics/deref-track-symbolic-region.c
cfe/trunk/test/Analysis/diagnostics/report-issues-within-main-file.cpp
cfe/trunk/test/Analysis/diagnostics/undef-value-caller.c
cfe/trunk/test/Analysis/diagnostics/undef-value-param.c
cfe/trunk/test/Analysis/diagnostics/undef-value-param.m
cfe/trunk/test/Analysis/edges-new.mm
cfe/trunk/test/Analysis/generics.m
cfe/trunk/test/Analysis/inline-plist.c
cfe/trunk/test/Analysis/inline-unique-reports.c
cfe/trunk/test/Analysis/inlining/eager-reclamation-path-notes.c
cfe/trunk/test/Analysis/inlining/eager-reclamation-path-notes.cpp
cfe/trunk/test/Analysis/inlining/path-notes.c
cfe/trunk/test/Analysis/inlining/path-notes.cpp
cfe/trunk/test/Analysis/inlining/path-notes.m
cfe/trunk/test/Analysis/lit.local.cfg
cfe/trunk/test/Analysis/method-call-path-notes.cpp
cfe/trunk/test/Analysis/model-file.cpp
cfe/trunk/test/Analysis/null-deref-path-notes.m
cfe/trunk/test/Analysis/nullability-notes.m
cfe/trunk/test/Analysis/objc-arc.m
cfe/trunk/test/Analysis/plist-macros.cpp
cfe/trunk/test/Analysis/plist-output-alternate.m
cfe/trunk/test/Analysis/plist-output.m
cfe/trunk/test/Analysis/retain-release-path-notes.m
cfe/trunk/test/Analysis/unix-fns.c

Modified: cfe/trunk/test/Analysis/NewDelete-path-notes.cpp
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/Analysis/NewDelete-path-notes.cpp?rev=342365=342364=342365=diff
==
--- cfe/trunk/test/Analysis/NewDelete-path-notes.cpp (original)
+++ cfe/trunk/test/Analysis/NewDelete-path-notes.cpp Mon Sep 17 03:19:46 2018
@@ -1,7 +1,7 @@
 // RUN: %clang_analyze_cc1 -analyzer-checker=cplusplus.NewDelete,unix.Malloc 
-analyzer-output=text -verify %s
 // RUN: %clang_analyze_cc1 -analyzer-checker=cplusplus.NewDelete,unix.Malloc 
-analyzer-output=text -analyzer-config c++-allocator-inlining=true -verify %s
 // RUN: %clang_analyze_cc1 -analyzer-checker=cplusplus.NewDelete,unix.Malloc 
-analyzer-output=plist %s -o %t.plist
-// RUN: cat %t.plist | diff -u -w -I "/" -I ".:" -I "version" 
- %S/Inputs/expected-plists/NewDelete-path-notes.cpp.plist
+// RUN: cat %t.plist | %diff_plist 
%S/Inputs/expected-plists/NewDelete-path-notes.cpp.plist
 
 void test() {
   int *p = new int;

Modified: cfe/trunk/test/Analysis/conditional-path-notes.c
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/Analysis/conditional-path-notes.c?rev=342365=342364=342365=diff
==
--- cfe/trunk/test/Analysis/conditional-path-notes.c (original)
+++ cfe/trunk/test/Analysis/conditional-path-notes.c Mon Sep 17 03:19:46 2018
@@ -1,6 +1,6 @@
 // RUN: %clang_analyze_cc1 %s -analyzer-checker=core.NullDereference 
-analyzer-output=text -verify
 // RUN: %clang_analyze_cc1 %s -analyzer-checker=core.NullDereference 
-analyzer-output=plist -o %t
-// RUN: cat %t | diff -u -w -I "/" -I ".:" -I "version" - 
%S/Inputs/expected-plists/conditional-path-notes.c.plist
+// RUN: cat %t | %diff_plist 
%S/Inputs/expected-plists/conditional-path-notes.c.plist
 
 void testCondOp(int *p) {
   int *x = p ? p : p;

Modified: 
cfe/trunk/test/Analysis/copypaste/plist-diagnostics-notes-as-events.cpp
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/Analysis/copypaste/plist-diagnostics-notes-as-events.cpp?rev=342365=342364=342365=diff
==
--- cfe/trunk/test/Analysis/copypaste/plist-diagnostics-notes-as-events.cpp 
(original)
+++ cfe/trunk/test/Analysis/copypaste/plist-diagnostics-notes-as-events.cpp Mon 
Sep 17 03:19:46 2018
@@ -1,5 +1,5 @@
 // RUN: %clang_analyze_cc1 -analyzer-output=plist -analyzer-config 
notes-as-events=true -o %t.plist -std=c++11 
-analyzer-checker=alpha.clone.CloneChecker -analyzer-config 
alpha.clone.CloneChecker:MinimumCloneComplexity=10 -verify %s
-// RUN: cat %t.plist | diff -u -w -I "/" -I ".:" -I "version" 
- %S/Inputs/expected-plists/plist-diagnostics-notes-as-events.cpp.plist
+// RUN: cat %t.plist | %diff_plist 
%S/Inputs/expected-plists/plist-diagnostics-notes-as-events.cpp.plist
 
 void log();
 

Modified: cfe/trunk/test/Analysis/copypaste/plist-diagnostics.cpp
URL: 

r342034 - [CodeGen][ARM] Coerce FP16 vectors to integer vectors when needed

[Mikhail Maltsev via cfe-commits]

Author: miyuki
Date: Wed Sep 12 02:19:19 2018
New Revision: 342034

URL: http://llvm.org/viewvc/llvm-project?rev=342034=rev
Log:
[CodeGen][ARM] Coerce FP16 vectors to integer vectors when needed

Summary:
On targets that do not support FP16 natively LLVM currently legalizes
vectors of FP16 values by scalarizing them and promoting to FP32. This
causes problems for the following code:

  void foo(int, ...);

  typedef __attribute__((neon_vector_type(4))) __fp16 float16x4_t;
  void bar(float16x4_t x) {
foo(42, x);
  }

According to the AAPCS (appendix A.2) float16x4_t is a containerized
vector fundamental type, so 'foo' expects that the 4 16-bit FP values
are packed into 2 32-bit registers, but instead bar promotes them to
4 single precision values.

Since we already handle scalar FP16 values in the frontend by
bitcasting them to/from integers, this patch adds similar handling for
vector types and homogeneous FP16 vector aggregates.

One existing test required some adjustments because we now generate
more bitcasts (so the patch changes the test to target a machine with
native FP16 support).

Reviewers: eli.friedman, olista01, SjoerdMeijer, javed.absar, efriedma

Reviewed By: javed.absar, efriedma

Subscribers: efriedma, kristof.beyls, cfe-commits, chrib

Differential Revision: https://reviews.llvm.org/D50507

Added:
cfe/trunk/test/CodeGen/arm-vfp16-arguments.c
Modified:
cfe/trunk/lib/CodeGen/TargetInfo.cpp
cfe/trunk/test/CodeGen/arm_neon_intrinsics.c

Modified: cfe/trunk/lib/CodeGen/TargetInfo.cpp
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/CodeGen/TargetInfo.cpp?rev=342034=342033=342034=diff
==
--- cfe/trunk/lib/CodeGen/TargetInfo.cpp (original)
+++ cfe/trunk/lib/CodeGen/TargetInfo.cpp Wed Sep 12 02:19:19 2018
@@ -5549,6 +5549,9 @@ public:
 private:
   ABIArgInfo classifyReturnType(QualType RetTy, bool isVariadic) const;
   ABIArgInfo classifyArgumentType(QualType RetTy, bool isVariadic) const;
+  ABIArgInfo classifyHomogeneousAggregate(QualType Ty, const Type *Base,
+  uint64_t Members) const;
+  ABIArgInfo coerceIllegalVector(QualType Ty) const;
   bool isIllegalVectorType(QualType Ty) const;
 
   bool isHomogeneousAggregateBaseType(QualType Ty) const override;
@@ -5723,6 +5726,41 @@ void ARMABIInfo::setCCs() {
 RuntimeCC = abiCC;
 }
 
+ABIArgInfo ARMABIInfo::coerceIllegalVector(QualType Ty) const {
+  uint64_t Size = getContext().getTypeSize(Ty);
+  if (Size <= 32) {
+llvm::Type *ResType =
+llvm::Type::getInt32Ty(getVMContext());
+return ABIArgInfo::getDirect(ResType);
+  }
+  if (Size == 64 || Size == 128) {
+llvm::Type *ResType = llvm::VectorType::get(
+llvm::Type::getInt32Ty(getVMContext()), Size / 32);
+return ABIArgInfo::getDirect(ResType);
+  }
+  return getNaturalAlignIndirect(Ty, /*ByVal=*/false);
+}
+
+ABIArgInfo ARMABIInfo::classifyHomogeneousAggregate(QualType Ty,
+const Type *Base,
+uint64_t Members) const {
+  assert(Base && "Base class should be set for homogeneous aggregate");
+  // Base can be a floating-point or a vector.
+  if (const VectorType *VT = Base->getAs()) {
+// FP16 vectors should be converted to integer vectors
+if (!getTarget().hasLegalHalfType() &&
+(VT->getElementType()->isFloat16Type() ||
+  VT->getElementType()->isHalfType())) {
+  uint64_t Size = getContext().getTypeSize(VT);
+  llvm::Type *NewVecTy = llvm::VectorType::get(
+  llvm::Type::getInt32Ty(getVMContext()), Size / 32);
+  llvm::Type *Ty = llvm::ArrayType::get(NewVecTy, Members);
+  return ABIArgInfo::getDirect(Ty, 0, nullptr, false);
+}
+  }
+  return ABIArgInfo::getDirect(nullptr, 0, nullptr, false);
+}
+
 ABIArgInfo ARMABIInfo::classifyArgumentType(QualType Ty,
 bool isVariadic) const {
   // 6.1.2.1 The following argument types are VFP CPRCs:
@@ -5737,25 +5775,8 @@ ABIArgInfo ARMABIInfo::classifyArgumentT
   Ty = useFirstFieldIfTransparentUnion(Ty);
 
   // Handle illegal vector types here.
-  if (isIllegalVectorType(Ty)) {
-uint64_t Size = getContext().getTypeSize(Ty);
-if (Size <= 32) {
-  llvm::Type *ResType =
-  llvm::Type::getInt32Ty(getVMContext());
-  return ABIArgInfo::getDirect(ResType);
-}
-if (Size == 64) {
-  llvm::Type *ResType = llvm::VectorType::get(
-  llvm::Type::getInt32Ty(getVMContext()), 2);
-  return ABIArgInfo::getDirect(ResType);
-}
-if (Size == 128) {
-  llvm::Type *ResType = llvm::VectorType::get(
-  llvm::Type::getInt32Ty(getVMContext()), 4);
-  return ABIArgInfo::getDirect(ResType);
-}
-return getNaturalAlignIndirect(Ty, /*ByVal=*/false);
-  }
+  if (isIllegalVectorType(Ty))
+return coerceIllegalVector(Ty);
 
   // _Float16 

r334414 - [Driver] Add aliases for -Qn/-Qy

[Mikhail Maltsev via cfe-commits]

Author: miyuki
Date: Mon Jun 11 09:10:06 2018
New Revision: 334414

URL: http://llvm.org/viewvc/llvm-project?rev=334414=rev
Log:
[Driver] Add aliases for -Qn/-Qy

This patch adds aliases for -Qn (-fno-ident) and -Qy (-fident) which
look less cryptic than -Qn/-Qy. The aliases are compatible with GCC.

Differential Revision: https://reviews.llvm.org/D48021

Modified:
cfe/trunk/include/clang/Driver/Options.td
cfe/trunk/test/CodeGen/no-ident-version.c

Modified: cfe/trunk/include/clang/Driver/Options.td
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/include/clang/Driver/Options.td?rev=334414=334413=334414=diff
==
--- cfe/trunk/include/clang/Driver/Options.td (original)
+++ cfe/trunk/include/clang/Driver/Options.td Mon Jun 11 09:10:06 2018
@@ -404,6 +404,8 @@ def Qy : Flag<["-"], "Qy">, Flags<[CC1Op
   HelpText<"Emit metadata containing compiler name and version">;
 def Qn : Flag<["-"], "Qn">, Flags<[CC1Option]>,
   HelpText<"Do not emit metadata containing compiler name and version">;
+def : Flag<["-"], "fident">, Group, Alias, Flags<[CC1Option]>;
+def : Flag<["-"], "fno-ident">, Group, Alias, Flags<[CC1Option]>;
 def Qunused_arguments : Flag<["-"], "Qunused-arguments">, Flags<[DriverOption, 
CoreOption]>,
   HelpText<"Don't emit warning for unused driver arguments">;
 def Q : Flag<["-"], "Q">, IgnoredGCCCompat;
@@ -2840,7 +2842,6 @@ defm gcse_after_reload: BooleanFFlag<"gc
 defm gcse_las: BooleanFFlag<"gcse-las">, 
Group;
 defm gcse_sm: BooleanFFlag<"gcse-sm">, 
Group;
 defm gnu : BooleanFFlag<"gnu">, Group;
-defm ident : BooleanFFlag<"ident">, Group;
 defm implicit_templates : BooleanFFlag<"implicit-templates">, 
Group;
 defm implement_inlines : BooleanFFlag<"implement-inlines">, 
Group;
 defm merge_constants : BooleanFFlag<"merge-constants">, 
Group;

Modified: cfe/trunk/test/CodeGen/no-ident-version.c
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGen/no-ident-version.c?rev=334414=334413=334414=diff
==
--- cfe/trunk/test/CodeGen/no-ident-version.c (original)
+++ cfe/trunk/test/CodeGen/no-ident-version.c Mon Jun 11 09:10:06 2018
@@ -2,8 +2,12 @@
 // RUN:   | FileCheck --check-prefix=CHECK-NONE %s
 // RUN: %clang_cc1 -Qn -emit-llvm -debug-info-kind=limited -o - %s \
 // RUN:   | FileCheck --check-prefix=CHECK-QN %s
+// RUN: %clang_cc1 -fno-ident -emit-llvm -debug-info-kind=limited -o - %s \
+// RUN:   | FileCheck --check-prefix=CHECK-QN %s
 // RUN: %clang_cc1 -Qy -emit-llvm -debug-info-kind=limited -o - %s \
 // RUN:   | FileCheck --check-prefix=CHECK-QY %s
+// RUN: %clang_cc1 -fident -emit-llvm -debug-info-kind=limited -o - %s \
+// RUN:   | FileCheck --check-prefix=CHECK-QY %s
 
 // CHECK-NONE: @main
 // CHECK-NONE: llvm.ident


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r331164 - [Targets] Implement getConstraintRegister for ARM and AArch64

[Mikhail Maltsev via cfe-commits]

Author: miyuki
Date: Mon Apr 30 02:11:08 2018
New Revision: 331164

URL: http://llvm.org/viewvc/llvm-project?rev=331164=rev
Log:
[Targets] Implement getConstraintRegister for ARM and AArch64

Summary:
The getConstraintRegister method is used by semantic checking of
inline assembly statements in order to diagnose conflicts between
clobber list and input/output lists. Currently ARM and AArch64 don't
override getConstraintRegister, so conflicts between registers
assigned to variables in asm labels and clobber lists are not
diagnosed. Such conflicts can cause assertion failures in the back end
and even miscompilations.

This patch implements getConstraintRegister for ARM and AArch64
targets. Since these targets don't have single-register constraints,
the implementation is trivial and just returns the register specified
in an asm label (if any).

Reviewers: eli.friedman, javed.absar, thopre

Reviewed By: thopre

Subscribers: rengolin, eraman, rogfer01, myatsina, kristof.beyls, cfe-commits, 
chrib

Differential Revision: https://reviews.llvm.org/D45965

Modified:
cfe/trunk/include/clang/Basic/TargetInfo.h
cfe/trunk/lib/Basic/Targets/AArch64.h
cfe/trunk/lib/Basic/Targets/ARM.h
cfe/trunk/test/Sema/arm-asm.c
cfe/trunk/test/Sema/arm64-inline-asm.c

Modified: cfe/trunk/include/clang/Basic/TargetInfo.h
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/include/clang/Basic/TargetInfo.h?rev=331164=331163=331164=diff
==
--- cfe/trunk/include/clang/Basic/TargetInfo.h (original)
+++ cfe/trunk/include/clang/Basic/TargetInfo.h Mon Apr 30 02:11:08 2018
@@ -629,6 +629,12 @@ public:
   StringRef getNormalizedGCCRegisterName(StringRef Name,
  bool ReturnCanonical = false) const;
 
+  /// \brief Extracts a register from the passed constraint (if it is a
+  /// single-register constraint) and the asm label expression related to a
+  /// variable in the input or output list of an inline asm statement.
+  ///
+  /// This function is used by Sema in order to diagnose conflicts between
+  /// the clobber list and the input/output lists.
   virtual StringRef getConstraintRegister(StringRef Constraint,
   StringRef Expression) const {
 return "";

Modified: cfe/trunk/lib/Basic/Targets/AArch64.h
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Basic/Targets/AArch64.h?rev=331164=331163=331164=diff
==
--- cfe/trunk/lib/Basic/Targets/AArch64.h (original)
+++ cfe/trunk/lib/Basic/Targets/AArch64.h Mon Apr 30 02:11:08 2018
@@ -82,6 +82,11 @@ public:
  std::string ) const override;
   const char *getClobbers() const override;
 
+  StringRef getConstraintRegister(StringRef Constraint,
+  StringRef Expression) const override {
+return Expression;
+  }
+
   int getEHDataRegisterNumber(unsigned RegNo) const override;
 };
 

Modified: cfe/trunk/lib/Basic/Targets/ARM.h
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Basic/Targets/ARM.h?rev=331164=331163=331164=diff
==
--- cfe/trunk/lib/Basic/Targets/ARM.h (original)
+++ cfe/trunk/lib/Basic/Targets/ARM.h Mon Apr 30 02:11:08 2018
@@ -156,6 +156,11 @@ public:
  std::string ) const override;
   const char *getClobbers() const override;
 
+  StringRef getConstraintRegister(StringRef Constraint,
+  StringRef Expression) const override {
+return Expression;
+  }
+
   CallingConvCheckResult checkCallingConvention(CallingConv CC) const override;
 
   int getEHDataRegisterNumber(unsigned RegNo) const override;

Modified: cfe/trunk/test/Sema/arm-asm.c
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/Sema/arm-asm.c?rev=331164=331163=331164=diff
==
--- cfe/trunk/test/Sema/arm-asm.c (original)
+++ cfe/trunk/test/Sema/arm-asm.c Mon Apr 30 02:11:08 2018
@@ -10,3 +10,10 @@ void test_64bit_r(void) {
   long long foo = 0, bar = 0;
   asm volatile("INST %0, %1" : "=r"(foo) : "r"(bar));
 }
+
+void test_clobber_conflict(void) {
+  register int x asm("r1");
+  asm volatile("nop" :: "r"(x) : "%r1"); // expected-error {{conflicts with 
asm clobber list}}
+  asm volatile("nop" :: "l"(x) : "%r1"); // expected-error {{conflicts with 
asm clobber list}}
+  asm volatile("nop" : "=r"(x) :: "%r1"); // expected-error {{conflicts with 
asm clobber list}}
+}

Modified: cfe/trunk/test/Sema/arm64-inline-asm.c
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/Sema/arm64-inline-asm.c?rev=331164=331163=331164=diff
==
--- cfe/trunk/test/Sema/arm64-inline-asm.c (original)
+++ 

r330575 - [CodeGen] Reland r330442: Add an option to suppress output of llvm.ident

[Mikhail Maltsev via cfe-commits]

Author: miyuki
Date: Mon Apr 23 03:08:46 2018
New Revision: 330575

URL: http://llvm.org/viewvc/llvm-project?rev=330575=rev
Log:
[CodeGen] Reland r330442: Add an option to suppress output of llvm.ident

The test case in the original patch was overly contrained and
failed on PPC targets.

Added:
cfe/trunk/test/CodeGen/no-ident-version.c
Modified:
cfe/trunk/include/clang/Driver/Options.td
cfe/trunk/include/clang/Frontend/CodeGenOptions.def
cfe/trunk/lib/CodeGen/CGDebugInfo.cpp
cfe/trunk/lib/CodeGen/CodeGenModule.cpp
cfe/trunk/lib/Driver/ToolChains/Clang.cpp
cfe/trunk/lib/Frontend/CompilerInvocation.cpp

Modified: cfe/trunk/include/clang/Driver/Options.td
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/include/clang/Driver/Options.td?rev=330575=330574=330575=diff
==
--- cfe/trunk/include/clang/Driver/Options.td (original)
+++ cfe/trunk/include/clang/Driver/Options.td Mon Apr 23 03:08:46 2018
@@ -396,7 +396,10 @@ def O_flag : Flag<["-"], "O">, Flags<[CC
 def Ofast : Joined<["-"], "Ofast">, Group, Flags<[CC1Option]>;
 def P : Flag<["-"], "P">, Flags<[CC1Option]>, Group,
   HelpText<"Disable linemarker output in -E mode">;
-def Qn : Flag<["-"], "Qn">, IgnoredGCCCompat;
+def Qy : Flag<["-"], "Qy">, Flags<[CC1Option]>,
+  HelpText<"Emit metadata containing compiler name and version">;
+def Qn : Flag<["-"], "Qn">, Flags<[CC1Option]>,
+  HelpText<"Do not emit metadata containing compiler name and version">;
 def Qunused_arguments : Flag<["-"], "Qunused-arguments">, Flags<[DriverOption, 
CoreOption]>,
   HelpText<"Don't emit warning for unused driver arguments">;
 def Q : Flag<["-"], "Q">, IgnoredGCCCompat;

Modified: cfe/trunk/include/clang/Frontend/CodeGenOptions.def
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/include/clang/Frontend/CodeGenOptions.def?rev=330575=330574=330575=diff
==
--- cfe/trunk/include/clang/Frontend/CodeGenOptions.def (original)
+++ cfe/trunk/include/clang/Frontend/CodeGenOptions.def Mon Apr 23 03:08:46 2018
@@ -69,6 +69,7 @@ CODEGENOPT(EmitDeclMetadata  , 1, 0) ///
  ///< Decl* various IR entities came from.
  ///< Only useful when running CodeGen as a
  ///< subroutine.
+CODEGENOPT(EmitVersionIdentMetadata , 1, 1) ///< Emit compiler version 
metadata.
 CODEGENOPT(EmitGcovArcs  , 1, 0) ///< Emit coverage data files, aka. GCDA.
 CODEGENOPT(EmitGcovNotes , 1, 0) ///< Emit coverage "notes" files, aka 
GCNO.
 CODEGENOPT(EmitOpenCLArgMetadata , 1, 0) ///< Emit OpenCL kernel arg metadata.

Modified: cfe/trunk/lib/CodeGen/CGDebugInfo.cpp
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/CodeGen/CGDebugInfo.cpp?rev=330575=330574=330575=diff
==
--- cfe/trunk/lib/CodeGen/CGDebugInfo.cpp (original)
+++ cfe/trunk/lib/CodeGen/CGDebugInfo.cpp Mon Apr 23 03:08:46 2018
@@ -577,7 +577,8 @@ void CGDebugInfo::CreateCompileUnit() {
   remapDIPath(getCurrentDirname()),
   CSInfo,
   getSource(SM, SM.getMainFileID())),
-  Producer, LO.Optimize || CGOpts.PrepareForLTO || CGOpts.EmitSummaryIndex,
+  CGOpts.EmitVersionIdentMetadata ? Producer : "",
+  LO.Optimize || CGOpts.PrepareForLTO || CGOpts.EmitSummaryIndex,
   CGOpts.DwarfDebugFlags, RuntimeVers,
   CGOpts.EnableSplitDwarf ? "" : CGOpts.SplitDwarfFile, EmissionKind,
   0 /* DWOid */, CGOpts.SplitDwarfInlining, CGOpts.DebugInfoForProfiling,

Modified: cfe/trunk/lib/CodeGen/CodeGenModule.cpp
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/CodeGen/CodeGenModule.cpp?rev=330575=330574=330575=diff
==
--- cfe/trunk/lib/CodeGen/CodeGenModule.cpp (original)
+++ cfe/trunk/lib/CodeGen/CodeGenModule.cpp Mon Apr 23 03:08:46 2018
@@ -571,7 +571,8 @@ void CodeGenModule::Release() {
   if (DebugInfo)
 DebugInfo->finalize();
 
-  EmitVersionIdentMetadata();
+  if (getCodeGenOpts().EmitVersionIdentMetadata)
+EmitVersionIdentMetadata();
 
   EmitTargetMetadata();
 }

Modified: cfe/trunk/lib/Driver/ToolChains/Clang.cpp
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Driver/ToolChains/Clang.cpp?rev=330575=330574=330575=diff
==
--- cfe/trunk/lib/Driver/ToolChains/Clang.cpp (original)
+++ cfe/trunk/lib/Driver/ToolChains/Clang.cpp Mon Apr 23 03:08:46 2018
@@ -4408,6 +4408,9 @@ void Clang::ConstructJob(Compilation ,
 }
   }
 
+  if (!Args.hasFlag(options::OPT_Qy, options::OPT_Qn, true))
+CmdArgs.push_back("-Qn");
+
   // -fcommon is the default unless compiling kernel code or the target says so
   bool NoCommonDefault = 

r330451 - Revert r330442, CodeGen/no-ident-version.c is failing on PPC

[Mikhail Maltsev via cfe-commits]

Author: miyuki
Date: Fri Apr 20 10:14:39 2018
New Revision: 330451

URL: http://llvm.org/viewvc/llvm-project?rev=330451=rev
Log:
Revert r330442, CodeGen/no-ident-version.c is failing on PPC

Removed:
cfe/trunk/test/CodeGen/no-ident-version.c
Modified:
cfe/trunk/include/clang/Driver/Options.td
cfe/trunk/include/clang/Frontend/CodeGenOptions.def
cfe/trunk/lib/CodeGen/CGDebugInfo.cpp
cfe/trunk/lib/CodeGen/CodeGenModule.cpp
cfe/trunk/lib/Driver/ToolChains/Clang.cpp
cfe/trunk/lib/Frontend/CompilerInvocation.cpp

Modified: cfe/trunk/include/clang/Driver/Options.td
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/include/clang/Driver/Options.td?rev=330451=330450=330451=diff
==
--- cfe/trunk/include/clang/Driver/Options.td (original)
+++ cfe/trunk/include/clang/Driver/Options.td Fri Apr 20 10:14:39 2018
@@ -396,10 +396,7 @@ def O_flag : Flag<["-"], "O">, Flags<[CC
 def Ofast : Joined<["-"], "Ofast">, Group, Flags<[CC1Option]>;
 def P : Flag<["-"], "P">, Flags<[CC1Option]>, Group,
   HelpText<"Disable linemarker output in -E mode">;
-def Qy : Flag<["-"], "Qy">, Flags<[CC1Option]>,
-  HelpText<"Emit metadata containing compiler name and version">;
-def Qn : Flag<["-"], "Qn">, Flags<[CC1Option]>,
-  HelpText<"Do not emit metadata containing compiler name and version">;
+def Qn : Flag<["-"], "Qn">, IgnoredGCCCompat;
 def Qunused_arguments : Flag<["-"], "Qunused-arguments">, Flags<[DriverOption, 
CoreOption]>,
   HelpText<"Don't emit warning for unused driver arguments">;
 def Q : Flag<["-"], "Q">, IgnoredGCCCompat;

Modified: cfe/trunk/include/clang/Frontend/CodeGenOptions.def
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/include/clang/Frontend/CodeGenOptions.def?rev=330451=330450=330451=diff
==
--- cfe/trunk/include/clang/Frontend/CodeGenOptions.def (original)
+++ cfe/trunk/include/clang/Frontend/CodeGenOptions.def Fri Apr 20 10:14:39 2018
@@ -69,7 +69,6 @@ CODEGENOPT(EmitDeclMetadata  , 1, 0) ///
  ///< Decl* various IR entities came from.
  ///< Only useful when running CodeGen as a
  ///< subroutine.
-CODEGENOPT(EmitVersionIdentMetadata , 1, 1) ///< Emit compiler version 
metadata.
 CODEGENOPT(EmitGcovArcs  , 1, 0) ///< Emit coverage data files, aka. GCDA.
 CODEGENOPT(EmitGcovNotes , 1, 0) ///< Emit coverage "notes" files, aka 
GCNO.
 CODEGENOPT(EmitOpenCLArgMetadata , 1, 0) ///< Emit OpenCL kernel arg metadata.

Modified: cfe/trunk/lib/CodeGen/CGDebugInfo.cpp
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/CodeGen/CGDebugInfo.cpp?rev=330451=330450=330451=diff
==
--- cfe/trunk/lib/CodeGen/CGDebugInfo.cpp (original)
+++ cfe/trunk/lib/CodeGen/CGDebugInfo.cpp Fri Apr 20 10:14:39 2018
@@ -577,8 +577,7 @@ void CGDebugInfo::CreateCompileUnit() {
   remapDIPath(getCurrentDirname()),
   CSInfo,
   getSource(SM, SM.getMainFileID())),
-  CGOpts.EmitVersionIdentMetadata ? Producer : "",
-  LO.Optimize || CGOpts.PrepareForLTO || CGOpts.EmitSummaryIndex,
+  Producer, LO.Optimize || CGOpts.PrepareForLTO || CGOpts.EmitSummaryIndex,
   CGOpts.DwarfDebugFlags, RuntimeVers,
   CGOpts.EnableSplitDwarf ? "" : CGOpts.SplitDwarfFile, EmissionKind,
   0 /* DWOid */, CGOpts.SplitDwarfInlining, CGOpts.DebugInfoForProfiling,

Modified: cfe/trunk/lib/CodeGen/CodeGenModule.cpp
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/CodeGen/CodeGenModule.cpp?rev=330451=330450=330451=diff
==
--- cfe/trunk/lib/CodeGen/CodeGenModule.cpp (original)
+++ cfe/trunk/lib/CodeGen/CodeGenModule.cpp Fri Apr 20 10:14:39 2018
@@ -571,8 +571,7 @@ void CodeGenModule::Release() {
   if (DebugInfo)
 DebugInfo->finalize();
 
-  if (getCodeGenOpts().EmitVersionIdentMetadata)
-EmitVersionIdentMetadata();
+  EmitVersionIdentMetadata();
 
   EmitTargetMetadata();
 }

Modified: cfe/trunk/lib/Driver/ToolChains/Clang.cpp
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Driver/ToolChains/Clang.cpp?rev=330451=330450=330451=diff
==
--- cfe/trunk/lib/Driver/ToolChains/Clang.cpp (original)
+++ cfe/trunk/lib/Driver/ToolChains/Clang.cpp Fri Apr 20 10:14:39 2018
@@ -4408,9 +4408,6 @@ void Clang::ConstructJob(Compilation ,
 }
   }
 
-  if (!Args.hasFlag(options::OPT_Qy, options::OPT_Qn, true))
-CmdArgs.push_back("-Qn");
-
   // -fcommon is the default unless compiling kernel code or the target says so
   bool NoCommonDefault = KernelOrKext || isNoCommonDefault(RawTriple);
   if (!Args.hasFlag(options::OPT_fcommon, 

r330442 - [CodeGen] Add an option to suppress output of llvm.ident

[Mikhail Maltsev via cfe-commits]

Author: miyuki
Date: Fri Apr 20 09:29:03 2018
New Revision: 330442

URL: http://llvm.org/viewvc/llvm-project?rev=330442=rev
Log:
[CodeGen] Add an option to suppress output of llvm.ident

Summary:
By default Clang outputs its version (including git commit hash, in
case of trunk builds) into object and assembly files. It might be
useful to have an option to disable this, especially for debugging
purposes.
This patch implements new command line flags -Qn and -Qy (the names
are chosen for compatibility with GCC). -Qn disables output of
the 'llvm.ident' metadata string and the 'producer' debug info. -Qy
(enabled by default) does the opposite.

Reviewers: faisalv, echristo, aprantl

Reviewed By: aprantl

Subscribers: aprantl, cfe-commits, JDevlieghere, rogfer01

Differential Revision: https://reviews.llvm.org/D45255

Added:
cfe/trunk/test/CodeGen/no-ident-version.c
Modified:
cfe/trunk/include/clang/Driver/Options.td
cfe/trunk/include/clang/Frontend/CodeGenOptions.def
cfe/trunk/lib/CodeGen/CGDebugInfo.cpp
cfe/trunk/lib/CodeGen/CodeGenModule.cpp
cfe/trunk/lib/Driver/ToolChains/Clang.cpp
cfe/trunk/lib/Frontend/CompilerInvocation.cpp

Modified: cfe/trunk/include/clang/Driver/Options.td
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/include/clang/Driver/Options.td?rev=330442=330441=330442=diff
==
--- cfe/trunk/include/clang/Driver/Options.td (original)
+++ cfe/trunk/include/clang/Driver/Options.td Fri Apr 20 09:29:03 2018
@@ -396,7 +396,10 @@ def O_flag : Flag<["-"], "O">, Flags<[CC
 def Ofast : Joined<["-"], "Ofast">, Group, Flags<[CC1Option]>;
 def P : Flag<["-"], "P">, Flags<[CC1Option]>, Group,
   HelpText<"Disable linemarker output in -E mode">;
-def Qn : Flag<["-"], "Qn">, IgnoredGCCCompat;
+def Qy : Flag<["-"], "Qy">, Flags<[CC1Option]>,
+  HelpText<"Emit metadata containing compiler name and version">;
+def Qn : Flag<["-"], "Qn">, Flags<[CC1Option]>,
+  HelpText<"Do not emit metadata containing compiler name and version">;
 def Qunused_arguments : Flag<["-"], "Qunused-arguments">, Flags<[DriverOption, 
CoreOption]>,
   HelpText<"Don't emit warning for unused driver arguments">;
 def Q : Flag<["-"], "Q">, IgnoredGCCCompat;

Modified: cfe/trunk/include/clang/Frontend/CodeGenOptions.def
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/include/clang/Frontend/CodeGenOptions.def?rev=330442=330441=330442=diff
==
--- cfe/trunk/include/clang/Frontend/CodeGenOptions.def (original)
+++ cfe/trunk/include/clang/Frontend/CodeGenOptions.def Fri Apr 20 09:29:03 2018
@@ -69,6 +69,7 @@ CODEGENOPT(EmitDeclMetadata  , 1, 0) ///
  ///< Decl* various IR entities came from.
  ///< Only useful when running CodeGen as a
  ///< subroutine.
+CODEGENOPT(EmitVersionIdentMetadata , 1, 1) ///< Emit compiler version 
metadata.
 CODEGENOPT(EmitGcovArcs  , 1, 0) ///< Emit coverage data files, aka. GCDA.
 CODEGENOPT(EmitGcovNotes , 1, 0) ///< Emit coverage "notes" files, aka 
GCNO.
 CODEGENOPT(EmitOpenCLArgMetadata , 1, 0) ///< Emit OpenCL kernel arg metadata.

Modified: cfe/trunk/lib/CodeGen/CGDebugInfo.cpp
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/CodeGen/CGDebugInfo.cpp?rev=330442=330441=330442=diff
==
--- cfe/trunk/lib/CodeGen/CGDebugInfo.cpp (original)
+++ cfe/trunk/lib/CodeGen/CGDebugInfo.cpp Fri Apr 20 09:29:03 2018
@@ -577,7 +577,8 @@ void CGDebugInfo::CreateCompileUnit() {
   remapDIPath(getCurrentDirname()),
   CSInfo,
   getSource(SM, SM.getMainFileID())),
-  Producer, LO.Optimize || CGOpts.PrepareForLTO || CGOpts.EmitSummaryIndex,
+  CGOpts.EmitVersionIdentMetadata ? Producer : "",
+  LO.Optimize || CGOpts.PrepareForLTO || CGOpts.EmitSummaryIndex,
   CGOpts.DwarfDebugFlags, RuntimeVers,
   CGOpts.EnableSplitDwarf ? "" : CGOpts.SplitDwarfFile, EmissionKind,
   0 /* DWOid */, CGOpts.SplitDwarfInlining, CGOpts.DebugInfoForProfiling,

Modified: cfe/trunk/lib/CodeGen/CodeGenModule.cpp
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/CodeGen/CodeGenModule.cpp?rev=330442=330441=330442=diff
==
--- cfe/trunk/lib/CodeGen/CodeGenModule.cpp (original)
+++ cfe/trunk/lib/CodeGen/CodeGenModule.cpp Fri Apr 20 09:29:03 2018
@@ -571,7 +571,8 @@ void CodeGenModule::Release() {
   if (DebugInfo)
 DebugInfo->finalize();
 
-  EmitVersionIdentMetadata();
+  if (getCodeGenOpts().EmitVersionIdentMetadata)
+EmitVersionIdentMetadata();
 
   EmitTargetMetadata();
 }

Modified: cfe/trunk/lib/Driver/ToolChains/Clang.cpp
URL: 

r326551 - [Sema] Improve test coverage of narrowing conversion diagnostics

[Mikhail Maltsev via cfe-commits]

Author: miyuki
Date: Fri Mar  2 02:03:02 2018
New Revision: 326551

URL: http://llvm.org/viewvc/llvm-project?rev=326551=rev
Log:
[Sema] Improve test coverage of narrowing conversion diagnostics

Summary:
This patch adds tests of narrowing conversion diagnostics for the
'unscoped enum -> integer' case.

Reviewers: faisalv, rsmith, rogfer01

Reviewed By: rogfer01

Subscribers: cfe-commits, rogfer01

Differential Revision: https://reviews.llvm.org/D43572

Modified:
cfe/trunk/test/CXX/dcl.decl/dcl.init/dcl.init.list/p7-0x.cpp

Modified: cfe/trunk/test/CXX/dcl.decl/dcl.init/dcl.init.list/p7-0x.cpp
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CXX/dcl.decl/dcl.init/dcl.init.list/p7-0x.cpp?rev=326551=326550=326551=diff
==
--- cfe/trunk/test/CXX/dcl.decl/dcl.init/dcl.init.list/p7-0x.cpp (original)
+++ cfe/trunk/test/CXX/dcl.decl/dcl.init/dcl.init.list/p7-0x.cpp Fri Mar  2 
02:03:02 2018
@@ -147,8 +147,10 @@ void int_to_float() {
 void shrink_int() {
   // Not a constant expression.
   short s = 1;
+  UnscopedEnum e = EnumVal;
   unsigned short us = 1;
   Agg c1 = {s};  // expected-error {{ cannot be narrowed }} 
expected-note {{silence}}
+  Agg c2 = {e};  // expected-error {{ cannot be narrowed }} 
expected-note {{silence}}
   Agg s1 = {s};  // expected-error {{ cannot be narrowed }} 
expected-note {{silence}}
   Agg s2 = {us};  // expected-error {{ cannot be narrowed }} 
expected-note {{silence}}
 
@@ -158,16 +160,19 @@ void shrink_int() {
   // long).
   long l1 = 1;
   Agg i1 = {l1};  // expected-error {{ cannot be narrowed }} 
expected-note {{silence}}
+  Agg i2 = {e};  // OK
   long long ll = 1;
   Agg l2 = {ll};  // OK
 
   // Constants.
-  Agg c2 = {127};  // OK
-  Agg c3 = {300};  // expected-error {{ cannot be narrowed }} 
expected-note {{silence}} expected-warning {{changes value}}
+  Agg c3 = {127};  // OK
+  Agg c4 = {300};  // expected-error {{ cannot be narrowed }} 
expected-note {{silence}} expected-warning {{changes value}}
+  Agg c5 = {EnumVal};  // expected-error {{ cannot be narrowed }} 
expected-note {{silence}} expected-warning {{changes value}}
 
-  Agg i2 = {0x7FFFU};  // OK
-  Agg i3 = {0x8000U};  // expected-error {{ cannot be narrowed }} 
expected-note {{silence}}
-  Agg i4 = {-0x8000L};  // expected-error {{ cannot be 
narrowed }} expected-note {{silence}}
+  Agg i3 = {0x7FFFU};  // OK
+  Agg i4 = {EnumVal};  // OK
+  Agg i5 = {0x8000U};  // expected-error {{ cannot be narrowed }} 
expected-note {{silence}}
+  Agg i6 = {-0x8000L};  // expected-error {{ cannot be 
narrowed }} expected-note {{silence}}
 
   // Bool is also an integer type, but conversions to it are a different AST
   // node.


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[libcxx] r325760 - [libcxx] Do not include the C math.h header before __config

[Mikhail Maltsev via cfe-commits]

Author: miyuki
Date: Thu Feb 22 01:34:08 2018
New Revision: 325760

URL: http://llvm.org/viewvc/llvm-project?rev=325760=rev
Log:
[libcxx] Do not include the C math.h header before __config

Summary:
Certain C libraries require configuration macros defined in __config
to provide the correct functionality for libc++. This patch ensures
that the C header math.h is always included after the __config
header. It also adds a Windows-specific #if guard for the case when
the C math.h file is included the second time, as suggested by
Marshall in https://reviews.llvm.org/rL323490.

Fixes PR36382.

Reviewers: mclow.lists, EricWF

Reviewed By: mclow.lists

Subscribers: cfe-commits, pcc, christof, rogfer01

Differential Revision: https://reviews.llvm.org/D43579

Modified:
libcxx/trunk/include/math.h

Modified: libcxx/trunk/include/math.h
URL: 
http://llvm.org/viewvc/llvm-project/libcxx/trunk/include/math.h?rev=325760=325759=325760=diff
==
--- libcxx/trunk/include/math.h (original)
+++ libcxx/trunk/include/math.h Thu Feb 22 01:34:08 2018
@@ -8,16 +8,6 @@
 //
 
//===--===//
 
-// This include lives outside the header guard in order to support an MSVC
-// extension which allows users to do:
-//
-// #define _USE_MATH_DEFINES
-// #include 
-//
-// and receive the definitions of mathematical constants, even if 
-// has previously been included.
-#include_next 
-
 #ifndef _LIBCPP_MATH_H
 #define _LIBCPP_MATH_H
 
@@ -308,6 +298,8 @@ long doubletruncl(long double x);
 #pragma GCC system_header
 #endif
 
+#include_next 
+
 #ifdef __cplusplus
 
 // We support including .h headers inside 'extern "C"' contexts, so switch
@@ -1494,4 +1486,18 @@ trunc(_A1 __lcpp_x) _NOEXCEPT {return ::
 
 #endif // __cplusplus
 
+#else // _LIBCPP_MATH_H
+
+// This include lives outside the header guard in order to support an MSVC
+// extension which allows users to do:
+//
+// #define _USE_MATH_DEFINES
+// #include 
+//
+// and receive the definitions of mathematical constants, even if 
+// has previously been included.
+#if defined(_LIBCPP_MSVCRT) && defined(_USE_MATH_DEFINES)
+#include_next 
+#endif
+
 #endif  // _LIBCPP_MATH_H


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r325668 - [Sema] Classify conversions from enum to float as narrowing

[Mikhail Maltsev via cfe-commits]

Author: miyuki
Date: Wed Feb 21 02:08:18 2018
New Revision: 325668

URL: http://llvm.org/viewvc/llvm-project?rev=325668=rev
Log:
[Sema] Classify conversions from enum to float as narrowing

Summary:
According to [dcl.init.list]p7:
  A narrowing conversion is an implicit conversion
  - ...
  - from an integer type or unscoped enumeration type to a
floating-point type, except where the source is a constant
expression and the actual value after conversion will fit into
the target type and will produce the original value when
converted back to the original type, or
  - ...

Currently clang does not handle the 'unscoped enumeration' case. This
patch fixes the corresponding check.

Reviewers: faisalv, rsmith, rogfer01

Reviewed By: rogfer01

Subscribers: rogfer01, cfe-commits

Differential Revision: https://reviews.llvm.org/D42545

Modified:
cfe/trunk/lib/Sema/SemaOverload.cpp
cfe/trunk/test/CXX/dcl.decl/dcl.init/dcl.init.list/p7-0x.cpp

Modified: cfe/trunk/lib/Sema/SemaOverload.cpp
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Sema/SemaOverload.cpp?rev=325668=325667=325668=diff
==
--- cfe/trunk/lib/Sema/SemaOverload.cpp (original)
+++ cfe/trunk/lib/Sema/SemaOverload.cpp Wed Feb 21 02:08:18 2018
@@ -327,7 +327,8 @@ StandardConversionSequence::getNarrowing
   FloatingIntegralConversion:
 if (FromType->isRealFloatingType() && ToType->isIntegralType(Ctx)) {
   return NK_Type_Narrowing;
-} else if (FromType->isIntegralType(Ctx) && ToType->isRealFloatingType()) {
+} else if (FromType->isIntegralOrUnscopedEnumerationType() &&
+   ToType->isRealFloatingType()) {
   llvm::APSInt IntConstantValue;
   const Expr *Initializer = IgnoreNarrowingConversion(Converted);
   assert(Initializer && "Unknown conversion expression");

Modified: cfe/trunk/test/CXX/dcl.decl/dcl.init/dcl.init.list/p7-0x.cpp
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CXX/dcl.decl/dcl.init/dcl.init.list/p7-0x.cpp?rev=325668=325667=325668=diff
==
--- cfe/trunk/test/CXX/dcl.decl/dcl.init/dcl.init.list/p7-0x.cpp (original)
+++ cfe/trunk/test/CXX/dcl.decl/dcl.init/dcl.init.list/p7-0x.cpp Wed Feb 21 
02:08:18 2018
@@ -24,6 +24,10 @@ void std_example() {
 { 2, f(2), f(2.0) };  // OK: the double-to-int conversion is not at the 
top level
 }
 
+enum UnscopedEnum {
+  EnumVal = 300
+};
+
 // Test each rule individually.
 
 template
@@ -115,15 +119,21 @@ void shrink_float() {
 void int_to_float() {
   // Not a constant expression.
   char c = 1;
+  UnscopedEnum e = EnumVal;
 
   // Variables.  Yes, even though all char's will fit into any floating type.
   Agg f1 = {c};  // expected-error {{ cannot be narrowed }} 
expected-note {{silence}}
   Agg f2 = {c};  // expected-error {{ cannot be narrowed }} 
expected-note {{silence}}
   Agg f3 = {c};  // expected-error {{ cannot be narrowed }} 
expected-note {{silence}}
 
+  Agg f4 = {e};  // expected-error {{ cannot be narrowed }} 
expected-note {{silence}}
+  Agg f5 = {e};  // expected-error {{ cannot be narrowed }} 
expected-note {{silence}}
+  Agg f6 = {e};  // expected-error {{ cannot be narrowed }} 
expected-note {{silence}}
+
   // Constants.
-  Agg f4 = {12345678};  // OK (exactly fits in a float)
-  Agg f5 = {123456789};  // expected-error {{ cannot be narrowed }} 
expected-note {{silence}}
+  Agg f7 = {12345678};  // OK (exactly fits in a float)
+  Agg f8 = {EnumVal};  // OK
+  Agg f9 = {123456789};  // expected-error {{ cannot be narrowed }} 
expected-note {{silence}}
 
   Agg ce1 = { Convert(123456789) }; // expected-error {{constant 
expression evaluates to 123456789 which cannot be narrowed to type 'float'}} 
expected-note {{silence}}
   Agg ce2 = { ConvertVar() }; // expected-error 
{{non-constant-expression cannot be narrowed from type 'long long' to 
'double'}} expected-note {{silence}}


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[libcxx] r325510 - [libcxx] Improve accuracy of complex asinh and acosh

[Mikhail Maltsev via cfe-commits]

Author: miyuki
Date: Mon Feb 19 07:41:36 2018
New Revision: 325510

URL: http://llvm.org/viewvc/llvm-project?rev=325510=rev
Log:
[libcxx] Improve accuracy of complex asinh and acosh

Summary:
Currently std::asinh and std::acosh use std::pow to compute x^2. This
results in a significant error when computing e.g. asinh(i) or
acosh(-1).

This patch expresses x^2 directly via x.real() and x.imag(), like it
is done in libstdc++/glibc, and adds tests that checks the accuracy.

Reviewers: EricWF, mclow.lists

Reviewed By: mclow.lists

Subscribers: christof, cfe-commits

Differential Revision: https://reviews.llvm.org/D41629

Added:
libcxx/trunk/test/libcxx/numerics/complex.number/__sqr.pass.cpp
Modified:
libcxx/trunk/include/complex

libcxx/trunk/test/std/numerics/complex.number/complex.transcendentals/acosh.pass.cpp

libcxx/trunk/test/std/numerics/complex.number/complex.transcendentals/asinh.pass.cpp

Modified: libcxx/trunk/include/complex
URL: 
http://llvm.org/viewvc/llvm-project/libcxx/trunk/include/complex?rev=325510=325509=325510=diff
==
--- libcxx/trunk/include/complex (original)
+++ libcxx/trunk/include/complex Mon Feb 19 07:41:36 2018
@@ -1125,6 +1125,17 @@ pow(const _Tp& __x, const complex<_Up>&
 return _VSTD::pow(result_type(__x), result_type(__y));
 }
 
+// __sqr, computes pow(x, 2)
+
+template
+inline _LIBCPP_INLINE_VISIBILITY
+complex<_Tp>
+__sqr(const complex<_Tp>& __x)
+{
+return complex<_Tp>((__x.real() - __x.imag()) * (__x.real() + __x.imag()),
+_Tp(2) * __x.real() * __x.imag());
+}
+
 // asinh
 
 template
@@ -1150,7 +1161,7 @@ asinh(const complex<_Tp>& __x)
 }
 if (__libcpp_isinf_or_builtin(__x.imag()))
 return complex<_Tp>(copysign(__x.imag(), __x.real()), 
copysign(__pi/_Tp(2), __x.imag()));
-complex<_Tp> __z = log(__x + sqrt(pow(__x, _Tp(2)) + _Tp(1)));
+complex<_Tp> __z = log(__x + sqrt(__sqr(__x) + _Tp(1)));
 return complex<_Tp>(copysign(__z.real(), __x.real()), copysign(__z.imag(), 
__x.imag()));
 }
 
@@ -1184,7 +1195,7 @@ acosh(const complex<_Tp>& __x)
 }
 if (__libcpp_isinf_or_builtin(__x.imag()))
 return complex<_Tp>(abs(__x.imag()), copysign(__pi/_Tp(2), 
__x.imag()));
-complex<_Tp> __z = log(__x + sqrt(pow(__x, _Tp(2)) - _Tp(1)));
+complex<_Tp> __z = log(__x + sqrt(__sqr(__x) - _Tp(1)));
 return complex<_Tp>(copysign(__z.real(), _Tp(0)), copysign(__z.imag(), 
__x.imag()));
 }
 
@@ -1318,7 +1329,7 @@ acos(const complex<_Tp>& __x)
 return complex<_Tp>(__pi/_Tp(2), -__x.imag());
 if (__x.real() == 0 && (__x.imag() == 0 || isnan(__x.imag(
 return complex<_Tp>(__pi/_Tp(2), -__x.imag());
-complex<_Tp> __z = log(__x + sqrt(pow(__x, _Tp(2)) - _Tp(1)));
+complex<_Tp> __z = log(__x + sqrt(__sqr(__x) - _Tp(1)));
 if (signbit(__x.imag()))
 return complex<_Tp>(abs(__z.imag()), abs(__z.real()));
 return complex<_Tp>(abs(__z.imag()), -abs(__z.real()));

Added: libcxx/trunk/test/libcxx/numerics/complex.number/__sqr.pass.cpp
URL: 
http://llvm.org/viewvc/llvm-project/libcxx/trunk/test/libcxx/numerics/complex.number/__sqr.pass.cpp?rev=325510=auto
==
--- libcxx/trunk/test/libcxx/numerics/complex.number/__sqr.pass.cpp (added)
+++ libcxx/trunk/test/libcxx/numerics/complex.number/__sqr.pass.cpp Mon Feb 19 
07:41:36 2018
@@ -0,0 +1,81 @@
+//===--===//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file is dual licensed under the MIT and the University of Illinois Open
+// Source Licenses. See LICENSE.TXT for details.
+//
+//===--===//
+
+// 
+
+// template
+//   complex
+//   __sqr(const complex& x);
+
+#include 
+#include 
+
+template 
+void
+test()
+{
+const T tolerance = std::is_same::value ? 1.e-6 : 1.e-14;
+
+typedef std::complex cplx;
+struct test_case
+{
+cplx value;
+cplx expected;
+};
+
+const test_case cases[] = {
+{cplx( 0,  0), cplx( 0,  0)},
+{cplx( 1,  0), cplx( 1,  0)},
+{cplx( 2,  0), cplx( 4,  0)},
+{cplx(-1,  0), cplx( 1,  0)},
+{cplx( 0,  1), cplx(-1,  0)},
+{cplx( 0,  2), cplx(-4,  0)},
+{cplx( 0, -1), cplx(-1,  0)},
+{cplx( 1,  1), cplx( 0,  2)},
+{cplx( 1, -1), cplx( 0, -2)},
+{cplx(-1, -1), cplx( 0,  2)},
+{cplx(0.5, 0), cplx(0.25, 0)},
+};
+
+const unsigned num_cases = sizeof(cases) / sizeof(test_case);
+for (unsigned i = 0; i < num_cases; ++i)
+{
+const test_case& test = cases[i];
+const std::complex actual = std::__sqr(test.value);
+assert(std::abs(actual.real() - test.expected.real()) < tolerance);
+assert(std::abs(actual.imag() - 

r325117 - [Sema] Fix decltype of static data members

[Mikhail Maltsev via cfe-commits]

Author: miyuki
Date: Wed Feb 14 03:34:25 2018
New Revision: 325117

URL: http://llvm.org/viewvc/llvm-project?rev=325117=rev
Log:
[Sema] Fix decltype of static data members

Summary:
According to the C++11 standard [dcl.type.simple]p4:
  The type denoted by decltype(e) is defined as follows:
  - if e is an unparenthesized id-expression or an unparenthesized
class member access (5.2.5), decltype(e) is the type of the entity
named by e.

Currently Clang handles the 'member access' case incorrectly for
static data members (decltype returns T& instead of T). This patch
fixes the issue.

Reviewers: faisalv, rsmith, rogfer01

Reviewed By: rogfer01

Subscribers: rogfer01, cfe-commits

Differential Revision: https://reviews.llvm.org/D42969

Modified:
cfe/trunk/lib/Sema/SemaType.cpp
cfe/trunk/test/CXX/dcl.dcl/dcl.spec/dcl.type/dcl.type.simple/p4-cxx0x.cpp

Modified: cfe/trunk/lib/Sema/SemaType.cpp
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Sema/SemaType.cpp?rev=325117=325116=325117=diff
==
--- cfe/trunk/lib/Sema/SemaType.cpp (original)
+++ cfe/trunk/lib/Sema/SemaType.cpp Wed Feb 14 03:34:25 2018
@@ -7868,8 +7868,9 @@ static QualType getDecltypeForExpr(Sema
 if (const ValueDecl *VD = dyn_cast(DRE->getDecl()))
   return VD->getType();
   } else if (const MemberExpr *ME = dyn_cast(E)) {
-if (const FieldDecl *FD = dyn_cast(ME->getMemberDecl()))
-  return FD->getType();
+if (const ValueDecl *VD = ME->getMemberDecl())
+  if (isa(VD) || isa(VD))
+return VD->getType();
   } else if (const ObjCIvarRefExpr *IR = dyn_cast(E)) {
 return IR->getDecl()->getType();
   } else if (const ObjCPropertyRefExpr *PR = dyn_cast(E)) 
{

Modified: 
cfe/trunk/test/CXX/dcl.dcl/dcl.spec/dcl.type/dcl.type.simple/p4-cxx0x.cpp
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CXX/dcl.dcl/dcl.spec/dcl.type/dcl.type.simple/p4-cxx0x.cpp?rev=325117=325116=325117=diff
==
--- cfe/trunk/test/CXX/dcl.dcl/dcl.spec/dcl.type/dcl.type.simple/p4-cxx0x.cpp 
(original)
+++ cfe/trunk/test/CXX/dcl.dcl/dcl.spec/dcl.type/dcl.type.simple/p4-cxx0x.cpp 
Wed Feb 14 03:34:25 2018
@@ -12,13 +12,18 @@ struct is_same {
 
 const int&& foo();
 int i;
-struct A { double x; };
+struct A {
+  double x;
+  static int y;
+};
 const A* a = new A();
 
 static_assert(is_same::value, "");
 static_assert(is_same::value, "");
 static_assert(is_samex), double>::value, "");
 static_assert(is_samex)), const double&>::value, "");
+static_assert(is_samey), int>::value, "");
+static_assert(is_samey)), int&>::value, "");
 static_assert(is_same(i)), int&&>::value, "");
 
 int f0(int); // expected-note{{possible target}}


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[libcxx] r324596 - [libcxx] Avoid spurious construction of valarray elements

[Mikhail Maltsev via cfe-commits]

Author: miyuki
Date: Thu Feb  8 03:33:48 2018
New Revision: 324596

URL: http://llvm.org/viewvc/llvm-project?rev=324596=rev
Log:
[libcxx] Avoid spurious construction of valarray elements

Summary:
Currently libc++ implements some operations on valarray by using the
resize method. This method has a parameter with a default value.
Because of this, valarray may spuriously construct and destruct
objects of valarray's element type.

This patch fixes this issue and adds corresponding test cases.


Reviewers: EricWF, mclow.lists

Reviewed By: mclow.lists

Subscribers: rogfer01, cfe-commits

Differential Revision: https://reviews.llvm.org/D41992

Modified:
libcxx/trunk/include/valarray

libcxx/trunk/test/std/numerics/numarray/template.valarray/valarray.assign/copy_assign.pass.cpp

libcxx/trunk/test/std/numerics/numarray/template.valarray/valarray.assign/initializer_list_assign.pass.cpp

libcxx/trunk/test/std/numerics/numarray/template.valarray/valarray.cons/default.pass.cpp

libcxx/trunk/test/std/numerics/numarray/template.valarray/valarray.cons/size.pass.cpp

Modified: libcxx/trunk/include/valarray
URL: 
http://llvm.org/viewvc/llvm-project/libcxx/trunk/include/valarray?rev=324596=324595=324596=diff
==
--- libcxx/trunk/include/valarray (original)
+++ libcxx/trunk/include/valarray Thu Feb  8 03:33:48 2018
@@ -1053,6 +1053,9 @@ private:
 friend
 const _Up*
 end(const valarray<_Up>& __v);
+
+void __clear();
+valarray& __assign_range(const value_type* __f, const value_type* __l);
 };
 
 _LIBCPP_EXTERN_TEMPLATE(_LIBCPP_FUNC_VIS valarray::valarray(size_t))
@@ -2750,7 +2753,24 @@ valarray<_Tp>::valarray(size_t __n)
 : __begin_(0),
   __end_(0)
 {
-resize(__n);
+if (__n)
+{
+__begin_ = __end_ = static_cast(_VSTD::__allocate(__n * 
sizeof(value_type)));
+#ifndef _LIBCPP_NO_EXCEPTIONS
+try
+{
+#endif  // _LIBCPP_NO_EXCEPTIONS
+for (; __n; --__n, ++__end_)
+::new (__end_) value_type();
+#ifndef _LIBCPP_NO_EXCEPTIONS
+}
+catch (...)
+{
+__clear();
+throw;
+}
+#endif  // _LIBCPP_NO_EXCEPTIONS
+}
 }
 
 template 
@@ -2780,7 +2800,7 @@ valarray<_Tp>::valarray(const value_type
 }
 catch (...)
 {
-resize(0);
+__clear();
 throw;
 }
 #endif  // _LIBCPP_NO_EXCEPTIONS
@@ -2805,7 +2825,7 @@ valarray<_Tp>::valarray(const valarray&
 }
 catch (...)
 {
-resize(0);
+__clear();
 throw;
 }
 #endif  // _LIBCPP_NO_EXCEPTIONS
@@ -2842,7 +2862,7 @@ valarray<_Tp>::valarray(initializer_list
 }
 catch (...)
 {
-resize(0);
+__clear();
 throw;
 }
 #endif  // _LIBCPP_NO_EXCEPTIONS
@@ -2870,7 +2890,7 @@ valarray<_Tp>::valarray(const slice_arra
 }
 catch (...)
 {
-resize(0);
+__clear();
 throw;
 }
 #endif  // _LIBCPP_NO_EXCEPTIONS
@@ -2899,7 +2919,7 @@ valarray<_Tp>::valarray(const gslice_arr
 }
 catch (...)
 {
-resize(0);
+__clear();
 throw;
 }
 #endif  // _LIBCPP_NO_EXCEPTIONS
@@ -2928,7 +2948,7 @@ valarray<_Tp>::valarray(const mask_array
 }
 catch (...)
 {
-resize(0);
+__clear();
 throw;
 }
 #endif  // _LIBCPP_NO_EXCEPTIONS
@@ -2957,7 +2977,7 @@ valarray<_Tp>::valarray(const indirect_a
 }
 catch (...)
 {
-resize(0);
+__clear();
 throw;
 }
 #endif  // _LIBCPP_NO_EXCEPTIONS
@@ -2968,22 +2988,35 @@ template 
 inline
 valarray<_Tp>::~valarray()
 {
-resize(0);
+__clear();
 }
 
 template 
 valarray<_Tp>&
-valarray<_Tp>::operator=(const valarray& __v)
+valarray<_Tp>::__assign_range(const value_type* __f, const value_type* __l)
 {
-if (this != &__v)
+size_t __n = __l - __f;
+if (size() != __n)
 {
-if (size() != __v.size())
-resize(__v.size());
-_VSTD::copy(__v.__begin_, __v.__end_, __begin_);
+__clear();
+__begin_ = static_cast(_VSTD::__allocate(__n * 
sizeof(value_type)));
+__end_ = __begin_ + __n;
+_VSTD::uninitialized_copy(__f, __l, __begin_);
+} else {
+_VSTD::copy(__f, __l, __begin_);
 }
 return *this;
 }
 
+template 
+valarray<_Tp>&
+valarray<_Tp>::operator=(const valarray& __v)
+{
+if (this != &__v)
+return __assign_range(__v.__begin_, __v.__end_);
+return *this;
+}
+
 #ifndef _LIBCPP_CXX03_LANG
 
 template 
@@ -2991,7 +3024,7 @@ inline
 valarray<_Tp>&
 valarray<_Tp>::operator=(valarray&& __v) _NOEXCEPT
 {
-resize(0);
+__clear();
 __begin_ = __v.__begin_;
 __end_ = __v.__end_;
   

[libcxx] r323322 - [libcxx] Correctly handle invalid regex character class names

[Mikhail Maltsev via cfe-commits]

Author: miyuki
Date: Wed Jan 24 04:45:18 2018
New Revision: 323322

URL: http://llvm.org/viewvc/llvm-project?rev=323322=rev
Log:
[libcxx] Correctly handle invalid regex character class names

Summary:
Currently when a regular expression contains an invalid character
class name std::regex constructors throw an std::regex_error with
std::regex_constants::error_brack code.

This patch changes the code to std::regex_constants::error_ctype and
adds a test.

Reviewers: EricWF, mclow.lists

Reviewed By: mclow.lists

Subscribers: cfe-commits

Differential Revision: https://reviews.llvm.org/D42291

Added:
libcxx/trunk/test/std/re/re.regex/re.regex.construct/bad_ctype.pass.cpp
Modified:
libcxx/trunk/include/regex

Modified: libcxx/trunk/include/regex
URL: 
http://llvm.org/viewvc/llvm-project/libcxx/trunk/include/regex?rev=323322=323321=323322=diff
==
--- libcxx/trunk/include/regex (original)
+++ libcxx/trunk/include/regex Wed Jan 24 04:45:18 2018
@@ -4013,7 +4013,7 @@ basic_regex<_CharT, _Traits>::__parse_ch
 char_class_type __class_type =
 __traits_.lookup_classname(__first, __temp, __flags_ & icase);
 if (__class_type == 0)
-__throw_regex_error();
+__throw_regex_error();
 __ml->__add_class(__class_type);
 __first = _VSTD::next(__temp, 2);
 return __first;

Added: libcxx/trunk/test/std/re/re.regex/re.regex.construct/bad_ctype.pass.cpp
URL: 
http://llvm.org/viewvc/llvm-project/libcxx/trunk/test/std/re/re.regex/re.regex.construct/bad_ctype.pass.cpp?rev=323322=auto
==
--- libcxx/trunk/test/std/re/re.regex/re.regex.construct/bad_ctype.pass.cpp 
(added)
+++ libcxx/trunk/test/std/re/re.regex/re.regex.construct/bad_ctype.pass.cpp Wed 
Jan 24 04:45:18 2018
@@ -0,0 +1,37 @@
+//===--===//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file is dual licensed under the MIT and the University of Illinois Open
+// Source Licenses. See LICENSE.TXT for details.
+//
+//===--===//
+
+// UNSUPPORTED: libcpp-no-exceptions
+// 
+
+// template > class 
basic_regex;
+
+// template 
+//basic_regex(const basic_string& s);
+
+#include 
+#include 
+#include "test_macros.h"
+
+static bool error_ctype_thrown(const char *pat)
+{
+bool result = false;
+try {
+std::regex re(pat);
+} catch (const std::regex_error ) {
+result = (ex.code() == std::regex_constants::error_ctype);
+}
+return result;
+}
+
+int main()
+{
+assert(error_ctype_thrown("[[::]]"));
+assert(error_ctype_thrown("[[:error:]]"));
+}


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