[clang] [FMV][AArch64] Don't optimize backward compatible features in resolver. (PR #90928)
lenary wrote: Is this check even right for MTE? FEAT_MTE uses encodings that are undefined (rather than nop-compatible) in the base architecture, even though those encodings are not doing tag checking until you enable at least FEAT_MTE2 - so I cannot execute e.g. `IRG` on a base armv8.0a architecture. https://github.com/llvm/llvm-project/pull/90928 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[llvm] [flang] [clang] [NFC][AMDGPU] Move address space enum to LLVM directory (PR #73944)
lenary wrote: The reason TargetParser exists is because Target directories are only added to the include path if you enable that target, but some cross-project target code needs to always be available, such as the code for Triples, even when the relevant targets are disabled. I think these address space constants have the same needs, so this location makes sense to me, but I could be wrong. It is strange that the AMDGPU stuff is in the file called TargetParser.h, but that's because I wasn't able to move that code around when I originally split out TargetParser. Now might be a good time to put it in its own header, like was done for all other targets. https://github.com/llvm/llvm-project/pull/73944 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[libunwind] ce3d1c6 - [libunwind][RISCV] Add 64-bit RISC-V support
Author: Sam Elliott
Date: 2019-12-16T16:36:56Z
New Revision: ce3d1c6d61dcd96f44492516f8b613bbcadaeb8e
URL:
https://github.com/llvm/llvm-project/commit/ce3d1c6d61dcd96f44492516f8b613bbcadaeb8e
DIFF:
https://github.com/llvm/llvm-project/commit/ce3d1c6d61dcd96f44492516f8b613bbcadaeb8e.diff
LOG: [libunwind][RISCV] Add 64-bit RISC-V support
Summary:
Add unwinding support for 64-bit RISC-V.
This is from the FreeBSD implementation with the following minor
changes:
- Renamed and renumbered DWARF registers to match the RISC-V ABI [1]
- Use the ABI mneumonics in getRegisterName() instead of the exact
register names
- Include checks for __riscv_xlen == 64 to facilitate adding the 32-bit
ABI in the future.
[1] https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md
Patch by Mitchell Horne (mhorne)
Reviewers: lenary, luismarques, compnerd, phosek
Reviewed By: lenary, luismarques
Subscribers: arichardson, sameer.abuasal, abidh, asb, aprantl, krytarowski,
simoncook, kito-cheng, christof, shiva0217, rogfer01, rkruppe, PkmX, psnobl,
benna, lenary, s.egerton, luismarques, emaste, cfe-commits
Differential Revision: https://reviews.llvm.org/D68362
Added:
Modified:
libunwind/include/__libunwind_config.h
libunwind/include/libunwind.h
libunwind/src/Registers.hpp
libunwind/src/UnwindCursor.hpp
libunwind/src/UnwindRegistersRestore.S
libunwind/src/UnwindRegistersSave.S
libunwind/src/config.h
libunwind/src/libunwind.cpp
Removed:
diff --git a/libunwind/include/__libunwind_config.h
b/libunwind/include/__libunwind_config.h
index 6e7e5e6f7f86..4d03bd83d8c6 100644
--- a/libunwind/include/__libunwind_config.h
+++ b/libunwind/include/__libunwind_config.h
@@ -23,6 +23,7 @@
#define _LIBUNWIND_HIGHEST_DWARF_REGISTER_OR1K 32
#define _LIBUNWIND_HIGHEST_DWARF_REGISTER_MIPS 65
#define _LIBUNWIND_HIGHEST_DWARF_REGISTER_SPARC 31
+#define _LIBUNWIND_HIGHEST_DWARF_REGISTER_RISCV 64
#if defined(_LIBUNWIND_IS_NATIVE_ONLY)
# if defined(__i386__)
@@ -118,6 +119,15 @@
#define _LIBUNWIND_HIGHEST_DWARF_REGISTER
_LIBUNWIND_HIGHEST_DWARF_REGISTER_SPARC
#define _LIBUNWIND_CONTEXT_SIZE 16
#define _LIBUNWIND_CURSOR_SIZE 23
+# elif defined(__riscv)
+# if __riscv_xlen == 64
+#define _LIBUNWIND_TARGET_RISCV 1
+#define _LIBUNWIND_CONTEXT_SIZE 64
+#define _LIBUNWIND_CURSOR_SIZE 76
+# else
+#error "Unsupported RISC-V ABI"
+# endif
+# define _LIBUNWIND_HIGHEST_DWARF_REGISTER
_LIBUNWIND_HIGHEST_DWARF_REGISTER_RISCV
# else
# error "Unsupported architecture."
# endif
@@ -132,6 +142,7 @@
# define _LIBUNWIND_TARGET_MIPS_O32 1
# define _LIBUNWIND_TARGET_MIPS_NEWABI 1
# define _LIBUNWIND_TARGET_SPARC 1
+# define _LIBUNWIND_TARGET_RISCV 1
# define _LIBUNWIND_CONTEXT_SIZE 167
# define _LIBUNWIND_CURSOR_SIZE 179
# define _LIBUNWIND_HIGHEST_DWARF_REGISTER 287
diff --git a/libunwind/include/libunwind.h b/libunwind/include/libunwind.h
index d06724d3c31f..1a501b867dda 100644
--- a/libunwind/include/libunwind.h
+++ b/libunwind/include/libunwind.h
@@ -832,4 +832,75 @@ enum {
UNW_SPARC_I7 = 31,
};
+// RISC-V registers. These match the DWARF register numbers defined by section
+// 4 of the RISC-V ELF psABI specification, which can be found at:
+//
+// https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md
+enum {
+ UNW_RISCV_X0 = 0,
+ UNW_RISCV_X1 = 1,
+ UNW_RISCV_X2 = 2,
+ UNW_RISCV_X3 = 3,
+ UNW_RISCV_X4 = 4,
+ UNW_RISCV_X5 = 5,
+ UNW_RISCV_X6 = 6,
+ UNW_RISCV_X7 = 7,
+ UNW_RISCV_X8 = 8,
+ UNW_RISCV_X9 = 9,
+ UNW_RISCV_X10 = 10,
+ UNW_RISCV_X11 = 11,
+ UNW_RISCV_X12 = 12,
+ UNW_RISCV_X13 = 13,
+ UNW_RISCV_X14 = 14,
+ UNW_RISCV_X15 = 15,
+ UNW_RISCV_X16 = 16,
+ UNW_RISCV_X17 = 17,
+ UNW_RISCV_X18 = 18,
+ UNW_RISCV_X19 = 19,
+ UNW_RISCV_X20 = 20,
+ UNW_RISCV_X21 = 21,
+ UNW_RISCV_X22 = 22,
+ UNW_RISCV_X23 = 23,
+ UNW_RISCV_X24 = 24,
+ UNW_RISCV_X25 = 25,
+ UNW_RISCV_X26 = 26,
+ UNW_RISCV_X27 = 27,
+ UNW_RISCV_X28 = 28,
+ UNW_RISCV_X29 = 29,
+ UNW_RISCV_X30 = 30,
+ UNW_RISCV_X31 = 31,
+ UNW_RISCV_F0 = 32,
+ UNW_RISCV_F1 = 33,
+ UNW_RISCV_F2 = 34,
+ UNW_RISCV_F3 = 35,
+ UNW_RISCV_F4 = 36,
+ UNW_RISCV_F5 = 37,
+ UNW_RISCV_F6 = 38,
+ UNW_RISCV_F7 = 39,
+ UNW_RISCV_F8 = 40,
+ UNW_RISCV_F9 = 41,
+ UNW_RISCV_F10 = 42,
+ UNW_RISCV_F11 = 43,
+ UNW_RISCV_F12 = 44,
+ UNW_RISCV_F13 = 45,
+ UNW_RISCV_F14 = 46,
+ UNW_RISCV_F15 = 47,
+ UNW_RISCV_F16 = 48,
+ UNW_RISCV_F17 = 49,
+ UNW_RISCV_F18 = 50,
+ UNW_RISCV_F19 = 51,
+ UNW_RISCV_F20 = 52,
+ UNW_RISCV_F21 = 53,
+ UNW_RISCV_F22 = 54,
+ UNW_RISCV_F23 = 55,
+ UNW_RISCV_F24 = 56,
+ UNW_RISCV_F25 = 57,
+ UNW_RISCV_F26 = 58,
+ UNW_RISCV_F27 = 59,
+ UNW_RISCV_F28 = 60,
+ UNW_RISCV_F29 = 61,
+ UNW_RISCV_F30 = 62,
+ UNW_RISCV_F31 = 63,
+};
+
#endif
diff --git a/libunwind/src/Registers.hpp b/libunwind/src/Registers.hpp
[clang] e3d5ff5 - [RISCV] Match GCC `-march`/`-mabi` driver defaults
Author: Sam Elliott
Date: 2019-11-15T15:10:42Z
New Revision: e3d5ff5a0b102febcddd9d58f24f18b00d4ecb4e
URL:
https://github.com/llvm/llvm-project/commit/e3d5ff5a0b102febcddd9d58f24f18b00d4ecb4e
DIFF:
https://github.com/llvm/llvm-project/commit/e3d5ff5a0b102febcddd9d58f24f18b00d4ecb4e.diff
LOG: [RISCV] Match GCC `-march`/`-mabi` driver defaults
Summary:
Clang/LLVM is a cross-compiler, and so we don't have to make a choice
about `-march`/`-mabi` at build-time, but we may have to compute a
default `-march`/`-mabi` when compiling a program. Until now, each
place that has needed a default `-march` has calculated one itself.
This patch adds a single place where a default `-march` is calculated,
in order to avoid calculating different defaults in different places.
This patch adds a new function `riscv::getRISCVArch` which encapsulates
this logic based on GCC's for computing a default `-march` value
when none is provided. This patch also updates the logic in
`riscv::getRISCVABI` to match the logic in GCC's build system for
computing a default `-mabi`.
This patch also updates anywhere that `-march` is used to now use the
new function which can compute a default. In particular, we now
explicitly pass a `-march` value down to the gnu assembler.
GCC has convoluted logic in its build system to choose a default
`-march`/`-mabi` based on build options, which would be good to match.
This patch is based on the logic in GCC 9.2.0. This commit's logic is
different to GCC's only for baremetal targets, where we default
to rv32imac/ilp32 or rv64imac/lp64 depending on the target triple.
Tests have been updated to match the new logic.
Reviewers: asb, luismarques, rogfer01, kito-cheng, khchen
Reviewed By: asb, luismarques
Subscribers: sameer.abuasal, rbar, johnrusso, simoncook, apazos, sabuasal,
niosHD, shiva0217, jrtc27, MaskRay, zzheng, edward-jones, MartinMosbeck,
brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, Jim, s.egerton,
pzheng, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D69383
Added:
Modified:
clang/docs/ReleaseNotes.rst
clang/lib/Driver/ToolChains/Arch/RISCV.cpp
clang/lib/Driver/ToolChains/Arch/RISCV.h
clang/lib/Driver/ToolChains/Gnu.cpp
clang/test/Driver/riscv-abi.c
clang/test/Driver/riscv-gnutools.c
Removed:
diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst
index 1139116ed101..aa0d88db1c9f 100644
--- a/clang/docs/ReleaseNotes.rst
+++ b/clang/docs/ReleaseNotes.rst
@@ -223,6 +223,15 @@ ABI Changes in Clang
element. Clang now matches the gcc behavior on Linux and NetBSD. You can
switch back to old API behavior with flag: -fclang-abi-compat=9.0.
+- RISC-V now chooses a default ``-march=`` and ``-mabi=`` to match (in almost
+ all cases) the GCC defaults. On baremetal targets, where neither ``-march=``
+ nor ``-mabi=`` are specified, Clang now
diff ers from GCC by defaulting to
+ ``-march=rv32imac -mabi=ilp32`` or ``-march=rv64imac -mabi=lp64`` depending
on
+ the architecture in the target triple. These do not always match the defaults
+ in Clang 9. We strongly suggest that you explicitly pass `-march=` and
+ `-mabi=` when compiling for RISC-V, due to how extensible this architecture
+ is.
+
OpenMP Support in Clang
---
diff --git a/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
b/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
index a26f723a5073..8c343b8693f3 100644
--- a/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
+++ b/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
@@ -357,14 +357,9 @@ static bool getArchFeatures(const Driver , StringRef
MArch,
void riscv::getRISCVTargetFeatures(const Driver , const llvm::Triple ,
const ArgList ,
std::vector ) {
- llvm::Optional MArch;
- if (const Arg *A = Args.getLastArg(options::OPT_march_EQ))
-MArch = A->getValue();
- else if (Triple.getOS() == llvm::Triple::Linux)
-// RISC-V Linux defaults to rv{32,64}gc.
-MArch = Triple.getArch() == llvm::Triple::riscv32 ? "rv32gc" : "rv64gc";
+ StringRef MArch = getRISCVArch(Args, Triple);
- if (MArch.hasValue() && !getArchFeatures(D, *MArch, Features, Args))
+ if (!getArchFeatures(D, MArch, Features, Args))
return;
// Handle features corresponding to "-ffixed-X" options
@@ -455,12 +450,132 @@ StringRef riscv::getRISCVABI(const ArgList , const
llvm::Triple ) {
Triple.getArch() == llvm::Triple::riscv64) &&
"Unexpected triple");
+ // GCC's logic around choosing a default `-mabi=` is complex. If GCC is not
+ // configured using `--with-abi=`, then the logic for the default choice is
+ // defined in config.gcc. This function is based on the logic in GCC 9.2.0.
We
+ // deviate from GCC's default only on baremetal targets (UnknownOS) where
+ // neither `-march` nor `-mabi` is specified.
+ //
+
r374774 - [RISCV] enable LTO support, pass some options to linker.
Author: lenary
Date: Mon Oct 14 07:00:13 2019
New Revision: 374774
URL: http://llvm.org/viewvc/llvm-project?rev=374774=rev
Log:
[RISCV] enable LTO support, pass some options to linker.
Summary:
1. enable LTO need to pass target feature and abi to LTO code generation
RISCV backend need the target feature to decide which extension used in
code generation.
2. move getTargetFeatures to CommonArgs.h and add ForLTOPlugin flag
3. add general tools::getTargetABI in CommonArgs.h because different target
uses different
way to get the target ABI.
Patch by Kuan Hsu Chen (khchen)
Reviewers: lenary, lewis-revill, asb, MaskRay
Reviewed By: lenary
Subscribers: hiraditya, dschuff, aheejin, fedor.sergeev, mehdi_amini,
inglorion, asb, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD,
kito-cheng, shiva0217, jrtc27, MaskRay, zzheng, edward-jones, steven_wu,
rogfer01, MartinMosbeck, brucehoult, the_o, dexonsmith, rkruppe, PkmX, jocewei,
psnobl, benna, Jim, lenary, s.egerton, pzheng, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D67409
Modified:
cfe/trunk/lib/Driver/ToolChains/Clang.cpp
cfe/trunk/lib/Driver/ToolChains/CommonArgs.cpp
cfe/trunk/lib/Driver/ToolChains/CommonArgs.h
cfe/trunk/lib/Driver/ToolChains/RISCVToolchain.cpp
cfe/trunk/lib/Driver/ToolChains/RISCVToolchain.h
cfe/trunk/test/Driver/gold-lto.c
Modified: cfe/trunk/lib/Driver/ToolChains/Clang.cpp
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Driver/ToolChains/Clang.cpp?rev=374774=374773=374774=diff
==
--- cfe/trunk/lib/Driver/ToolChains/Clang.cpp (original)
+++ cfe/trunk/lib/Driver/ToolChains/Clang.cpp Mon Oct 14 07:00:13 2019
@@ -302,95 +302,6 @@ static void ParseMPreferVectorWidth(cons
}
}
-static void getWebAssemblyTargetFeatures(const ArgList ,
- std::vector ) {
- handleTargetFeaturesGroup(Args, Features,
options::OPT_m_wasm_Features_Group);
-}
-
-static void getTargetFeatures(const ToolChain , const llvm::Triple ,
- const ArgList , ArgStringList ,
- bool ForAS) {
- const Driver = TC.getDriver();
- std::vector Features;
- switch (Triple.getArch()) {
- default:
-break;
- case llvm::Triple::mips:
- case llvm::Triple::mipsel:
- case llvm::Triple::mips64:
- case llvm::Triple::mips64el:
-mips::getMIPSTargetFeatures(D, Triple, Args, Features);
-break;
-
- case llvm::Triple::arm:
- case llvm::Triple::armeb:
- case llvm::Triple::thumb:
- case llvm::Triple::thumbeb:
-arm::getARMTargetFeatures(TC, Triple, Args, CmdArgs, Features, ForAS);
-break;
-
- case llvm::Triple::ppc:
- case llvm::Triple::ppc64:
- case llvm::Triple::ppc64le:
-ppc::getPPCTargetFeatures(D, Triple, Args, Features);
-break;
- case llvm::Triple::riscv32:
- case llvm::Triple::riscv64:
-riscv::getRISCVTargetFeatures(D, Triple, Args, Features);
-break;
- case llvm::Triple::systemz:
-systemz::getSystemZTargetFeatures(Args, Features);
-break;
- case llvm::Triple::aarch64:
- case llvm::Triple::aarch64_be:
-aarch64::getAArch64TargetFeatures(D, Triple, Args, Features);
-break;
- case llvm::Triple::x86:
- case llvm::Triple::x86_64:
-x86::getX86TargetFeatures(D, Triple, Args, Features);
-break;
- case llvm::Triple::hexagon:
-hexagon::getHexagonTargetFeatures(D, Args, Features);
-break;
- case llvm::Triple::wasm32:
- case llvm::Triple::wasm64:
-getWebAssemblyTargetFeatures(Args, Features);
-break;
- case llvm::Triple::sparc:
- case llvm::Triple::sparcel:
- case llvm::Triple::sparcv9:
-sparc::getSparcTargetFeatures(D, Args, Features);
-break;
- case llvm::Triple::r600:
- case llvm::Triple::amdgcn:
-amdgpu::getAMDGPUTargetFeatures(D, Args, Features);
-break;
- case llvm::Triple::msp430:
-msp430::getMSP430TargetFeatures(D, Args, Features);
- }
-
- // Find the last of each feature.
- llvm::StringMap LastOpt;
- for (unsigned I = 0, N = Features.size(); I < N; ++I) {
-StringRef Name = Features[I];
-assert(Name[0] == '-' || Name[0] == '+');
-LastOpt[Name.drop_front(1)] = I;
- }
-
- for (unsigned I = 0, N = Features.size(); I < N; ++I) {
-// If this feature was overridden, ignore it.
-StringRef Name = Features[I];
-llvm::StringMap::iterator LastI =
LastOpt.find(Name.drop_front(1));
-assert(LastI != LastOpt.end());
-unsigned Last = LastI->second;
-if (Last != I)
- continue;
-
-CmdArgs.push_back("-target-feature");
-CmdArgs.push_back(Name.data());
- }
-}
-
static bool
shouldUseExceptionTablesForObjCExceptions(const ObjCRuntime ,
const llvm::Triple ) {
Modified: cfe/trunk/lib/Driver/ToolChains/CommonArgs.cpp
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Driver/ToolChains/CommonArgs.cpp?rev=374774=374773=374774=diff
r370709 - [RISCV] Correct Logic around ilp32e macros
Author: lenary
Date: Tue Sep 3 01:47:58 2019
New Revision: 370709
URL: http://llvm.org/viewvc/llvm-project?rev=370709=rev
Log:
[RISCV] Correct Logic around ilp32e macros
Summary:
GCC seperates the `__riscv_float_abi_*` macros and the
`__riscv_abi_rve` macro. If the chosen abi is ilp32e, `gcc -march=rv32i
-mabi=ilp32i -E -dM` shows that both `__riscv_float_abi_soft` and
`__riscv_abi_rve` are set.
This patch corrects the compiler logic around these defines.
At the moment, this patch will not change clang's behaviour, because we do not
accept the `ilp32e` abi yet.
Reviewers: luismarques, asb
Reviewed By: luismarques
Subscribers: rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng,
shiva0217, jrtc27, MaskRay, zzheng, edward-jones, rogfer01, MartinMosbeck,
brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, Jim, s.egerton,
pzheng, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D66591
Modified:
cfe/trunk/lib/Basic/Targets/RISCV.cpp
Modified: cfe/trunk/lib/Basic/Targets/RISCV.cpp
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Basic/Targets/RISCV.cpp?rev=370709=370708=370709=diff
==
--- cfe/trunk/lib/Basic/Targets/RISCV.cpp (original)
+++ cfe/trunk/lib/Basic/Targets/RISCV.cpp Tue Sep 3 01:47:58 2019
@@ -96,11 +96,12 @@ void RISCVTargetInfo::getTargetDefines(c
Builder.defineMacro("__riscv_float_abi_single");
else if (ABIName == "ilp32d" || ABIName == "lp64d")
Builder.defineMacro("__riscv_float_abi_double");
- else if (ABIName == "ilp32e")
-Builder.defineMacro("__riscv_abi_rve");
else
Builder.defineMacro("__riscv_float_abi_soft");
+ if (ABIName == "ilp32e")
+Builder.defineMacro("__riscv_abi_rve");
+
if (HasM) {
Builder.defineMacro("__riscv_mul");
Builder.defineMacro("__riscv_div");
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
r370073 - [RISCV] Set MaxAtomicInlineWidth and MaxAtomicPromoteWidth for RV32/RV64 targets with atomics
Author: lenary
Date: Tue Aug 27 08:41:16 2019
New Revision: 370073
URL: http://llvm.org/viewvc/llvm-project?rev=370073=rev
Log:
[RISCV] Set MaxAtomicInlineWidth and MaxAtomicPromoteWidth for RV32/RV64
targets with atomics
Summary: This ensures that libcalls aren't generated when the target supports
atomics. Atomics aren't in the base RV32I/RV64I instruction sets, so
MaxAtomicInlineWidth and MaxAtomicPromoteWidth are set only when the atomics
extension is being targeted. This must be done in setMaxAtomicWidth, as this
should be done after handleTargetFeatures has been called.
Reviewers: jfb, jyknight, wmi, asb
Reviewed By: asb
Subscribers: pzheng, MaskRay, s.egerton, lenary, dexonsmith, psnobl, benna,
Jim, JohnLLVM, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD,
kito-cheng, shiva0217, jrtc27, zzheng, edward-jones, rogfer01, MartinMosbeck,
brucehoult, the_o, rkruppe, PkmX, jocewei, lewis-revill, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D57450
Added:
cfe/trunk/test/CodeGen/riscv-atomics.c
Modified:
cfe/trunk/lib/Basic/Targets/RISCV.h
cfe/trunk/test/Driver/riscv32-toolchain.c
cfe/trunk/test/Driver/riscv64-toolchain.c
Modified: cfe/trunk/lib/Basic/Targets/RISCV.h
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Basic/Targets/RISCV.h?rev=370073=370072=370073=diff
==
--- cfe/trunk/lib/Basic/Targets/RISCV.h (original)
+++ cfe/trunk/lib/Basic/Targets/RISCV.h Tue Aug 27 08:41:16 2019
@@ -93,6 +93,13 @@ public:
}
return false;
}
+
+ void setMaxAtomicWidth() override {
+MaxAtomicPromoteWidth = 128;
+
+if (HasA)
+ MaxAtomicInlineWidth = 32;
+ }
};
class LLVM_LIBRARY_VISIBILITY RISCV64TargetInfo : public RISCVTargetInfo {
public:
@@ -110,6 +117,13 @@ public:
}
return false;
}
+
+ void setMaxAtomicWidth() override {
+MaxAtomicPromoteWidth = 128;
+
+if (HasA)
+ MaxAtomicInlineWidth = 64;
+ }
};
} // namespace targets
} // namespace clang
Added: cfe/trunk/test/CodeGen/riscv-atomics.c
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGen/riscv-atomics.c?rev=370073=auto
==
--- cfe/trunk/test/CodeGen/riscv-atomics.c (added)
+++ cfe/trunk/test/CodeGen/riscv-atomics.c Tue Aug 27 08:41:16 2019
@@ -0,0 +1,68 @@
+// RUN: %clang_cc1 -triple riscv32 -O1 -emit-llvm %s -o - \
+// RUN: | FileCheck %s -check-prefix=RV32I
+// RUN: %clang_cc1 -triple riscv32 -target-feature +a -O1 -emit-llvm %s -o - \
+// RUN: | FileCheck %s -check-prefix=RV32IA
+// RUN: %clang_cc1 -triple riscv64 -O1 -emit-llvm %s -o - \
+// RUN: | FileCheck %s -check-prefix=RV64I
+// RUN: %clang_cc1 -triple riscv64 -target-feature +a -O1 -emit-llvm %s -o - \
+// RUN: | FileCheck %s -check-prefix=RV64IA
+
+// This test demonstrates that MaxAtomicInlineWidth is set appropriately when
+// the atomics instruction set extension is enabled.
+
+#include
+#include
+
+void test_i8_atomics(_Atomic(int8_t) * a, int8_t b) {
+ // RV32I: call zeroext i8 @__atomic_load_1
+ // RV32I: call void @__atomic_store_1
+ // RV32I: call zeroext i8 @__atomic_fetch_add_1
+ // RV32IA: load atomic i8, i8* %a seq_cst, align 1
+ // RV32IA: store atomic i8 %b, i8* %a seq_cst, align 1
+ // RV32IA: atomicrmw add i8* %a, i8 %b seq_cst
+ // RV64I: call zeroext i8 @__atomic_load_1
+ // RV64I: call void @__atomic_store_1
+ // RV64I: call zeroext i8 @__atomic_fetch_add_1
+ // RV64IA: load atomic i8, i8* %a seq_cst, align 1
+ // RV64IA: store atomic i8 %b, i8* %a seq_cst, align 1
+ // RV64IA: atomicrmw add i8* %a, i8 %b seq_cst
+ __c11_atomic_load(a, memory_order_seq_cst);
+ __c11_atomic_store(a, b, memory_order_seq_cst);
+ __c11_atomic_fetch_add(a, b, memory_order_seq_cst);
+}
+
+void test_i32_atomics(_Atomic(int32_t) * a, int32_t b) {
+ // RV32I: call i32 @__atomic_load_4
+ // RV32I: call void @__atomic_store_4
+ // RV32I: call i32 @__atomic_fetch_add_4
+ // RV32IA: load atomic i32, i32* %a seq_cst, align 4
+ // RV32IA: store atomic i32 %b, i32* %a seq_cst, align 4
+ // RV32IA: atomicrmw add i32* %a, i32 %b seq_cst
+ // RV64I: call signext i32 @__atomic_load_4
+ // RV64I: call void @__atomic_store_4
+ // RV64I: call signext i32 @__atomic_fetch_add_4
+ // RV64IA: load atomic i32, i32* %a seq_cst, align 4
+ // RV64IA: store atomic i32 %b, i32* %a seq_cst, align 4
+ // RV64IA: atomicrmw add i32* %a, i32 %b seq_cst
+ __c11_atomic_load(a, memory_order_seq_cst);
+ __c11_atomic_store(a, b, memory_order_seq_cst);
+ __c11_atomic_fetch_add(a, b, memory_order_seq_cst);
+}
+
+void test_i64_atomics(_Atomic(int64_t) * a, int64_t b) {
+ // RV32I: call i64 @__atomic_load_8
+ // RV32I: call void @__atomic_store_8
+ // RV32I: call i64 @__atomic_fetch_add_8
+ // RV32IA: call i64 @__atomic_load_8
+ // RV32IA: call void @__atomic_store_8
+ // RV32IA: call i64
r367565 - Add support for openSUSE RISC-V triple
Author: lenary
Date: Thu Aug 1 07:23:56 2019
New Revision: 367565
URL: http://llvm.org/viewvc/llvm-project?rev=367565=rev
Log:
Add support for openSUSE RISC-V triple
Reviewers: asb
Reviewed By: asb
Subscribers: lenary, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD,
jrtc27, zzheng, edward-jones, MartinMosbeck, brucehoult, the_o, PkmX, jocewei,
lebedev.ri, kito-cheng, shiva0217, rogfer01, dexonsmith, rkruppe, cfe-commits,
llvm-commits
Tags: #clang, #llvm
Differential Revision: https://reviews.llvm.org/D63497
Patch by Andreas Schwab (schwab)
Added:
cfe/trunk/test/Driver/Inputs/opensuse_tumbleweed_riscv64_tree/
cfe/trunk/test/Driver/Inputs/opensuse_tumbleweed_riscv64_tree/usr/
cfe/trunk/test/Driver/Inputs/opensuse_tumbleweed_riscv64_tree/usr/lib64/
cfe/trunk/test/Driver/Inputs/opensuse_tumbleweed_riscv64_tree/usr/lib64/crt1.o
cfe/trunk/test/Driver/Inputs/opensuse_tumbleweed_riscv64_tree/usr/lib64/crti.o
cfe/trunk/test/Driver/Inputs/opensuse_tumbleweed_riscv64_tree/usr/lib64/crtn.o
cfe/trunk/test/Driver/Inputs/opensuse_tumbleweed_riscv64_tree/usr/lib64/gcc/
cfe/trunk/test/Driver/Inputs/opensuse_tumbleweed_riscv64_tree/usr/lib64/gcc/riscv64-suse-linux/
cfe/trunk/test/Driver/Inputs/opensuse_tumbleweed_riscv64_tree/usr/lib64/gcc/riscv64-suse-linux/9/
cfe/trunk/test/Driver/Inputs/opensuse_tumbleweed_riscv64_tree/usr/lib64/gcc/riscv64-suse-linux/9/crtbegin.o
cfe/trunk/test/Driver/Inputs/opensuse_tumbleweed_riscv64_tree/usr/lib64/gcc/riscv64-suse-linux/9/crtend.o
Modified:
cfe/trunk/lib/Driver/ToolChains/Gnu.cpp
cfe/trunk/test/Driver/linux-ld.c
Modified: cfe/trunk/lib/Driver/ToolChains/Gnu.cpp
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Driver/ToolChains/Gnu.cpp?rev=367565=367564=367565=diff
==
--- cfe/trunk/lib/Driver/ToolChains/Gnu.cpp (original)
+++ cfe/trunk/lib/Driver/ToolChains/Gnu.cpp Thu Aug 1 07:23:56 2019
@@ -2017,7 +2017,8 @@ void Generic_GCC::GCCInstallationDetecto
static const char *const RISCV64LibDirs[] = {"/lib64", "/lib"};
static const char *const RISCV64Triples[] = {"riscv64-unknown-linux-gnu",
"riscv64-linux-gnu",
- "riscv64-unknown-elf"};
+ "riscv64-unknown-elf",
+ "riscv64-suse-linux"};
static const char *const SPARCv8LibDirs[] = {"/lib32", "/lib"};
static const char *const SPARCv8Triples[] = {"sparc-linux-gnu",
Added:
cfe/trunk/test/Driver/Inputs/opensuse_tumbleweed_riscv64_tree/usr/lib64/crt1.o
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/Driver/Inputs/opensuse_tumbleweed_riscv64_tree/usr/lib64/crt1.o?rev=367565=auto
==
(empty)
Added:
cfe/trunk/test/Driver/Inputs/opensuse_tumbleweed_riscv64_tree/usr/lib64/crti.o
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/Driver/Inputs/opensuse_tumbleweed_riscv64_tree/usr/lib64/crti.o?rev=367565=auto
==
(empty)
Added:
cfe/trunk/test/Driver/Inputs/opensuse_tumbleweed_riscv64_tree/usr/lib64/crtn.o
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/Driver/Inputs/opensuse_tumbleweed_riscv64_tree/usr/lib64/crtn.o?rev=367565=auto
==
(empty)
Added:
cfe/trunk/test/Driver/Inputs/opensuse_tumbleweed_riscv64_tree/usr/lib64/gcc/riscv64-suse-linux/9/crtbegin.o
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/Driver/Inputs/opensuse_tumbleweed_riscv64_tree/usr/lib64/gcc/riscv64-suse-linux/9/crtbegin.o?rev=367565=auto
==
(empty)
Added:
cfe/trunk/test/Driver/Inputs/opensuse_tumbleweed_riscv64_tree/usr/lib64/gcc/riscv64-suse-linux/9/crtend.o
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/Driver/Inputs/opensuse_tumbleweed_riscv64_tree/usr/lib64/gcc/riscv64-suse-linux/9/crtend.o?rev=367565=auto
==
(empty)
Modified: cfe/trunk/test/Driver/linux-ld.c
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/Driver/linux-ld.c?rev=367565=367564=367565=diff
==
--- cfe/trunk/test/Driver/linux-ld.c (original)
+++ cfe/trunk/test/Driver/linux-ld.c Thu Aug 1 07:23:56 2019
@@ -859,6 +859,26 @@
// CHECK-OPENSUSE-TW-ARMV7HL:
"{{.*}}/usr/lib/gcc/armv7hl-suse-linux-gnueabi/5{{/|}}crtend.o"
// CHECK-OPENSUSE-TW-ARMV7HL:
"{{.*}}/usr/lib/gcc/armv7hl-suse-linux-gnueabi/5/../../../../lib{{/|}}crtn.o"
//
+// Check openSUSE Tumbleweed on riscv64
+// RUN: %clang -no-canonical-prefixes %s -### -o %t.o
r367557 - [RISCV] Add FreeBSD targets
Author: lenary
Date: Thu Aug 1 06:14:30 2019
New Revision: 367557
URL: http://llvm.org/viewvc/llvm-project?rev=367557=rev
Log:
[RISCV] Add FreeBSD targets
Reviewers: asb
Reviewed By: asb
Subscribers: simoncook, s.egerton, lenary, psnobl, benna, mhorne, emaste,
kito-cheng, shiva0217, rogfer01, rkruppe, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D57795
Patch by James Clarke (jrtc27)
Modified:
cfe/trunk/lib/Basic/Targets.cpp
cfe/trunk/lib/Driver/ToolChains/FreeBSD.cpp
cfe/trunk/test/Driver/freebsd.c
Modified: cfe/trunk/lib/Basic/Targets.cpp
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Basic/Targets.cpp?rev=367557=367556=367557=diff
==
--- cfe/trunk/lib/Basic/Targets.cpp (original)
+++ cfe/trunk/lib/Basic/Targets.cpp Thu Aug 1 06:14:30 2019
@@ -363,15 +363,26 @@ TargetInfo *AllocateTarget(const llvm::T
return new AMDGPUTargetInfo(Triple, Opts);
case llvm::Triple::riscv32:
-// TODO: add cases for FreeBSD, NetBSD, RTEMS once tested.
-if (os == llvm::Triple::Linux)
+// TODO: add cases for NetBSD, RTEMS once tested.
+switch (os) {
+case llvm::Triple::FreeBSD:
+ return new FreeBSDTargetInfo(Triple, Opts);
+case llvm::Triple::Linux:
return new LinuxTargetInfo(Triple, Opts);
-return new RISCV32TargetInfo(Triple, Opts);
+default:
+ return new RISCV32TargetInfo(Triple, Opts);
+}
+
case llvm::Triple::riscv64:
-// TODO: add cases for FreeBSD, NetBSD, RTEMS once tested.
-if (os == llvm::Triple::Linux)
+// TODO: add cases for NetBSD, RTEMS once tested.
+switch (os) {
+case llvm::Triple::FreeBSD:
+ return new FreeBSDTargetInfo(Triple, Opts);
+case llvm::Triple::Linux:
return new LinuxTargetInfo(Triple, Opts);
-return new RISCV64TargetInfo(Triple, Opts);
+default:
+ return new RISCV64TargetInfo(Triple, Opts);
+}
case llvm::Triple::sparc:
switch (os) {
Modified: cfe/trunk/lib/Driver/ToolChains/FreeBSD.cpp
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Driver/ToolChains/FreeBSD.cpp?rev=367557=367556=367557=diff
==
--- cfe/trunk/lib/Driver/ToolChains/FreeBSD.cpp (original)
+++ cfe/trunk/lib/Driver/ToolChains/FreeBSD.cpp Thu Aug 1 06:14:30 2019
@@ -197,6 +197,14 @@ void freebsd::Linker::ConstructJob(Compi
else
CmdArgs.push_back("elf64ltsmip_fbsd");
break;
+ case llvm::Triple::riscv32:
+CmdArgs.push_back("-m");
+CmdArgs.push_back("elf32lriscv");
+break;
+ case llvm::Triple::riscv64:
+CmdArgs.push_back("-m");
+CmdArgs.push_back("elf64lriscv");
+break;
default:
break;
}
Modified: cfe/trunk/test/Driver/freebsd.c
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/Driver/freebsd.c?rev=367557=367556=367557=diff
==
--- cfe/trunk/test/Driver/freebsd.c (original)
+++ cfe/trunk/test/Driver/freebsd.c Thu Aug 1 06:14:30 2019
@@ -63,6 +63,15 @@
// RUN: | FileCheck --check-prefix=CHECK-MIPSN32EL-LD %s
// CHECK-MIPSN32EL-LD: ld{{.*}}" {{.*}} "-m" "elf32ltsmipn32_fbsd"
//
+// Check that RISC-V passes the correct linker emulation.
+//
+// RUN: %clang -target riscv32-freebsd %s -### %s 2>&1 \
+// RUN: | FileCheck --check-prefix=CHECK-RV32I-LD %s
+// CHECK-RV32I-LD: ld{{.*}}" {{.*}} "-m" "elf32lriscv"
+// RUN: %clang -target riscv64-freebsd %s -### %s 2>&1 \
+// RUN: | FileCheck --check-prefix=CHECK-RV64I-LD %s
+// CHECK-RV64I-LD: ld{{.*}}" {{.*}} "-m" "elf64lriscv"
+//
// Check that the new linker flags are passed to FreeBSD
// RUN: %clang -no-canonical-prefixes -target x86_64-pc-freebsd8 -m32 %s \
// RUN: --sysroot=%S/Inputs/multiarch_freebsd64_tree -### 2>&1 \
___
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r367403 - [RISCV] Support 'f' Inline Assembly Constraint
Author: lenary
Date: Wed Jul 31 02:45:55 2019
New Revision: 367403
URL: http://llvm.org/viewvc/llvm-project?rev=367403=rev
Log:
[RISCV] Support 'f' Inline Assembly Constraint
Summary:
This adds the 'f' inline assembly constraint, as supported by GCC. An
'f'-constrained operand is passed in a floating point register. Exactly
which kind of floating-point register (32-bit or 64-bit) is decided
based on the operand type and the available standard extensions (-f and
-d, respectively).
This patch adds support in both the clang frontend, and LLVM itself.
Reviewers: asb, lewis-revill
Reviewed By: asb
Subscribers: hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD,
kito-cheng, shiva0217, jrtc27, MaskRay, zzheng, edward-jones, rogfer01,
MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, Jim,
s.egerton, cfe-commits, llvm-commits
Tags: #clang, #llvm
Differential Revision: https://reviews.llvm.org/D65500
Modified:
cfe/trunk/lib/Basic/Targets/RISCV.cpp
cfe/trunk/test/CodeGen/riscv-inline-asm.c
Modified: cfe/trunk/lib/Basic/Targets/RISCV.cpp
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Basic/Targets/RISCV.cpp?rev=367403=367402=367403=diff
==
--- cfe/trunk/lib/Basic/Targets/RISCV.cpp (original)
+++ cfe/trunk/lib/Basic/Targets/RISCV.cpp Wed Jul 31 02:45:55 2019
@@ -71,6 +71,10 @@ bool RISCVTargetInfo::validateAsmConstra
// A 5-bit unsigned immediate for CSR access instructions.
Info.setRequiresImmediate(0, 31);
return true;
+ case 'f':
+// A floating-point register.
+Info.setAllowsRegister();
+return true;
}
}
Modified: cfe/trunk/test/CodeGen/riscv-inline-asm.c
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGen/riscv-inline-asm.c?rev=367403=367402=367403=diff
==
--- cfe/trunk/test/CodeGen/riscv-inline-asm.c (original)
+++ cfe/trunk/test/CodeGen/riscv-inline-asm.c Wed Jul 31 02:45:55 2019
@@ -26,3 +26,15 @@ void test_K() {
// CHECK: call void asm sideeffect "", "K"(i32 0)
asm volatile ("" :: "K"(0));
}
+
+float f;
+double d;
+void test_f() {
+// CHECK-LABEL: define void @test_f()
+// CHECK: [[FLT_ARG:%[a-zA-Z_0-9]+]] = load float, float* @f
+// CHECK: call void asm sideeffect "", "f"(float [[FLT_ARG]])
+ asm volatile ("" :: "f"(f));
+// CHECK: [[FLT_ARG:%[a-zA-Z_0-9]+]] = load double, double* @d
+// CHECK: call void asm sideeffect "", "f"(double [[FLT_ARG]])
+ asm volatile ("" :: "f"(d));
+}
___
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r364777 - [RISCV] Avoid save-restore target feature warning
Author: lenary
Date: Mon Jul 1 07:53:56 2019
New Revision: 364777
URL: http://llvm.org/viewvc/llvm-project?rev=364777=rev
Log:
[RISCV] Avoid save-restore target feature warning
Summary:
LLVM issues a warning if passed unknown target features. Neither I nor
@asb noticed this until after https://reviews.llvm.org/D63498 landed.
This patch stops passing the (unknown) "save-restore" target feature to
the LLVM backend, but continues to emit a warning if a driver asks for
`-msave-restore`. The default of assuming `-mno-save-restore` (and
emitting no warnings) remains.
Reviewers: asb
Reviewed By: asb
Subscribers: rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng,
shiva0217, jrtc27, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult,
the_o, rkruppe, PkmX, jocewei, psnobl, benna, Jim, cfe-commits, asb
Tags: #clang
Differential Revision: https://reviews.llvm.org/D64008
Modified:
cfe/trunk/lib/Driver/ToolChains/Arch/RISCV.cpp
cfe/trunk/test/Driver/riscv-features.c
Modified: cfe/trunk/lib/Driver/ToolChains/Arch/RISCV.cpp
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Driver/ToolChains/Arch/RISCV.cpp?rev=364777=364776=364777=diff
==
--- cfe/trunk/lib/Driver/ToolChains/Arch/RISCV.cpp (original)
+++ cfe/trunk/lib/Driver/ToolChains/Arch/RISCV.cpp Mon Jul 1 07:53:56 2019
@@ -358,14 +358,12 @@ void riscv::getRISCVTargetFeatures(const
else
Features.push_back("-relax");
- // -mno-save-restore is default, unless -msave-restore is specified.
+ // GCC Compatibility: -mno-save-restore is default, unless -msave-restore is
+ // specified...
if (Args.hasFlag(options::OPT_msave_restore, options::OPT_mno_save_restore,
false)) {
-Features.push_back("+save-restore");
-// ... but we don't yet support +save-restore, so issue a warning.
+// ... but we don't support -msave-restore, so issue a warning.
D.Diag(diag::warn_drv_clang_unsupported)
<< Args.getLastArg(options::OPT_msave_restore)->getAsString(Args);
- } else {
-Features.push_back("-save-restore");
}
// Now add any that the user explicitly requested on the command line,
Modified: cfe/trunk/test/Driver/riscv-features.c
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/Driver/riscv-features.c?rev=364777=364776=364777=diff
==
--- cfe/trunk/test/Driver/riscv-features.c (original)
+++ cfe/trunk/test/Driver/riscv-features.c Mon Jul 1 07:53:56 2019
@@ -17,9 +17,5 @@
// RUN: %clang -target riscv32-unknown-elf -### %s -mno-save-restore 2>&1 |
FileCheck %s -check-prefix=NO-SAVE-RESTORE
// SAVE-RESTORE: warning: the clang compiler does not support '-msave-restore'
-// DEFAULT-NOT: warning: the clang compiler does not support
-
-// SAVE-RESTORE: "-target-feature" "+save-restore"
-// NO-SAVE-RESTORE: "-target-feature" "-save-restore"
-// DEFAULT: "-target-feature" "-save-restore"
-// DEFAULT-NOT: "-target-feature" "+save-restore"
\ No newline at end of file
+// NO-SAVE-RESTORE-NOT: warning: the clang compiler does not support
+// DEFAULT-NOT: warning: the clang compiler does not support
\ No newline at end of file
___
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r364018 - [RISC-V] Add -msave-restore and -mno-save-restore to clang driver
Author: lenary
Date: Fri Jun 21 03:03:31 2019
New Revision: 364018
URL: http://llvm.org/viewvc/llvm-project?rev=364018=rev
Log:
[RISC-V] Add -msave-restore and -mno-save-restore to clang driver
Summary:
The GCC RISC-V toolchain accepts `-msave-restore` and `-mno-save-restore`
to control whether libcalls are used for saving and restoring the stack within
prologues and epilogues.
Clang currently errors if someone passes -msave-restore or -mno-save-restore.
This means that people need to change build configurations to use clang. This
patch adds these flags, so that clang invocations can now match gcc.
As the RISC-V backend does not currently have a `save-restore` target feature,
we emit a warning if someone requests `-msave-restore`. LLVM does not error if
we pass the (unimplemented) target features `+save-restore` or `-save-restore`.
Reviewers: asb, luismarques
Reviewed By: asb
Subscribers: rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng,
shiva0217, jrtc27, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult,
the_o, rkruppe, PkmX, jocewei, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D63498
Modified:
cfe/trunk/include/clang/Driver/Options.td
cfe/trunk/lib/Driver/ToolChains/Arch/RISCV.cpp
cfe/trunk/test/Driver/riscv-features.c
Modified: cfe/trunk/include/clang/Driver/Options.td
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/include/clang/Driver/Options.td?rev=364018=364017=364018=diff
==
--- cfe/trunk/include/clang/Driver/Options.td (original)
+++ cfe/trunk/include/clang/Driver/Options.td Fri Jun 21 03:03:31 2019
@@ -2130,6 +2130,10 @@ def mrelax : Flag<["-"], "mrelax">, Grou
HelpText<"Enable linker relaxation">;
def mno_relax : Flag<["-"], "mno-relax">, Group,
HelpText<"Disable linker relaxation">;
+def msave_restore : Flag<["-"], "msave-restore">,
Group,
+ HelpText<"Enable using library calls for save and restore">;
+def mno_save_restore : Flag<["-"], "mno-save-restore">,
Group,
+ HelpText<"Disable using library calls for save and restore">;
def munaligned_access : Flag<["-"], "munaligned-access">,
Group,
HelpText<"Allow memory accesses to be unaligned (AArch32/AArch64 only)">;
Modified: cfe/trunk/lib/Driver/ToolChains/Arch/RISCV.cpp
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Driver/ToolChains/Arch/RISCV.cpp?rev=364018=364017=364018=diff
==
--- cfe/trunk/lib/Driver/ToolChains/Arch/RISCV.cpp (original)
+++ cfe/trunk/lib/Driver/ToolChains/Arch/RISCV.cpp Fri Jun 21 03:03:31 2019
@@ -358,6 +358,16 @@ void riscv::getRISCVTargetFeatures(const
else
Features.push_back("-relax");
+ // -mno-save-restore is default, unless -msave-restore is specified.
+ if (Args.hasFlag(options::OPT_msave_restore, options::OPT_mno_save_restore,
false)) {
+Features.push_back("+save-restore");
+// ... but we don't yet support +save-restore, so issue a warning.
+D.Diag(diag::warn_drv_clang_unsupported)
+ << Args.getLastArg(options::OPT_msave_restore)->getAsString(Args);
+ } else {
+Features.push_back("-save-restore");
+ }
+
// Now add any that the user explicitly requested on the command line,
// which may override the defaults.
handleTargetFeaturesGroup(Args, Features,
options::OPT_m_riscv_Features_Group);
Modified: cfe/trunk/test/Driver/riscv-features.c
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/Driver/riscv-features.c?rev=364018=364017=364018=diff
==
--- cfe/trunk/test/Driver/riscv-features.c (original)
+++ cfe/trunk/test/Driver/riscv-features.c Fri Jun 21 03:03:31 2019
@@ -3,11 +3,23 @@
// CHECK: fno-signed-char
+// RUN: %clang -target riscv32-unknown-elf -### %s 2>&1 | FileCheck %s
-check-prefix=DEFAULT
+
// RUN: %clang -target riscv32-unknown-elf -### %s -mrelax 2>&1 | FileCheck %s
-check-prefix=RELAX
// RUN: %clang -target riscv32-unknown-elf -### %s -mno-relax 2>&1 | FileCheck
%s -check-prefix=NO-RELAX
-// RUN: %clang -target riscv32-unknown-elf -### %s 2>&1 | FileCheck %s
-check-prefix=DEFAULT
// RELAX: "-target-feature" "+relax"
// NO-RELAX: "-target-feature" "-relax"
// DEFAULT: "-target-feature" "+relax"
// DEFAULT-NOT: "-target-feature" "-relax"
+
+// RUN: %clang -target riscv32-unknown-elf -### %s -msave-restore 2>&1 |
FileCheck %s -check-prefix=SAVE-RESTORE
+// RUN: %clang -target riscv32-unknown-elf -### %s -mno-save-restore 2>&1 |
FileCheck %s -check-prefix=NO-SAVE-RESTORE
+
+// SAVE-RESTORE: warning: the clang compiler does not support '-msave-restore'
+// DEFAULT-NOT: warning: the clang compiler does not support
+
+// SAVE-RESTORE: "-target-feature" "+save-restore"
+// NO-SAVE-RESTORE: "-target-feature" "-save-restore"
+// DEFAULT: "-target-feature" "-save-restore"
+// DEFAULT-NOT: "-target-feature"
r311347 - [clang] Fix tests for Emitting Single Inline Remark
Author: lenary
Date: Mon Aug 21 09:40:35 2017
New Revision: 311347
URL: http://llvm.org/viewvc/llvm-project?rev=311347=rev
Log:
[clang] Fix tests for Emitting Single Inline Remark
Summary: This change depends on https://reviews.llvm.org/D36054 and should be
landed at the same time.
Reviewers: anemet
Reviewed By: anemet
Subscribers: cfe-commits
Differential Revision: https://reviews.llvm.org/D36949
Modified:
cfe/trunk/test/Frontend/optimization-remark-with-hotness.c
cfe/trunk/test/Frontend/optimization-remark.c
Modified: cfe/trunk/test/Frontend/optimization-remark-with-hotness.c
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/Frontend/optimization-remark-with-hotness.c?rev=311347=311346=311347=diff
==
--- cfe/trunk/test/Frontend/optimization-remark-with-hotness.c (original)
+++ cfe/trunk/test/Frontend/optimization-remark-with-hotness.c Mon Aug 21
09:40:35 2017
@@ -56,8 +56,7 @@ void bar(int x) {
// THRESHOLD-NOT: hotness
// NO_PGO: '-fdiagnostics-show-hotness' requires profile-guided optimization
information
// NO_PGO: '-fdiagnostics-hotness-threshold=' requires profile-guided
optimization information
- // expected-remark@+2 {{foo should always be inlined (cost=always) (hotness:
30)}}
- // expected-remark@+1 {{foo inlined into bar (hotness: 30)}}
+ // expected-remark@+1 {{foo inlined into bar with cost=always}}
sum += foo(x, x - 2);
}
Modified: cfe/trunk/test/Frontend/optimization-remark.c
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/Frontend/optimization-remark.c?rev=311347=311346=311347=diff
==
--- cfe/trunk/test/Frontend/optimization-remark.c (original)
+++ cfe/trunk/test/Frontend/optimization-remark.c Mon Aug 21 09:40:35 2017
@@ -42,9 +42,8 @@ float foz(int x, int y) { return x * y;
// twice.
//
int bar(int j) {
-// expected-remark@+4 {{foz not inlined into bar because it should never be
inlined (cost=never)}}
// expected-remark@+3 {{foz not inlined into bar because it should never be
inlined (cost=never)}}
-// expected-remark@+2 {{foo should always be inlined}}
+// expected-remark@+2 {{foz not inlined into bar because it should never be
inlined (cost=never)}}
// expected-remark@+1 {{foo inlined into bar}}
return foo(j, j - 2) * foz(j - 2, j);
}
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