[clang] 5bf0858 - Return "[InstCombine] Simplify compare of Phi with constant inputs against a constant"

2020-06-17 Thread Sam Parker via cfe-commits 

Author: Sam Parker
Date: 2020-06-17T11:38:59+01:00
New Revision: 5bf0858c0b4cb5237fa4bf0cf58a76ec5076ef5a

URL: 
https://github.com/llvm/llvm-project/commit/5bf0858c0b4cb5237fa4bf0cf58a76ec5076ef5a
DIFF: 
https://github.com/llvm/llvm-project/commit/5bf0858c0b4cb5237fa4bf0cf58a76ec5076ef5a.diff

LOG: Return "[InstCombine] Simplify compare of Phi with constant inputs against 
a constant"

I originally reverted the patch because it was causing performance
issues, but now I think it's just enabling simplify-cfg to do
something that I don't want instead :)

Sorry for the noise.

This reverts commit 3e39760f8eaad4770efa05824768e67237915cf5.

Added: 


Modified: 
clang/test/CodeGenObjC/exceptions.m
llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
llvm/test/Transforms/InstCombine/icmp-constant-phi.ll
llvm/test/Transforms/InstCombine/indexed-gep-compares.ll
llvm/test/Transforms/InstCombine/zext-or-icmp.ll

Removed: 




diff  --git a/clang/test/CodeGenObjC/exceptions.m 
b/clang/test/CodeGenObjC/exceptions.m
index 741f8a819158..3bb4f86cf025 100644
--- a/clang/test/CodeGenObjC/exceptions.m
+++ b/clang/test/CodeGenObjC/exceptions.m
@@ -97,7 +97,7 @@ void f3() {
 // CHECK:call void @objc_exception_try_exit(
 f3_helper(0, );
   } @finally {
-// CHECK:[[DEST1:%.*]] = phi i32 [ 0, {{%.*}} ], [ 3, {{%.*}} ]
+// CHECK:[[DEST1:%.*]] = phi i1 [ true, {{%.*}} ], [ false, {{%.*}} ]
 // CHECK:call void @objc_exception_try_enter
 // CHECK:call i32 @_setjmp
 @try {
@@ -105,7 +105,7 @@ void f3() {
   // CHECK:  call void @objc_exception_try_exit(
   f3_helper(1, );
 } @finally {
-  // CHECK:  [[DEST2:%.*]] = phi i32 [ 0, {{%.*}} ], [ 5, {{%.*}} ]
+  // CHECK:  [[DEST2:%.*]] = phi i1 [ true, {{%.*}} ], [ false, {{%.*}} ]
   // CHECK:  call void @f3_helper(i32 2, i32* nonnull [[X]])
   f3_helper(2, );
 

diff  --git a/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp 
b/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
index 48375a1a323f..a7b9ecb9bf3b 100644
--- a/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
@@ -1452,6 +1452,27 @@ Instruction *InstCombiner::foldICmpWithConstant(ICmpInst 
) {
 if (Instruction *Res = processUGT_ADDCST_ADD(Cmp, A, B, CI2, CI, *this))
   return Res;
 
+  // icmp(phi(C1, C2, ...), C) -> phi(icmp(C1, C), icmp(C2, C), ...).
+  Constant *C = dyn_cast(Op1);
+  if (!C)
+return nullptr;
+
+  if (auto *Phi = dyn_cast(Op0))
+if (all_of(Phi->operands(), [](Value *V) { return isa(V); })) {
+  Type *Ty = Cmp.getType();
+  Builder.SetInsertPoint(Phi);
+  PHINode *NewPhi =
+  Builder.CreatePHI(Ty, Phi->getNumOperands());
+  for (BasicBlock *Predecessor : predecessors(Phi->getParent())) {
+auto *Input =
+cast(Phi->getIncomingValueForBlock(Predecessor));
+auto *BoolInput = ConstantExpr::getCompare(Pred, Input, C);
+NewPhi->addIncoming(BoolInput, Predecessor);
+  }
+  NewPhi->takeName();
+  return replaceInstUsesWith(Cmp, NewPhi);
+}
+
   return nullptr;
 }
 

diff  --git a/llvm/test/Transforms/InstCombine/icmp-constant-phi.ll 
b/llvm/test/Transforms/InstCombine/icmp-constant-phi.ll
index 9753149f8012..7d4b9294143f 100644
--- a/llvm/test/Transforms/InstCombine/icmp-constant-phi.ll
+++ b/llvm/test/Transforms/InstCombine/icmp-constant-phi.ll
@@ -2,8 +2,6 @@
 ; RUN: opt < %s -instcombine -S | FileCheck %s
 ; RUN: opt < %s -passes=instcombine -S | FileCheck %s
 
-; TODO: Replace with boolean Phi.
-
 define i1 @test_eq(i1 %cond) {
 ; CHECK-LABEL: @test_eq(
 ; CHECK-NEXT:  entry:
@@ -13,10 +11,9 @@ define i1 @test_eq(i1 %cond) {
 ; CHECK:   if.false:
 ; CHECK-NEXT:br label [[MERGE]]
 ; CHECK:   merge:
-; CHECK-NEXT:[[PHI:%.*]] = phi i32 [ 123, [[IF_TRUE]] ], [ 456, 
[[IF_FALSE]] ]
+; CHECK-NEXT:[[COMPARE:%.*]] = phi i1 [ true, [[IF_FALSE]] ], [ false, 
[[IF_TRUE]] ]
 ; CHECK-NEXT:br label [[EXIT:%.*]]
 ; CHECK:   exit:
-; CHECK-NEXT:[[COMPARE:%.*]] = icmp eq i32 [[PHI]], 456
 ; CHECK-NEXT:ret i1 [[COMPARE]]
 ;
 entry:
@@ -46,10 +43,9 @@ define i1 @test_slt(i1 %cond) {
 ; CHECK:   if.false:
 ; CHECK-NEXT:br label [[MERGE]]
 ; CHECK:   merge:
-; CHECK-NEXT:[[PHI:%.*]] = phi i32 [ 123, [[IF_TRUE]] ], [ 456, 
[[IF_FALSE]] ]
+; CHECK-NEXT:[[COMPARE:%.*]] = phi i1 [ false, [[IF_FALSE]] ], [ true, 
[[IF_TRUE]] ]
 ; CHECK-NEXT:br label [[EXIT:%.*]]
 ; CHECK:   exit:
-; CHECK-NEXT:[[COMPARE:%.*]] = icmp ult i32 [[PHI]], 456
 ; CHECK-NEXT:ret i1 [[COMPARE]]
 ;
 entry:
@@ -110,10 +106,9 @@ define i1 @test_ne(i1 %cond) {
 ; CHECK:   if.false:
 ; CHECK-NEXT:br label [[MERGE]]
 ; CHECK:   merge:
-; CHECK-NEXT:[[PHI:%.*]] = phi i32 [ 123, [[IF_TRUE]] ], [ 456, 
[[IF_FALSE]] ]
+; CHECK-NEXT:

Re: [clang] 3e39760 - Revert "Return "[InstCombine] Simplify compare of Phi with constant inputs against a constant""

2020-06-15 Thread Sam Parker via cfe-commits 
Yeah, I will work on getting some today.


Sam Parker

Compilation Tools Engineer | Arm

. . . . . . . . . . . . . . . . . . . . . . . . . . .

Arm.com


From: Roman Lebedev 
Sent: 15 June 2020 07:56
To: Sam Parker ; Sam Parker 
Cc: cfe-commits@lists.llvm.org 
Subject: Re: [clang] 3e39760 - Revert "Return "[InstCombine] Simplify compare 
of Phi with constant inputs against a constant""

Reproducers?

On Mon, Jun 15, 2020 at 9:47 AM Sam Parker via cfe-commits
 wrote:
>
>
> Author: Sam Parker
> Date: 2020-06-15T07:46:28+01:00
> New Revision: 3e39760f8eaad4770efa05824768e67237915cf5
>
> URL: 
> https://github.com/llvm/llvm-project/commit/3e39760f8eaad4770efa05824768e67237915cf5
> DIFF: 
> https://github.com/llvm/llvm-project/commit/3e39760f8eaad4770efa05824768e67237915cf5.diff
>
> LOG: Revert "Return "[InstCombine] Simplify compare of Phi with constant 
> inputs against a constant""
>
> This reverts commit 23291b9863c8af7ad348c4a7d85d8d784df88eb1.
>
> This caused performance regressions.
>
> Added:
>
>
> Modified:
> clang/test/CodeGenObjC/exceptions.m
> llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
> llvm/test/Transforms/InstCombine/icmp-constant-phi.ll
> llvm/test/Transforms/InstCombine/indexed-gep-compares.ll
> llvm/test/Transforms/InstCombine/zext-or-icmp.ll
>
> Removed:
>
>
>
> 
> diff  --git a/clang/test/CodeGenObjC/exceptions.m 
> b/clang/test/CodeGenObjC/exceptions.m
> index 3bb4f86cf025..741f8a819158 100644
> --- a/clang/test/CodeGenObjC/exceptions.m
> +++ b/clang/test/CodeGenObjC/exceptions.m
> @@ -97,7 +97,7 @@ void f3() {
>  // CHECK:call void @objc_exception_try_exit(
>  f3_helper(0, );
>} @finally {
> -// CHECK:[[DEST1:%.*]] = phi i1 [ true, {{%.*}} ], [ false, {{%.*}} ]
> +// CHECK:[[DEST1:%.*]] = phi i32 [ 0, {{%.*}} ], [ 3, {{%.*}} ]
>  // CHECK:call void @objc_exception_try_enter
>  // CHECK:call i32 @_setjmp
>  @try {
> @@ -105,7 +105,7 @@ void f3() {
>// CHECK:  call void @objc_exception_try_exit(
>f3_helper(1, );
>  } @finally {
> -  // CHECK:  [[DEST2:%.*]] = phi i1 [ true, {{%.*}} ], [ false, {{%.*}} ]
> +  // CHECK:  [[DEST2:%.*]] = phi i32 [ 0, {{%.*}} ], [ 5, {{%.*}} ]
>// CHECK:  call void @f3_helper(i32 2, i32* nonnull [[X]])
>f3_helper(2, );
>
>
> diff  --git a/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp 
> b/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
> index a7b9ecb9bf3b..48375a1a323f 100644
> --- a/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
> +++ b/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
> @@ -1452,27 +1452,6 @@ Instruction 
> *InstCombiner::foldICmpWithConstant(ICmpInst ) {
>  if (Instruction *Res = processUGT_ADDCST_ADD(Cmp, A, B, CI2, CI, *this))
>return Res;
>
> -  // icmp(phi(C1, C2, ...), C) -> phi(icmp(C1, C), icmp(C2, C), ...).
> -  Constant *C = dyn_cast(Op1);
> -  if (!C)
> -return nullptr;
> -
> -  if (auto *Phi = dyn_cast(Op0))
> -if (all_of(Phi->operands(), [](Value *V) { return isa(V); })) {
> -  Type *Ty = Cmp.getType();
> -  Builder.SetInsertPoint(Phi);
> -  PHINode *NewPhi =
> -  Builder.CreatePHI(Ty, Phi->getNumOperands());
> -  for (BasicBlock *Predecessor : predecessors(Phi->getParent())) {
> -auto *Input =
> -cast(Phi->getIncomingValueForBlock(Predecessor));
> -auto *BoolInput = ConstantExpr::getCompare(Pred, Input, C);
> -NewPhi->addIncoming(BoolInput, Predecessor);
> -  }
> -  NewPhi->takeName();
> -  return replaceInstUsesWith(Cmp, NewPhi);
> -}
> -
>return nullptr;
>  }
>
>
> diff  --git a/llvm/test/Transforms/InstCombine/icmp-constant-phi.ll 
> b/llvm/test/Transforms/InstCombine/icmp-constant-phi.ll
> index 7d4b9294143f..9753149f8012 100644
> --- a/llvm/test/Transforms/InstCombine/icmp-constant-phi.ll
> +++ b/llvm/test/Transforms/InstCombine/icmp-constant-phi.ll
> @@ -2,6 +2,8 @@
>  ; RUN: opt < %s -instcombine -S | FileCheck %s
>  ; RUN: opt < %s -passes=instcombine -S | FileCheck %s
>
> +; TODO: Replace with boolean Phi.
> +
>  define i1 @test_eq(i1 %cond) {
>  ; CHECK-LABEL: @test_eq(
>  ; CHECK-NEXT:  entry:
> @@ -11,9 +13,10 @@ define i1 @test_eq(i1 %cond) {
>  ; CHECK:   if.false:
>  ; CHECK-NEXT:br label [[MERGE]]
>  ; CHECK:   merge:
> -; CHECK-NEXT:[[COMPARE:%.*]] = phi i1 [ true, [[IF_FALSE]] ], [ false, 
> [[IF_TRUE]] ]
> +; CHECK-NEXT:[

[clang] 3e39760 - Revert "Return "[InstCombine] Simplify compare of Phi with constant inputs against a constant""

2020-06-15 Thread Sam Parker via cfe-commits 

Author: Sam Parker
Date: 2020-06-15T07:46:28+01:00
New Revision: 3e39760f8eaad4770efa05824768e67237915cf5

URL: 
https://github.com/llvm/llvm-project/commit/3e39760f8eaad4770efa05824768e67237915cf5
DIFF: 
https://github.com/llvm/llvm-project/commit/3e39760f8eaad4770efa05824768e67237915cf5.diff

LOG: Revert "Return "[InstCombine] Simplify compare of Phi with constant inputs 
against a constant""

This reverts commit 23291b9863c8af7ad348c4a7d85d8d784df88eb1.

This caused performance regressions.

Added: 


Modified: 
clang/test/CodeGenObjC/exceptions.m
llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
llvm/test/Transforms/InstCombine/icmp-constant-phi.ll
llvm/test/Transforms/InstCombine/indexed-gep-compares.ll
llvm/test/Transforms/InstCombine/zext-or-icmp.ll

Removed: 




diff  --git a/clang/test/CodeGenObjC/exceptions.m 
b/clang/test/CodeGenObjC/exceptions.m
index 3bb4f86cf025..741f8a819158 100644
--- a/clang/test/CodeGenObjC/exceptions.m
+++ b/clang/test/CodeGenObjC/exceptions.m
@@ -97,7 +97,7 @@ void f3() {
 // CHECK:call void @objc_exception_try_exit(
 f3_helper(0, );
   } @finally {
-// CHECK:[[DEST1:%.*]] = phi i1 [ true, {{%.*}} ], [ false, {{%.*}} ]
+// CHECK:[[DEST1:%.*]] = phi i32 [ 0, {{%.*}} ], [ 3, {{%.*}} ]
 // CHECK:call void @objc_exception_try_enter
 // CHECK:call i32 @_setjmp
 @try {
@@ -105,7 +105,7 @@ void f3() {
   // CHECK:  call void @objc_exception_try_exit(
   f3_helper(1, );
 } @finally {
-  // CHECK:  [[DEST2:%.*]] = phi i1 [ true, {{%.*}} ], [ false, {{%.*}} ]
+  // CHECK:  [[DEST2:%.*]] = phi i32 [ 0, {{%.*}} ], [ 5, {{%.*}} ]
   // CHECK:  call void @f3_helper(i32 2, i32* nonnull [[X]])
   f3_helper(2, );
 

diff  --git a/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp 
b/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
index a7b9ecb9bf3b..48375a1a323f 100644
--- a/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
@@ -1452,27 +1452,6 @@ Instruction *InstCombiner::foldICmpWithConstant(ICmpInst 
) {
 if (Instruction *Res = processUGT_ADDCST_ADD(Cmp, A, B, CI2, CI, *this))
   return Res;
 
-  // icmp(phi(C1, C2, ...), C) -> phi(icmp(C1, C), icmp(C2, C), ...).
-  Constant *C = dyn_cast(Op1);
-  if (!C)
-return nullptr;
-
-  if (auto *Phi = dyn_cast(Op0))
-if (all_of(Phi->operands(), [](Value *V) { return isa(V); })) {
-  Type *Ty = Cmp.getType();
-  Builder.SetInsertPoint(Phi);
-  PHINode *NewPhi =
-  Builder.CreatePHI(Ty, Phi->getNumOperands());
-  for (BasicBlock *Predecessor : predecessors(Phi->getParent())) {
-auto *Input =
-cast(Phi->getIncomingValueForBlock(Predecessor));
-auto *BoolInput = ConstantExpr::getCompare(Pred, Input, C);
-NewPhi->addIncoming(BoolInput, Predecessor);
-  }
-  NewPhi->takeName();
-  return replaceInstUsesWith(Cmp, NewPhi);
-}
-
   return nullptr;
 }
 

diff  --git a/llvm/test/Transforms/InstCombine/icmp-constant-phi.ll 
b/llvm/test/Transforms/InstCombine/icmp-constant-phi.ll
index 7d4b9294143f..9753149f8012 100644
--- a/llvm/test/Transforms/InstCombine/icmp-constant-phi.ll
+++ b/llvm/test/Transforms/InstCombine/icmp-constant-phi.ll
@@ -2,6 +2,8 @@
 ; RUN: opt < %s -instcombine -S | FileCheck %s
 ; RUN: opt < %s -passes=instcombine -S | FileCheck %s
 
+; TODO: Replace with boolean Phi.
+
 define i1 @test_eq(i1 %cond) {
 ; CHECK-LABEL: @test_eq(
 ; CHECK-NEXT:  entry:
@@ -11,9 +13,10 @@ define i1 @test_eq(i1 %cond) {
 ; CHECK:   if.false:
 ; CHECK-NEXT:br label [[MERGE]]
 ; CHECK:   merge:
-; CHECK-NEXT:[[COMPARE:%.*]] = phi i1 [ true, [[IF_FALSE]] ], [ false, 
[[IF_TRUE]] ]
+; CHECK-NEXT:[[PHI:%.*]] = phi i32 [ 123, [[IF_TRUE]] ], [ 456, 
[[IF_FALSE]] ]
 ; CHECK-NEXT:br label [[EXIT:%.*]]
 ; CHECK:   exit:
+; CHECK-NEXT:[[COMPARE:%.*]] = icmp eq i32 [[PHI]], 456
 ; CHECK-NEXT:ret i1 [[COMPARE]]
 ;
 entry:
@@ -43,9 +46,10 @@ define i1 @test_slt(i1 %cond) {
 ; CHECK:   if.false:
 ; CHECK-NEXT:br label [[MERGE]]
 ; CHECK:   merge:
-; CHECK-NEXT:[[COMPARE:%.*]] = phi i1 [ false, [[IF_FALSE]] ], [ true, 
[[IF_TRUE]] ]
+; CHECK-NEXT:[[PHI:%.*]] = phi i32 [ 123, [[IF_TRUE]] ], [ 456, 
[[IF_FALSE]] ]
 ; CHECK-NEXT:br label [[EXIT:%.*]]
 ; CHECK:   exit:
+; CHECK-NEXT:[[COMPARE:%.*]] = icmp ult i32 [[PHI]], 456
 ; CHECK-NEXT:ret i1 [[COMPARE]]
 ;
 entry:
@@ -106,9 +110,10 @@ define i1 @test_ne(i1 %cond) {
 ; CHECK:   if.false:
 ; CHECK-NEXT:br label [[MERGE]]
 ; CHECK:   merge:
-; CHECK-NEXT:[[COMPARE:%.*]] = phi i1 [ false, [[IF_FALSE]] ], [ true, 
[[IF_TRUE]] ]
+; CHECK-NEXT:[[PHI:%.*]] = phi i32 [ 123, [[IF_TRUE]] ], [ 456, 
[[IF_FALSE]] ]
 ; CHECK-NEXT:br label [[EXIT:%.*]]
 ; CHECK:   exit:
+;

Re: r351740 - [AArch64] Use LL for 64-bit intrinsic arguments

2019-01-29 Thread Sam Parker via cfe-commits 
Hi Hans,


I've recommitted the change in r352463.


cheers,

Sam


Sam Parker

Compilation Tools Engineer | Arm

. . . . . . . . . . . . . . . . . . . . . . . . . . .

Arm.com


From: Hans Wennborg 
Sent: 25 January 2019 18:26:48
To: Sam Parker
Cc: cfe-commits
Subject: Re: r351740 - [AArch64] Use LL for 64-bit intrinsic arguments

I see this was reverted later, but please keep me posted on the
resolution as I think we might want to merge this to the 8.0 release
branch as well.

Thanks,
Hans

On Mon, Jan 21, 2019 at 3:01 AM Sam Parker via cfe-commits
 wrote:
>
> Author: sam_parker
> Date: Mon Jan 21 03:01:05 2019
> New Revision: 351740
>
> URL: http://llvm.org/viewvc/llvm-project?rev=351740=rev
> Log:
> [AArch64] Use LL for 64-bit intrinsic arguments
>
> The ACLE states that 64-bit crc32, wsr, rsr and rbit operands are
> uint64_t so we should have the clang builtin match this description
> - which is what we already do for AArch32.
>
> Differential Revision: https://reviews.llvm.org/D56852
>
> Modified:
> cfe/trunk/include/clang/Basic/BuiltinsAArch64.def
> cfe/trunk/test/CodeGen/arm64-crc32.c
> cfe/trunk/test/CodeGen/builtins-arm64.c
>
> Modified: cfe/trunk/include/clang/Basic/BuiltinsAArch64.def
> URL: 
> http://llvm.org/viewvc/llvm-project/cfe/trunk/include/clang/Basic/BuiltinsAArch64.def?rev=351740=351739=351740=diff
> ==
> --- cfe/trunk/include/clang/Basic/BuiltinsAArch64.def (original)
> +++ cfe/trunk/include/clang/Basic/BuiltinsAArch64.def Mon Jan 21 03:01:05 2019
> @@ -32,7 +32,7 @@ BUILTIN(__builtin_arm_clrex, "v", "")
>
>  // Bit manipulation
>  BUILTIN(__builtin_arm_rbit, "UiUi", "nc")
> -BUILTIN(__builtin_arm_rbit64, "LUiLUi", "nc")
> +BUILTIN(__builtin_arm_rbit64, "LLUiLLUi", "nc")
>
>  // HINT
>  BUILTIN(__builtin_arm_nop, "v", "")
> @@ -49,8 +49,8 @@ BUILTIN(__builtin_arm_crc32h, "UiUiUs",
>  BUILTIN(__builtin_arm_crc32ch, "UiUiUs", "nc")
>  BUILTIN(__builtin_arm_crc32w, "UiUiUi", "nc")
>  BUILTIN(__builtin_arm_crc32cw, "UiUiUi", "nc")
> -BUILTIN(__builtin_arm_crc32d, "UiUiLUi", "nc")
> -BUILTIN(__builtin_arm_crc32cd, "UiUiLUi", "nc")
> +BUILTIN(__builtin_arm_crc32d, "UiUiLLUi", "nc")
> +BUILTIN(__builtin_arm_crc32cd, "UiUiLLUi", "nc")
>
>  // Memory barrier
>  BUILTIN(__builtin_arm_dmb, "vUi", "nc")
> @@ -62,10 +62,10 @@ BUILTIN(__builtin_arm_prefetch, "vvC*UiU
>
>  // System Registers
>  BUILTIN(__builtin_arm_rsr, "UicC*", "nc")
> -BUILTIN(__builtin_arm_rsr64, "LUicC*", "nc")
> +BUILTIN(__builtin_arm_rsr64, "LLUicC*", "nc")
>  BUILTIN(__builtin_arm_rsrp, "v*cC*", "nc")
>  BUILTIN(__builtin_arm_wsr, "vcC*Ui", "nc")
> -BUILTIN(__builtin_arm_wsr64, "vcC*LUi", "nc")
> +BUILTIN(__builtin_arm_wsr64, "vcC*LLUi", "nc")
>  BUILTIN(__builtin_arm_wsrp, "vcC*vC*", "nc")
>
>  // MSVC
>
> Modified: cfe/trunk/test/CodeGen/arm64-crc32.c
> URL: 
> http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGen/arm64-crc32.c?rev=351740=351739=351740=diff
> ==
> --- cfe/trunk/test/CodeGen/arm64-crc32.c (original)
> +++ cfe/trunk/test/CodeGen/arm64-crc32.c Mon Jan 21 03:01:05 2019
> @@ -1,54 +1,57 @@
>  // REQUIRES: aarch64-registered-target
>  // RUN: %clang_cc1 -triple arm64-none-linux-gnu \
>  // RUN:  -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | 
> FileCheck %s
> +// RUN: %clang_cc1 -triple aarch64-windows \
> +// RUN:  -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | 
> FileCheck %s
> +#include 
>
> -int crc32b(int a, char b)
> +uint32_t crc32b(uint32_t a, uint8_t b)
>  {
>  return __builtin_arm_crc32b(a,b);
>  // CHECK: [[T0:%[0-9]+]] = zext i8 %b to i32
>  // CHECK: call i32 @llvm.aarch64.crc32b(i32 %a, i32 [[T0]])
>  }
>
> -int crc32cb(int a, char b)
> +uint32_t crc32cb(uint32_t a, uint8_t b)
>  {
>  return __builtin_arm_crc32cb(a,b);
>  // CHECK: [[T0:%[0-9]+]] = zext i8 %b to i32
>  // CHECK: call i32 @llvm.aarch64.crc32cb(i32 %a, i32 [[T0]])
>  }
>
> -int crc32h(int a, short b)
> +uint32_t crc32h(uint32_t a, uint16_t b)
>  {
>  return __builtin_arm_crc32h(a,b);
>  // CHECK: [[T0:%[0-9]+]] = zext i16 %b to i32
>  // CHECK: call i32 @llvm.aarch

r352463 - [AArch64] Update int64_t ACLE builtin arguments

2019-01-29 Thread Sam Parker via cfe-commits 
Author: sam_parker
Date: Tue Jan 29 01:04:03 2019
New Revision: 352463

URL: http://llvm.org/viewvc/llvm-project?rev=352463=rev
Log:
[AArch64] Update int64_t ACLE builtin arguments

Re-applying r351740 with fixes (changing LL to W).

Differential Revision: https://reviews.llvm.org/D56852

Modified:
cfe/trunk/include/clang/Basic/BuiltinsAArch64.def
cfe/trunk/test/CodeGen/arm64-crc32.c
cfe/trunk/test/CodeGen/builtins-arm64.c

Modified: cfe/trunk/include/clang/Basic/BuiltinsAArch64.def
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/include/clang/Basic/BuiltinsAArch64.def?rev=352463=352462=352463=diff
==
--- cfe/trunk/include/clang/Basic/BuiltinsAArch64.def (original)
+++ cfe/trunk/include/clang/Basic/BuiltinsAArch64.def Tue Jan 29 01:04:03 2019
@@ -32,7 +32,7 @@ BUILTIN(__builtin_arm_clrex, "v", "")
 
 // Bit manipulation
 BUILTIN(__builtin_arm_rbit, "UiUi", "nc")
-BUILTIN(__builtin_arm_rbit64, "LUiLUi", "nc")
+BUILTIN(__builtin_arm_rbit64, "WUiWUi", "nc")
 
 // HINT
 BUILTIN(__builtin_arm_nop, "v", "")
@@ -49,8 +49,8 @@ BUILTIN(__builtin_arm_crc32h, "UiUiUs",
 BUILTIN(__builtin_arm_crc32ch, "UiUiUs", "nc")
 BUILTIN(__builtin_arm_crc32w, "UiUiUi", "nc")
 BUILTIN(__builtin_arm_crc32cw, "UiUiUi", "nc")
-BUILTIN(__builtin_arm_crc32d, "UiUiLUi", "nc")
-BUILTIN(__builtin_arm_crc32cd, "UiUiLUi", "nc")
+BUILTIN(__builtin_arm_crc32d, "UiUiWUi", "nc")
+BUILTIN(__builtin_arm_crc32cd, "UiUiWUi", "nc")
 
 // Memory barrier
 BUILTIN(__builtin_arm_dmb, "vUi", "nc")
@@ -62,10 +62,10 @@ BUILTIN(__builtin_arm_prefetch, "vvC*UiU
 
 // System Registers
 BUILTIN(__builtin_arm_rsr, "UicC*", "nc")
-BUILTIN(__builtin_arm_rsr64, "LUicC*", "nc")
+BUILTIN(__builtin_arm_rsr64, "WUicC*", "nc")
 BUILTIN(__builtin_arm_rsrp, "v*cC*", "nc")
 BUILTIN(__builtin_arm_wsr, "vcC*Ui", "nc")
-BUILTIN(__builtin_arm_wsr64, "vcC*LUi", "nc")
+BUILTIN(__builtin_arm_wsr64, "vcC*WUi", "nc")
 BUILTIN(__builtin_arm_wsrp, "vcC*vC*", "nc")
 
 // MSVC

Modified: cfe/trunk/test/CodeGen/arm64-crc32.c
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGen/arm64-crc32.c?rev=352463=352462=352463=diff
==
--- cfe/trunk/test/CodeGen/arm64-crc32.c (original)
+++ cfe/trunk/test/CodeGen/arm64-crc32.c Tue Jan 29 01:04:03 2019
@@ -1,54 +1,57 @@
 // REQUIRES: aarch64-registered-target
 // RUN: %clang_cc1 -triple arm64-none-linux-gnu \
 // RUN:  -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | 
FileCheck %s
+// RUN: %clang_cc1 -triple aarch64-windows \
+// RUN:  -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | 
FileCheck %s
+#include 
 
-int crc32b(int a, char b)
+uint32_t crc32b(uint32_t a, uint8_t b)
 {
 return __builtin_arm_crc32b(a,b);
 // CHECK: [[T0:%[0-9]+]] = zext i8 %b to i32
 // CHECK: call i32 @llvm.aarch64.crc32b(i32 %a, i32 [[T0]])
 }
 
-int crc32cb(int a, char b)
+uint32_t crc32cb(uint32_t a, uint8_t b)
 {
 return __builtin_arm_crc32cb(a,b);
 // CHECK: [[T0:%[0-9]+]] = zext i8 %b to i32
 // CHECK: call i32 @llvm.aarch64.crc32cb(i32 %a, i32 [[T0]])
 }
 
-int crc32h(int a, short b)
+uint32_t crc32h(uint32_t a, uint16_t b)
 {
 return __builtin_arm_crc32h(a,b);
 // CHECK: [[T0:%[0-9]+]] = zext i16 %b to i32
 // CHECK: call i32 @llvm.aarch64.crc32h(i32 %a, i32 [[T0]])
 }
 
-int crc32ch(int a, short b)
+uint32_t crc32ch(uint32_t a, uint16_t b)
 {
 return __builtin_arm_crc32ch(a,b);
 // CHECK: [[T0:%[0-9]+]] = zext i16 %b to i32
 // CHECK: call i32 @llvm.aarch64.crc32ch(i32 %a, i32 [[T0]])
 }
 
-int crc32w(int a, int b)
+uint32_t crc32w(uint32_t a, uint32_t b)
 {
 return __builtin_arm_crc32w(a,b);
 // CHECK: call i32 @llvm.aarch64.crc32w(i32 %a, i32 %b)
 }
 
-int crc32cw(int a, int b)
+uint32_t crc32cw(uint32_t a, uint32_t b)
 {
 return __builtin_arm_crc32cw(a,b);
 // CHECK: call i32 @llvm.aarch64.crc32cw(i32 %a, i32 %b)
 }
 
-int crc32d(int a, long b)
+uint32_t crc32d(uint32_t a, uint64_t b)
 {
 return __builtin_arm_crc32d(a,b);
 // CHECK: call i32 @llvm.aarch64.crc32x(i32 %a, i64 %b)
 }
 
-int crc32cd(int a, long b)
+uint32_t crc32cd(uint32_t a, uint64_t b)
 {
 return __builtin_arm_crc32cd(a,b);
 // CHECK: call i32 @llvm.aarch64.crc32cx(i32 %a, i64 %b)

Modified: cfe/trunk/test/CodeGen/builtins-arm64.c
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGen/builtins-arm64.c?rev=352463=352462=352463=diff
==
--- cfe/trunk/test/CodeGen/builtins-arm64.c (original)
+++ cfe/trunk/test/CodeGen/builtins-arm64.c Tue Jan 29 01:04:03 2019
@@ -1,4 +1,5 @@
-// RUN: %clang_cc1 -triple arm64-unknown-linux -disable-O0-optnone -emit-llvm 
-o - %s | opt -S -mem2reg | FileCheck %s
+// RUN: %clang_cc1 -triple arm64-unknown-linux -disable-O0-optnone -emit-llvm 
-o - %s | opt -S -mem2reg | FileCheck %s --check-prefix=CHECK

r351740 - [AArch64] Use LL for 64-bit intrinsic arguments

2019-01-21 Thread Sam Parker via cfe-commits 
Author: sam_parker
Date: Mon Jan 21 03:01:05 2019
New Revision: 351740

URL: http://llvm.org/viewvc/llvm-project?rev=351740=rev
Log:
[AArch64] Use LL for 64-bit intrinsic arguments

The ACLE states that 64-bit crc32, wsr, rsr and rbit operands are
uint64_t so we should have the clang builtin match this description
- which is what we already do for AArch32.

Differential Revision: https://reviews.llvm.org/D56852

Modified:
cfe/trunk/include/clang/Basic/BuiltinsAArch64.def
cfe/trunk/test/CodeGen/arm64-crc32.c
cfe/trunk/test/CodeGen/builtins-arm64.c

Modified: cfe/trunk/include/clang/Basic/BuiltinsAArch64.def
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/include/clang/Basic/BuiltinsAArch64.def?rev=351740=351739=351740=diff
==
--- cfe/trunk/include/clang/Basic/BuiltinsAArch64.def (original)
+++ cfe/trunk/include/clang/Basic/BuiltinsAArch64.def Mon Jan 21 03:01:05 2019
@@ -32,7 +32,7 @@ BUILTIN(__builtin_arm_clrex, "v", "")
 
 // Bit manipulation
 BUILTIN(__builtin_arm_rbit, "UiUi", "nc")
-BUILTIN(__builtin_arm_rbit64, "LUiLUi", "nc")
+BUILTIN(__builtin_arm_rbit64, "LLUiLLUi", "nc")
 
 // HINT
 BUILTIN(__builtin_arm_nop, "v", "")
@@ -49,8 +49,8 @@ BUILTIN(__builtin_arm_crc32h, "UiUiUs",
 BUILTIN(__builtin_arm_crc32ch, "UiUiUs", "nc")
 BUILTIN(__builtin_arm_crc32w, "UiUiUi", "nc")
 BUILTIN(__builtin_arm_crc32cw, "UiUiUi", "nc")
-BUILTIN(__builtin_arm_crc32d, "UiUiLUi", "nc")
-BUILTIN(__builtin_arm_crc32cd, "UiUiLUi", "nc")
+BUILTIN(__builtin_arm_crc32d, "UiUiLLUi", "nc")
+BUILTIN(__builtin_arm_crc32cd, "UiUiLLUi", "nc")
 
 // Memory barrier
 BUILTIN(__builtin_arm_dmb, "vUi", "nc")
@@ -62,10 +62,10 @@ BUILTIN(__builtin_arm_prefetch, "vvC*UiU
 
 // System Registers
 BUILTIN(__builtin_arm_rsr, "UicC*", "nc")
-BUILTIN(__builtin_arm_rsr64, "LUicC*", "nc")
+BUILTIN(__builtin_arm_rsr64, "LLUicC*", "nc")
 BUILTIN(__builtin_arm_rsrp, "v*cC*", "nc")
 BUILTIN(__builtin_arm_wsr, "vcC*Ui", "nc")
-BUILTIN(__builtin_arm_wsr64, "vcC*LUi", "nc")
+BUILTIN(__builtin_arm_wsr64, "vcC*LLUi", "nc")
 BUILTIN(__builtin_arm_wsrp, "vcC*vC*", "nc")
 
 // MSVC

Modified: cfe/trunk/test/CodeGen/arm64-crc32.c
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGen/arm64-crc32.c?rev=351740=351739=351740=diff
==
--- cfe/trunk/test/CodeGen/arm64-crc32.c (original)
+++ cfe/trunk/test/CodeGen/arm64-crc32.c Mon Jan 21 03:01:05 2019
@@ -1,54 +1,57 @@
 // REQUIRES: aarch64-registered-target
 // RUN: %clang_cc1 -triple arm64-none-linux-gnu \
 // RUN:  -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | 
FileCheck %s
+// RUN: %clang_cc1 -triple aarch64-windows \
+// RUN:  -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | 
FileCheck %s
+#include 
 
-int crc32b(int a, char b)
+uint32_t crc32b(uint32_t a, uint8_t b)
 {
 return __builtin_arm_crc32b(a,b);
 // CHECK: [[T0:%[0-9]+]] = zext i8 %b to i32
 // CHECK: call i32 @llvm.aarch64.crc32b(i32 %a, i32 [[T0]])
 }
 
-int crc32cb(int a, char b)
+uint32_t crc32cb(uint32_t a, uint8_t b)
 {
 return __builtin_arm_crc32cb(a,b);
 // CHECK: [[T0:%[0-9]+]] = zext i8 %b to i32
 // CHECK: call i32 @llvm.aarch64.crc32cb(i32 %a, i32 [[T0]])
 }
 
-int crc32h(int a, short b)
+uint32_t crc32h(uint32_t a, uint16_t b)
 {
 return __builtin_arm_crc32h(a,b);
 // CHECK: [[T0:%[0-9]+]] = zext i16 %b to i32
 // CHECK: call i32 @llvm.aarch64.crc32h(i32 %a, i32 [[T0]])
 }
 
-int crc32ch(int a, short b)
+uint32_t crc32ch(uint32_t a, uint16_t b)
 {
 return __builtin_arm_crc32ch(a,b);
 // CHECK: [[T0:%[0-9]+]] = zext i16 %b to i32
 // CHECK: call i32 @llvm.aarch64.crc32ch(i32 %a, i32 [[T0]])
 }
 
-int crc32w(int a, int b)
+uint32_t crc32w(uint32_t a, uint32_t b)
 {
 return __builtin_arm_crc32w(a,b);
 // CHECK: call i32 @llvm.aarch64.crc32w(i32 %a, i32 %b)
 }
 
-int crc32cw(int a, int b)
+uint32_t crc32cw(uint32_t a, uint32_t b)
 {
 return __builtin_arm_crc32cw(a,b);
 // CHECK: call i32 @llvm.aarch64.crc32cw(i32 %a, i32 %b)
 }
 
-int crc32d(int a, long b)
+uint32_t crc32d(uint32_t a, uint64_t b)
 {
 return __builtin_arm_crc32d(a,b);
 // CHECK: call i32 @llvm.aarch64.crc32x(i32 %a, i64 %b)
 }
 
-int crc32cd(int a, long b)
+uint32_t crc32cd(uint32_t a, uint64_t b)
 {
 return __builtin_arm_crc32cd(a,b);
 // CHECK: call i32 @llvm.aarch64.crc32cx(i32 %a, i64 %b)

Modified: cfe/trunk/test/CodeGen/builtins-arm64.c
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGen/builtins-arm64.c?rev=351740=351739=351740=diff
==
--- cfe/trunk/test/CodeGen/builtins-arm64.c (original)
+++ cfe/trunk/test/CodeGen/builtins-arm64.c Mon Jan 21 03:01:05 2019
@@ -1,4 +1,6 @@
 // RUN: %clang_cc1 -triple arm64-unknown-linux -disable-O0-optnone -emit-llvm 
-o - %s | opt -S -mem2reg | FileCheck %s
+// RUN: %clang_cc1

r347577 - [NFC] Replace magic numbers with CodeGenOpt enums

2018-11-26 Thread Sam Parker via cfe-commits 
Author: sam_parker
Date: Mon Nov 26 09:26:49 2018
New Revision: 347577

URL: http://llvm.org/viewvc/llvm-project?rev=347577=rev
Log:
[NFC] Replace magic numbers with CodeGenOpt enums

Use enum values from llvm/Support/CodeGen.h for the optimisation
levels in CompilerInvocation.

Modified:
cfe/trunk/lib/Frontend/CompilerInvocation.cpp

Modified: cfe/trunk/lib/Frontend/CompilerInvocation.cpp
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Frontend/CompilerInvocation.cpp?rev=347577=347576=347577=diff
==
--- cfe/trunk/lib/Frontend/CompilerInvocation.cpp (original)
+++ cfe/trunk/lib/Frontend/CompilerInvocation.cpp Mon Nov 26 09:26:49 2018
@@ -120,25 +120,25 @@ CompilerInvocationBase::~CompilerInvocat
 
 static unsigned getOptimizationLevel(ArgList , InputKind IK,
  DiagnosticsEngine ) {
-  unsigned DefaultOpt = 0;
+  unsigned DefaultOpt = llvm::CodeGenOpt::None;
   if (IK.getLanguage() == InputKind::OpenCL && 
!Args.hasArg(OPT_cl_opt_disable))
-DefaultOpt = 2;
+DefaultOpt = llvm::CodeGenOpt::Default;
 
   if (Arg *A = Args.getLastArg(options::OPT_O_Group)) {
 if (A->getOption().matches(options::OPT_O0))
-  return 0;
+  return llvm::CodeGenOpt::None;
 
 if (A->getOption().matches(options::OPT_Ofast))
-  return 3;
+  return llvm::CodeGenOpt::Aggressive;
 
 assert(A->getOption().matches(options::OPT_O));
 
 StringRef S(A->getValue());
 if (S == "s" || S == "z" || S.empty())
-  return 2;
+  return llvm::CodeGenOpt::Default;
 
 if (S == "g")
-  return 1;
+  return llvm::CodeGenOpt::Less;
 
 return getLastArgIntValue(Args, OPT_O, DefaultOpt, Diags);
   }


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r343309 - [ARM] Prevent DSP and SIM32 being set for v6m

2018-09-28 Thread Sam Parker via cfe-commits 
Author: sam_parker
Date: Fri Sep 28 03:18:02 2018
New Revision: 343309

URL: http://llvm.org/viewvc/llvm-project?rev=343309=rev
Log:
[ARM] Prevent DSP and SIM32 being set for v6m

My previous change (rL340911) set the two features for architectures
>= 6, which wrongly includes v6m. Now set to >= 6 and not Cortex-M.

Differential Revision: https://reviews.llvm.org/D52644

Modified:
cfe/trunk/lib/Basic/Targets/ARM.cpp
cfe/trunk/test/Preprocessor/arm-acle-6.4.c

Modified: cfe/trunk/lib/Basic/Targets/ARM.cpp
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Basic/Targets/ARM.cpp?rev=343309=343308=343309=diff
==
--- cfe/trunk/lib/Basic/Targets/ARM.cpp (original)
+++ cfe/trunk/lib/Basic/Targets/ARM.cpp Fri Sep 28 03:18:02 2018
@@ -663,7 +663,7 @@ void ARMTargetInfo::getTargetDefines(con
   }
 
   // ACLE 6.4.9 32-bit SIMD instructions
-  if (ArchVersion >= 6 || (CPUProfile == "M" && DSP))
+  if ((CPUProfile != "M" && ArchVersion >= 6) || (CPUProfile == "M" && DSP))
 Builder.defineMacro("__ARM_FEATURE_SIMD32", "1");
 
   // ACLE 6.4.10 Hardware Integer Divide

Modified: cfe/trunk/test/Preprocessor/arm-acle-6.4.c
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/Preprocessor/arm-acle-6.4.c?rev=343309=343308=343309=diff
==
--- cfe/trunk/test/Preprocessor/arm-acle-6.4.c (original)
+++ cfe/trunk/test/Preprocessor/arm-acle-6.4.c Fri Sep 28 03:18:02 2018
@@ -174,15 +174,22 @@
 // CHECK-V7M: __ARM_FEATURE_SAT 1
 // CHECK-V7M: __ARM_FEATURE_UNALIGNED 1
 
+// RUN: %clang -target arm-none-linux-eabi -march=armv7-m -x c -E -dM %s -o - 
| FileCheck %s -check-prefix CHECK-M-NODSP
 // RUN: %clang -target arm-none-linux-eabi -march=armv7e-m -x c -E -dM %s -o - 
| FileCheck %s -check-prefix CHECK-M-DSP
+// RUN: %clang --target=arm-arm-none-eabi -mcpu=cortex-m3 -x c -E -dM %s -o - 
| FileCheck %s -check-prefix CHECK-M-NODSP
 // RUN: %clang --target=arm-arm-none-eabi -mcpu=cortex-m4 -x c -E -dM %s -o - 
| FileCheck %s -check-prefix CHECK-M-DSP
 // RUN: %clang --target=arm-arm-none-eabi -mcpu=cortex-m7 -x c -E -dM %s -o - 
| FileCheck %s -check-prefix CHECK-M-DSP
+// RUN: %clang --target=arm-arm-none-eabi -mcpu=cortex-m0plus -x c -E -dM %s 
-o - | FileCheck %s -check-prefix CHECK-M-NODSP
+// RUN: %clang --target=arm-arm-none-eabi -mcpu=cortex-m23 -x c -E -dM %s -o - 
| FileCheck %s -check-prefix CHECK-M-NODSP
 // RUN: %clang --target=arm-arm-none-eabi -mcpu=cortex-m33 -x c -E -dM %s -o - 
| FileCheck %s -check-prefix CHECK-M-DSP
 // RUN: %clang --target=arm-arm-none-eabi -march=armv8m.main+dsp -x c -E -dM 
%s -o - | FileCheck %s -check-prefix CHECK-M-DSP
 
 // CHECK-M-DSP: __ARM_FEATURE_DSP 1
 // CHECK-M-DSP: __ARM_FEATURE_SIMD32 1
 
+// CHECK-M-NODSP-NOT: __ARM_FEATURE_DSP 1
+// CHECK-M-NODSP-NOT: __ARM_FEATURE_SIMD32 1
+
 // RUN: %clang -target arm-none-linux-eabi -march=armv8-a -x c -E -dM %s -o - 
| FileCheck %s -check-prefix CHECK-V8A
 
 // CHECK-V8A: __ARM_ARCH 8


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r340911 - [ARM] Set __ARM_FEATURE_SIMD32 for +dsp cores

2018-08-29 Thread Sam Parker via cfe-commits 
Author: sam_parker
Date: Wed Aug 29 03:39:03 2018
New Revision: 340911

URL: http://llvm.org/viewvc/llvm-project?rev=340911=rev
Log:
[ARM] Set __ARM_FEATURE_SIMD32 for +dsp cores

ARM_FEATURE_DSP is already set for targets with the +dsp feature. In
the backend, this target feature is also used to represent the
availability of the of the instructions that the ACLE guard through
the __ARM_FEATURE_SIMD32 macro. We don't have any cores that
implement one and not the other, so set this macro for cores later
than V6 or for Cortex-M cores that the target parser, or user, reports
that the 'dsp' instructions are supported.

Differential Revision: https://reviews.llvm.org/D51093

Modified:
cfe/trunk/lib/Basic/Targets/ARM.cpp
cfe/trunk/test/Preprocessor/arm-acle-6.4.c

Modified: cfe/trunk/lib/Basic/Targets/ARM.cpp
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Basic/Targets/ARM.cpp?rev=340911=340910=340911=diff
==
--- cfe/trunk/lib/Basic/Targets/ARM.cpp (original)
+++ cfe/trunk/lib/Basic/Targets/ARM.cpp Wed Aug 29 03:39:03 2018
@@ -661,7 +661,7 @@ void ARMTargetInfo::getTargetDefines(con
   }
 
   // ACLE 6.4.9 32-bit SIMD instructions
-  if (ArchVersion >= 6 && (CPUProfile != "M" || CPUAttr == "7EM"))
+  if (ArchVersion >= 6 || (CPUProfile == "M" && DSP))
 Builder.defineMacro("__ARM_FEATURE_SIMD32", "1");
 
   // ACLE 6.4.10 Hardware Integer Divide

Modified: cfe/trunk/test/Preprocessor/arm-acle-6.4.c
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/Preprocessor/arm-acle-6.4.c?rev=340911=340910=340911=diff
==
--- cfe/trunk/test/Preprocessor/arm-acle-6.4.c (original)
+++ cfe/trunk/test/Preprocessor/arm-acle-6.4.c Wed Aug 29 03:39:03 2018
@@ -174,10 +174,14 @@
 // CHECK-V7M: __ARM_FEATURE_SAT 1
 // CHECK-V7M: __ARM_FEATURE_UNALIGNED 1
 
-// RUN: %clang -target arm-none-linux-eabi -march=armv7e-m -x c -E -dM %s -o - 
| FileCheck %s -check-prefix CHECK-V7EM
+// RUN: %clang -target arm-none-linux-eabi -march=armv7e-m -x c -E -dM %s -o - 
| FileCheck %s -check-prefix CHECK-M-DSP
+// RUN: %clang --target=arm-arm-none-eabi -mcpu=cortex-m4 -x c -E -dM %s -o - 
| FileCheck %s -check-prefix CHECK-M-DSP
+// RUN: %clang --target=arm-arm-none-eabi -mcpu=cortex-m7 -x c -E -dM %s -o - 
| FileCheck %s -check-prefix CHECK-M-DSP
+// RUN: %clang --target=arm-arm-none-eabi -mcpu=cortex-m33 -x c -E -dM %s -o - 
| FileCheck %s -check-prefix CHECK-M-DSP
+// RUN: %clang --target=arm-arm-none-eabi -march=armv8m.main+dsp -x c -E -dM 
%s -o - | FileCheck %s -check-prefix CHECK-M-DSP
 
-// CHECK-V7EM: __ARM_FEATURE_DSP 1
-// CHECK-V7EM: __ARM_FEATURE_SIMD32 1
+// CHECK-M-DSP: __ARM_FEATURE_DSP 1
+// CHECK-M-DSP: __ARM_FEATURE_SIMD32 1
 
 // RUN: %clang -target arm-none-linux-eabi -march=armv8-a -x c -E -dM %s -o - 
| FileCheck %s -check-prefix CHECK-V8A
 


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r311319 - [ARM][AArch64] Cortex-A75 and Cortex-A55 tests

2017-08-21 Thread Sam Parker via cfe-commits 
Author: sam_parker
Date: Mon Aug 21 01:52:45 2017
New Revision: 311319

URL: http://llvm.org/viewvc/llvm-project?rev=311319=rev
Log:
[ARM][AArch64] Cortex-A75 and Cortex-A55 tests

Add frontend tests for Cortex-A75 and Cortex-A55, Arm's latest
big.LITTLE A-class cores. They implement the ARMv8.2-A architecture,
including the cryptography and RAS extensions, plus the optional dot
product extension. They also implement the RCpc AArch64 extension
from ARMv8.3-A.

Cortex-A75:
https://developer.arm.com/products/processors/cortex-a/cortex-a75

Cortex-A55:
https://developer.arm.com/products/processors/cortex-a/cortex-a55

Differential Revision: https://reviews.llvm.org/D36731

Added:
cfe/trunk/test/Driver/aarch64-dotprod.c
cfe/trunk/test/Driver/aarch64-rcpc.s
cfe/trunk/test/Driver/arm-dotprod.c
Modified:
cfe/trunk/lib/Driver/ToolChains/Arch/ARM.cpp
cfe/trunk/test/Driver/aarch64-cpus.c
cfe/trunk/test/Driver/aarch64-ras.c
cfe/trunk/test/Driver/arm-cortex-cpus.c
cfe/trunk/test/Driver/arm-ras.c

Modified: cfe/trunk/lib/Driver/ToolChains/Arch/ARM.cpp
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Driver/ToolChains/Arch/ARM.cpp?rev=311319=311318=311319=diff
==
--- cfe/trunk/lib/Driver/ToolChains/Arch/ARM.cpp (original)
+++ cfe/trunk/lib/Driver/ToolChains/Arch/ARM.cpp Mon Aug 21 01:52:45 2017
@@ -87,6 +87,15 @@ static bool DecodeARMFeatures(const Driv
   return true;
 }
 
+static void DecodeARMFeaturesFromCPU(const Driver , StringRef CPU,
+ std::vector ) {
+  if (CPU != "generic") {
+llvm::ARM::ArchKind ArchKind = llvm::ARM::parseCPUArch(CPU);
+unsigned Extension = llvm::ARM::getDefaultExtensions(CPU, ArchKind);
+llvm::ARM::getExtensionFeatures(Extension, Features);
+  }
+}
+
 // Check if -march is valid by checking if it can be canonicalised and parsed.
 // getARMArch is used here instead of just checking the -march value in order
 // to handle -march=native correctly.
@@ -331,6 +340,8 @@ void arm::getARMTargetFeatures(const Too
   for (auto  : HostFeatures)
 Features.push_back(
 Args.MakeArgString((F.second ? "+" : "-") + F.first()));
+  } else if (!CPUName.empty()) {
+DecodeARMFeaturesFromCPU(D, CPUName, Features);
   }
 
   // Honor -mfpu=. ClangAs gives preference to -Wa,-mfpu=.

Modified: cfe/trunk/test/Driver/aarch64-cpus.c
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/Driver/aarch64-cpus.c?rev=311319=311318=311319=diff
==
--- cfe/trunk/test/Driver/aarch64-cpus.c (original)
+++ cfe/trunk/test/Driver/aarch64-cpus.c Mon Aug 21 01:52:45 2017
@@ -46,6 +46,19 @@
 // RUN: %clang -target arm64 -mlittle-endian -mtune=cortex-a53 -### -c %s 2>&1 
| FileCheck -check-prefix=ARM64-CA53 %s
 // ARM64-CA53: "-cc1"{{.*}} "-triple" "arm64{{.*}}" "-target-cpu" "cortex-a53"
 
+// RUN: %clang -target aarch64 -mcpu=cortex-a55 -### -c %s 2>&1 | FileCheck 
-check-prefix=CA55 %s
+// RUN: %clang -target aarch64 -mlittle-endian -mcpu=cortex-a55 -### -c %s 
2>&1 | FileCheck -check-prefix=CA55 %s
+// RUN: %clang -target aarch64_be -mlittle-endian -mcpu=cortex-a55 -### -c %s 
2>&1 | FileCheck -check-prefix=CA55 %s
+// RUN: %clang -target aarch64 -mtune=cortex-a55 -### -c %s 2>&1 | FileCheck 
-check-prefix=CA55 %s
+// RUN: %clang -target aarch64_be -mlittle-endian -mtune=cortex-a55 -### -c %s 
2>&1 | FileCheck -check-prefix=CA55 %s
+// CA55: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "cortex-a55"
+
+// RUN: %clang -target arm64 -mcpu=cortex-a55 -### -c %s 2>&1 | FileCheck 
-check-prefix=ARM64-CA55 %s
+// RUN: %clang -target arm64 -mlittle-endian -mcpu=cortex-a55 -### -c %s 2>&1 
| FileCheck -check-prefix=ARM64-CA55 %s
+// RUN: %clang -target arm64 -mtune=cortex-a55 -### -c %s 2>&1 | FileCheck 
-check-prefix=ARM64-CA55 %s
+// RUN: %clang -target arm64 -mlittle-endian -mtune=cortex-a55 -### -c %s 2>&1 
| FileCheck -check-prefix=ARM64-CA55 %s
+// ARM64-CA55: "-cc1"{{.*}} "-triple" "arm64{{.*}}" "-target-cpu" "cortex-a55"
+
 // RUN: %clang -target aarch64 -mcpu=cortex-a57 -### -c %s 2>&1 | FileCheck 
-check-prefix=CA57 %s
 // RUN: %clang -target aarch64 -mlittle-endian -mcpu=cortex-a57 -### -c %s 
2>&1 | FileCheck -check-prefix=CA57 %s
 // RUN: %clang -target aarch64_be -mlittle-endian -mcpu=cortex-a57 -### -c %s 
2>&1 | FileCheck -check-prefix=CA57 %s
@@ -88,6 +101,20 @@
 // RUN: %clang -target arm64 -mlittle-endian -mtune=cortex-a73 -### -c %s 2>&1 
| FileCheck -check-prefix=ARM64-CORTEX-A73 %s
 // ARM64-CORTEX-A73: "-cc1"{{.*}} "-triple" "arm64{{.*}}" "-target-cpu" 
"cortex-a73"
 
+// RUN: %clang -target aarch64 -mcpu=cortex-a75 -### -c %s 2>&1 | FileCheck 
-check-prefix=CORTEX-A75 %s
+// RUN: %clang -target aarch64 -mlittle-endian -mcpu=cortex-a75 -### -c %s 
2>&1 | FileCheck -check-prefix=CORTEX-A75 %s
+// RUN: %clang -target aarch64_be -mlittle-endian

r302131 - [ARM] ACLE Chapter 9 intrinsics

2017-05-04 Thread Sam Parker via cfe-commits 
Author: sam_parker
Date: Thu May  4 03:37:59 2017
New Revision: 302131

URL: http://llvm.org/viewvc/llvm-project?rev=302131=rev
Log:
[ARM] ACLE Chapter 9 intrinsics

Implemented the remaining integer data processing intrinsics from
the ARM ACLE v2.1 spec, such as parallel arithemtic and DSP style
multiplications.

Differential Revision: https://reviews.llvm.org/D32282

Modified:
cfe/trunk/include/clang/Basic/BuiltinsARM.def
cfe/trunk/lib/Headers/arm_acle.h
cfe/trunk/test/CodeGen/arm_acle.c

Modified: cfe/trunk/include/clang/Basic/BuiltinsARM.def
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/include/clang/Basic/BuiltinsARM.def?rev=302131=302130=302131=diff
==
--- cfe/trunk/include/clang/Basic/BuiltinsARM.def (original)
+++ cfe/trunk/include/clang/Basic/BuiltinsARM.def Thu May  4 03:37:59 2017
@@ -25,11 +25,93 @@
 // In libgcc
 BUILTIN(__clear_cache, "vv*v*", "i")
 
+// 16-bit multiplications
+BUILTIN(__builtin_arm_smulbb, "iii", "nc")
+BUILTIN(__builtin_arm_smulbt, "iii", "nc")
+BUILTIN(__builtin_arm_smultb, "iii", "nc")
+BUILTIN(__builtin_arm_smultt, "iii", "nc")
+BUILTIN(__builtin_arm_smulwb, "iii", "nc")
+BUILTIN(__builtin_arm_smulwt, "iii", "nc")
+
 // Saturating arithmetic
 BUILTIN(__builtin_arm_qadd, "iii", "nc")
 BUILTIN(__builtin_arm_qsub, "iii", "nc")
 BUILTIN(__builtin_arm_ssat, "iiUi", "nc")
-BUILTIN(__builtin_arm_usat, "UiUiUi", "nc")
+BUILTIN(__builtin_arm_usat, "UiiUi", "nc")
+
+BUILTIN(__builtin_arm_smlabb, "", "nc")
+BUILTIN(__builtin_arm_smlabt, "", "nc")
+BUILTIN(__builtin_arm_smlatb, "", "nc")
+BUILTIN(__builtin_arm_smlatt, "", "nc")
+BUILTIN(__builtin_arm_smlawb, "", "nc")
+BUILTIN(__builtin_arm_smlawt, "", "nc")
+
+BUILTIN(__builtin_arm_ssat16, "iii", "nc")
+BUILTIN(__builtin_arm_usat16, "iii", "nc")
+
+BUILTIN(__builtin_arm_sxtab16, "iii", "nc")
+BUILTIN(__builtin_arm_sxtb16, "ii", "nc")
+BUILTIN(__builtin_arm_uxtab16, "iii", "nc")
+BUILTIN(__builtin_arm_uxtb16, "ii", "nc")
+
+BUILTIN(__builtin_arm_sel, "iii", "nc")
+
+BUILTIN(__builtin_arm_qadd8, "iii", "nc")
+BUILTIN(__builtin_arm_qsub8, "iii", "nc")
+BUILTIN(__builtin_arm_sadd8, "iii", "nc")
+BUILTIN(__builtin_arm_shadd8, "iii", "nc")
+BUILTIN(__builtin_arm_shsub8, "iii", "nc")
+BUILTIN(__builtin_arm_ssub8, "iii", "nc")
+BUILTIN(__builtin_arm_uadd8, "UiUiUi", "nc")
+BUILTIN(__builtin_arm_uhadd8, "UiUiUi", "nc")
+BUILTIN(__builtin_arm_uhsub8, "UiUiUi", "nc")
+BUILTIN(__builtin_arm_uqadd8, "UiUiUi", "nc")
+BUILTIN(__builtin_arm_uqsub8, "UiUiUi", "nc")
+BUILTIN(__builtin_arm_usub8, "UiUiUi", "nc")
+
+// Sum of 8-bit absolute differences
+BUILTIN(__builtin_arm_usad8, "UiUiUi", "nc")
+BUILTIN(__builtin_arm_usada8, "UiUiUiUi", "nc")
+
+// Parallel 16-bit addition and subtraction
+BUILTIN(__builtin_arm_qadd16, "iii", "nc")
+BUILTIN(__builtin_arm_qasx, "iii", "nc")
+BUILTIN(__builtin_arm_qsax, "iii", "nc")
+BUILTIN(__builtin_arm_qsub16, "iii", "nc")
+BUILTIN(__builtin_arm_sadd16, "iii", "nc")
+BUILTIN(__builtin_arm_sasx, "iii", "nc")
+BUILTIN(__builtin_arm_shadd16, "iii", "nc")
+BUILTIN(__builtin_arm_shasx, "iii", "nc")
+BUILTIN(__builtin_arm_shsax, "iii", "nc")
+BUILTIN(__builtin_arm_shsub16, "iii", "nc")
+BUILTIN(__builtin_arm_ssax, "iii", "nc")
+BUILTIN(__builtin_arm_ssub16, "iii", "nc")
+BUILTIN(__builtin_arm_uadd16, "UiUiUi", "nc")
+BUILTIN(__builtin_arm_uasx, "UiUiUi", "nc")
+BUILTIN(__builtin_arm_uhadd16, "UiUiUi", "nc")
+BUILTIN(__builtin_arm_uhasx, "UiUiUi", "nc")
+BUILTIN(__builtin_arm_uhsax, "UiUiUi", "nc")
+BUILTIN(__builtin_arm_uhsub16, "UiUiUi", "nc")
+BUILTIN(__builtin_arm_uqadd16, "UiUiUi", "nc")
+BUILTIN(__builtin_arm_uqasx, "UiUiUi", "nc")
+BUILTIN(__builtin_arm_uqsax, "UiUiUi", "nc")
+BUILTIN(__builtin_arm_uqsub16, "UiUiUi", "nc")
+BUILTIN(__builtin_arm_usax, "UiUiUi", "nc")
+BUILTIN(__builtin_arm_usub16, "UiUiUi", "nc")
+
+// Parallel 16-bit multiplication
+BUILTIN(__builtin_arm_smlad, "", "nc")
+BUILTIN(__builtin_arm_smladx, "", "nc")
+BUILTIN(__builtin_arm_smlald, "LLiiiLLi", "nc")
+BUILTIN(__builtin_arm_smlaldx, "LLiiiLLi", "nc")
+BUILTIN(__builtin_arm_smlsd, "", "nc")
+BUILTIN(__builtin_arm_smlsdx, "", "nc")
+BUILTIN(__builtin_arm_smlsld, "LLiiiLLi", "nc")
+BUILTIN(__builtin_arm_smlsldx, "LLiiiLLi", "nc")
+BUILTIN(__builtin_arm_smuad, "iii", "nc")
+BUILTIN(__builtin_arm_smuadx, "iii", "nc")
+BUILTIN(__builtin_arm_smusd, "iii", "nc")
+BUILTIN(__builtin_arm_smusdx, "iii", "nc")
 
 // Bit manipulation
 BUILTIN(__builtin_arm_rbit, "UiUi", "nc")

Modified: cfe/trunk/lib/Headers/arm_acle.h
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Headers/arm_acle.h?rev=302131=302130=302131=diff
==
--- cfe/trunk/lib/Headers/arm_acle.h (original)
+++ cfe/trunk/lib/Headers/arm_acle.h Thu May  4 03:37:59 2017
@@ -225,19 +225,49 @@ __rbitl(unsigned long __t) {
 }
 
 /*
+ * 9.3 16-bit multiplications
+ */
+#if

Re: [PATCH] D18311: Clang tests for ARM Cortex-A32 support.

2016-03-21 Thread Sam Parker via cfe-commits 
samparker updated this revision to Diff 51173.
samparker added a comment.

Combined the two diffs


http://reviews.llvm.org/D18311

Files:
  test/CodeGen/arm-target-features.c
  test/Driver/arm-cortex-cpus.c
  test/Preprocessor/arm-target-features.c

Index: test/Preprocessor/arm-target-features.c
===
--- test/Preprocessor/arm-target-features.c
+++ test/Preprocessor/arm-target-features.c
@@ -345,16 +345,18 @@
 // SWIFT-THUMB:#define __ARM_FEATURE_DSP
 // SWIFT-THUMB:#define __ARM_FP 0xE
 
-// Test whether predefines are as expected when targeting cortex-a53.
-// RUN: %clang -target armv8 -mcpu=cortex-a53 -x c -E -dM %s -o - | FileCheck --check-prefix=A53-ARM %s
-// A53-ARM:#define __ARM_ARCH_EXT_IDIV__ 1
-// A53-ARM:#define __ARM_FEATURE_DSP
-// A53-ARM:#define __ARM_FP 0xE
-
-// RUN: %clang -target armv8 -mthumb -mcpu=cortex-a53 -x c -E -dM %s -o - | FileCheck --check-prefix=A53-THUMB %s
-// A53-THUMB:#define __ARM_ARCH_EXT_IDIV__ 1
-// A53-THUMB:#define __ARM_FEATURE_DSP
-// A53-THUMB:#define __ARM_FP 0xE
+// Test whether predefines are as expected when targeting ARMv8-A Cortex implementations
+// RUN: %clang -target armv8 -mcpu=cortex-a32 -x c -E -dM %s -o - | FileCheck --check-prefix=ARMV8-ARM %s
+// RUN: %clang -target armv8 -mcpu=cortex-a53 -x c -E -dM %s -o - | FileCheck --check-prefix=ARMV8-ARM %s
+// ARMV8-ARM:#define __ARM_ARCH_EXT_IDIV__ 1
+// ARMV8-ARM:#define __ARM_FEATURE_DSP
+// ARMV8-ARM:#define __ARM_FP 0xE
+
+// RUN: %clang -target armv8 -mthumb -mcpu=cortex-a32 -x c -E -dM %s -o - | FileCheck --check-prefix=ARMV8-THUMB %s
+// RUN: %clang -target armv8 -mthumb -mcpu=cortex-a53 -x c -E -dM %s -o - | FileCheck --check-prefix=ARMV8-THUMB %s
+// ARMV8-THUMB:#define __ARM_ARCH_EXT_IDIV__ 1
+// ARMV8-THUMB:#define __ARM_FEATURE_DSP
+// ARMV8-THUMB:#define __ARM_FP 0xE
 
 // Test whether predefines are as expected when targeting cortex-r4.
 // RUN: %clang -target armv7 -mcpu=cortex-r4 -x c -E -dM %s -o - | FileCheck --check-prefix=R4-ARM %s
Index: test/Driver/arm-cortex-cpus.c
===
--- test/Driver/arm-cortex-cpus.c
+++ test/Driver/arm-cortex-cpus.c
@@ -463,11 +463,13 @@
 // RUN: %clang -target arm-linux-gnueabi -mcpu=cortex-r8 -mbig-endian -mthumb -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-BE-CPUV7R-THUMB %s
 // CHECK-BE-CPUV7R-THUMB: "-cc1"{{.*}} "-triple" "thumbebv7r-{{.*}}
 
+// RUN: %clang -target arm -mcpu=cortex-a32 -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-CPUV8A %s
 // RUN: %clang -target arm -mcpu=cortex-a35 -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-CPUV8A %s
 // RUN: %clang -target arm -mcpu=cortex-a53 -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-CPUV8A %s
 // RUN: %clang -target arm -mcpu=cortex-a57 -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-CPUV8A %s
 // RUN: %clang -target arm -mcpu=cortex-a72 -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-CPUV8A %s
 // RUN: %clang -target arm -mcpu=exynos-m1 -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-CPUV8A %s
+// RUN: %clang -target arm -mcpu=cortex-a32 -mlittle-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-CPUV8A %s
 // RUN: %clang -target arm -mcpu=cortex-a35 -mlittle-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-CPUV8A %s
 // RUN: %clang -target arm -mcpu=cortex-a53 -mlittle-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-CPUV8A %s
 // RUN: %clang -target arm -mcpu=cortex-a57 -mlittle-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-CPUV8A %s
@@ -475,11 +477,13 @@
 // RUN: %clang -target arm -mcpu=exynos-m1 -mlittle-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-CPUV8A %s
 // CHECK-CPUV8A: "-cc1"{{.*}} "-triple" "armv8-{{.*}}
 
+// RUN: %clang -target armeb -mcpu=cortex-a32 -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-BE-CPUV8A %s
 // RUN: %clang -target armeb -mcpu=cortex-a35 -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-BE-CPUV8A %s
 // RUN: %clang -target armeb -mcpu=cortex-a53 -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-BE-CPUV8A %s
 // RUN: %clang -target armeb -mcpu=cortex-a57 -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-BE-CPUV8A %s
 // RUN: %clang -target armeb -mcpu=cortex-a72 -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-BE-CPUV8A %s
 // RUN: %clang -target armeb -mcpu=exynos-m1 -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-BE-CPUV8A %s
+// RUN: %clang -target arm -mcpu=cortex-a32 -mbig-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-BE-CPUV8A %s
 // RUN: %clang -target arm -mcpu=cortex-a35 -mbig-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-BE-CPUV8A %s
 // RUN: %clang -target arm -mcpu=cortex-a53 -mbig-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-BE-CPUV8A %s
 // RUN: %clang -target arm -mcpu=cortex-a57 -mbig-endian -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-BE-CPUV8A %s
@@ -487,11 +491,13 @@
 // RUN: %clang -target arm -mcpu=exynos-m1 -mbig-endian -### -c %s 2>&1 | FileCheck

Re: [PATCH] D18311: Clang tests for ARM Cortex-A32 support.

2016-03-21 Thread Sam Parker via cfe-commits 
samparker added a comment.

Hi Renato,

Thanks for the tips, one patch makes much more sense. I'm currently in the 
process of obtaining commit access and this patch depends on 
http://reviews.llvm.org/D18239.

Thanks again,
sam


http://reviews.llvm.org/D18311



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Re: [PATCH] D18311: Clang tests for ARM Cortex-A32 support.

2016-03-21 Thread Sam Parker via cfe-commits 
samparker updated this revision to Diff 51165.
samparker added a comment.

Changed A53-ARM and A53-THUMB test prefixes to ARMV8-ARM and ARMV8-THUMB.


http://reviews.llvm.org/D18311

Files:
  test/Preprocessor/arm-target-features.c

Index: test/Preprocessor/arm-target-features.c
===
--- test/Preprocessor/arm-target-features.c
+++ test/Preprocessor/arm-target-features.c
@@ -346,17 +346,17 @@
 // SWIFT-THUMB:#define __ARM_FP 0xE
 
 // Test whether predefines are as expected when targeting ARMv8-A Cortex 
implementations
-// RUN: %clang -target armv8 -mcpu=cortex-a32 -x c -E -dM %s -o - | FileCheck 
--check-prefix=A53-ARM %s
-// RUN: %clang -target armv8 -mcpu=cortex-a53 -x c -E -dM %s -o - | FileCheck 
--check-prefix=A53-ARM %s
-// A53-ARM:#define __ARM_ARCH_EXT_IDIV__ 1
-// A53-ARM:#define __ARM_FEATURE_DSP
-// A53-ARM:#define __ARM_FP 0xE
-
-// RUN: %clang -target armv8 -mthumb -mcpu=cortex-a32 -x c -E -dM %s -o - | 
FileCheck --check-prefix=A53-THUMB %s
-// RUN: %clang -target armv8 -mthumb -mcpu=cortex-a53 -x c -E -dM %s -o - | 
FileCheck --check-prefix=A53-THUMB %s
-// A53-THUMB:#define __ARM_ARCH_EXT_IDIV__ 1
-// A53-THUMB:#define __ARM_FEATURE_DSP
-// A53-THUMB:#define __ARM_FP 0xE
+// RUN: %clang -target armv8 -mcpu=cortex-a32 -x c -E -dM %s -o - | FileCheck 
--check-prefix=ARMV8-ARM %s
+// RUN: %clang -target armv8 -mcpu=cortex-a53 -x c -E -dM %s -o - | FileCheck 
--check-prefix=ARMV8-ARM %s
+// ARMV8-ARM:#define __ARM_ARCH_EXT_IDIV__ 1
+// ARMV8-ARM:#define __ARM_FEATURE_DSP
+// ARMV8-ARM:#define __ARM_FP 0xE
+
+// RUN: %clang -target armv8 -mthumb -mcpu=cortex-a32 -x c -E -dM %s -o - | 
FileCheck --check-prefix=ARMV8-THUMB %s
+// RUN: %clang -target armv8 -mthumb -mcpu=cortex-a53 -x c -E -dM %s -o - | 
FileCheck --check-prefix=ARMV8-THUMB %s
+// ARMV8-THUMB:#define __ARM_ARCH_EXT_IDIV__ 1
+// ARMV8-THUMB:#define __ARM_FEATURE_DSP
+// ARMV8-THUMB:#define __ARM_FP 0xE
 
 // Test whether predefines are as expected when targeting cortex-r4.
 // RUN: %clang -target armv7 -mcpu=cortex-r4 -x c -E -dM %s -o - | FileCheck 
--check-prefix=R4-ARM %s


Index: test/Preprocessor/arm-target-features.c
===
--- test/Preprocessor/arm-target-features.c
+++ test/Preprocessor/arm-target-features.c
@@ -346,17 +346,17 @@
 // SWIFT-THUMB:#define __ARM_FP 0xE
 
 // Test whether predefines are as expected when targeting ARMv8-A Cortex implementations
-// RUN: %clang -target armv8 -mcpu=cortex-a32 -x c -E -dM %s -o - | FileCheck --check-prefix=A53-ARM %s
-// RUN: %clang -target armv8 -mcpu=cortex-a53 -x c -E -dM %s -o - | FileCheck --check-prefix=A53-ARM %s
-// A53-ARM:#define __ARM_ARCH_EXT_IDIV__ 1
-// A53-ARM:#define __ARM_FEATURE_DSP
-// A53-ARM:#define __ARM_FP 0xE
-
-// RUN: %clang -target armv8 -mthumb -mcpu=cortex-a32 -x c -E -dM %s -o - | FileCheck --check-prefix=A53-THUMB %s
-// RUN: %clang -target armv8 -mthumb -mcpu=cortex-a53 -x c -E -dM %s -o - | FileCheck --check-prefix=A53-THUMB %s
-// A53-THUMB:#define __ARM_ARCH_EXT_IDIV__ 1
-// A53-THUMB:#define __ARM_FEATURE_DSP
-// A53-THUMB:#define __ARM_FP 0xE
+// RUN: %clang -target armv8 -mcpu=cortex-a32 -x c -E -dM %s -o - | FileCheck --check-prefix=ARMV8-ARM %s
+// RUN: %clang -target armv8 -mcpu=cortex-a53 -x c -E -dM %s -o - | FileCheck --check-prefix=ARMV8-ARM %s
+// ARMV8-ARM:#define __ARM_ARCH_EXT_IDIV__ 1
+// ARMV8-ARM:#define __ARM_FEATURE_DSP
+// ARMV8-ARM:#define __ARM_FP 0xE
+
+// RUN: %clang -target armv8 -mthumb -mcpu=cortex-a32 -x c -E -dM %s -o - | FileCheck --check-prefix=ARMV8-THUMB %s
+// RUN: %clang -target armv8 -mthumb -mcpu=cortex-a53 -x c -E -dM %s -o - | FileCheck --check-prefix=ARMV8-THUMB %s
+// ARMV8-THUMB:#define __ARM_ARCH_EXT_IDIV__ 1
+// ARMV8-THUMB:#define __ARM_FEATURE_DSP
+// ARMV8-THUMB:#define __ARM_FP 0xE
 
 // Test whether predefines are as expected when targeting cortex-r4.
 // RUN: %clang -target armv7 -mcpu=cortex-r4 -x c -E -dM %s -o - | FileCheck --check-prefix=R4-ARM %s
___
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[PATCH] D18311: Clang tests for ARM Cortex-A32 support.

2016-03-21 Thread Sam Parker via cfe-commits 
samparker created this revision.
samparker added a subscriber: cfe-commits.
Herald added subscribers: rengolin, aemerson.

http://reviews.llvm.org/D18311

Files:
  test/CodeGen/arm-target-features.c
  test/Driver/arm-cortex-cpus.c
  test/Preprocessor/arm-target-features.c

Index: test/Preprocessor/arm-target-features.c
===
--- test/Preprocessor/arm-target-features.c
+++ test/Preprocessor/arm-target-features.c
@@ -345,12 +345,14 @@
 // SWIFT-THUMB:#define __ARM_FEATURE_DSP
 // SWIFT-THUMB:#define __ARM_FP 0xE
 
-// Test whether predefines are as expected when targeting cortex-a53.
+// Test whether predefines are as expected when targeting ARMv8-A Cortex 
implementations
+// RUN: %clang -target armv8 -mcpu=cortex-a32 -x c -E -dM %s -o - | FileCheck 
--check-prefix=A53-ARM %s
 // RUN: %clang -target armv8 -mcpu=cortex-a53 -x c -E -dM %s -o - | FileCheck 
--check-prefix=A53-ARM %s
 // A53-ARM:#define __ARM_ARCH_EXT_IDIV__ 1
 // A53-ARM:#define __ARM_FEATURE_DSP
 // A53-ARM:#define __ARM_FP 0xE
 
+// RUN: %clang -target armv8 -mthumb -mcpu=cortex-a32 -x c -E -dM %s -o - | 
FileCheck --check-prefix=A53-THUMB %s
 // RUN: %clang -target armv8 -mthumb -mcpu=cortex-a53 -x c -E -dM %s -o - | 
FileCheck --check-prefix=A53-THUMB %s
 // A53-THUMB:#define __ARM_ARCH_EXT_IDIV__ 1
 // A53-THUMB:#define __ARM_FEATURE_DSP
Index: test/Driver/arm-cortex-cpus.c
===
--- test/Driver/arm-cortex-cpus.c
+++ test/Driver/arm-cortex-cpus.c
@@ -458,11 +458,13 @@
 // RUN: %clang -target arm-linux-gnueabi -mcpu=cortex-r8 -mbig-endian -mthumb 
-### -c %s 2>&1 | FileCheck -check-prefix=CHECK-BE-CPUV7R-THUMB %s
 // CHECK-BE-CPUV7R-THUMB: "-cc1"{{.*}} "-triple" "thumbebv7r-{{.*}}
 
+// RUN: %clang -target arm -mcpu=cortex-a32 -### -c %s 2>&1 | FileCheck 
-check-prefix=CHECK-CPUV8A %s
 // RUN: %clang -target arm -mcpu=cortex-a35 -### -c %s 2>&1 | FileCheck 
-check-prefix=CHECK-CPUV8A %s
 // RUN: %clang -target arm -mcpu=cortex-a53 -### -c %s 2>&1 | FileCheck 
-check-prefix=CHECK-CPUV8A %s
 // RUN: %clang -target arm -mcpu=cortex-a57 -### -c %s 2>&1 | FileCheck 
-check-prefix=CHECK-CPUV8A %s
 // RUN: %clang -target arm -mcpu=cortex-a72 -### -c %s 2>&1 | FileCheck 
-check-prefix=CHECK-CPUV8A %s
 // RUN: %clang -target arm -mcpu=exynos-m1 -### -c %s 2>&1 | FileCheck 
-check-prefix=CHECK-CPUV8A %s
+// RUN: %clang -target arm -mcpu=cortex-a32 -mlittle-endian -### -c %s 2>&1 | 
FileCheck -check-prefix=CHECK-CPUV8A %s
 // RUN: %clang -target arm -mcpu=cortex-a35 -mlittle-endian -### -c %s 2>&1 | 
FileCheck -check-prefix=CHECK-CPUV8A %s
 // RUN: %clang -target arm -mcpu=cortex-a53 -mlittle-endian -### -c %s 2>&1 | 
FileCheck -check-prefix=CHECK-CPUV8A %s
 // RUN: %clang -target arm -mcpu=cortex-a57 -mlittle-endian -### -c %s 2>&1 | 
FileCheck -check-prefix=CHECK-CPUV8A %s
@@ -470,11 +472,13 @@
 // RUN: %clang -target arm -mcpu=exynos-m1 -mlittle-endian -### -c %s 2>&1 | 
FileCheck -check-prefix=CHECK-CPUV8A %s
 // CHECK-CPUV8A: "-cc1"{{.*}} "-triple" "armv8-{{.*}}
 
+// RUN: %clang -target armeb -mcpu=cortex-a32 -### -c %s 2>&1 | FileCheck 
-check-prefix=CHECK-BE-CPUV8A %s
 // RUN: %clang -target armeb -mcpu=cortex-a35 -### -c %s 2>&1 | FileCheck 
-check-prefix=CHECK-BE-CPUV8A %s
 // RUN: %clang -target armeb -mcpu=cortex-a53 -### -c %s 2>&1 | FileCheck 
-check-prefix=CHECK-BE-CPUV8A %s
 // RUN: %clang -target armeb -mcpu=cortex-a57 -### -c %s 2>&1 | FileCheck 
-check-prefix=CHECK-BE-CPUV8A %s
 // RUN: %clang -target armeb -mcpu=cortex-a72 -### -c %s 2>&1 | FileCheck 
-check-prefix=CHECK-BE-CPUV8A %s
 // RUN: %clang -target armeb -mcpu=exynos-m1 -### -c %s 2>&1 | FileCheck 
-check-prefix=CHECK-BE-CPUV8A %s
+// RUN: %clang -target arm -mcpu=cortex-a32 -mbig-endian -### -c %s 2>&1 | 
FileCheck -check-prefix=CHECK-BE-CPUV8A %s
 // RUN: %clang -target arm -mcpu=cortex-a35 -mbig-endian -### -c %s 2>&1 | 
FileCheck -check-prefix=CHECK-BE-CPUV8A %s
 // RUN: %clang -target arm -mcpu=cortex-a53 -mbig-endian -### -c %s 2>&1 | 
FileCheck -check-prefix=CHECK-BE-CPUV8A %s
 // RUN: %clang -target arm -mcpu=cortex-a57 -mbig-endian -### -c %s 2>&1 | 
FileCheck -check-prefix=CHECK-BE-CPUV8A %s
@@ -482,11 +486,13 @@
 // RUN: %clang -target arm -mcpu=exynos-m1 -mbig-endian -### -c %s 2>&1 | 
FileCheck -check-prefix=CHECK-BE-CPUV8A %s
 // CHECK-BE-CPUV8A: "-cc1"{{.*}} "-triple" "armebv8-{{.*}}
 
+// RUN: %clang -target arm -mcpu=cortex-a32 -mthumb -### -c %s 2>&1 | 
FileCheck -check-prefix=CHECK-CPUV8A-THUMB %s
 // RUN: %clang -target arm -mcpu=cortex-a35 -mthumb -### -c %s 2>&1 | 
FileCheck -check-prefix=CHECK-CPUV8A-THUMB %s
 // RUN: %clang -target arm -mcpu=cortex-a53 -mthumb -### -c %s 2>&1 | 
FileCheck -check-prefix=CHECK-CPUV8A-THUMB %s
 // RUN: %clang -target arm -mcpu=cortex-a57 -mthumb -### -c %s 2>&1 | 
FileCheck -check-prefix=CHECK-CPUV8A-THUMB %s
 // RUN: %clang -target arm -mcpu=cortex-a72 -mthumb -### -c %s 2>&1 | 
FileCheck