r340391 - [clang][mips] Set __mips_fpr correctly for -mfpxx
Author: smaksimovic
Date: Wed Aug 22 02:26:25 2018
New Revision: 340391
URL: http://llvm.org/viewvc/llvm-project?rev=340391=rev
Log:
[clang][mips] Set __mips_fpr correctly for -mfpxx
Set __mips_fpr to 0 if o32 ABI is used with either -mfpxx
or none of -mfp32, -mfpxx, -mfp64 being specified.
Introduce additional checks:
-mfpxx is only to be used in conjunction with the o32 ABI.
report an error when incompatible options are provided.
Formerly no errors were raised when combining n32/n64 ABIs
with -mfp32 and -mfpxx.
There are other cases when __mips_fpr should be set to 0
that are not covered, ex. using o32 on a mips64 cpu
which is valid but not supported in the backend as of yet.
Differential Revision: https://reviews.llvm.org/D50557
Modified:
cfe/trunk/include/clang/Basic/DiagnosticCommonKinds.td
cfe/trunk/lib/Basic/Targets/Mips.cpp
cfe/trunk/lib/Basic/Targets/Mips.h
cfe/trunk/test/Preprocessor/init.c
Modified: cfe/trunk/include/clang/Basic/DiagnosticCommonKinds.td
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/include/clang/Basic/DiagnosticCommonKinds.td?rev=340391=340390=340391=diff
==
--- cfe/trunk/include/clang/Basic/DiagnosticCommonKinds.td (original)
+++ cfe/trunk/include/clang/Basic/DiagnosticCommonKinds.td Wed Aug 22 02:26:25
2018
@@ -199,6 +199,9 @@ def err_target_unknown_abi : Error<"unkn
def err_target_unsupported_abi : Error<"ABI '%0' is not supported on CPU
'%1'">;
def err_target_unsupported_abi_for_triple : Error<
"ABI '%0' is not supported for '%1'">;
+def err_unsupported_abi_for_opt : Error<"'%0' can only be used with the '%1'
ABI">;
+def err_mips_fp64_req : Error<
+"'%0' can only be used if the target supports the mfhc1 and mthc1
instructions">;
def err_target_unknown_fpmath : Error<"unknown FP unit '%0'">;
def err_target_unsupported_fpmath : Error<
"the '%0' unit is not supported with this instruction set">;
Modified: cfe/trunk/lib/Basic/Targets/Mips.cpp
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Basic/Targets/Mips.cpp?rev=340391=340390=340391=diff
==
--- cfe/trunk/lib/Basic/Targets/Mips.cpp (original)
+++ cfe/trunk/lib/Basic/Targets/Mips.cpp Wed Aug 22 02:26:25 2018
@@ -59,6 +59,16 @@ void MipsTargetInfo::fillValidCPUList(
Values.append(std::begin(ValidCPUNames), std::end(ValidCPUNames));
}
+unsigned MipsTargetInfo::getISARev() const {
+ return llvm::StringSwitch(getCPU())
+ .Cases("mips32", "mips64", 1)
+ .Cases("mips32r2", "mips64r2", 2)
+ .Cases("mips32r3", "mips64r3", 3)
+ .Cases("mips32r5", "mips64r5", 5)
+ .Cases("mips32r6", "mips64r6", 6)
+ .Default(0);
+}
+
void MipsTargetInfo::getTargetDefines(const LangOptions ,
MacroBuilder ) const {
if (BigEndian) {
@@ -84,13 +94,8 @@ void MipsTargetInfo::getTargetDefines(co
Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS64");
}
- const std::string ISARev = llvm::StringSwitch(getCPU())
- .Cases("mips32", "mips64", "1")
- .Cases("mips32r2", "mips64r2", "2")
- .Cases("mips32r3", "mips64r3", "3")
- .Cases("mips32r5", "mips64r5", "5")
- .Cases("mips32r6", "mips64r6", "6")
- .Default("");
+ const std::string ISARev = std::to_string(getISARev());
+
if (!ISARev.empty())
Builder.defineMacro("__mips_isa_rev", ISARev);
@@ -129,9 +134,22 @@ void MipsTargetInfo::getTargetDefines(co
if (IsSingleFloat)
Builder.defineMacro("__mips_single_float", Twine(1));
- Builder.defineMacro("__mips_fpr", HasFP64 ? Twine(64) : Twine(32));
- Builder.defineMacro("_MIPS_FPSET",
- Twine(32 / (HasFP64 || IsSingleFloat ? 1 : 2)));
+ switch (FPMode) {
+ case FPXX:
+Builder.defineMacro("__mips_fpr", Twine(0));
+break;
+ case FP32:
+Builder.defineMacro("__mips_fpr", Twine(32));
+break;
+ case FP64:
+Builder.defineMacro("__mips_fpr", Twine(64));
+break;
+}
+
+ if (FPMode == FP64 || IsSingleFloat)
+Builder.defineMacro("_MIPS_FPSET", Twine(32));
+ else
+Builder.defineMacro("_MIPS_FPSET", Twine(16));
if (IsMips16)
Builder.defineMacro("__mips16", Twine(1));
@@ -189,7 +207,7 @@ void MipsTargetInfo::getTargetDefines(co
bool MipsTargetInfo::hasFeature(StringRef Feature) const {
return llvm::StringSwitch(Feature)
.Case("mips", true)
- .Case("fp64", HasFP64)
+ .Case("fp64", FPMode == FP64)
.Default(false);
}
@@ -235,5 +253,30 @@ bool MipsTargetInfo::validateTarget(Diag
return false;
}
+ // -fpxx is valid only for the o32 ABI
+ if (FPMode == FPXX && (ABI == "n32" || ABI == "n64")) {
+
[libunwind] r339878 - [libunwind][mips] Include gcc_s for linkage
Author: smaksimovic
Date: Thu Aug 16 06:40:16 2018
New Revision: 339878
URL: http://llvm.org/viewvc/llvm-project?rev=339878=rev
Log:
[libunwind][mips] Include gcc_s for linkage
When compiling with optimizations, mips requires various helper
routines(__ashldi3 and the like) contained in libgcc_s.
Conditionally include libgcc_s in the set of libraries to be linked to.
Differential Revision: https://reviews.llvm.org/D50243
Modified:
libunwind/trunk/src/CMakeLists.txt
Modified: libunwind/trunk/src/CMakeLists.txt
URL:
http://llvm.org/viewvc/llvm-project/libunwind/trunk/src/CMakeLists.txt?rev=339878=339877=339878=diff
==
--- libunwind/trunk/src/CMakeLists.txt (original)
+++ libunwind/trunk/src/CMakeLists.txt Thu Aug 16 06:40:16 2018
@@ -52,6 +52,7 @@ set(LIBUNWIND_SOURCES
# Generate library list.
set(libraries ${LIBUNWINDCXX_ABI_LIBRARIES})
append_if(libraries LIBUNWIND_HAS_C_LIB c)
+append_if(libraries LIBUNWIND_HAS_GCC_S_LIB gcc_s)
append_if(libraries LIBUNWIND_HAS_DL_LIB dl)
if (LIBUNWIND_ENABLE_THREADS)
append_if(libraries LIBUNWIND_HAS_PTHREAD_LIB pthread)
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[libunwind] r339848 - [libunwind][mips] Modify the __mips_fpr macro check
Author: smaksimovic Date: Thu Aug 16 01:47:43 2018 New Revision: 339848 URL: http://llvm.org/viewvc/llvm-project?rev=339848=rev Log: [libunwind][mips] Modify the __mips_fpr macro check The __mips_fpr macro can take the value of 0 as well, change to account for that case. Differential Revision: https://reviews.llvm.org/D50245 Modified: libunwind/trunk/src/UnwindRegistersRestore.S libunwind/trunk/src/UnwindRegistersSave.S Modified: libunwind/trunk/src/UnwindRegistersRestore.S URL: http://llvm.org/viewvc/llvm-project/libunwind/trunk/src/UnwindRegistersRestore.S?rev=339848=339847=339848=diff == --- libunwind/trunk/src/UnwindRegistersRestore.S (original) +++ libunwind/trunk/src/UnwindRegistersRestore.S Thu Aug 16 01:47:43 2018 @@ -815,7 +815,7 @@ DEFINE_LIBUNWIND_PRIVATE_FUNCTION(_ZN9li .set noreorder .set nomacro #ifdef __mips_hard_float -#if __mips_fpr == 32 +#if __mips_fpr != 64 ldc1 $f0, (4 * 36 + 8 * 0)($4) ldc1 $f2, (4 * 36 + 8 * 2)($4) ldc1 $f4, (4 * 36 + 8 * 4)($4) Modified: libunwind/trunk/src/UnwindRegistersSave.S URL: http://llvm.org/viewvc/llvm-project/libunwind/trunk/src/UnwindRegistersSave.S?rev=339848=339847=339848=diff == --- libunwind/trunk/src/UnwindRegistersSave.S (original) +++ libunwind/trunk/src/UnwindRegistersSave.S Thu Aug 16 01:47:43 2018 @@ -168,7 +168,7 @@ DEFINE_LIBUNWIND_FUNCTION(unw_getcontext mflo $8 sw$8, (4 * 34)($4) #ifdef __mips_hard_float -#if __mips_fpr == 32 +#if __mips_fpr != 64 sdc1 $f0, (4 * 36 + 8 * 0)($4) sdc1 $f2, (4 * 36 + 8 * 2)($4) sdc1 $f4, (4 * 36 + 8 * 4)($4) ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[libunwind] r339849 - [libunwind][mips] Guard accumulator registers
Author: smaksimovic Date: Thu Aug 16 01:49:50 2018 New Revision: 339849 URL: http://llvm.org/viewvc/llvm-project?rev=339849=rev Log: [libunwind][mips] Guard accumulator registers Mipsr6 does not possess HI and LO accumulator registers, adjust validRegister functions to respect that. Differential Revision: https://reviews.llvm.org/D50244 Modified: libunwind/trunk/src/Registers.hpp Modified: libunwind/trunk/src/Registers.hpp URL: http://llvm.org/viewvc/llvm-project/libunwind/trunk/src/Registers.hpp?rev=339849=339848=339849=diff == --- libunwind/trunk/src/Registers.hpp (original) +++ libunwind/trunk/src/Registers.hpp Thu Aug 16 01:49:50 2018 @@ -2759,10 +2759,12 @@ inline bool Registers_mips_o32::validReg return false; if (regNum <= UNW_MIPS_R31) return true; +#if __mips_isa_rev != 6 if (regNum == UNW_MIPS_HI) return true; if (regNum == UNW_MIPS_LO) return true; +#endif #if defined(__mips_hard_float) && __mips_fpr == 32 if (regNum >= UNW_MIPS_F0 && regNum <= UNW_MIPS_F31) return true; @@ -3073,10 +3075,12 @@ inline bool Registers_mips_newabi::valid return false; if (regNum <= UNW_MIPS_R31) return true; +#if __mips_isa_rev != 6 if (regNum == UNW_MIPS_HI) return true; if (regNum == UNW_MIPS_LO) return true; +#endif // FIXME: Hard float, DSP accumulator registers, MSA registers return false; } ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
Re: r338239 - [mips64][clang] Provide the signext attribute for i32 return values
I missed to include the changes to tests affected by that commit. I've included them in r338246. Regards, Stefan From: Friedman, Eli Sent: 30 July 2018 21:22:45 To: Stefan Maksimovic; cfe-commits@lists.llvm.org Subject: Re: r338239 - [mips64][clang] Provide the signext attribute for i32 return values On 7/30/2018 3:44 AM, Stefan Maksimovic via cfe-commits wrote: > Author: smaksimovic > Date: Mon Jul 30 03:44:46 2018 > New Revision: 338239 > > URL: http://llvm.org/viewvc/llvm-project?rev=338239=rev > Log: > [mips64][clang] Provide the signext attribute for i32 return values > > Additional info: see r338019. > > Differential Revision: https://reviews.llvm.org/D49289 > > Modified: > cfe/trunk/lib/CodeGen/TargetInfo.cpp I'd like to see some test coverage for this. -El -- Employee of Qualcomm Innovation Center, Inc. Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
r338246 - [mips64][clang] Adjust tests to account for changes in r338239
Author: smaksimovic
Date: Mon Jul 30 05:27:40 2018
New Revision: 338246
URL: http://llvm.org/viewvc/llvm-project?rev=338246=rev
Log:
[mips64][clang] Adjust tests to account for changes in r338239
Modified:
cfe/trunk/test/CodeGen/mips-unsigned-ext-var.c
cfe/trunk/test/CodeGen/mips-varargs.c
cfe/trunk/test/CodeGen/mips-vector-arg.c
Modified: cfe/trunk/test/CodeGen/mips-unsigned-ext-var.c
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGen/mips-unsigned-ext-var.c?rev=338246=338245=338246=diff
==
--- cfe/trunk/test/CodeGen/mips-unsigned-ext-var.c (original)
+++ cfe/trunk/test/CodeGen/mips-unsigned-ext-var.c Mon Jul 30 05:27:40 2018
@@ -17,6 +17,6 @@ void foo1() {
foo(1,f);
}
-//N64: call i32 (i32, ...) @foo(i32 signext undef, i32 signext -32)
-//N32: call i32 (i32, ...) @foo(i32 signext undef, i32 signext -32)
-//O32: call i32 (i32, ...) @foo(i32 signext undef, i32 signext -32)
\ No newline at end of file
+//N64: call signext i32 (i32, ...) @foo(i32 signext undef, i32 signext -32)
+//N32: call signext i32 (i32, ...) @foo(i32 signext undef, i32 signext -32)
+//O32: call i32 (i32, ...) @foo(i32 signext undef, i32 signext -32)
Modified: cfe/trunk/test/CodeGen/mips-varargs.c
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGen/mips-varargs.c?rev=338246=338245=338246=diff
==
--- cfe/trunk/test/CodeGen/mips-varargs.c (original)
+++ cfe/trunk/test/CodeGen/mips-varargs.c Mon Jul 30 05:27:40 2018
@@ -19,7 +19,9 @@ int test_i32(char *fmt, ...) {
return v;
}
-// ALL-LABEL: define i32 @test_i32(i8*{{.*}} %fmt, ...)
+// O32-LABEL: define i32 @test_i32(i8*{{.*}} %fmt, ...)
+// N32-LABEL: define signext i32 @test_i32(i8*{{.*}} %fmt, ...)
+// N64-LABEL: define signext i32 @test_i32(i8*{{.*}} %fmt, ...)
//
// O32: %va = alloca i8*, align [[$PTRALIGN:4]]
// N32: %va = alloca i8*, align [[$PTRALIGN:4]]
@@ -133,7 +135,9 @@ int test_v4i32(char *fmt, ...) {
return v[0];
}
-// ALL-LABEL: define i32 @test_v4i32(i8*{{.*}} %fmt, ...)
+// O32-LABEL: define i32 @test_v4i32(i8*{{.*}} %fmt, ...)
+// N32-LABEL: define signext i32 @test_v4i32(i8*{{.*}} %fmt, ...)
+// N64-LABEL: define signext i32 @test_v4i32(i8*{{.*}} %fmt, ...)
//
// ALL: %va = alloca i8*, align [[$PTRALIGN]]
// ALL: [[V:%.+]] = alloca <4 x i32>, align 16
Modified: cfe/trunk/test/CodeGen/mips-vector-arg.c
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGen/mips-vector-arg.c?rev=338246=338245=338246=diff
==
--- cfe/trunk/test/CodeGen/mips-vector-arg.c (original)
+++ cfe/trunk/test/CodeGen/mips-vector-arg.c Mon Jul 30 05:27:40 2018
@@ -11,7 +11,7 @@ typedef int v4i32 __attribute__ ((__vect
// O32: define void @test_v4sf(i32 inreg %a1.coerce0, i32 inreg %a1.coerce1,
i32 inreg %a1.coerce2, i32 inreg %a1.coerce3, i32 signext %a2, i32, i32 inreg
%a3.coerce0, i32 inreg %a3.coerce1, i32 inreg %a3.coerce2, i32 inreg
%a3.coerce3) local_unnamed_addr [[NUW:#[0-9]+]]
// O32: declare i32 @test_v4sf_2(i32 inreg, i32 inreg, i32 inreg, i32 inreg,
i32 signext, i32, i32 inreg, i32 inreg, i32 inreg, i32 inreg)
// N64: define void @test_v4sf(i64 inreg %a1.coerce0, i64 inreg %a1.coerce1,
i32 signext %a2, i64, i64 inreg %a3.coerce0, i64 inreg %a3.coerce1)
local_unnamed_addr [[NUW:#[0-9]+]]
-// N64: declare i32 @test_v4sf_2(i64 inreg, i64 inreg, i32 signext, i64, i64
inreg, i64 inreg)
+// N64: declare signext i32 @test_v4sf_2(i64 inreg, i64 inreg, i32 signext,
i64, i64 inreg, i64 inreg)
extern test_v4sf_2(v4sf, int, v4sf);
void test_v4sf(v4sf a1, int a2, v4sf a3) {
test_v4sf_2(a3, a2, a1);
@@ -20,7 +20,7 @@ void test_v4sf(v4sf a1, int a2, v4sf a3)
// O32: define void @test_v4i32(i32 inreg %a1.coerce0, i32 inreg %a1.coerce1,
i32 inreg %a1.coerce2, i32 inreg %a1.coerce3, i32 signext %a2, i32, i32 inreg
%a3.coerce0, i32 inreg %a3.coerce1, i32 inreg %a3.coerce2, i32 inreg
%a3.coerce3) local_unnamed_addr [[NUW]]
// O32: declare i32 @test_v4i32_2(i32 inreg, i32 inreg, i32 inreg, i32 inreg,
i32 signext, i32, i32 inreg, i32 inreg, i32 inreg, i32 inreg)
// N64: define void @test_v4i32(i64 inreg %a1.coerce0, i64 inreg %a1.coerce1,
i32 signext %a2, i64, i64 inreg %a3.coerce0, i64 inreg %a3.coerce1)
local_unnamed_addr [[NUW]]
-// N64: declare i32 @test_v4i32_2(i64 inreg, i64 inreg, i32 signext, i64, i64
inreg, i64 inreg)
+// N64: declare signext i32 @test_v4i32_2(i64 inreg, i64 inreg, i32 signext,
i64, i64 inreg, i64 inreg)
extern test_v4i32_2(v4i32, int, v4i32);
void test_v4i32(v4i32 a1, int a2, v4i32 a3) {
test_v4i32_2(a3, a2, a1);
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r338239 - [mips64][clang] Provide the signext attribute for i32 return values
Author: smaksimovic
Date: Mon Jul 30 03:44:46 2018
New Revision: 338239
URL: http://llvm.org/viewvc/llvm-project?rev=338239=rev
Log:
[mips64][clang] Provide the signext attribute for i32 return values
Additional info: see r338019.
Differential Revision: https://reviews.llvm.org/D49289
Modified:
cfe/trunk/lib/CodeGen/TargetInfo.cpp
Modified: cfe/trunk/lib/CodeGen/TargetInfo.cpp
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/CodeGen/TargetInfo.cpp?rev=338239=338238=338239=diff
==
--- cfe/trunk/lib/CodeGen/TargetInfo.cpp (original)
+++ cfe/trunk/lib/CodeGen/TargetInfo.cpp Mon Jul 30 03:44:46 2018
@@ -6985,8 +6985,14 @@ ABIArgInfo MipsABIInfo::classifyReturnTy
if (const EnumType *EnumTy = RetTy->getAs())
RetTy = EnumTy->getDecl()->getIntegerType();
- return (RetTy->isPromotableIntegerType() ? ABIArgInfo::getExtend(RetTy)
- : ABIArgInfo::getDirect());
+ if (RetTy->isPromotableIntegerType())
+return ABIArgInfo::getExtend(RetTy);
+
+ if ((RetTy->isUnsignedIntegerOrEnumerationType() ||
+ RetTy->isSignedIntegerOrEnumerationType()) && Size == 32 && !IsO32)
+return ABIArgInfo::getSignExtend(RetTy);
+
+ return ABIArgInfo::getDirect();
}
void MipsABIInfo::computeInfo(CGFunctionInfo ) const {
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r325899 - [mips] Revert r325872
Author: smaksimovic
Date: Fri Feb 23 05:46:14 2018
New Revision: 325899
URL: http://llvm.org/viewvc/llvm-project?rev=325899=rev
Log:
[mips] Revert r325872
There are still outstanding issues with byVal arguments
that prevent this from being committed. Revert for now.
Removed:
cfe/trunk/test/CodeGen/mips-aggregate-arg.c
Modified:
cfe/trunk/lib/CodeGen/TargetInfo.cpp
Modified: cfe/trunk/lib/CodeGen/TargetInfo.cpp
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/CodeGen/TargetInfo.cpp?rev=325899=325898=325899=diff
==
--- cfe/trunk/lib/CodeGen/TargetInfo.cpp (original)
+++ cfe/trunk/lib/CodeGen/TargetInfo.cpp Fri Feb 23 05:46:14 2018
@@ -6870,14 +6870,6 @@ MipsABIInfo::classifyArgumentType(QualTy
return getNaturalAlignIndirect(Ty, RAA == CGCXXABI::RAA_DirectInMemory);
}
-// Use indirect if the aggregate cannot fit into registers for
-// passing arguments according to the ABI
-unsigned Threshold = IsO32 ? 16 : 64;
-
-if(getContext().getTypeSizeInChars(Ty) >
CharUnits::fromQuantity(Threshold))
- return ABIArgInfo::getIndirect(CharUnits::fromQuantity(Align), true,
- getContext().getTypeAlign(Ty) / 8 >
Align);
-
// If we have reached here, aggregates are passed directly by coercing to
// another structure type. Padding is inserted if the offset of the
// aggregate is unaligned.
Removed: cfe/trunk/test/CodeGen/mips-aggregate-arg.c
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGen/mips-aggregate-arg.c?rev=325898=auto
==
--- cfe/trunk/test/CodeGen/mips-aggregate-arg.c (original)
+++ cfe/trunk/test/CodeGen/mips-aggregate-arg.c (removed)
@@ -1,38 +0,0 @@
-// RUN: %clang_cc1 -triple mipsel-unknown-linux-gnu -S -emit-llvm -o - %s |
FileCheck -check-prefix=O32 %s
-// RUN: %clang_cc1 -triple mips64el-unknown-linux-gnu -S -emit-llvm -o - %s
-target-abi n32 | FileCheck -check-prefix=N32-N64 %s
-// RUN: %clang_cc1 -triple mips64el-unknown-linux-gnu -S -emit-llvm -o - %s
-target-abi n64 | FileCheck -check-prefix=N32-N64 %s
-
-struct t1 {
- char t1[10];
-};
-
-struct t2 {
- char t2[20];
-};
-
-struct t3 {
- char t3[65];
-};
-
-extern struct t1 g1;
-extern struct t2 g2;
-extern struct t3 g3;
-extern void f1(struct t1);
-extern void f2(struct t2);
-extern void f3(struct t3);
-
-void f() {
-
-// O32: call void @f1(i32 inreg %{{[0-9]+}}, i32 inreg %{{[0-9]+}}, i16 inreg
%{{[0-9]+}})
-// O32: call void @f2(%struct.t2* byval align 4 %{{.*}})
-// O32: call void @f3(%struct.t3* byval align 4 %{{.*}})
-
-// N32-N64: call void @f1(i64 inreg %{{[0-9]+}}, i16 inreg %{{[0-9]+}})
-// N32-N64: call void @f2(i64 inreg %{{[0-9]+}}, i64 inreg %{{[0-9]+}}, i32
inreg %{{[0-9]+}})
-// N32-N64: call void @f3(%struct.t3* byval align 8 %{{.*}})
-
- f1(g1);
- f2(g2);
- f3(g3);
-}
-
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r325872 - [mips] Reland r310704
Author: smaksimovic Date: Fri Feb 23 00:37:48 2018 New Revision: 325872 URL: http://llvm.org/viewvc/llvm-project?rev=325872=rev Log: [mips] Reland r310704 Recommit this change which was previously reverted for the 5.0.0 release since the failures identified were dealt with in r325782. Added: cfe/trunk/test/CodeGen/mips-aggregate-arg.c - copied unchanged from r310703, cfe/trunk/test/CodeGen/mips-aggregate-arg.c Modified: cfe/trunk/lib/CodeGen/TargetInfo.cpp Modified: cfe/trunk/lib/CodeGen/TargetInfo.cpp URL: http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/CodeGen/TargetInfo.cpp?rev=325872=325871=325872=diff == --- cfe/trunk/lib/CodeGen/TargetInfo.cpp (original) +++ cfe/trunk/lib/CodeGen/TargetInfo.cpp Fri Feb 23 00:37:48 2018 @@ -6870,6 +6870,14 @@ MipsABIInfo::classifyArgumentType(QualTy return getNaturalAlignIndirect(Ty, RAA == CGCXXABI::RAA_DirectInMemory); } +// Use indirect if the aggregate cannot fit into registers for +// passing arguments according to the ABI +unsigned Threshold = IsO32 ? 16 : 64; + +if(getContext().getTypeSizeInChars(Ty) > CharUnits::fromQuantity(Threshold)) + return ABIArgInfo::getIndirect(CharUnits::fromQuantity(Align), true, + getContext().getTypeAlign(Ty) / 8 > Align); + // If we have reached here, aggregates are passed directly by coercing to // another structure type. Padding is inserted if the offset of the // aggregate is unaligned. ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
r310704 - Revert r302670 for the upcoming 5.0.0 release
Author: smaksimovic
Date: Fri Aug 11 04:39:07 2017
New Revision: 310704
URL: http://llvm.org/viewvc/llvm-project?rev=310704=rev
Log:
Revert r302670 for the upcoming 5.0.0 release
This is causing failures when compiling clang with -O3
as one of the structures used by clang is passed by
value and uses the fastcc calling convention.
Faliures manifest for stage2 mips build.
Removed:
cfe/trunk/test/CodeGen/mips-aggregate-arg.c
Modified:
cfe/trunk/lib/CodeGen/TargetInfo.cpp
Modified: cfe/trunk/lib/CodeGen/TargetInfo.cpp
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/CodeGen/TargetInfo.cpp?rev=310704=310703=310704=diff
==
--- cfe/trunk/lib/CodeGen/TargetInfo.cpp (original)
+++ cfe/trunk/lib/CodeGen/TargetInfo.cpp Fri Aug 11 04:39:07 2017
@@ -6821,14 +6821,6 @@ MipsABIInfo::classifyArgumentType(QualTy
return getNaturalAlignIndirect(Ty, RAA == CGCXXABI::RAA_DirectInMemory);
}
-// Use indirect if the aggregate cannot fit into registers for
-// passing arguments according to the ABI
-unsigned Threshold = IsO32 ? 16 : 64;
-
-if(getContext().getTypeSizeInChars(Ty) >
CharUnits::fromQuantity(Threshold))
- return ABIArgInfo::getIndirect(CharUnits::fromQuantity(Align), true,
- getContext().getTypeAlign(Ty) / 8 >
Align);
-
// If we have reached here, aggregates are passed directly by coercing to
// another structure type. Padding is inserted if the offset of the
// aggregate is unaligned.
Removed: cfe/trunk/test/CodeGen/mips-aggregate-arg.c
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGen/mips-aggregate-arg.c?rev=310703=auto
==
--- cfe/trunk/test/CodeGen/mips-aggregate-arg.c (original)
+++ cfe/trunk/test/CodeGen/mips-aggregate-arg.c (removed)
@@ -1,38 +0,0 @@
-// RUN: %clang_cc1 -triple mipsel-unknown-linux-gnu -S -emit-llvm -o - %s |
FileCheck -check-prefix=O32 %s
-// RUN: %clang_cc1 -triple mips64el-unknown-linux-gnu -S -emit-llvm -o - %s
-target-abi n32 | FileCheck -check-prefix=N32-N64 %s
-// RUN: %clang_cc1 -triple mips64el-unknown-linux-gnu -S -emit-llvm -o - %s
-target-abi n64 | FileCheck -check-prefix=N32-N64 %s
-
-struct t1 {
- char t1[10];
-};
-
-struct t2 {
- char t2[20];
-};
-
-struct t3 {
- char t3[65];
-};
-
-extern struct t1 g1;
-extern struct t2 g2;
-extern struct t3 g3;
-extern void f1(struct t1);
-extern void f2(struct t2);
-extern void f3(struct t3);
-
-void f() {
-
-// O32: call void @f1(i32 inreg %{{[0-9]+}}, i32 inreg %{{[0-9]+}}, i16 inreg
%{{[0-9]+}})
-// O32: call void @f2(%struct.t2* byval align 4 %{{.*}})
-// O32: call void @f3(%struct.t3* byval align 4 %{{.*}})
-
-// N32-N64: call void @f1(i64 inreg %{{[0-9]+}}, i16 inreg %{{[0-9]+}})
-// N32-N64: call void @f2(i64 inreg %{{[0-9]+}}, i64 inreg %{{[0-9]+}}, i32
inreg %{{[0-9]+}})
-// N32-N64: call void @f3(%struct.t3* byval align 8 %{{.*}})
-
- f1(g1);
- f2(g2);
- f3(g3);
-}
-
___
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r310702 - Revert r310057
Author: smaksimovic
Date: Fri Aug 11 04:03:54 2017
New Revision: 310702
URL: http://llvm.org/viewvc/llvm-project?rev=310702=rev
Log:
Revert r310057
Bring back changes which r304953 introduced since
they were in fact not the cause of failures described
in r310057 commit message.
Added:
cfe/trunk/test/CodeGen/mips-madd4.c
- copied unchanged from r310056, cfe/trunk/test/CodeGen/mips-madd4.c
Modified:
cfe/trunk/include/clang/Driver/Options.td
cfe/trunk/lib/Basic/Targets/Mips.cpp
cfe/trunk/lib/Basic/Targets/Mips.h
cfe/trunk/lib/Driver/ToolChains/Arch/Mips.cpp
cfe/trunk/test/Preprocessor/init.c
Modified: cfe/trunk/include/clang/Driver/Options.td
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/include/clang/Driver/Options.td?rev=310702=310701=310702=diff
==
--- cfe/trunk/include/clang/Driver/Options.td (original)
+++ cfe/trunk/include/clang/Driver/Options.td Fri Aug 11 04:03:54 2017
@@ -2027,6 +2027,10 @@ def mdspr2 : Flag<["-"], "mdspr2">, Grou
def mno_dspr2 : Flag<["-"], "mno-dspr2">, Group;
def msingle_float : Flag<["-"], "msingle-float">, Group;
def mdouble_float : Flag<["-"], "mdouble-float">, Group;
+def mmadd4 : Flag<["-"], "mmadd4">, Group,
+ HelpText<"Enable the generation of 4-operand madd.s, madd.d and related
instructions.">;
+def mno_madd4 : Flag<["-"], "mno-madd4">, Group,
+ HelpText<"Disable the generation of 4-operand madd.s, madd.d and related
instructions.">;
def mmsa : Flag<["-"], "mmsa">, Group,
HelpText<"Enable MSA ASE (MIPS only)">;
def mno_msa : Flag<["-"], "mno-msa">, Group,
Modified: cfe/trunk/lib/Basic/Targets/Mips.cpp
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Basic/Targets/Mips.cpp?rev=310702=310701=310702=diff
==
--- cfe/trunk/lib/Basic/Targets/Mips.cpp (original)
+++ cfe/trunk/lib/Basic/Targets/Mips.cpp Fri Aug 11 04:03:54 2017
@@ -166,6 +166,9 @@ void MipsTargetInfo::getTargetDefines(co
if (HasMSA)
Builder.defineMacro("__mips_msa", Twine(1));
+ if (DisableMadd4)
+Builder.defineMacro("__mips_no_madd4", Twine(1));
+
Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0)));
Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth()));
Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth()));
Modified: cfe/trunk/lib/Basic/Targets/Mips.h
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Basic/Targets/Mips.h?rev=310702=310701=310702=diff
==
--- cfe/trunk/lib/Basic/Targets/Mips.h (original)
+++ cfe/trunk/lib/Basic/Targets/Mips.h Fri Aug 11 04:03:54 2017
@@ -52,6 +52,7 @@ class LLVM_LIBRARY_VISIBILITY MipsTarget
enum MipsFloatABI { HardFloat, SoftFloat } FloatABI;
enum DspRevEnum { NoDSP, DSP1, DSP2 } DspRev;
bool HasMSA;
+ bool DisableMadd4;
protected:
bool HasFP64;
@@ -62,7 +63,7 @@ public:
: TargetInfo(Triple), IsMips16(false), IsMicromips(false),
IsNan2008(false), IsSingleFloat(false), IsNoABICalls(false),
CanUseBSDABICalls(false), FloatABI(HardFloat), DspRev(NoDSP),
-HasMSA(false), HasFP64(false) {
+HasMSA(false), DisableMadd4(false), HasFP64(false) {
TheCXXABI.set(TargetCXXABI::GenericMIPS);
setABI((getTriple().getArch() == llvm::Triple::mips ||
@@ -319,6 +320,8 @@ public:
DspRev = std::max(DspRev, DSP2);
else if (Feature == "+msa")
HasMSA = true;
+ else if (Feature == "+nomadd4")
+DisableMadd4 = true;
else if (Feature == "+fp64")
HasFP64 = true;
else if (Feature == "-fp64")
Modified: cfe/trunk/lib/Driver/ToolChains/Arch/Mips.cpp
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Driver/ToolChains/Arch/Mips.cpp?rev=310702=310701=310702=diff
==
--- cfe/trunk/lib/Driver/ToolChains/Arch/Mips.cpp (original)
+++ cfe/trunk/lib/Driver/ToolChains/Arch/Mips.cpp Fri Aug 11 04:03:54 2017
@@ -319,6 +319,8 @@ void mips::getMIPSTargetFeatures(const D
AddTargetFeature(Args, Features, options::OPT_mno_odd_spreg,
options::OPT_modd_spreg, "nooddspreg");
+ AddTargetFeature(Args, Features, options::OPT_mno_madd4, options::OPT_mmadd4,
+ "nomadd4");
AddTargetFeature(Args, Features, options::OPT_mmt, options::OPT_mno_mt,
"mt");
}
Modified: cfe/trunk/test/Preprocessor/init.c
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/Preprocessor/init.c?rev=310702=310701=310702=diff
==
--- cfe/trunk/test/Preprocessor/init.c (original)
+++ cfe/trunk/test/Preprocessor/init.c Fri Aug 11 04:03:54 2017
@@ -4840,6 +4840,16 @@
// RUN: | FileCheck -match-full-lines -check-prefix MIPS-MSA %s
// MIPS-MSA:#define __mips_msa 1
//
+// RUN: %clang_cc1
r310057 - Revert r304953 for release 5.0.0
Author: smaksimovic
Date: Fri Aug 4 05:37:34 2017
New Revision: 310057
URL: http://llvm.org/viewvc/llvm-project?rev=310057=rev
Log:
Revert r304953 for release 5.0.0
This is causing failures when compiling clang with -O3
as one of the structures used by clang is passed by
value and uses the fastcc calling convention.
Faliures manifest for stage2 mips build.
Removed:
cfe/trunk/test/CodeGen/mips-madd4.c
Modified:
cfe/trunk/include/clang/Driver/Options.td
cfe/trunk/lib/Basic/Targets/Mips.cpp
cfe/trunk/lib/Basic/Targets/Mips.h
cfe/trunk/lib/Driver/ToolChains/Arch/Mips.cpp
cfe/trunk/test/Preprocessor/init.c
Modified: cfe/trunk/include/clang/Driver/Options.td
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/include/clang/Driver/Options.td?rev=310057=310056=310057=diff
==
--- cfe/trunk/include/clang/Driver/Options.td (original)
+++ cfe/trunk/include/clang/Driver/Options.td Fri Aug 4 05:37:34 2017
@@ -2019,10 +2019,6 @@ def mdspr2 : Flag<["-"], "mdspr2">, Grou
def mno_dspr2 : Flag<["-"], "mno-dspr2">, Group;
def msingle_float : Flag<["-"], "msingle-float">, Group;
def mdouble_float : Flag<["-"], "mdouble-float">, Group;
-def mmadd4 : Flag<["-"], "mmadd4">, Group,
- HelpText<"Enable the generation of 4-operand madd.s, madd.d and related
instructions.">;
-def mno_madd4 : Flag<["-"], "mno-madd4">, Group,
- HelpText<"Disable the generation of 4-operand madd.s, madd.d and related
instructions.">;
def mmsa : Flag<["-"], "mmsa">, Group,
HelpText<"Enable MSA ASE (MIPS only)">;
def mno_msa : Flag<["-"], "mno-msa">, Group,
Modified: cfe/trunk/lib/Basic/Targets/Mips.cpp
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Basic/Targets/Mips.cpp?rev=310057=310056=310057=diff
==
--- cfe/trunk/lib/Basic/Targets/Mips.cpp (original)
+++ cfe/trunk/lib/Basic/Targets/Mips.cpp Fri Aug 4 05:37:34 2017
@@ -166,9 +166,6 @@ void MipsTargetInfo::getTargetDefines(co
if (HasMSA)
Builder.defineMacro("__mips_msa", Twine(1));
- if (DisableMadd4)
-Builder.defineMacro("__mips_no_madd4", Twine(1));
-
Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0)));
Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth()));
Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth()));
Modified: cfe/trunk/lib/Basic/Targets/Mips.h
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Basic/Targets/Mips.h?rev=310057=310056=310057=diff
==
--- cfe/trunk/lib/Basic/Targets/Mips.h (original)
+++ cfe/trunk/lib/Basic/Targets/Mips.h Fri Aug 4 05:37:34 2017
@@ -52,7 +52,6 @@ class LLVM_LIBRARY_VISIBILITY MipsTarget
enum MipsFloatABI { HardFloat, SoftFloat } FloatABI;
enum DspRevEnum { NoDSP, DSP1, DSP2 } DspRev;
bool HasMSA;
- bool DisableMadd4;
protected:
bool HasFP64;
@@ -63,7 +62,7 @@ public:
: TargetInfo(Triple), IsMips16(false), IsMicromips(false),
IsNan2008(false), IsSingleFloat(false), IsNoABICalls(false),
CanUseBSDABICalls(false), FloatABI(HardFloat), DspRev(NoDSP),
-HasMSA(false), DisableMadd4(false), HasFP64(false) {
+HasMSA(false), HasFP64(false) {
TheCXXABI.set(TargetCXXABI::GenericMIPS);
setABI((getTriple().getArch() == llvm::Triple::mips ||
@@ -320,8 +319,6 @@ public:
DspRev = std::max(DspRev, DSP2);
else if (Feature == "+msa")
HasMSA = true;
- else if (Feature == "+nomadd4")
-DisableMadd4 = true;
else if (Feature == "+fp64")
HasFP64 = true;
else if (Feature == "-fp64")
Modified: cfe/trunk/lib/Driver/ToolChains/Arch/Mips.cpp
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Driver/ToolChains/Arch/Mips.cpp?rev=310057=310056=310057=diff
==
--- cfe/trunk/lib/Driver/ToolChains/Arch/Mips.cpp (original)
+++ cfe/trunk/lib/Driver/ToolChains/Arch/Mips.cpp Fri Aug 4 05:37:34 2017
@@ -297,8 +297,6 @@ void mips::getMIPSTargetFeatures(const D
AddTargetFeature(Args, Features, options::OPT_mno_odd_spreg,
options::OPT_modd_spreg, "nooddspreg");
- AddTargetFeature(Args, Features, options::OPT_mno_madd4, options::OPT_mmadd4,
- "nomadd4");
AddTargetFeature(Args, Features, options::OPT_mlong_calls,
options::OPT_mno_long_calls, "long-calls");
AddTargetFeature(Args, Features, options::OPT_mmt, options::OPT_mno_mt,
"mt");
Removed: cfe/trunk/test/CodeGen/mips-madd4.c
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGen/mips-madd4.c?rev=310056=auto
==
--- cfe/trunk/test/CodeGen/mips-madd4.c (original)
+++ cfe/trunk/test/CodeGen/mips-madd4.c (removed)
@@ -1,87 +0,0 @@
-// REQUIRES: mips-registered-target
-//
