[clang] [Clang] Enable AIX local-dynamic TLS mode (PR #66972)
orcguru wrote: It's not expected that this commit includes all commits from the backend patch. Maybe I have to serialize the code review. Close this now. https://github.com/llvm/llvm-project/pull/66972 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [Clang] Enable AIX local-dynamic TLS mode (PR #66972)
https://github.com/orcguru closed https://github.com/llvm/llvm-project/pull/66972 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] ee703b5 - [clang][PowerPC] PPC64 VAArg fix right-alignment for aggregates fit in register
Author: Ting Wang
Date: 2022-10-16T22:01:47-04:00
New Revision: ee703b5cb134d182c2b589360714feab97f6a1cc
URL:
https://github.com/llvm/llvm-project/commit/ee703b5cb134d182c2b589360714feab97f6a1cc
DIFF:
https://github.com/llvm/llvm-project/commit/ee703b5cb134d182c2b589360714feab97f6a1cc.diff
LOG: [clang][PowerPC] PPC64 VAArg fix right-alignment for aggregates fit in
register
PPC64 ABI pass aggregates smaller than a register into the least
significant bits of the register. In the case of variadic functions,
they will end up right-aligned in their argument slots in the argument
area on big-endian targets. Apply right-alignment for these aggregates.
Fixes #55900.
Reviewed By: rjmccall
Differential Revision: https://reviews.llvm.org/D18
Added:
Modified:
clang/lib/CodeGen/TargetInfo.cpp
clang/test/CodeGen/PowerPC/ppc64-align-struct.c
Removed:
diff --git a/clang/lib/CodeGen/TargetInfo.cpp
b/clang/lib/CodeGen/TargetInfo.cpp
index bfe0fbec2ad5..8253d15c26df 100644
--- a/clang/lib/CodeGen/TargetInfo.cpp
+++ b/clang/lib/CodeGen/TargetInfo.cpp
@@ -322,13 +322,17 @@ static llvm::Value
*emitRoundPointerUpToAlignment(CodeGenFunction ,
/// leaving one or more empty slots behind as padding. If this
/// is false, the returned address might be less-aligned than
/// DirectAlign.
+/// \param ForceRightAdjust - Default is false. On big-endian platform and
+/// if the argument is smaller than a slot, set this flag will force
+/// right-adjust the argument in its slot irrespective of the type.
static Address emitVoidPtrDirectVAArg(CodeGenFunction ,
Address VAListAddr,
llvm::Type *DirectTy,
CharUnits DirectSize,
CharUnits DirectAlign,
CharUnits SlotSize,
- bool AllowHigherAlign) {
+ bool AllowHigherAlign,
+ bool ForceRightAdjust = false) {
// Cast the element type to i8* if necessary. Some platforms define
// va_list as a struct containing an i8* instead of just an i8*.
if (VAListAddr.getElementType() != CGF.Int8PtrTy)
@@ -354,7 +358,7 @@ static Address emitVoidPtrDirectVAArg(CodeGenFunction ,
// If the argument is smaller than a slot, and this is a big-endian
// target, the argument will be right-adjusted in its slot.
if (DirectSize < SlotSize && CGF.CGM.getDataLayout().isBigEndian() &&
- !DirectTy->isStructTy()) {
+ (!DirectTy->isStructTy() || ForceRightAdjust)) {
Addr = CGF.Builder.CreateConstInBoundsByteGEP(Addr, SlotSize - DirectSize);
}
@@ -375,11 +379,15 @@ static Address emitVoidPtrDirectVAArg(CodeGenFunction
,
/// an argument type with an alignment greater than the slot size
/// will be emitted on a higher-alignment address, potentially
/// leaving one or more empty slots behind as padding.
+/// \param ForceRightAdjust - Default is false. On big-endian platform and
+/// if the argument is smaller than a slot, set this flag will force
+/// right-adjust the argument in its slot irrespective of the type.
static Address emitVoidPtrVAArg(CodeGenFunction , Address VAListAddr,
QualType ValueTy, bool IsIndirect,
TypeInfoChars ValueInfo,
CharUnits SlotSizeAndAlign,
-bool AllowHigherAlign) {
+bool AllowHigherAlign,
+bool ForceRightAdjust = false) {
// The size and alignment of the value that was passed directly.
CharUnits DirectSize, DirectAlign;
if (IsIndirect) {
@@ -395,9 +403,9 @@ static Address emitVoidPtrVAArg(CodeGenFunction ,
Address VAListAddr,
if (IsIndirect)
DirectTy = DirectTy->getPointerTo(0);
- Address Addr =
- emitVoidPtrDirectVAArg(CGF, VAListAddr, DirectTy, DirectSize,
DirectAlign,
- SlotSizeAndAlign, AllowHigherAlign);
+ Address Addr = emitVoidPtrDirectVAArg(CGF, VAListAddr, DirectTy, DirectSize,
+DirectAlign, SlotSizeAndAlign,
+AllowHigherAlign, ForceRightAdjust);
if (IsIndirect) {
Addr = Address(CGF.Builder.CreateLoad(Addr), ElementTy, ValueInfo.Align);
@@ -5451,8 +5459,21 @@ Address PPC64_SVR4_ABIInfo::EmitVAArg(CodeGenFunction
, Address VAListAddr,
}
// Otherwise, just use the general rule.
- return emitVoidPtrVAArg(CGF, VAListAddr, Ty, /*Indirect*/ false,
- TypeInfo, SlotSize, /*AllowHigher*/ true);
+ //
+ // The PPC64 ABI passes some arguments in integer registers, even to variadic
+ // functions. To allow va_list to use the simple "void*"
[clang] 00b9bed - [clang][PowerPC][NFC] Add base test case for PPC64 VAArg aggregate smaller than a slot
Author: Ting Wang
Date: 2022-10-13T22:57:40-04:00
New Revision: 00b9bed1f05a72962643f8a41d30256c55bd19f5
URL:
https://github.com/llvm/llvm-project/commit/00b9bed1f05a72962643f8a41d30256c55bd19f5
DIFF:
https://github.com/llvm/llvm-project/commit/00b9bed1f05a72962643f8a41d30256c55bd19f5.diff
LOG: [clang][PowerPC][NFC] Add base test case for PPC64 VAArg aggregate smaller
than a slot
Reviewed By: shchenz
Differential Revision: https://reviews.llvm.org/D133488
Added:
Modified:
clang/test/CodeGen/PowerPC/ppc64-align-struct.c
Removed:
diff --git a/clang/test/CodeGen/PowerPC/ppc64-align-struct.c
b/clang/test/CodeGen/PowerPC/ppc64-align-struct.c
index ab179e3654010..273b187483bde 100644
--- a/clang/test/CodeGen/PowerPC/ppc64-align-struct.c
+++ b/clang/test/CodeGen/PowerPC/ppc64-align-struct.c
@@ -9,6 +9,8 @@ struct test4 { int x; int y; int z; };
struct test5 { int x[17]; };
struct test6 { int x[17]; } __attribute__((aligned (16)));
struct test7 { int x[17]; } __attribute__((aligned (32)));
+struct test8 { char x; };
+struct test9 { _Complex char x; };
// CHECK: define{{.*}} void @test1(i32 noundef signext %x, i64 %y.coerce)
void test1 (int x, struct test1 y)
@@ -48,6 +50,16 @@ void test7 (int x, struct test7 y)
{
}
+// CHECK: define{{.*}} void @test8(i32 noundef signext %x, i8 %y.coerce)
+void test8 (int x, struct test8 y)
+{
+}
+
+// CHECK: define{{.*}} void @test9(i32 noundef signext %x, i16 %y.coerce)
+void test9 (int x, struct test9 y)
+{
+}
+
// CHECK: define{{.*}} void @test1va(ptr noalias sret(%struct.test1) align 4
%[[AGG_RESULT:.*]], i32 noundef signext %x, ...)
// CHECK: %[[CUR:[^ ]+]] = load ptr, ptr %ap
// CHECK: %[[NEXT:[^ ]+]] = getelementptr inbounds i8, ptr %[[CUR]], i64 8
@@ -116,6 +128,38 @@ struct test4 test4va (int x, ...)
return y;
}
+// Error pattern will be fixed in https://reviews.llvm.org/D18
+// CHECK: define{{.*}} void @test8va(ptr noalias sret(%struct.test8) align 1
%[[AGG_RESULT:.*]], i32 noundef signext %x, ...)
+// CHECK: %[[CUR:[^ ]+]] = load ptr, ptr %ap
+// CHECK: %[[NEXT:[^ ]+]] = getelementptr inbounds i8, ptr %[[CUR]], i64 8
+// CHECK: store ptr %[[NEXT]], ptr %ap
+// CHECK: call void @llvm.memcpy.p0.p0.i64(ptr align 1 %[[AGG_RESULT]], ptr
align 8 %[[CUR]], i64 1, i1 false)
+struct test8 test8va (int x, ...)
+{
+ struct test8 y;
+ va_list ap;
+ va_start(ap, x);
+ y = va_arg (ap, struct test8);
+ va_end(ap);
+ return y;
+}
+
+// Error pattern will be fixed in https://reviews.llvm.org/D18
+// CHECK: define{{.*}} void @test9va(ptr noalias sret(%struct.test9) align 1
%[[AGG_RESULT:.*]], i32 noundef signext %x, ...)
+// CHECK: %[[CUR:[^ ]+]] = load ptr, ptr %ap
+// CHECK: %[[NEXT:[^ ]+]] = getelementptr inbounds i8, ptr %[[CUR]], i64 8
+// CHECK: store ptr %[[NEXT]], ptr %ap
+// CHECK: call void @llvm.memcpy.p0.p0.i64(ptr align 1 %[[AGG_RESULT]], ptr
align 8 %[[CUR]], i64 2, i1 false)
+struct test9 test9va (int x, ...)
+{
+ struct test9 y;
+ va_list ap;
+ va_start(ap, x);
+ y = va_arg (ap, struct test9);
+ va_end(ap);
+ return y;
+}
+
// CHECK: define{{.*}} void @testva_longdouble(ptr noalias
sret(%struct.test_longdouble) align 16 %[[AGG_RESULT:.*]], i32 noundef signext
%x, ...)
// CHECK: %[[CUR:[^ ]+]] = load ptr, ptr %ap
// CHECK: %[[NEXT:[^ ]+]] = getelementptr inbounds i8, ptr %[[CUR]], i64 16
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[clang] d2d77e0 - [PowerPC][Coroutines] Add tail-call check with call information for coroutines
Author: Ting Wang
Date: 2022-08-21T22:20:40-04:00
New Revision: d2d77e050b32ce3f917688aeeb9e6f8f3c209560
URL:
https://github.com/llvm/llvm-project/commit/d2d77e050b32ce3f917688aeeb9e6f8f3c209560
DIFF:
https://github.com/llvm/llvm-project/commit/d2d77e050b32ce3f917688aeeb9e6f8f3c209560.diff
LOG: [PowerPC][Coroutines] Add tail-call check with call information for
coroutines
Fixes #56679.
Reviewed By: ChuanqiXu, shchenz
Differential Revision: https://reviews.llvm.org/D131953
Added:
llvm/test/Transforms/Coroutines/coro-split-musttail-ppc64le.ll
Modified:
clang/test/CodeGenCoroutines/pr56329.cpp
llvm/include/llvm/Analysis/TargetTransformInfo.h
llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
llvm/lib/Analysis/TargetTransformInfo.cpp
llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
llvm/lib/Target/PowerPC/PPCTargetTransformInfo.h
llvm/lib/Transforms/Coroutines/CoroSplit.cpp
Removed:
diff --git a/clang/test/CodeGenCoroutines/pr56329.cpp
b/clang/test/CodeGenCoroutines/pr56329.cpp
index 3918acae0f08f..2e9a1a244e218 100644
--- a/clang/test/CodeGenCoroutines/pr56329.cpp
+++ b/clang/test/CodeGenCoroutines/pr56329.cpp
@@ -1,6 +1,8 @@
// Test for PR56919. Tests the we won't contain the resumption of final
suspend point.
//
// RUN: %clang_cc1 -triple %itanium_abi_triple -std=c++20 %s -O3 -S -emit-llvm
-o - | FileCheck %s
+// This test is expected to fail on PowerPC.
+// XFAIL: powerpc
#include "Inputs/coroutine.h"
diff --git a/llvm/include/llvm/Analysis/TargetTransformInfo.h
b/llvm/include/llvm/Analysis/TargetTransformInfo.h
index 04db5a9484a76..4dffc3a36a578 100644
--- a/llvm/include/llvm/Analysis/TargetTransformInfo.h
+++ b/llvm/include/llvm/Analysis/TargetTransformInfo.h
@@ -765,6 +765,9 @@ class TargetTransformInfo {
/// If the target supports tail calls.
bool supportsTailCalls() const;
+ /// If target supports tail call on \p CB
+ bool supportsTailCallFor(const CallBase *CB) const;
+
/// Don't restrict interleaved unrolling to small loops.
bool enableAggressiveInterleaving(bool LoopHasReductions) const;
@@ -1635,6 +1638,7 @@ class TargetTransformInfo::Concept {
ArrayRef Tys) = 0;
virtual bool supportsEfficientVectorElementLoadStore() = 0;
virtual bool supportsTailCalls() = 0;
+ virtual bool supportsTailCallFor(const CallBase *CB) = 0;
virtual bool enableAggressiveInterleaving(bool LoopHasReductions) = 0;
virtual MemCmpExpansionOptions
enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const = 0;
@@ -2109,6 +2113,9 @@ class TargetTransformInfo::Model final : public
TargetTransformInfo::Concept {
}
bool supportsTailCalls() override { return Impl.supportsTailCalls(); }
+ bool supportsTailCallFor(const CallBase *CB) override {
+return Impl.supportsTailCallFor(CB);
+ }
bool enableAggressiveInterleaving(bool LoopHasReductions) override {
return Impl.enableAggressiveInterleaving(LoopHasReductions);
diff --git a/llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
b/llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
index 116606973b398..38deff576092c 100644
--- a/llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
+++ b/llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
@@ -343,6 +343,10 @@ class TargetTransformInfoImplBase {
bool supportsTailCalls() const { return true; }
+ bool supportsTailCallFor(const CallBase *CB) const {
+return supportsTailCalls();
+ }
+
bool enableAggressiveInterleaving(bool LoopHasReductions) const {
return false;
}
diff --git a/llvm/lib/Analysis/TargetTransformInfo.cpp
b/llvm/lib/Analysis/TargetTransformInfo.cpp
index f9855ecf3d6e1..c81b8ba6e7857 100644
--- a/llvm/lib/Analysis/TargetTransformInfo.cpp
+++ b/llvm/lib/Analysis/TargetTransformInfo.cpp
@@ -528,6 +528,10 @@ bool TargetTransformInfo::supportsTailCalls() const {
return TTIImpl->supportsTailCalls();
}
+bool TargetTransformInfo::supportsTailCallFor(const CallBase *CB) const {
+ return TTIImpl->supportsTailCallFor(CB);
+}
+
bool TargetTransformInfo::enableAggressiveInterleaving(
bool LoopHasReductions) const {
return TTIImpl->enableAggressiveInterleaving(LoopHasReductions);
diff --git a/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
b/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
index d6a56628d47a4..88a43a582a1fd 100644
--- a/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
+++ b/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
@@ -1461,3 +1461,19 @@ InstructionCost PPCTTIImpl::getVPMemoryOpCost(unsigned
Opcode, Type *Src,
// evl but no mask, on Power 9/10. Otherwise, we must scalarize.
return getMaskedMemoryOpCost(Opcode, Src, Alignment, AddressSpace, CostKind);
}
+
+bool PPCTTIImpl::supportsTailCallFor(const CallBase *CB) const {
+ // Subtargets using PC-Relative addressing supported.
+ if
[clang] 289236d - [PowerPC] Fix PPCISD::STBRX selection issue on A2
Author: Ting Wang
Date: 2022-05-10T20:47:51-04:00
New Revision: 289236d597a228484dfd9607da6889603b9210a8
URL:
https://github.com/llvm/llvm-project/commit/289236d597a228484dfd9607da6889603b9210a8
DIFF:
https://github.com/llvm/llvm-project/commit/289236d597a228484dfd9607da6889603b9210a8.diff
LOG: [PowerPC] Fix PPCISD::STBRX selection issue on A2
Enable FeatureISA2_06 on Power A2 target
Reviewed By: nemanjai
Differential Revision: https://reviews.llvm.org/D125203
Added:
Modified:
clang/lib/Basic/Targets/PPC.cpp
clang/test/Driver/ppc-isa-features.cpp
llvm/lib/Target/PowerPC/PPC.td
llvm/test/CodeGen/PowerPC/bswap-load-store.ll
Removed:
diff --git a/clang/lib/Basic/Targets/PPC.cpp b/clang/lib/Basic/Targets/PPC.cpp
index a2e50f37d854f..dacb7eeea12a8 100644
--- a/clang/lib/Basic/Targets/PPC.cpp
+++ b/clang/lib/Basic/Targets/PPC.cpp
@@ -549,6 +549,7 @@ bool PPCTargetInfo::initFeatureMap(
.Case("pwr9", true)
.Case("pwr8", true)
.Case("pwr7", true)
+ .Case("a2", true)
.Default(false);
Features["isa-v207-instructions"] = llvm::StringSwitch(CPU)
diff --git a/clang/test/Driver/ppc-isa-features.cpp
b/clang/test/Driver/ppc-isa-features.cpp
index 87a3a808e012f..92c5bc82f72b8 100644
--- a/clang/test/Driver/ppc-isa-features.cpp
+++ b/clang/test/Driver/ppc-isa-features.cpp
@@ -1,4 +1,5 @@
// RUN: %clang -target powerpc64-unknown-unknown -mcpu=pwr6 -S -emit-llvm %s
-o - | FileCheck %s -check-prefix=CHECK-PWR6
+// RUN: %clang -target powerpc64-unknown-unknown -mcpu=a2 -S -emit-llvm %s -o
- | FileCheck %s -check-prefix=CHECK-A2
// RUN: %clang -target powerpc64-unknown-unknown -mcpu=pwr7 -S -emit-llvm %s
-o - | FileCheck %s -check-prefix=CHECK-PWR7
// RUN: %clang -target powerpc64le-unknown-unknown -mcpu=pwr8 -S -emit-llvm %s
-o - | FileCheck %s -check-prefix=CHECK-PWR8
// RUN: %clang -target powerpc64-unknown-aix -mcpu=pwr9 -S -emit-llvm %s -o -
| FileCheck %s -check-prefix=CHECK-PWR9
@@ -8,6 +9,10 @@
// CHECK-PWR6: -isa-v207-instructions
// CHECK-PWR6: -isa-v30-instructions
+// CHECK-A2: +isa-v206-instructions
+// CHECK-A2: -isa-v207-instructions
+// CHECK-A2: -isa-v30-instructions
+
// CHECK-PWR7: +isa-v206-instructions
// CHECK-PWR7: -isa-v207-instructions
// CHECK-PWR7: -isa-v30-instructions
diff --git a/llvm/lib/Target/PowerPC/PPC.td b/llvm/lib/Target/PowerPC/PPC.td
index 44a323df34614..15c149df5abeb 100644
--- a/llvm/lib/Target/PowerPC/PPC.td
+++ b/llvm/lib/Target/PowerPC/PPC.td
@@ -592,7 +592,8 @@ def : ProcessorModel<"a2", PPCA2Model,
FeatureSTFIWX, FeatureLFIWAX,
FeatureFPRND, FeatureFPCVT, FeatureISEL,
FeatureSlowPOPCNTD, FeatureCMPB, FeatureLDBRX,
- Feature64Bit /*, Feature64BitRegs */, FeatureMFTB]>;
+ Feature64Bit /*, Feature64BitRegs */, FeatureMFTB,
+ FeatureISA2_06]>;
def : ProcessorModel<"pwr3", G5Model,
[DirectivePwr3, FeatureAltivec,
FeatureFRES, FeatureFRSQRTE, FeatureMFOCRF,
diff --git a/llvm/test/CodeGen/PowerPC/bswap-load-store.ll
b/llvm/test/CodeGen/PowerPC/bswap-load-store.ll
index 0c9b7a7094517..ecd29aa0d6317 100644
--- a/llvm/test/CodeGen/PowerPC/bswap-load-store.ll
+++ b/llvm/test/CodeGen/PowerPC/bswap-load-store.ll
@@ -3,6 +3,7 @@
; RUN: llc -ppc-asm-full-reg-names -verify-machineinstrs < %s -mtriple=ppc32--
-mcpu=pwr7 | FileCheck %s --check-prefixes=X32,PWR7_32
; RUN: llc -ppc-asm-full-reg-names -verify-machineinstrs < %s
-mtriple=powerpc64-- -mcpu=ppc64 | FileCheck %s --check-prefixes=X64
; RUN: llc -ppc-asm-full-reg-names -verify-machineinstrs < %s
-mtriple=powerpc64-- -mcpu=pwr7 | FileCheck %s --check-prefixes=PWR7_64
+; RUN: llc -ppc-asm-full-reg-names -verify-machineinstrs < %s
-mtriple=powerpc64-- -mcpu=a2| FileCheck %s --check-prefixes=A2_64
define void @STWBRX(i32 %i, i8* %ptr, i32 %off) {
@@ -22,6 +23,12 @@ define void @STWBRX(i32 %i, i8* %ptr, i32 %off) {
; PWR7_64-NEXT:extsw r5, r5
; PWR7_64-NEXT:stwbrx r3, r4, r5
; PWR7_64-NEXT:blr
+;
+; A2_64-LABEL: STWBRX:
+; A2_64: # %bb.0:
+; A2_64-NEXT:extsw r5, r5
+; A2_64-NEXT:stwbrx r3, r4, r5
+; A2_64-NEXT:blr
%tmp1 = getelementptr i8, i8* %ptr, i32 %off
%tmp1.upgrd.1 = bitcast i8* %tmp1 to i32*
%tmp13 = tail call i32 @llvm.bswap.i32( i32 %i )
@@ -46,6 +53,12 @@ define i32 @LWBRX(i8* %ptr, i32 %off) {
; PWR7_64-NEXT:extsw r4, r4
; PWR7_64-NEXT:lwbrx r3, r3, r4
; PWR7_64-NEXT:blr
+;
+; A2_64-LABEL: LWBRX:
+; A2_64: # %bb.0:
+; A2_64-NEXT:extsw r4, r4
+; A2_64-NEXT:lwbrx r3, r3, r4
+; A2_64-NEXT:blr
%tmp1 = getelementptr i8, i8* %ptr, i32
[clang] b389354 - [Clang][PowerPC] Add max/min intrinsics to Clang and PPC backend
Author: Ting Wang
Date: 2022-04-05T22:43:48-04:00
New Revision: b389354b285744f700fd9372c8707fa056d7cb37
URL:
https://github.com/llvm/llvm-project/commit/b389354b285744f700fd9372c8707fa056d7cb37
DIFF:
https://github.com/llvm/llvm-project/commit/b389354b285744f700fd9372c8707fa056d7cb37.diff
LOG: [Clang][PowerPC] Add max/min intrinsics to Clang and PPC backend
Add support for builtin_[max|min] which has below prototype:
A builtin_max (A1, A2, A3, ...)
All arguments must have the same type; they must all be float, double, or long
double.
Internally use SelectCC to get the result.
Reviewed By: qiucf
Differential Revision: https://reviews.llvm.org/D122478
Added:
llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-maxmin.ll
Modified:
clang/include/clang/Basic/BuiltinsPPC.def
clang/lib/Basic/Targets/PPC.cpp
clang/lib/CodeGen/CGBuiltin.cpp
clang/lib/Sema/SemaChecking.cpp
clang/test/CodeGen/PowerPC/builtins-ppc.c
clang/test/Sema/builtins-ppc.c
llvm/include/llvm/IR/IntrinsicsPowerPC.td
llvm/lib/Target/PowerPC/PPCISelLowering.cpp
Removed:
diff --git a/clang/include/clang/Basic/BuiltinsPPC.def
b/clang/include/clang/Basic/BuiltinsPPC.def
index 70b0184f199f8..8a4c5b4eead27 100644
--- a/clang/include/clang/Basic/BuiltinsPPC.def
+++ b/clang/include/clang/Basic/BuiltinsPPC.def
@@ -152,6 +152,13 @@ BUILTIN(__builtin_ppc_mtmsr, "vUi", "")
BUILTIN(__builtin_ppc_mtspr, "vIiULi", "")
BUILTIN(__builtin_ppc_stfiw, "viC*d", "")
BUILTIN(__builtin_ppc_addex, "LLiLLiLLiCIi", "")
+// select
+BUILTIN(__builtin_ppc_maxfe, "LdLdLdLd.", "t")
+BUILTIN(__builtin_ppc_maxfl, ".", "t")
+BUILTIN(__builtin_ppc_maxfs, ".", "t")
+BUILTIN(__builtin_ppc_minfe, "LdLdLdLd.", "t")
+BUILTIN(__builtin_ppc_minfl, ".", "t")
+BUILTIN(__builtin_ppc_minfs, ".", "t")
BUILTIN(__builtin_ppc_get_timebase, "ULLi", "n")
diff --git a/clang/lib/Basic/Targets/PPC.cpp b/clang/lib/Basic/Targets/PPC.cpp
index 1eb0317af60b6..bafcc23b38334 100644
--- a/clang/lib/Basic/Targets/PPC.cpp
+++ b/clang/lib/Basic/Targets/PPC.cpp
@@ -247,6 +247,12 @@ static void defineXLCompatMacros(MacroBuilder ) {
Builder.defineMacro("__test_data_class", "__builtin_ppc_test_data_class");
Builder.defineMacro("__swdiv", "__builtin_ppc_swdiv");
Builder.defineMacro("__swdivs", "__builtin_ppc_swdivs");
+ Builder.defineMacro("__builtin_maxfe", "__builtin_ppc_maxfe");
+ Builder.defineMacro("__builtin_maxfl", "__builtin_ppc_maxfl");
+ Builder.defineMacro("__builtin_maxfs", "__builtin_ppc_maxfs");
+ Builder.defineMacro("__builtin_minfe", "__builtin_ppc_minfe");
+ Builder.defineMacro("__builtin_minfl", "__builtin_ppc_minfl");
+ Builder.defineMacro("__builtin_minfs", "__builtin_ppc_minfs");
}
/// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific
diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
index 8ca4b2d0bf15d..661c0a105f427 100644
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -16302,6 +16302,18 @@ Value *CodeGenFunction::EmitPPCBuiltinExpr(unsigned
BuiltinID,
return Builder.CreateCall(CGM.getIntrinsic(IntrinsicID), Ops,
"test_data_class");
}
+ case PPC::BI__builtin_ppc_maxfe:
+return Builder.CreateCall(CGM.getIntrinsic(Intrinsic::ppc_maxfe), Ops);
+ case PPC::BI__builtin_ppc_maxfl:
+return Builder.CreateCall(CGM.getIntrinsic(Intrinsic::ppc_maxfl), Ops);
+ case PPC::BI__builtin_ppc_maxfs:
+return Builder.CreateCall(CGM.getIntrinsic(Intrinsic::ppc_maxfs), Ops);
+ case PPC::BI__builtin_ppc_minfe:
+return Builder.CreateCall(CGM.getIntrinsic(Intrinsic::ppc_minfe), Ops);
+ case PPC::BI__builtin_ppc_minfl:
+return Builder.CreateCall(CGM.getIntrinsic(Intrinsic::ppc_minfl), Ops);
+ case PPC::BI__builtin_ppc_minfs:
+return Builder.CreateCall(CGM.getIntrinsic(Intrinsic::ppc_minfs), Ops);
case PPC::BI__builtin_ppc_swdiv:
case PPC::BI__builtin_ppc_swdivs:
return Builder.CreateFDiv(Ops[0], Ops[1], "swdiv");
diff --git a/clang/lib/Sema/SemaChecking.cpp b/clang/lib/Sema/SemaChecking.cpp
index 7e73988c33b74..9331d169f800f 100644
--- a/clang/lib/Sema/SemaChecking.cpp
+++ b/clang/lib/Sema/SemaChecking.cpp
@@ -3904,6 +3904,33 @@ bool Sema::CheckPPCBuiltinFunctionCall(const TargetInfo
, unsigned BuiltinID,
diag::err_ppc_builtin_requires_vsx) ||
SemaBuiltinConstantArgRange(TheCall, 1, 0, 127);
}
+ case PPC::BI__builtin_ppc_maxfe:
+ case PPC::BI__builtin_ppc_minfe:
+ case PPC::BI__builtin_ppc_maxfl:
+ case PPC::BI__builtin_ppc_minfl:
+ case PPC::BI__builtin_ppc_maxfs:
+ case PPC::BI__builtin_ppc_minfs: {
+if (Context.getTargetInfo().getTriple().isOSAIX() &&
+(BuiltinID == PPC::BI__builtin_ppc_maxfe ||
+ BuiltinID == PPC::BI__builtin_ppc_minfe))
+ return Diag(TheCall->getBeginLoc(),
