[PATCH] D78129: Add Marvell ThunderX3T110 support

2020-05-19 Thread Wei Zhao via Phabricator via cfe-commits 
wxz2020 added a comment.

Thanks, Just sent Tom an email.


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[PATCH] D78129: Add Marvell ThunderX3T110 support

2020-05-19 Thread Wei Zhao via Phabricator via cfe-commits 
wxz2020 added a comment.

I have a question here. Our customers need the TX3 support urgently, they asked 
me to put this TX3 support to LLVM 10.0.1 and if there is 9.0.2 release 
planned, they also need it there.

How can I do this?  To put this checkin to LLVM 10.0.1 branch and 9.0.2 branch?

Is it possible? What steps I should follow?

Thanks,


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[PATCH] D78129: Add Marvell ThunderX3T110 support

2020-05-13 Thread Wei Zhao via Phabricator via cfe-commits 
wxz2020 added a comment.

Joel will help me to commit it. Thanks,


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[PATCH] D78129: Add Marvell ThunderX3T110 support

2020-05-12 Thread Wei Zhao via Phabricator via cfe-commits 
wxz2020 updated this revision to Diff 263582.
wxz2020 added a comment.

Correct the wrong version of llvm/unittests/Support/TargetParserTest.cpp which 
causes the test failure.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D78129/new/

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Files:
  clang/test/Driver/aarch64-cpus.c
  llvm/include/llvm/Support/AArch64TargetParser.def
  llvm/lib/Target/AArch64/AArch64.td
  llvm/lib/Target/AArch64/AArch64SchedA53.td
  llvm/lib/Target/AArch64/AArch64SchedA57.td
  llvm/lib/Target/AArch64/AArch64SchedCyclone.td
  llvm/lib/Target/AArch64/AArch64SchedExynosM3.td
  llvm/lib/Target/AArch64/AArch64SchedExynosM4.td
  llvm/lib/Target/AArch64/AArch64SchedExynosM5.td
  llvm/lib/Target/AArch64/AArch64SchedFalkor.td
  llvm/lib/Target/AArch64/AArch64SchedKryo.td
  llvm/lib/Target/AArch64/AArch64SchedThunderX.td
  llvm/lib/Target/AArch64/AArch64SchedThunderX2T99.td
  llvm/lib/Target/AArch64/AArch64SchedThunderX3T110.td
  llvm/lib/Target/AArch64/AArch64Subtarget.cpp
  llvm/lib/Target/AArch64/AArch64Subtarget.h
  llvm/test/CodeGen/AArch64/aarch64-combine-fmul-fsub.mir
  llvm/test/CodeGen/AArch64/cpus.ll
  llvm/test/CodeGen/AArch64/machine-combiner-madd.ll
  llvm/test/CodeGen/AArch64/preferred-function-alignment.ll
  llvm/test/CodeGen/AArch64/remat.ll
  llvm/unittests/Support/TargetParserTest.cpp

Index: llvm/unittests/Support/TargetParserTest.cpp
===
--- llvm/unittests/Support/TargetParserTest.cpp
+++ llvm/unittests/Support/TargetParserTest.cpp
@@ -942,6 +942,13 @@
   "thunderx2t99", "armv8.1-a", "crypto-neon-fp-armv8",
   AArch64::AEK_CRC | AArch64::AEK_CRYPTO | AArch64::AEK_LSE |
   AArch64::AEK_RDM | AArch64::AEK_FP | AArch64::AEK_SIMD, "8.1-A"));
+  EXPECT_TRUE(testAArch64CPU(
+  "thunderx3t110", "armv8.3-a", "crypto-neon-fp-armv8",
+  AArch64::AEK_CRC | AArch64::AEK_CRYPTO | AArch64::AEK_LSE |
+  AArch64::AEK_RDM | AArch64::AEK_FP | AArch64::AEK_SIMD |
+  AArch64::AEK_PROFILE | AArch64::AEK_RAS | AArch64::AEK_RAND |
+  AArch64::AEK_RCPC,
+  "8.3-A"));
   EXPECT_TRUE(testAArch64CPU(
   "thunderx", "armv8-a", "crypto-neon-fp-armv8",
   AArch64::AEK_CRC | AArch64::AEK_CRYPTO | AArch64::AEK_SIMD |
@@ -983,7 +990,7 @@
   "8.2-A"));
 }
 
-static constexpr unsigned NumAArch64CPUArchs = 38;
+static constexpr unsigned NumAArch64CPUArchs = 39;
 
 TEST(TargetParserTest, testAArch64CPUArchList) {
   SmallVector List;
Index: llvm/test/CodeGen/AArch64/remat.ll
===
--- llvm/test/CodeGen/AArch64/remat.ll
+++ llvm/test/CodeGen/AArch64/remat.ll
@@ -19,6 +19,7 @@
 ; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=thunderx2t99 -o - %s | FileCheck %s
 ; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=tsv110 -o - %s | FileCheck %s
 ; RUN: llc -mtriple=aarch64-linux-gnuabi -mattr=+custom-cheap-as-move -o - %s | FileCheck %s
+; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=thunderx3t110 -o - %s | FileCheck %s
 
 %X = type { i64, i64, i64 }
 declare void @f(%X*)
Index: llvm/test/CodeGen/AArch64/preferred-function-alignment.ll
===
--- llvm/test/CodeGen/AArch64/preferred-function-alignment.ll
+++ llvm/test/CodeGen/AArch64/preferred-function-alignment.ll
@@ -19,6 +19,7 @@
 ; RUN: llc -mtriple=aarch64-unknown-linux -mcpu=thunderxt83 < %s | FileCheck --check-prefixes=ALIGN3,CHECK %s
 ; RUN: llc -mtriple=aarch64-unknown-linux -mcpu=thunderxt88 < %s | FileCheck --check-prefixes=ALIGN3,CHECK %s
 ; RUN: llc -mtriple=aarch64-unknown-linux -mcpu=thunderx2t99 < %s | FileCheck --check-prefixes=ALIGN3,CHECK %s
+; RUN: llc -mtriple=aarch64-unknown-linux -mcpu=thunderx3t110 < %s | FileCheck --check-prefixes=ALIGN4,CHECK %s
 ; RUN: llc -mtriple=aarch64-unknown-linux -mcpu=exynos-m3 < %s | FileCheck --check-prefixes=ALIGN5,CHECK %s
 
 define void @test() {
Index: llvm/test/CodeGen/AArch64/machine-combiner-madd.ll
===
--- llvm/test/CodeGen/AArch64/machine-combiner-madd.ll
+++ llvm/test/CodeGen/AArch64/machine-combiner-madd.ll
@@ -6,6 +6,7 @@
 ; RUN: llc -mtriple=aarch64-linux-gnu -mcpu=exynos-m3  < %s | FileCheck %s
 ; RUN: llc -mtriple=aarch64-linux-gnu -mcpu=kryo   < %s | FileCheck %s
 ; RUN: llc -mtriple=aarch64-linux-gnu -mcpu=thunderx2t99 < %s | FileCheck %s
+; RUN: llc -mtriple=aarch64-linux-gnu -mcpu=thunderx3t110 < %s | FileCheck %s
 
 ; Make sure that inst-combine fuses the multiply add in the addressing mode of
 ; the load.
Index: llvm/test/CodeGen/AArch64/cpus.ll
===
--- llvm/test/CodeGen/AArch64/cpus.ll
+++ llvm/test/CodeGen/AArch64/cpus.ll
@@ -24,6 +24,7 @@
 ; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=saphira 2>&1 | FileCheck %s
 ; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=kryo 2>&1 |

[PATCH] D78129: Add Marvell ThunderX3T110 support

2020-05-12 Thread Wei Zhao via Phabricator via cfe-commits 
wxz2020 updated this revision to Diff 263543.
wxz2020 added a comment.

1. in clang/test/Driver/aarch64-cpus.c, expanded the the same tests for 
thunderx2t99 to thunderx3t110
2. in llvm/unittest/Support/TargetParserTest.cpp, fix the missing target 
features

So far all the existing issues are fixed according to review feedbacks

Thanks


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D78129/new/

https://reviews.llvm.org/D78129

Files:
  clang/test/Driver/aarch64-cpus.c
  llvm/include/llvm/Support/AArch64TargetParser.def
  llvm/lib/Target/AArch64/AArch64.td
  llvm/lib/Target/AArch64/AArch64SchedA53.td
  llvm/lib/Target/AArch64/AArch64SchedA57.td
  llvm/lib/Target/AArch64/AArch64SchedCyclone.td
  llvm/lib/Target/AArch64/AArch64SchedExynosM3.td
  llvm/lib/Target/AArch64/AArch64SchedExynosM4.td
  llvm/lib/Target/AArch64/AArch64SchedExynosM5.td
  llvm/lib/Target/AArch64/AArch64SchedFalkor.td
  llvm/lib/Target/AArch64/AArch64SchedKryo.td
  llvm/lib/Target/AArch64/AArch64SchedThunderX.td
  llvm/lib/Target/AArch64/AArch64SchedThunderX2T99.td
  llvm/lib/Target/AArch64/AArch64SchedThunderX3T110.td
  llvm/lib/Target/AArch64/AArch64Subtarget.cpp
  llvm/lib/Target/AArch64/AArch64Subtarget.h
  llvm/test/CodeGen/AArch64/aarch64-combine-fmul-fsub.mir
  llvm/test/CodeGen/AArch64/cpus.ll
  llvm/test/CodeGen/AArch64/machine-combiner-madd.ll
  llvm/test/CodeGen/AArch64/preferred-function-alignment.ll
  llvm/test/CodeGen/AArch64/remat.ll
  llvm/unittests/Support/TargetParserTest.cpp

Index: llvm/unittests/Support/TargetParserTest.cpp
===
--- llvm/unittests/Support/TargetParserTest.cpp
+++ llvm/unittests/Support/TargetParserTest.cpp
@@ -942,6 +942,12 @@
   "thunderx2t99", "armv8.1-a", "crypto-neon-fp-armv8",
   AArch64::AEK_CRC | AArch64::AEK_CRYPTO | AArch64::AEK_LSE |
   AArch64::AEK_RDM | AArch64::AEK_FP | AArch64::AEK_SIMD, "8.1-A"));
+  EXPECT_TRUE(testAArch64CPU(
+  "thunderx3t110", "armv8.3-a", "crypto-neon-fp-armv8",
+  AArch64::AEK_CRC | AArch64::AEK_CRYPTO | AArch64::AEK_LSE |
+  AArch64::AEK_RDM | AArch64::AEK_FP | AArch64::AEK_SIMD |
+  AArch64::AEK_PROFILE | AArch64::AEK_RAS,
+  "8.3-A"));
   EXPECT_TRUE(testAArch64CPU(
   "thunderx", "armv8-a", "crypto-neon-fp-armv8",
   AArch64::AEK_CRC | AArch64::AEK_CRYPTO | AArch64::AEK_SIMD |
@@ -983,7 +989,7 @@
   "8.2-A"));
 }
 
-static constexpr unsigned NumAArch64CPUArchs = 38;
+static constexpr unsigned NumAArch64CPUArchs = 39;
 
 TEST(TargetParserTest, testAArch64CPUArchList) {
   SmallVector List;
Index: llvm/test/CodeGen/AArch64/remat.ll
===
--- llvm/test/CodeGen/AArch64/remat.ll
+++ llvm/test/CodeGen/AArch64/remat.ll
@@ -19,6 +19,7 @@
 ; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=thunderx2t99 -o - %s | FileCheck %s
 ; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=tsv110 -o - %s | FileCheck %s
 ; RUN: llc -mtriple=aarch64-linux-gnuabi -mattr=+custom-cheap-as-move -o - %s | FileCheck %s
+; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=thunderx3t110 -o - %s | FileCheck %s
 
 %X = type { i64, i64, i64 }
 declare void @f(%X*)
Index: llvm/test/CodeGen/AArch64/preferred-function-alignment.ll
===
--- llvm/test/CodeGen/AArch64/preferred-function-alignment.ll
+++ llvm/test/CodeGen/AArch64/preferred-function-alignment.ll
@@ -19,6 +19,7 @@
 ; RUN: llc -mtriple=aarch64-unknown-linux -mcpu=thunderxt83 < %s | FileCheck --check-prefixes=ALIGN3,CHECK %s
 ; RUN: llc -mtriple=aarch64-unknown-linux -mcpu=thunderxt88 < %s | FileCheck --check-prefixes=ALIGN3,CHECK %s
 ; RUN: llc -mtriple=aarch64-unknown-linux -mcpu=thunderx2t99 < %s | FileCheck --check-prefixes=ALIGN3,CHECK %s
+; RUN: llc -mtriple=aarch64-unknown-linux -mcpu=thunderx3t110 < %s | FileCheck --check-prefixes=ALIGN4,CHECK %s
 ; RUN: llc -mtriple=aarch64-unknown-linux -mcpu=exynos-m3 < %s | FileCheck --check-prefixes=ALIGN5,CHECK %s
 
 define void @test() {
Index: llvm/test/CodeGen/AArch64/machine-combiner-madd.ll
===
--- llvm/test/CodeGen/AArch64/machine-combiner-madd.ll
+++ llvm/test/CodeGen/AArch64/machine-combiner-madd.ll
@@ -6,6 +6,7 @@
 ; RUN: llc -mtriple=aarch64-linux-gnu -mcpu=exynos-m3  < %s | FileCheck %s
 ; RUN: llc -mtriple=aarch64-linux-gnu -mcpu=kryo   < %s | FileCheck %s
 ; RUN: llc -mtriple=aarch64-linux-gnu -mcpu=thunderx2t99 < %s | FileCheck %s
+; RUN: llc -mtriple=aarch64-linux-gnu -mcpu=thunderx3t110 < %s | FileCheck %s
 
 ; Make sure that inst-combine fuses the multiply add in the addressing mode of
 ; the load.
Index: llvm/test/CodeGen/AArch64/cpus.ll
===
--- llvm/test/CodeGen/AArch64/cpus.ll
+++ llvm/test/CodeGen/AArch64/cpus.ll
@@ -24,6 +24,7 @@
 ; RUN: llc < %s

[PATCH] D78129: Add Marvell ThunderX3T110 support

2020-05-10 Thread Wei Zhao via Phabricator via cfe-commits 
wxz2020 updated this revision to Diff 263081.
wxz2020 added a comment.

fix a typo, thunderx3t110, not thunderx3t100 in TargetParserTest.cpp


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D78129/new/

https://reviews.llvm.org/D78129

Files:
  llvm/include/llvm/Support/AArch64TargetParser.def
  llvm/lib/Target/AArch64/AArch64.td
  llvm/lib/Target/AArch64/AArch64SchedA53.td
  llvm/lib/Target/AArch64/AArch64SchedA57.td
  llvm/lib/Target/AArch64/AArch64SchedCyclone.td
  llvm/lib/Target/AArch64/AArch64SchedExynosM3.td
  llvm/lib/Target/AArch64/AArch64SchedExynosM4.td
  llvm/lib/Target/AArch64/AArch64SchedExynosM5.td
  llvm/lib/Target/AArch64/AArch64SchedFalkor.td
  llvm/lib/Target/AArch64/AArch64SchedKryo.td
  llvm/lib/Target/AArch64/AArch64SchedThunderX.td
  llvm/lib/Target/AArch64/AArch64SchedThunderX2T99.td
  llvm/lib/Target/AArch64/AArch64SchedThunderX3T110.td
  llvm/lib/Target/AArch64/AArch64Subtarget.cpp
  llvm/lib/Target/AArch64/AArch64Subtarget.h
  llvm/test/CodeGen/AArch64/aarch64-combine-fmul-fsub.mir
  llvm/test/CodeGen/AArch64/cpus.ll
  llvm/test/CodeGen/AArch64/machine-combiner-madd.ll
  llvm/test/CodeGen/AArch64/preferred-function-alignment.ll
  llvm/test/CodeGen/AArch64/remat.ll
  llvm/unittests/Support/TargetParserTest.cpp

Index: llvm/unittests/Support/TargetParserTest.cpp
===
--- llvm/unittests/Support/TargetParserTest.cpp
+++ llvm/unittests/Support/TargetParserTest.cpp
@@ -942,6 +942,12 @@
   "thunderx2t99", "armv8.1-a", "crypto-neon-fp-armv8",
   AArch64::AEK_CRC | AArch64::AEK_CRYPTO | AArch64::AEK_LSE |
   AArch64::AEK_RDM | AArch64::AEK_FP | AArch64::AEK_SIMD, "8.1-A"));
+  EXPECT_TRUE(testAArch64CPU(
+  "thunderx3t110", "armv8.3-a", "crypto-neon-fp-armv8",
+  AArch64::AEK_CRC | AArch64::AEK_CRYPTO | AArch64::AEK_LSE |
+  AArch64::AEK_RDM | AArch64::AEK_FP | AArch64::AEK_SIMD |
+  AArch64::AEK_PROFILE | AArch64::AEK_RAS,
+  "8.3-A"));
   EXPECT_TRUE(testAArch64CPU(
   "thunderx", "armv8-a", "crypto-neon-fp-armv8",
   AArch64::AEK_CRC | AArch64::AEK_CRYPTO | AArch64::AEK_SIMD |
@@ -983,7 +989,7 @@
   "8.2-A"));
 }
 
-static constexpr unsigned NumAArch64CPUArchs = 38;
+static constexpr unsigned NumAArch64CPUArchs = 39;
 
 TEST(TargetParserTest, testAArch64CPUArchList) {
   SmallVector List;
Index: llvm/test/CodeGen/AArch64/remat.ll
===
--- llvm/test/CodeGen/AArch64/remat.ll
+++ llvm/test/CodeGen/AArch64/remat.ll
@@ -19,6 +19,7 @@
 ; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=thunderx2t99 -o - %s | FileCheck %s
 ; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=tsv110 -o - %s | FileCheck %s
 ; RUN: llc -mtriple=aarch64-linux-gnuabi -mattr=+custom-cheap-as-move -o - %s | FileCheck %s
+; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=thunderx3t110 -o - %s | FileCheck %s
 
 %X = type { i64, i64, i64 }
 declare void @f(%X*)
Index: llvm/test/CodeGen/AArch64/preferred-function-alignment.ll
===
--- llvm/test/CodeGen/AArch64/preferred-function-alignment.ll
+++ llvm/test/CodeGen/AArch64/preferred-function-alignment.ll
@@ -19,6 +19,7 @@
 ; RUN: llc -mtriple=aarch64-unknown-linux -mcpu=thunderxt83 < %s | FileCheck --check-prefixes=ALIGN3,CHECK %s
 ; RUN: llc -mtriple=aarch64-unknown-linux -mcpu=thunderxt88 < %s | FileCheck --check-prefixes=ALIGN3,CHECK %s
 ; RUN: llc -mtriple=aarch64-unknown-linux -mcpu=thunderx2t99 < %s | FileCheck --check-prefixes=ALIGN3,CHECK %s
+; RUN: llc -mtriple=aarch64-unknown-linux -mcpu=thunderx3t110 < %s | FileCheck --check-prefixes=ALIGN4,CHECK %s
 ; RUN: llc -mtriple=aarch64-unknown-linux -mcpu=exynos-m3 < %s | FileCheck --check-prefixes=ALIGN5,CHECK %s
 
 define void @test() {
Index: llvm/test/CodeGen/AArch64/machine-combiner-madd.ll
===
--- llvm/test/CodeGen/AArch64/machine-combiner-madd.ll
+++ llvm/test/CodeGen/AArch64/machine-combiner-madd.ll
@@ -6,6 +6,7 @@
 ; RUN: llc -mtriple=aarch64-linux-gnu -mcpu=exynos-m3  < %s | FileCheck %s
 ; RUN: llc -mtriple=aarch64-linux-gnu -mcpu=kryo   < %s | FileCheck %s
 ; RUN: llc -mtriple=aarch64-linux-gnu -mcpu=thunderx2t99 < %s | FileCheck %s
+; RUN: llc -mtriple=aarch64-linux-gnu -mcpu=thunderx3t110 < %s | FileCheck %s
 
 ; Make sure that inst-combine fuses the multiply add in the addressing mode of
 ; the load.
Index: llvm/test/CodeGen/AArch64/cpus.ll
===
--- llvm/test/CodeGen/AArch64/cpus.ll
+++ llvm/test/CodeGen/AArch64/cpus.ll
@@ -24,6 +24,7 @@
 ; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=saphira 2>&1 | FileCheck %s
 ; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=kryo 2>&1 | FileCheck %s
 ; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=thunderx2t99 2>&1 | FileCheck %s
+; RUN: llc < %s -mtriple=arm64-unknown-unknown

[PATCH] D78129: Add Marvell ThunderX3T110 support

2020-05-10 Thread Wei Zhao via Phabricator via cfe-commits 
wxz2020 updated this revision to Diff 263079.
wxz2020 added a comment.

Fix the format issue in TargetParserTest.cpp


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D78129/new/

https://reviews.llvm.org/D78129

Files:
  llvm/include/llvm/Support/AArch64TargetParser.def
  llvm/lib/Target/AArch64/AArch64.td
  llvm/lib/Target/AArch64/AArch64SchedA53.td
  llvm/lib/Target/AArch64/AArch64SchedA57.td
  llvm/lib/Target/AArch64/AArch64SchedCyclone.td
  llvm/lib/Target/AArch64/AArch64SchedExynosM3.td
  llvm/lib/Target/AArch64/AArch64SchedExynosM4.td
  llvm/lib/Target/AArch64/AArch64SchedExynosM5.td
  llvm/lib/Target/AArch64/AArch64SchedFalkor.td
  llvm/lib/Target/AArch64/AArch64SchedKryo.td
  llvm/lib/Target/AArch64/AArch64SchedThunderX.td
  llvm/lib/Target/AArch64/AArch64SchedThunderX2T99.td
  llvm/lib/Target/AArch64/AArch64SchedThunderX3T110.td
  llvm/lib/Target/AArch64/AArch64Subtarget.cpp
  llvm/lib/Target/AArch64/AArch64Subtarget.h
  llvm/test/CodeGen/AArch64/aarch64-combine-fmul-fsub.mir
  llvm/test/CodeGen/AArch64/cpus.ll
  llvm/test/CodeGen/AArch64/machine-combiner-madd.ll
  llvm/test/CodeGen/AArch64/preferred-function-alignment.ll
  llvm/test/CodeGen/AArch64/remat.ll
  llvm/unittests/Support/TargetParserTest.cpp

Index: llvm/unittests/Support/TargetParserTest.cpp
===
--- llvm/unittests/Support/TargetParserTest.cpp
+++ llvm/unittests/Support/TargetParserTest.cpp
@@ -942,6 +942,12 @@
   "thunderx2t99", "armv8.1-a", "crypto-neon-fp-armv8",
   AArch64::AEK_CRC | AArch64::AEK_CRYPTO | AArch64::AEK_LSE |
   AArch64::AEK_RDM | AArch64::AEK_FP | AArch64::AEK_SIMD, "8.1-A"));
+  EXPECT_TRUE(testAArch64CPU(
+  "thunderx3t100", "armv8.3-a", "crypto-neon-fp-armv8",
+  AArch64::AEK_CRC | AArch64::AEK_CRYPTO | AArch64::AEK_LSE |
+  AArch64::AEK_RDM | AArch64::AEK_FP | AArch64::AEK_SIMD |
+  AArch64::AEK_PROFILE | AArch64::AEK_RAS,
+  "8.3-A"));
   EXPECT_TRUE(testAArch64CPU(
   "thunderx", "armv8-a", "crypto-neon-fp-armv8",
   AArch64::AEK_CRC | AArch64::AEK_CRYPTO | AArch64::AEK_SIMD |
@@ -983,7 +989,7 @@
   "8.2-A"));
 }
 
-static constexpr unsigned NumAArch64CPUArchs = 38;
+static constexpr unsigned NumAArch64CPUArchs = 39;
 
 TEST(TargetParserTest, testAArch64CPUArchList) {
   SmallVector List;
Index: llvm/test/CodeGen/AArch64/remat.ll
===
--- llvm/test/CodeGen/AArch64/remat.ll
+++ llvm/test/CodeGen/AArch64/remat.ll
@@ -19,6 +19,7 @@
 ; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=thunderx2t99 -o - %s | FileCheck %s
 ; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=tsv110 -o - %s | FileCheck %s
 ; RUN: llc -mtriple=aarch64-linux-gnuabi -mattr=+custom-cheap-as-move -o - %s | FileCheck %s
+; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=thunderx3t110 -o - %s | FileCheck %s
 
 %X = type { i64, i64, i64 }
 declare void @f(%X*)
Index: llvm/test/CodeGen/AArch64/preferred-function-alignment.ll
===
--- llvm/test/CodeGen/AArch64/preferred-function-alignment.ll
+++ llvm/test/CodeGen/AArch64/preferred-function-alignment.ll
@@ -19,6 +19,7 @@
 ; RUN: llc -mtriple=aarch64-unknown-linux -mcpu=thunderxt83 < %s | FileCheck --check-prefixes=ALIGN3,CHECK %s
 ; RUN: llc -mtriple=aarch64-unknown-linux -mcpu=thunderxt88 < %s | FileCheck --check-prefixes=ALIGN3,CHECK %s
 ; RUN: llc -mtriple=aarch64-unknown-linux -mcpu=thunderx2t99 < %s | FileCheck --check-prefixes=ALIGN3,CHECK %s
+; RUN: llc -mtriple=aarch64-unknown-linux -mcpu=thunderx3t110 < %s | FileCheck --check-prefixes=ALIGN4,CHECK %s
 ; RUN: llc -mtriple=aarch64-unknown-linux -mcpu=exynos-m3 < %s | FileCheck --check-prefixes=ALIGN5,CHECK %s
 
 define void @test() {
Index: llvm/test/CodeGen/AArch64/machine-combiner-madd.ll
===
--- llvm/test/CodeGen/AArch64/machine-combiner-madd.ll
+++ llvm/test/CodeGen/AArch64/machine-combiner-madd.ll
@@ -6,6 +6,7 @@
 ; RUN: llc -mtriple=aarch64-linux-gnu -mcpu=exynos-m3  < %s | FileCheck %s
 ; RUN: llc -mtriple=aarch64-linux-gnu -mcpu=kryo   < %s | FileCheck %s
 ; RUN: llc -mtriple=aarch64-linux-gnu -mcpu=thunderx2t99 < %s | FileCheck %s
+; RUN: llc -mtriple=aarch64-linux-gnu -mcpu=thunderx3t110 < %s | FileCheck %s
 
 ; Make sure that inst-combine fuses the multiply add in the addressing mode of
 ; the load.
Index: llvm/test/CodeGen/AArch64/cpus.ll
===
--- llvm/test/CodeGen/AArch64/cpus.ll
+++ llvm/test/CodeGen/AArch64/cpus.ll
@@ -24,6 +24,7 @@
 ; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=saphira 2>&1 | FileCheck %s
 ; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=kryo 2>&1 | FileCheck %s
 ; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=thunderx2t99 2>&1 | FileCheck %s
+; RUN: llc < %s -mtriple=arm64-unknown-unknown

[PATCH] D78129: Add Marvell ThunderX3T110 support

2020-05-10 Thread Wei Zhao via Phabricator via cfe-commits 
wxz2020 updated this revision to Diff 263070.
wxz2020 added a comment.

1. Added the predicates as suggested
2. brought back the TargetParserTest.cpp which was missed last time


Repository:
  rG LLVM Github Monorepo

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Files:
  llvm/include/llvm/Support/AArch64TargetParser.def
  llvm/lib/Target/AArch64/AArch64.td
  llvm/lib/Target/AArch64/AArch64SchedA53.td
  llvm/lib/Target/AArch64/AArch64SchedA57.td
  llvm/lib/Target/AArch64/AArch64SchedCyclone.td
  llvm/lib/Target/AArch64/AArch64SchedExynosM3.td
  llvm/lib/Target/AArch64/AArch64SchedExynosM4.td
  llvm/lib/Target/AArch64/AArch64SchedExynosM5.td
  llvm/lib/Target/AArch64/AArch64SchedFalkor.td
  llvm/lib/Target/AArch64/AArch64SchedKryo.td
  llvm/lib/Target/AArch64/AArch64SchedThunderX.td
  llvm/lib/Target/AArch64/AArch64SchedThunderX2T99.td
  llvm/lib/Target/AArch64/AArch64SchedThunderX3T110.td
  llvm/lib/Target/AArch64/AArch64Subtarget.cpp
  llvm/lib/Target/AArch64/AArch64Subtarget.h
  llvm/test/CodeGen/AArch64/aarch64-combine-fmul-fsub.mir
  llvm/test/CodeGen/AArch64/cpus.ll
  llvm/test/CodeGen/AArch64/machine-combiner-madd.ll
  llvm/test/CodeGen/AArch64/preferred-function-alignment.ll
  llvm/test/CodeGen/AArch64/remat.ll
  llvm/unittests/Support/TargetParserTest.cpp

Index: llvm/unittests/Support/TargetParserTest.cpp
===
--- llvm/unittests/Support/TargetParserTest.cpp
+++ llvm/unittests/Support/TargetParserTest.cpp
@@ -942,6 +942,11 @@
   "thunderx2t99", "armv8.1-a", "crypto-neon-fp-armv8",
   AArch64::AEK_CRC | AArch64::AEK_CRYPTO | AArch64::AEK_LSE |
   AArch64::AEK_RDM | AArch64::AEK_FP | AArch64::AEK_SIMD, "8.1-A"));
+  EXPECT_TRUE(testAArch64CPU(
+  "thunderx3t100", "armv8.3-a", "crypto-neon-fp-armv8",
+  AArch64::AEK_CRC | AArch64::AEK_CRYPTO | AArch64::AEK_LSE |
+  AArch64::AEK_RDM | AArch64::AEK_FP | AArch64::AEK_SIMD |
+  AArch64::AEK_PROFILE | AArch64::AEK_RAS, "8.3-A"));
   EXPECT_TRUE(testAArch64CPU(
   "thunderx", "armv8-a", "crypto-neon-fp-armv8",
   AArch64::AEK_CRC | AArch64::AEK_CRYPTO | AArch64::AEK_SIMD |
@@ -983,7 +988,7 @@
   "8.2-A"));
 }
 
-static constexpr unsigned NumAArch64CPUArchs = 38;
+static constexpr unsigned NumAArch64CPUArchs = 39;
 
 TEST(TargetParserTest, testAArch64CPUArchList) {
   SmallVector List;
Index: llvm/test/CodeGen/AArch64/remat.ll
===
--- llvm/test/CodeGen/AArch64/remat.ll
+++ llvm/test/CodeGen/AArch64/remat.ll
@@ -19,6 +19,7 @@
 ; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=thunderx2t99 -o - %s | FileCheck %s
 ; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=tsv110 -o - %s | FileCheck %s
 ; RUN: llc -mtriple=aarch64-linux-gnuabi -mattr=+custom-cheap-as-move -o - %s | FileCheck %s
+; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=thunderx3t110 -o - %s | FileCheck %s
 
 %X = type { i64, i64, i64 }
 declare void @f(%X*)
Index: llvm/test/CodeGen/AArch64/preferred-function-alignment.ll
===
--- llvm/test/CodeGen/AArch64/preferred-function-alignment.ll
+++ llvm/test/CodeGen/AArch64/preferred-function-alignment.ll
@@ -19,6 +19,7 @@
 ; RUN: llc -mtriple=aarch64-unknown-linux -mcpu=thunderxt83 < %s | FileCheck --check-prefixes=ALIGN3,CHECK %s
 ; RUN: llc -mtriple=aarch64-unknown-linux -mcpu=thunderxt88 < %s | FileCheck --check-prefixes=ALIGN3,CHECK %s
 ; RUN: llc -mtriple=aarch64-unknown-linux -mcpu=thunderx2t99 < %s | FileCheck --check-prefixes=ALIGN3,CHECK %s
+; RUN: llc -mtriple=aarch64-unknown-linux -mcpu=thunderx3t110 < %s | FileCheck --check-prefixes=ALIGN4,CHECK %s
 ; RUN: llc -mtriple=aarch64-unknown-linux -mcpu=exynos-m3 < %s | FileCheck --check-prefixes=ALIGN5,CHECK %s
 
 define void @test() {
Index: llvm/test/CodeGen/AArch64/machine-combiner-madd.ll
===
--- llvm/test/CodeGen/AArch64/machine-combiner-madd.ll
+++ llvm/test/CodeGen/AArch64/machine-combiner-madd.ll
@@ -6,6 +6,7 @@
 ; RUN: llc -mtriple=aarch64-linux-gnu -mcpu=exynos-m3  < %s | FileCheck %s
 ; RUN: llc -mtriple=aarch64-linux-gnu -mcpu=kryo   < %s | FileCheck %s
 ; RUN: llc -mtriple=aarch64-linux-gnu -mcpu=thunderx2t99 < %s | FileCheck %s
+; RUN: llc -mtriple=aarch64-linux-gnu -mcpu=thunderx3t110 < %s | FileCheck %s
 
 ; Make sure that inst-combine fuses the multiply add in the addressing mode of
 ; the load.
Index: llvm/test/CodeGen/AArch64/cpus.ll
===
--- llvm/test/CodeGen/AArch64/cpus.ll
+++ llvm/test/CodeGen/AArch64/cpus.ll
@@ -24,6 +24,7 @@
 ; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=saphira 2>&1 | FileCheck %s
 ; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=kryo 2>&1 | FileCheck %s
 ; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=thunderx2t99 2>&1 | FileCheck %s
+;

[PATCH] D78129: Add Marvell ThunderX3T110 support

2020-05-08 Thread Wei Zhao via Phabricator via cfe-commits 
wxz2020 added a comment.

Sure I will add Joel's suggestion and other fixes later.

Thanks,


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[PATCH] D78129: Add Marvell ThunderX3T110 support

2020-05-08 Thread Wei Zhao via Phabricator via cfe-commits 
wxz2020 added a comment.

I think I made all the changes mentioned in the feedbacks. Please take sometime 
to review the current version. We are eager to get the first thunderx3t110 
checked in.

There are a few things we plan to do after the 1st version:

1. add more tests as suggested in the review
2. make changes to the predicate for clarity and easy readability
3. solve the PA instruction issue

Let me know if there is anything missing. Thanks,


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[PATCH] D78129: Add Marvell ThunderX3T110 support

2020-05-08 Thread Wei Zhao via Phabricator via cfe-commits 
wxz2020 updated this revision to Diff 262876.
wxz2020 added a comment.

Removed the PA related instructions from the .md file as suggested.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
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Files:
  llvm/include/llvm/Support/AArch64TargetParser.def
  llvm/lib/Target/AArch64/AArch64.td
  llvm/lib/Target/AArch64/AArch64SchedThunderX3T110.td
  llvm/lib/Target/AArch64/AArch64Subtarget.cpp
  llvm/lib/Target/AArch64/AArch64Subtarget.h
  llvm/test/CodeGen/AArch64/aarch64-combine-fmul-fsub.mir
  llvm/test/CodeGen/AArch64/cpus.ll
  llvm/test/CodeGen/AArch64/machine-combiner-madd.ll
  llvm/test/CodeGen/AArch64/preferred-function-alignment.ll
  llvm/test/CodeGen/AArch64/remat.ll

Index: llvm/test/CodeGen/AArch64/remat.ll
===
--- llvm/test/CodeGen/AArch64/remat.ll
+++ llvm/test/CodeGen/AArch64/remat.ll
@@ -19,6 +19,7 @@
 ; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=thunderx2t99 -o - %s | FileCheck %s
 ; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=tsv110 -o - %s | FileCheck %s
 ; RUN: llc -mtriple=aarch64-linux-gnuabi -mattr=+custom-cheap-as-move -o - %s | FileCheck %s
+; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=thunderx3t110 -o - %s | FileCheck %s
 
 %X = type { i64, i64, i64 }
 declare void @f(%X*)
Index: llvm/test/CodeGen/AArch64/preferred-function-alignment.ll
===
--- llvm/test/CodeGen/AArch64/preferred-function-alignment.ll
+++ llvm/test/CodeGen/AArch64/preferred-function-alignment.ll
@@ -19,6 +19,7 @@
 ; RUN: llc -mtriple=aarch64-unknown-linux -mcpu=thunderxt83 < %s | FileCheck --check-prefixes=ALIGN3,CHECK %s
 ; RUN: llc -mtriple=aarch64-unknown-linux -mcpu=thunderxt88 < %s | FileCheck --check-prefixes=ALIGN3,CHECK %s
 ; RUN: llc -mtriple=aarch64-unknown-linux -mcpu=thunderx2t99 < %s | FileCheck --check-prefixes=ALIGN3,CHECK %s
+; RUN: llc -mtriple=aarch64-unknown-linux -mcpu=thunderx3t110 < %s | FileCheck --check-prefixes=ALIGN4,CHECK %s
 ; RUN: llc -mtriple=aarch64-unknown-linux -mcpu=exynos-m3 < %s | FileCheck --check-prefixes=ALIGN5,CHECK %s
 
 define void @test() {
Index: llvm/test/CodeGen/AArch64/machine-combiner-madd.ll
===
--- llvm/test/CodeGen/AArch64/machine-combiner-madd.ll
+++ llvm/test/CodeGen/AArch64/machine-combiner-madd.ll
@@ -6,6 +6,7 @@
 ; RUN: llc -mtriple=aarch64-linux-gnu -mcpu=exynos-m3  < %s | FileCheck %s
 ; RUN: llc -mtriple=aarch64-linux-gnu -mcpu=kryo   < %s | FileCheck %s
 ; RUN: llc -mtriple=aarch64-linux-gnu -mcpu=thunderx2t99 < %s | FileCheck %s
+; RUN: llc -mtriple=aarch64-linux-gnu -mcpu=thunderx3t110 < %s | FileCheck %s
 
 ; Make sure that inst-combine fuses the multiply add in the addressing mode of
 ; the load.
Index: llvm/test/CodeGen/AArch64/cpus.ll
===
--- llvm/test/CodeGen/AArch64/cpus.ll
+++ llvm/test/CodeGen/AArch64/cpus.ll
@@ -24,6 +24,7 @@
 ; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=saphira 2>&1 | FileCheck %s
 ; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=kryo 2>&1 | FileCheck %s
 ; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=thunderx2t99 2>&1 | FileCheck %s
+; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=thunderx3t110 2>&1 | FileCheck %s
 ; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=tsv110 2>&1 | FileCheck %s
 ; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=apple-latest 2>&1 | FileCheck %s
 ; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=a64fx 2>&1 | FileCheck %s
Index: llvm/test/CodeGen/AArch64/aarch64-combine-fmul-fsub.mir
===
--- llvm/test/CodeGen/AArch64/aarch64-combine-fmul-fsub.mir
+++ llvm/test/CodeGen/AArch64/aarch64-combine-fmul-fsub.mir
@@ -2,6 +2,7 @@
 # RUN: llc -run-pass=machine-combiner -o - -mtriple=aarch64-unknown-linux -mcpu=falkor -enable-unsafe-fp-math %s -machine-combiner-verify-pattern-order=true | FileCheck --check-prefixes=PROFITABLE,ALL %s
 # RUN: llc -run-pass=machine-combiner -o - -mtriple=aarch64-unknown-linux -mcpu=exynos-m3 -enable-unsafe-fp-math -machine-combiner-verify-pattern-order=true %s | FileCheck --check-prefixes=PROFITABLE,ALL %s
 # RUN: llc -run-pass=machine-combiner -o - -mtriple=aarch64-unknown-linux -mcpu=thunderx2t99 -enable-unsafe-fp-math -machine-combiner-verify-pattern-order=true %s | FileCheck --check-prefixes=PROFITABLE,ALL %s
+# RUN: llc -run-pass=machine-combiner -o - -mtriple=aarch64-unknown-linux -mcpu=thunderx3t110 -enable-unsafe-fp-math -machine-combiner-verify-pattern-order=true %s | FileCheck --check-prefixes=PROFITABLE,ALL %s
 #
 name:f1_2s
 registers:
Index: llvm/lib/Target/AArch64/AArch64Subtarget.h
===
--- llvm/lib/Target/AArch64/AArch64Subtarget.h
+++

[PATCH] D78129: Add Marvell ThunderX3T110 support

2020-05-07 Thread Wei Zhao via Phabricator via cfe-commits 
wxz2020 added a comment.

I will put the "PAUnsupported" predicate later once this got passed.


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[PATCH] D78129: Add Marvell ThunderX3T110 support

2020-05-07 Thread Wei Zhao via Phabricator via cfe-commits 
wxz2020 updated this revision to Diff 262665.
wxz2020 added a comment.

I put every people's feedbacks into the code and upload them here.

I think we can use it as the start point for TX3, and add more when we move on.

Thank you all for great help,


Repository:
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Files:
  llvm/include/llvm/Support/AArch64TargetParser.def
  llvm/lib/Target/AArch64/AArch64.td
  llvm/lib/Target/AArch64/AArch64SchedThunderX3T110.td
  llvm/lib/Target/AArch64/AArch64Subtarget.cpp
  llvm/lib/Target/AArch64/AArch64Subtarget.h
  llvm/test/CodeGen/AArch64/aarch64-combine-fmul-fsub.mir
  llvm/test/CodeGen/AArch64/cpus.ll
  llvm/test/CodeGen/AArch64/machine-combiner-madd.ll
  llvm/test/CodeGen/AArch64/preferred-function-alignment.ll
  llvm/test/CodeGen/AArch64/remat.ll

Index: llvm/test/CodeGen/AArch64/remat.ll
===
--- llvm/test/CodeGen/AArch64/remat.ll
+++ llvm/test/CodeGen/AArch64/remat.ll
@@ -19,6 +19,7 @@
 ; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=thunderx2t99 -o - %s | FileCheck %s
 ; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=tsv110 -o - %s | FileCheck %s
 ; RUN: llc -mtriple=aarch64-linux-gnuabi -mattr=+custom-cheap-as-move -o - %s | FileCheck %s
+; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=thunderx3t110 -o - %s | FileCheck %s
 
 %X = type { i64, i64, i64 }
 declare void @f(%X*)
Index: llvm/test/CodeGen/AArch64/preferred-function-alignment.ll
===
--- llvm/test/CodeGen/AArch64/preferred-function-alignment.ll
+++ llvm/test/CodeGen/AArch64/preferred-function-alignment.ll
@@ -19,6 +19,7 @@
 ; RUN: llc -mtriple=aarch64-unknown-linux -mcpu=thunderxt83 < %s | FileCheck --check-prefixes=ALIGN3,CHECK %s
 ; RUN: llc -mtriple=aarch64-unknown-linux -mcpu=thunderxt88 < %s | FileCheck --check-prefixes=ALIGN3,CHECK %s
 ; RUN: llc -mtriple=aarch64-unknown-linux -mcpu=thunderx2t99 < %s | FileCheck --check-prefixes=ALIGN3,CHECK %s
+; RUN: llc -mtriple=aarch64-unknown-linux -mcpu=thunderx3t110 < %s | FileCheck --check-prefixes=ALIGN4,CHECK %s
 ; RUN: llc -mtriple=aarch64-unknown-linux -mcpu=exynos-m3 < %s | FileCheck --check-prefixes=ALIGN5,CHECK %s
 
 define void @test() {
Index: llvm/test/CodeGen/AArch64/machine-combiner-madd.ll
===
--- llvm/test/CodeGen/AArch64/machine-combiner-madd.ll
+++ llvm/test/CodeGen/AArch64/machine-combiner-madd.ll
@@ -6,6 +6,7 @@
 ; RUN: llc -mtriple=aarch64-linux-gnu -mcpu=exynos-m3  < %s | FileCheck %s
 ; RUN: llc -mtriple=aarch64-linux-gnu -mcpu=kryo   < %s | FileCheck %s
 ; RUN: llc -mtriple=aarch64-linux-gnu -mcpu=thunderx2t99 < %s | FileCheck %s
+; RUN: llc -mtriple=aarch64-linux-gnu -mcpu=thunderx3t110 < %s | FileCheck %s
 
 ; Make sure that inst-combine fuses the multiply add in the addressing mode of
 ; the load.
Index: llvm/test/CodeGen/AArch64/cpus.ll
===
--- llvm/test/CodeGen/AArch64/cpus.ll
+++ llvm/test/CodeGen/AArch64/cpus.ll
@@ -24,6 +24,7 @@
 ; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=saphira 2>&1 | FileCheck %s
 ; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=kryo 2>&1 | FileCheck %s
 ; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=thunderx2t99 2>&1 | FileCheck %s
+; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=thunderx3t110 2>&1 | FileCheck %s
 ; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=tsv110 2>&1 | FileCheck %s
 ; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=apple-latest 2>&1 | FileCheck %s
 ; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=a64fx 2>&1 | FileCheck %s
Index: llvm/test/CodeGen/AArch64/aarch64-combine-fmul-fsub.mir
===
--- llvm/test/CodeGen/AArch64/aarch64-combine-fmul-fsub.mir
+++ llvm/test/CodeGen/AArch64/aarch64-combine-fmul-fsub.mir
@@ -2,6 +2,7 @@
 # RUN: llc -run-pass=machine-combiner -o - -mtriple=aarch64-unknown-linux -mcpu=falkor -enable-unsafe-fp-math %s -machine-combiner-verify-pattern-order=true | FileCheck --check-prefixes=PROFITABLE,ALL %s
 # RUN: llc -run-pass=machine-combiner -o - -mtriple=aarch64-unknown-linux -mcpu=exynos-m3 -enable-unsafe-fp-math -machine-combiner-verify-pattern-order=true %s | FileCheck --check-prefixes=PROFITABLE,ALL %s
 # RUN: llc -run-pass=machine-combiner -o - -mtriple=aarch64-unknown-linux -mcpu=thunderx2t99 -enable-unsafe-fp-math -machine-combiner-verify-pattern-order=true %s | FileCheck --check-prefixes=PROFITABLE,ALL %s
+# RUN: llc -run-pass=machine-combiner -o - -mtriple=aarch64-unknown-linux -mcpu=thunderx3t110 -enable-unsafe-fp-math -machine-combiner-verify-pattern-order=true %s | FileCheck --check-prefixes=PROFITABLE,ALL %s
 #
 name:f1_2s
 registers:
Index: llvm/lib/Target/AArch64/AArch64Subtarget.h

[PATCH] D78129: Add Marvell ThunderX3T110 support

2020-05-06 Thread Wei Zhao via Phabricator via cfe-commits 
wxz2020 added a comment.

I can confirm your findings, basically as long as we comment out the new 
instructions, it will be OK to build.

Agree with your changes 1), 2) and 3).

4. this seems does not matter to build, as long as we comment out the new 
instructions in 5), setting it "1" or "0", both are OK. they all can be compiled

5. if we comment out these instructions, then we will not be able to schedule 
them efficiently in the instruction scheduler. I know in other models or 
earlier versions, they could be treated as NOP, but in our new machine, they do 
have a timing effect, 7 cycles to finish. Any way to represent this in .md?

Thanks a lot for the help,


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[PATCH] D78129: Add Marvell ThunderX3T110 support

2020-05-06 Thread Wei Zhao via Phabricator via cfe-commits 
wxz2020 marked an inline comment as done.
wxz2020 added a comment.

I tried to set CompleteModel = 0 on line 25 in file 
llvm/lib/Target/AArch64/AArch64SchedThunderX3T110.td

The same error is still there.




Comment at: llvm/lib/Target/AArch64/AArch64InstrInfo.td:849-857
+// These pointer authentication instructions require armv8.3a
+let Predicates = [HasV8_3a, HasPA] in {
 let Uses = [LR], Defs = [LR] in {
   def PACIAZ   : SystemNoOperands<0b000, "hint\t#24">;
   def PACIBZ   : SystemNoOperands<0b010, "hint\t#26">;
   let isAuthenticated = 1 in {
 def AUTIAZ   : SystemNoOperands<0b100, "hint\t#28">;

wxz2020 wrote:
> chill wrote:
> > wxz2020 wrote:
> > > wxz2020 wrote:
> > > > ktkachov wrote:
> > > > > IIRC these instructions are deliberately allowed in pre-armv8.3 
> > > > > targets because they are encoded in the NOP-space and can be deployed 
> > > > > on pre-armv8.3 targets 
> > > > I will do some research on this.
> > > According to the documents, pointer authenticatoin got officially 
> > > supporoted starting from armv8.3.  
> > These instructions are executed as NOP on pre v8.3-A architectures. It 
> > allows you to have a single compatible binary that works correctly on pre 
> > v8.3-a (ofc, without pointer authentication), as well as on
> > 8.3-a and later cores, with pointer authentication.
> > 
> > Please, remove the predicates.
> Agree. Will remove it.
One questions here, we want to model these instructions in our machine model, 
scroll down to line 1992-1997, in
llvm/lib/Target/AArch64/AArch64SchedThunderX3T110.td below.

However, if we remove this predicate here, tblgen will complain the following 
errors for all the instructions defined in line 1992-1997: 

error message from tblgen
=
Included from 
/home/wei/project/tx3/llvm-project/llvm/lib/Target/AArch64/AArch64.td:439:
/home/wei/project/tx3/llvm-project/llvm/lib/Target/AArch64/AArch64InstrInfo.td:961:5:
 error: 'CycloneModel' lacks information for 'AUTDZA'
def DZA  : SignAuthZero;
^
In the end:
Incomplete schedule models found.
- Consider setting 'CompleteModel = 0' while developing new models.
- Pseudo instructions can be marked with 'hasNoSchedulingInfo = 1'.
- Instructions should usually have Sched<[...]> as a superclass, you may 
temporarily use an empty list.
- Instructions related to unsupported features can be excluded with 
list UnsupportedFeatures = [HasA,..,HasY]; in the processor model.

error: Incomplete schedule model
=

Anyone has clue why we have this problem? How should I model these instructions 
in the .md file.

Thanks,


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[PATCH] D78129: Add Marvell ThunderX3T110 support

2020-05-01 Thread Wei Zhao via Phabricator via cfe-commits 
wxz2020 updated this revision to Diff 261497.
wxz2020 marked an inline comment as done.
wxz2020 added a comment.

fixed all the feedback suggestions. Thanks,


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Files:
  llvm/include/llvm/Support/AArch64TargetParser.def
  llvm/lib/Target/AArch64/AArch64.td
  llvm/lib/Target/AArch64/AArch64InstrInfo.td
  llvm/lib/Target/AArch64/AArch64SchedA53.td
  llvm/lib/Target/AArch64/AArch64SchedA57.td
  llvm/lib/Target/AArch64/AArch64SchedCyclone.td
  llvm/lib/Target/AArch64/AArch64SchedExynosM3.td
  llvm/lib/Target/AArch64/AArch64SchedExynosM4.td
  llvm/lib/Target/AArch64/AArch64SchedExynosM5.td
  llvm/lib/Target/AArch64/AArch64SchedFalkor.td
  llvm/lib/Target/AArch64/AArch64SchedKryo.td
  llvm/lib/Target/AArch64/AArch64SchedThunderX.td
  llvm/lib/Target/AArch64/AArch64SchedThunderX2T99.td
  llvm/lib/Target/AArch64/AArch64SchedThunderX3T110.td
  llvm/lib/Target/AArch64/AArch64Subtarget.cpp
  llvm/lib/Target/AArch64/AArch64Subtarget.h
  llvm/test/CodeGen/AArch64/aarch64-combine-fmul-fsub.mir
  llvm/test/CodeGen/AArch64/cpus.ll
  llvm/test/CodeGen/AArch64/machine-combiner-madd.ll
  llvm/test/CodeGen/AArch64/preferred-function-alignment.ll
  llvm/test/CodeGen/AArch64/remat.ll
  llvm/unittests/Support/TargetParserTest.cpp

Index: llvm/unittests/Support/TargetParserTest.cpp
===
--- llvm/unittests/Support/TargetParserTest.cpp
+++ llvm/unittests/Support/TargetParserTest.cpp
@@ -943,6 +943,11 @@
   AArch64::AEK_CRC | AArch64::AEK_CRYPTO | AArch64::AEK_LSE |
   AArch64::AEK_RDM | AArch64::AEK_FP | AArch64::AEK_SIMD, "8.1-A"));
   EXPECT_TRUE(testAArch64CPU(
+  "thunderx3t110", "armv8.3-a", "crypto-neon-fp-armv8",
+  AArch64::AEK_CRC | AArch64::AEK_CRYPTO | AArch64::AEK_LSE |
+  AArch64::AEK_RDM | AArch64::AEK_FP | AArch64::AEK_SIMD |
+  AArch64::AEK_RAS | AArch64::AEK_PROFILE, "8.3-A"));
+  EXPECT_TRUE(testAArch64CPU(
   "thunderx", "armv8-a", "crypto-neon-fp-armv8",
   AArch64::AEK_CRC | AArch64::AEK_CRYPTO | AArch64::AEK_SIMD |
   AArch64::AEK_FP | AArch64::AEK_PROFILE,
@@ -977,7 +982,7 @@
   "8.2-A"));
 }
 
-static constexpr unsigned NumAArch64CPUArchs = 37;
+static constexpr unsigned NumAArch64CPUArchs = 38;
 
 TEST(TargetParserTest, testAArch64CPUArchList) {
   SmallVector List;
Index: llvm/test/CodeGen/AArch64/remat.ll
===
--- llvm/test/CodeGen/AArch64/remat.ll
+++ llvm/test/CodeGen/AArch64/remat.ll
@@ -19,6 +19,7 @@
 ; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=thunderx2t99 -o - %s | FileCheck %s
 ; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=tsv110 -o - %s | FileCheck %s
 ; RUN: llc -mtriple=aarch64-linux-gnuabi -mattr=+custom-cheap-as-move -o - %s | FileCheck %s
+; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=thunderx3t110 -o - %s | FileCheck %s
 
 %X = type { i64, i64, i64 }
 declare void @f(%X*)
Index: llvm/test/CodeGen/AArch64/preferred-function-alignment.ll
===
--- llvm/test/CodeGen/AArch64/preferred-function-alignment.ll
+++ llvm/test/CodeGen/AArch64/preferred-function-alignment.ll
@@ -19,6 +19,7 @@
 ; RUN: llc -mtriple=aarch64-unknown-linux -mcpu=thunderxt83 < %s | FileCheck --check-prefixes=ALIGN3,CHECK %s
 ; RUN: llc -mtriple=aarch64-unknown-linux -mcpu=thunderxt88 < %s | FileCheck --check-prefixes=ALIGN3,CHECK %s
 ; RUN: llc -mtriple=aarch64-unknown-linux -mcpu=thunderx2t99 < %s | FileCheck --check-prefixes=ALIGN3,CHECK %s
+; RUN: llc -mtriple=aarch64-unknown-linux -mcpu=thunderx3t110 < %s | FileCheck --check-prefixes=ALIGN4,CHECK %s
 ; RUN: llc -mtriple=aarch64-unknown-linux -mcpu=exynos-m3 < %s | FileCheck --check-prefixes=ALIGN5,CHECK %s
 
 define void @test() {
Index: llvm/test/CodeGen/AArch64/machine-combiner-madd.ll
===
--- llvm/test/CodeGen/AArch64/machine-combiner-madd.ll
+++ llvm/test/CodeGen/AArch64/machine-combiner-madd.ll
@@ -6,6 +6,7 @@
 ; RUN: llc -mtriple=aarch64-linux-gnu -mcpu=exynos-m3  < %s | FileCheck %s
 ; RUN: llc -mtriple=aarch64-linux-gnu -mcpu=kryo   < %s | FileCheck %s
 ; RUN: llc -mtriple=aarch64-linux-gnu -mcpu=thunderx2t99 < %s | FileCheck %s
+; RUN: llc -mtriple=aarch64-linux-gnu -mcpu=thunderx3t110 < %s | FileCheck %s
 
 ; Make sure that inst-combine fuses the multiply add in the addressing mode of
 ; the load.
Index: llvm/test/CodeGen/AArch64/cpus.ll
===
--- llvm/test/CodeGen/AArch64/cpus.ll
+++ llvm/test/CodeGen/AArch64/cpus.ll
@@ -23,6 +23,7 @@
 ; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=saphira 2>&1 | FileCheck %s
 ; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=kryo 2>&1 | FileCheck %s
 ; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=thunderx2t99 2>&1 |

[PATCH] D78129: Add Marvell ThunderX3T110 support

2020-05-01 Thread Wei Zhao via Phabricator via cfe-commits 
wxz2020 marked 7 inline comments as done.
wxz2020 added inline comments.



Comment at: clang/lib/Driver/ToolChains/Arch/AArch64.cpp:89
 CPU = llvm::sys::getHostCPUName();
-
   if (CPU == "generic") {

DavidSpickett wrote:
> Remove stray change.
Removed



Comment at: llvm/include/llvm/Support/AArch64TargetParser.def:167
 AARCH64_CPU_NAME("thunderx2t99", ARMV8_1A, FK_CRYPTO_NEON_FP_ARMV8, false,
- (AArch64::AEK_NONE))
+ (AArch64::AEK_CRC | AEK_CRYPTO | AEK_FP | AEK_SIMD | AEK_LSE 
| AEK_RAND))
+AARCH64_CPU_NAME("thunderx3t110", ARMV8_3A, FK_CRYPTO_NEON_FP_ARMV8, false,

DavidSpickett wrote:
> Is this change also correcting the options for the x2t99? I think that should 
> be a separate patch if so.
I will have it removed. irrelevant to this change.



Comment at: llvm/include/llvm/Support/AArch64TargetParser.def:168
+ (AArch64::AEK_CRC | AEK_CRYPTO | AEK_FP | AEK_SIMD | AEK_LSE 
| AEK_RAND))
+AARCH64_CPU_NAME("thunderx3t110", ARMV8_3A, FK_CRYPTO_NEON_FP_ARMV8, false,
+ (AArch64::AEK_CRC | AEK_CRYPTO | AEK_FP | AEK_SIMD | AEK_LSE 
| AEK_RAND | AArch64::AEK_PROFILE | AArch64::AEK_RAS))

DavidSpickett wrote:
> Add a tests for this in llvm/unittests/Support/TargetParserTest.cpp (there 
> are existing ones for "thunderx2t99").
> Might need to update "NumAArch64CPUArchs" too.
OK, we will have it fixed



Comment at: llvm/lib/Target/AArch64/AArch64InstrInfo.td:849-857
+// These pointer authentication instructions require armv8.3a
+let Predicates = [HasV8_3a, HasPA] in {
 let Uses = [LR], Defs = [LR] in {
   def PACIAZ   : SystemNoOperands<0b000, "hint\t#24">;
   def PACIBZ   : SystemNoOperands<0b010, "hint\t#26">;
   let isAuthenticated = 1 in {
 def AUTIAZ   : SystemNoOperands<0b100, "hint\t#28">;

chill wrote:
> wxz2020 wrote:
> > wxz2020 wrote:
> > > ktkachov wrote:
> > > > IIRC these instructions are deliberately allowed in pre-armv8.3 targets 
> > > > because they are encoded in the NOP-space and can be deployed on 
> > > > pre-armv8.3 targets 
> > > I will do some research on this.
> > According to the documents, pointer authenticatoin got officially 
> > supporoted starting from armv8.3.  
> These instructions are executed as NOP on pre v8.3-A architectures. It allows 
> you to have a single compatible binary that works correctly on pre v8.3-a 
> (ofc, without pointer authentication), as well as on
> 8.3-a and later cores, with pointer authentication.
> 
> Please, remove the predicates.
Agree. Will remove it.



Comment at: llvm/lib/Target/AArch64/AArch64SchedThunderX3T110.td:13
+//===--===//
+
+//===--===//

SjoerdMeijer wrote:
> I don't intend to check the numbers here, but just curious if there's an 
> optimisation guide if people are curious?
We will release a document about the details soon.



Comment at: llvm/test/CodeGen/AArch64/loop-micro-op-buffer-size-t110.ll:25
+; CHECK: %val5 = add nuw nsw i32 %counter, 10
+; CHECK-NOT: %val = add i32 %counter, 5
+; CHECK-NOT: %val = add i32 %counter, 6

SjoerdMeijer wrote:
> I guess there won't be another define %val, it will be %val6, so this 
> CHECK-NOT will never match even if there's another add?
This test is for our internal use. Sorry, Will have it removed.


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[PATCH] D78129: Add Marvell ThunderX3T110 support

2020-04-28 Thread Wei Zhao via Phabricator via cfe-commits 
wxz2020 marked an inline comment as done.
wxz2020 added inline comments.



Comment at: llvm/lib/Target/AArch64/AArch64InstrInfo.td:849-857
+// These pointer authentication instructions require armv8.3a
+let Predicates = [HasV8_3a, HasPA] in {
 let Uses = [LR], Defs = [LR] in {
   def PACIAZ   : SystemNoOperands<0b000, "hint\t#24">;
   def PACIBZ   : SystemNoOperands<0b010, "hint\t#26">;
   let isAuthenticated = 1 in {
 def AUTIAZ   : SystemNoOperands<0b100, "hint\t#28">;

wxz2020 wrote:
> ktkachov wrote:
> > IIRC these instructions are deliberately allowed in pre-armv8.3 targets 
> > because they are encoded in the NOP-space and can be deployed on 
> > pre-armv8.3 targets 
> I will do some research on this.
According to the documents, pointer authenticatoin got officially supporoted 
starting from armv8.3.  


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[PATCH] D78129: Add Marvell ThunderX3T110 support

2020-04-28 Thread Wei Zhao via Phabricator via cfe-commits 
wxz2020 updated this revision to Diff 260680.
wxz2020 added a comment.
Herald added a project: LLVM.
Herald added a subscriber: llvm-commits.

Remove non-official target options.  We now only support -mcpu=thunderx3t110

Typo fix.


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Files:
  clang/lib/Driver/ToolChains/Arch/AArch64.cpp
  llvm/include/llvm/Support/AArch64TargetParser.def
  llvm/lib/Target/AArch64/AArch64.td
  llvm/lib/Target/AArch64/AArch64InstrInfo.td
  llvm/lib/Target/AArch64/AArch64SchedA53.td
  llvm/lib/Target/AArch64/AArch64SchedA57.td
  llvm/lib/Target/AArch64/AArch64SchedCyclone.td
  llvm/lib/Target/AArch64/AArch64SchedExynosM3.td
  llvm/lib/Target/AArch64/AArch64SchedExynosM4.td
  llvm/lib/Target/AArch64/AArch64SchedExynosM5.td
  llvm/lib/Target/AArch64/AArch64SchedFalkor.td
  llvm/lib/Target/AArch64/AArch64SchedKryo.td
  llvm/lib/Target/AArch64/AArch64SchedThunderX.td
  llvm/lib/Target/AArch64/AArch64SchedThunderX2T99.td
  llvm/lib/Target/AArch64/AArch64SchedThunderX3T110.td
  llvm/lib/Target/AArch64/AArch64Subtarget.cpp
  llvm/lib/Target/AArch64/AArch64Subtarget.h
  llvm/test/CodeGen/AArch64/aarch64-combine-fmul-fsub.mir
  llvm/test/CodeGen/AArch64/cpus.ll
  llvm/test/CodeGen/AArch64/loop-micro-op-buffer-size-t110.ll
  llvm/test/CodeGen/AArch64/machine-combiner-madd.ll
  llvm/test/CodeGen/AArch64/preferred-function-alignment.ll
  llvm/test/CodeGen/AArch64/remat.ll

Index: llvm/test/CodeGen/AArch64/remat.ll
===
--- llvm/test/CodeGen/AArch64/remat.ll
+++ llvm/test/CodeGen/AArch64/remat.ll
@@ -19,6 +19,7 @@
 ; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=thunderx2t99 -o - %s | FileCheck %s
 ; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=tsv110 -o - %s | FileCheck %s
 ; RUN: llc -mtriple=aarch64-linux-gnuabi -mattr=+custom-cheap-as-move -o - %s | FileCheck %s
+; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=thunderx3t110 -o - %s | FileCheck %s
 
 %X = type { i64, i64, i64 }
 declare void @f(%X*)
Index: llvm/test/CodeGen/AArch64/preferred-function-alignment.ll
===
--- llvm/test/CodeGen/AArch64/preferred-function-alignment.ll
+++ llvm/test/CodeGen/AArch64/preferred-function-alignment.ll
@@ -19,6 +19,7 @@
 ; RUN: llc -mtriple=aarch64-unknown-linux -mcpu=thunderxt83 < %s | FileCheck --check-prefixes=ALIGN3,CHECK %s
 ; RUN: llc -mtriple=aarch64-unknown-linux -mcpu=thunderxt88 < %s | FileCheck --check-prefixes=ALIGN3,CHECK %s
 ; RUN: llc -mtriple=aarch64-unknown-linux -mcpu=thunderx2t99 < %s | FileCheck --check-prefixes=ALIGN3,CHECK %s
+; RUN: llc -mtriple=aarch64-unknown-linux -mcpu=thunderx3t110 < %s | FileCheck --check-prefixes=ALIGN4,CHECK %s
 ; RUN: llc -mtriple=aarch64-unknown-linux -mcpu=exynos-m3 < %s | FileCheck --check-prefixes=ALIGN5,CHECK %s
 
 define void @test() {
Index: llvm/test/CodeGen/AArch64/machine-combiner-madd.ll
===
--- llvm/test/CodeGen/AArch64/machine-combiner-madd.ll
+++ llvm/test/CodeGen/AArch64/machine-combiner-madd.ll
@@ -6,6 +6,7 @@
 ; RUN: llc -mtriple=aarch64-linux-gnu -mcpu=exynos-m3  < %s | FileCheck %s
 ; RUN: llc -mtriple=aarch64-linux-gnu -mcpu=kryo   < %s | FileCheck %s
 ; RUN: llc -mtriple=aarch64-linux-gnu -mcpu=thunderx2t99 < %s | FileCheck %s
+; RUN: llc -mtriple=aarch64-linux-gnu -mcpu=thunderx3t110 < %s | FileCheck %s
 
 ; Make sure that inst-combine fuses the multiply add in the addressing mode of
 ; the load.
Index: llvm/test/CodeGen/AArch64/loop-micro-op-buffer-size-t110.ll
===
--- /dev/null
+++ llvm/test/CodeGen/AArch64/loop-micro-op-buffer-size-t110.ll
@@ -0,0 +1,124 @@
+; REQUIRES: asserts
+; RUN: opt -mcpu=thunderx3t110 -loop-unroll --debug-only=loop-unroll --debug-only=basicblock-utils -S -unroll-allow-partial < %s 2>&1 | FileCheck %s
+
+target triple = "aarch64-unknown-linux-gnu"
+
+; CHECK: Loop Unroll: F[foo] Loop %loop.2.header
+; CHECK: Loop Size = 19
+; CHECK: Trip Count = 512
+; CHECK: Trip Multiple = 512
+; CHECK: UNROLLING loop %loop.2.header by 4 with a breakout at trip 0
+; CHECK: Merging:
+; CHECK: Loop Unroll: F[foo] Loop %loop.header
+; CHECK:   Loop Size = 18
+; CHECK:   Trip Count = 512
+; CHECK:   Trip Multiple = 512
+; CHECK: UNROLLING loop %loop.header by 4 with a breakout at trip 0
+; CHECK: Merging:
+; CHECK: %counter = phi i32 [ 0, %entry ], [ %inc.3, %loop.inc.3 ]
+; CHECK: %val = add nuw nsw i32 %counter, 5
+; CHECK: %val1 = add nuw nsw i32 %counter, 6
+; CHECK: %val2 = add nuw nsw i32 %counter, 7
+; CHECK: %val3 = add nuw nsw i32 %counter, 8
+; CHECK: %val4 = add nuw nsw i32 %counter, 9
+; CHECK: %val5 = add nuw nsw i32 %counter, 10
+; CHECK-NOT: %val = add i32 %counter, 5
+; CHECK-NOT: %val = add i32 %counter, 6
+; CHECK-NOT: %val = add i32 %counter, 7
+; CHECK-NOT: %val = add i32 %counter, 8
+; CHECK-NOT: %val

[PATCH] D78129: Add Marvell ThunderX3T110 support

2020-04-24 Thread Wei Zhao via Phabricator via cfe-commits 
wxz2020 marked 2 inline comments as done.
wxz2020 added inline comments.



Comment at: llvm/lib/Target/AArch64/AArch64InstrInfo.td:849-857
+// These pointer authentication instructions require armv8.3a
+let Predicates = [HasV8_3a, HasPA] in {
 let Uses = [LR], Defs = [LR] in {
   def PACIAZ   : SystemNoOperands<0b000, "hint\t#24">;
   def PACIBZ   : SystemNoOperands<0b010, "hint\t#26">;
   let isAuthenticated = 1 in {
 def AUTIAZ   : SystemNoOperands<0b100, "hint\t#28">;

ktkachov wrote:
> IIRC these instructions are deliberately allowed in pre-armv8.3 targets 
> because they are encoded in the NOP-space and can be deployed on pre-armv8.3 
> targets 
I will do some research on this.



Comment at: llvm/lib/Target/AArch64/AArch64SchedThunderX3T110.td:9
+//
+// This file defines the scheduling model for Marvell ThunderX3T101
+// family of processors.

ktkachov wrote:
> Typo in the processor name?
Sure, thanks for spotting it. I will have it fixed.


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[PATCH] D78129: Add Marvell ThunderX3T110 support

2020-04-23 Thread Wei Zhao via Phabricator via cfe-commits 
wxz2020 added a comment.

Fix a format issue.


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[PATCH] D78129: Add Marvell ThunderX3T110 support

2020-04-23 Thread Wei Zhao via Phabricator via cfe-commits 
wxz2020 updated this revision to Diff 259737.
wxz2020 added a comment.

fix a format issus.


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Files:
  clang/lib/Driver/ToolChains/Arch/AArch64.cpp
  llvm/include/llvm/Support/AArch64TargetParser.def
  llvm/lib/Target/AArch64/AArch64.td
  llvm/lib/Target/AArch64/AArch64InstrInfo.td
  llvm/lib/Target/AArch64/AArch64SchedA53.td
  llvm/lib/Target/AArch64/AArch64SchedA57.td
  llvm/lib/Target/AArch64/AArch64SchedCyclone.td
  llvm/lib/Target/AArch64/AArch64SchedExynosM3.td
  llvm/lib/Target/AArch64/AArch64SchedExynosM4.td
  llvm/lib/Target/AArch64/AArch64SchedExynosM5.td
  llvm/lib/Target/AArch64/AArch64SchedFalkor.td
  llvm/lib/Target/AArch64/AArch64SchedKryo.td
  llvm/lib/Target/AArch64/AArch64SchedThunderX.td
  llvm/lib/Target/AArch64/AArch64SchedThunderX2T99.td
  llvm/lib/Target/AArch64/AArch64SchedThunderX3T110.td
  llvm/lib/Target/AArch64/AArch64Subtarget.cpp
  llvm/lib/Target/AArch64/AArch64Subtarget.h
  llvm/test/CodeGen/AArch64/aarch64-combine-fmul-fsub.mir
  llvm/test/CodeGen/AArch64/cpus.ll
  llvm/test/CodeGen/AArch64/loop-micro-op-buffer-size-t110.ll
  llvm/test/CodeGen/AArch64/machine-combiner-madd.ll
  llvm/test/CodeGen/AArch64/preferred-function-alignment.ll
  llvm/test/CodeGen/AArch64/remat.ll

Index: llvm/test/CodeGen/AArch64/remat.ll
===
--- llvm/test/CodeGen/AArch64/remat.ll
+++ llvm/test/CodeGen/AArch64/remat.ll
@@ -19,6 +19,7 @@
 ; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=thunderx2t99 -o - %s | FileCheck %s
 ; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=tsv110 -o - %s | FileCheck %s
 ; RUN: llc -mtriple=aarch64-linux-gnuabi -mattr=+custom-cheap-as-move -o - %s | FileCheck %s
+; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=thunderx3t110 -o - %s | FileCheck %s
 
 %X = type { i64, i64, i64 }
 declare void @f(%X*)
Index: llvm/test/CodeGen/AArch64/preferred-function-alignment.ll
===
--- llvm/test/CodeGen/AArch64/preferred-function-alignment.ll
+++ llvm/test/CodeGen/AArch64/preferred-function-alignment.ll
@@ -19,6 +19,7 @@
 ; RUN: llc -mtriple=aarch64-unknown-linux -mcpu=thunderxt83 < %s | FileCheck --check-prefixes=ALIGN3,CHECK %s
 ; RUN: llc -mtriple=aarch64-unknown-linux -mcpu=thunderxt88 < %s | FileCheck --check-prefixes=ALIGN3,CHECK %s
 ; RUN: llc -mtriple=aarch64-unknown-linux -mcpu=thunderx2t99 < %s | FileCheck --check-prefixes=ALIGN3,CHECK %s
+; RUN: llc -mtriple=aarch64-unknown-linux -mcpu=thunderx3t110 < %s | FileCheck --check-prefixes=ALIGN4,CHECK %s
 ; RUN: llc -mtriple=aarch64-unknown-linux -mcpu=exynos-m3 < %s | FileCheck --check-prefixes=ALIGN5,CHECK %s
 
 define void @test() {
Index: llvm/test/CodeGen/AArch64/machine-combiner-madd.ll
===
--- llvm/test/CodeGen/AArch64/machine-combiner-madd.ll
+++ llvm/test/CodeGen/AArch64/machine-combiner-madd.ll
@@ -6,6 +6,7 @@
 ; RUN: llc -mtriple=aarch64-linux-gnu -mcpu=exynos-m3  < %s | FileCheck %s
 ; RUN: llc -mtriple=aarch64-linux-gnu -mcpu=kryo   < %s | FileCheck %s
 ; RUN: llc -mtriple=aarch64-linux-gnu -mcpu=thunderx2t99 < %s | FileCheck %s
+; RUN: llc -mtriple=aarch64-linux-gnu -mcpu=thunderx3t110 < %s | FileCheck %s
 
 ; Make sure that inst-combine fuses the multiply add in the addressing mode of
 ; the load.
Index: llvm/test/CodeGen/AArch64/loop-micro-op-buffer-size-t110.ll
===
--- /dev/null
+++ llvm/test/CodeGen/AArch64/loop-micro-op-buffer-size-t110.ll
@@ -0,0 +1,124 @@
+; REQUIRES: asserts
+; RUN: opt -mcpu=thunderx3t110 -loop-unroll --debug-only=loop-unroll --debug-only=basicblock-utils -S -unroll-allow-partial < %s 2>&1 | FileCheck %s
+
+target triple = "aarch64-unknown-linux-gnu"
+
+; CHECK: Loop Unroll: F[foo] Loop %loop.2.header
+; CHECK: Loop Size = 19
+; CHECK: Trip Count = 512
+; CHECK: Trip Multiple = 512
+; CHECK: UNROLLING loop %loop.2.header by 4 with a breakout at trip 0
+; CHECK: Merging:
+; CHECK: Loop Unroll: F[foo] Loop %loop.header
+; CHECK:   Loop Size = 18
+; CHECK:   Trip Count = 512
+; CHECK:   Trip Multiple = 512
+; CHECK: UNROLLING loop %loop.header by 4 with a breakout at trip 0
+; CHECK: Merging:
+; CHECK: %counter = phi i32 [ 0, %entry ], [ %inc.3, %loop.inc.3 ]
+; CHECK: %val = add nuw nsw i32 %counter, 5
+; CHECK: %val1 = add nuw nsw i32 %counter, 6
+; CHECK: %val2 = add nuw nsw i32 %counter, 7
+; CHECK: %val3 = add nuw nsw i32 %counter, 8
+; CHECK: %val4 = add nuw nsw i32 %counter, 9
+; CHECK: %val5 = add nuw nsw i32 %counter, 10
+; CHECK-NOT: %val = add i32 %counter, 5
+; CHECK-NOT: %val = add i32 %counter, 6
+; CHECK-NOT: %val = add i32 %counter, 7
+; CHECK-NOT: %val = add i32 %counter, 8
+; CHECK-NOT: %val = add i32 %counter, 9
+; CHECK-NOT: %val = add i32 %counter, 10
+; CHECK: %counter.2 = phi i32 [ 0, %exit.0 ], [ %inc.2.3, %loop.2.inc.3 ]

[PATCH] D78129: Add Marvell ThunderX3T110 support

2020-04-23 Thread Wei Zhao via Phabricator via cfe-commits 
wxz2020 updated this revision to Diff 259605.
wxz2020 added a comment.

Resubmit as the previous one was rejected by test plan changes


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D78129/new/

https://reviews.llvm.org/D78129

Files:
  clang/lib/Driver/ToolChains/Arch/AArch64.cpp
  llvm/include/llvm/Support/AArch64TargetParser.def
  llvm/lib/Target/AArch64/AArch64.td
  llvm/lib/Target/AArch64/AArch64InstrInfo.td
  llvm/lib/Target/AArch64/AArch64SchedA53.td
  llvm/lib/Target/AArch64/AArch64SchedA57.td
  llvm/lib/Target/AArch64/AArch64SchedCyclone.td
  llvm/lib/Target/AArch64/AArch64SchedExynosM3.td
  llvm/lib/Target/AArch64/AArch64SchedExynosM4.td
  llvm/lib/Target/AArch64/AArch64SchedExynosM5.td
  llvm/lib/Target/AArch64/AArch64SchedFalkor.td
  llvm/lib/Target/AArch64/AArch64SchedKryo.td
  llvm/lib/Target/AArch64/AArch64SchedThunderX.td
  llvm/lib/Target/AArch64/AArch64SchedThunderX2T99.td
  llvm/lib/Target/AArch64/AArch64SchedThunderX3T110.td
  llvm/lib/Target/AArch64/AArch64Subtarget.cpp
  llvm/lib/Target/AArch64/AArch64Subtarget.h
  llvm/test/CodeGen/AArch64/aarch64-combine-fmul-fsub.mir
  llvm/test/CodeGen/AArch64/cpus.ll
  llvm/test/CodeGen/AArch64/loop-micro-op-buffer-size-t110.ll
  llvm/test/CodeGen/AArch64/machine-combiner-madd.ll
  llvm/test/CodeGen/AArch64/preferred-function-alignment.ll
  llvm/test/CodeGen/AArch64/remat.ll

Index: llvm/test/CodeGen/AArch64/remat.ll
===
--- llvm/test/CodeGen/AArch64/remat.ll
+++ llvm/test/CodeGen/AArch64/remat.ll
@@ -19,6 +19,7 @@
 ; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=thunderx2t99 -o - %s | FileCheck %s
 ; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=tsv110 -o - %s | FileCheck %s
 ; RUN: llc -mtriple=aarch64-linux-gnuabi -mattr=+custom-cheap-as-move -o - %s | FileCheck %s
+; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=thunderx3t110 -o - %s | FileCheck %s
 
 %X = type { i64, i64, i64 }
 declare void @f(%X*)
Index: llvm/test/CodeGen/AArch64/preferred-function-alignment.ll
===
--- llvm/test/CodeGen/AArch64/preferred-function-alignment.ll
+++ llvm/test/CodeGen/AArch64/preferred-function-alignment.ll
@@ -19,6 +19,7 @@
 ; RUN: llc -mtriple=aarch64-unknown-linux -mcpu=thunderxt83 < %s | FileCheck --check-prefixes=ALIGN3,CHECK %s
 ; RUN: llc -mtriple=aarch64-unknown-linux -mcpu=thunderxt88 < %s | FileCheck --check-prefixes=ALIGN3,CHECK %s
 ; RUN: llc -mtriple=aarch64-unknown-linux -mcpu=thunderx2t99 < %s | FileCheck --check-prefixes=ALIGN3,CHECK %s
+; RUN: llc -mtriple=aarch64-unknown-linux -mcpu=thunderx3t110 < %s | FileCheck --check-prefixes=ALIGN4,CHECK %s
 ; RUN: llc -mtriple=aarch64-unknown-linux -mcpu=exynos-m3 < %s | FileCheck --check-prefixes=ALIGN5,CHECK %s
 
 define void @test() {
Index: llvm/test/CodeGen/AArch64/machine-combiner-madd.ll
===
--- llvm/test/CodeGen/AArch64/machine-combiner-madd.ll
+++ llvm/test/CodeGen/AArch64/machine-combiner-madd.ll
@@ -6,6 +6,7 @@
 ; RUN: llc -mtriple=aarch64-linux-gnu -mcpu=exynos-m3  < %s | FileCheck %s
 ; RUN: llc -mtriple=aarch64-linux-gnu -mcpu=kryo   < %s | FileCheck %s
 ; RUN: llc -mtriple=aarch64-linux-gnu -mcpu=thunderx2t99 < %s | FileCheck %s
+; RUN: llc -mtriple=aarch64-linux-gnu -mcpu=thunderx3t110 < %s | FileCheck %s
 
 ; Make sure that inst-combine fuses the multiply add in the addressing mode of
 ; the load.
Index: llvm/test/CodeGen/AArch64/loop-micro-op-buffer-size-t110.ll
===
--- /dev/null
+++ llvm/test/CodeGen/AArch64/loop-micro-op-buffer-size-t110.ll
@@ -0,0 +1,124 @@
+; REQUIRES: asserts
+; RUN: opt -mcpu=thunderx3t110 -loop-unroll --debug-only=loop-unroll --debug-only=basicblock-utils -S -unroll-allow-partial < %s 2>&1 | FileCheck %s
+
+target triple = "aarch64-unknown-linux-gnu"
+
+; CHECK: Loop Unroll: F[foo] Loop %loop.2.header
+; CHECK: Loop Size = 19
+; CHECK: Trip Count = 512
+; CHECK: Trip Multiple = 512
+; CHECK: UNROLLING loop %loop.2.header by 4 with a breakout at trip 0
+; CHECK: Merging:
+; CHECK: Loop Unroll: F[foo] Loop %loop.header
+; CHECK:   Loop Size = 18
+; CHECK:   Trip Count = 512
+; CHECK:   Trip Multiple = 512
+; CHECK: UNROLLING loop %loop.header by 4 with a breakout at trip 0
+; CHECK: Merging:
+; CHECK: %counter = phi i32 [ 0, %entry ], [ %inc.3, %loop.inc.3 ]
+; CHECK: %val = add nuw nsw i32 %counter, 5
+; CHECK: %val1 = add nuw nsw i32 %counter, 6
+; CHECK: %val2 = add nuw nsw i32 %counter, 7
+; CHECK: %val3 = add nuw nsw i32 %counter, 8
+; CHECK: %val4 = add nuw nsw i32 %counter, 9
+; CHECK: %val5 = add nuw nsw i32 %counter, 10
+; CHECK-NOT: %val = add i32 %counter, 5
+; CHECK-NOT: %val = add i32 %counter, 6
+; CHECK-NOT: %val = add i32 %counter, 7
+; CHECK-NOT: %val = add i32 %counter, 8
+; CHECK-NOT: %val = add i32 %counter, 9
+; CHECK-NOT: %val = add i32

[PATCH] D78129: Add Marvell ThunderX3T110 support

2020-04-15 Thread Wei Zhao via Phabricator via cfe-commits 
wxz2020 updated this revision to Diff 257876.
wxz2020 added a comment.

The newly added two files were not accepted by the pre-merge check. Re worked 
on the diff file and uploaded it now.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D78129/new/

https://reviews.llvm.org/D78129

Files:
  clang/lib/Driver/ToolChains/Arch/AArch64.cpp
  llvm/include/llvm/Support/AArch64TargetParser.def
  llvm/lib/Target/AArch64/AArch64.td
  llvm/lib/Target/AArch64/AArch64InstrInfo.td
  llvm/lib/Target/AArch64/AArch64SchedA53.td
  llvm/lib/Target/AArch64/AArch64SchedA57.td
  llvm/lib/Target/AArch64/AArch64SchedCyclone.td
  llvm/lib/Target/AArch64/AArch64SchedExynosM3.td
  llvm/lib/Target/AArch64/AArch64SchedExynosM4.td
  llvm/lib/Target/AArch64/AArch64SchedExynosM5.td
  llvm/lib/Target/AArch64/AArch64SchedFalkor.td
  llvm/lib/Target/AArch64/AArch64SchedKryo.td
  llvm/lib/Target/AArch64/AArch64SchedThunderX.td
  llvm/lib/Target/AArch64/AArch64SchedThunderX2T99.td
  llvm/lib/Target/AArch64/AArch64SchedThunderX3T110.td
  llvm/lib/Target/AArch64/AArch64Subtarget.cpp
  llvm/lib/Target/AArch64/AArch64Subtarget.h
  llvm/test/CodeGen/AArch64/aarch64-combine-fmul-fsub.mir
  llvm/test/CodeGen/AArch64/cpus.ll
  llvm/test/CodeGen/AArch64/loop-micro-op-buffer-size-t110.ll
  llvm/test/CodeGen/AArch64/machine-combiner-madd.ll
  llvm/test/CodeGen/AArch64/preferred-function-alignment.ll
  llvm/test/CodeGen/AArch64/remat.ll

Index: llvm/test/CodeGen/AArch64/remat.ll
===
--- llvm/test/CodeGen/AArch64/remat.ll
+++ llvm/test/CodeGen/AArch64/remat.ll
@@ -19,6 +19,7 @@
 ; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=thunderx2t99 -o - %s | FileCheck %s
 ; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=tsv110 -o - %s | FileCheck %s
 ; RUN: llc -mtriple=aarch64-linux-gnuabi -mattr=+custom-cheap-as-move -o - %s | FileCheck %s
+; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=thunderx3t110 -o - %s | FileCheck %s
 
 %X = type { i64, i64, i64 }
 declare void @f(%X*)
Index: llvm/test/CodeGen/AArch64/preferred-function-alignment.ll
===
--- llvm/test/CodeGen/AArch64/preferred-function-alignment.ll
+++ llvm/test/CodeGen/AArch64/preferred-function-alignment.ll
@@ -19,6 +19,7 @@
 ; RUN: llc -mtriple=aarch64-unknown-linux -mcpu=thunderxt83 < %s | FileCheck --check-prefixes=ALIGN3,CHECK %s
 ; RUN: llc -mtriple=aarch64-unknown-linux -mcpu=thunderxt88 < %s | FileCheck --check-prefixes=ALIGN3,CHECK %s
 ; RUN: llc -mtriple=aarch64-unknown-linux -mcpu=thunderx2t99 < %s | FileCheck --check-prefixes=ALIGN3,CHECK %s
+; RUN: llc -mtriple=aarch64-unknown-linux -mcpu=thunderx3t110 < %s | FileCheck --check-prefixes=ALIGN4,CHECK %s
 ; RUN: llc -mtriple=aarch64-unknown-linux -mcpu=exynos-m3 < %s | FileCheck --check-prefixes=ALIGN5,CHECK %s
 
 define void @test() {
Index: llvm/test/CodeGen/AArch64/machine-combiner-madd.ll
===
--- llvm/test/CodeGen/AArch64/machine-combiner-madd.ll
+++ llvm/test/CodeGen/AArch64/machine-combiner-madd.ll
@@ -6,6 +6,7 @@
 ; RUN: llc -mtriple=aarch64-linux-gnu -mcpu=exynos-m3  < %s | FileCheck %s
 ; RUN: llc -mtriple=aarch64-linux-gnu -mcpu=kryo   < %s | FileCheck %s
 ; RUN: llc -mtriple=aarch64-linux-gnu -mcpu=thunderx2t99 < %s | FileCheck %s
+; RUN: llc -mtriple=aarch64-linux-gnu -mcpu=thunderx3t110 < %s | FileCheck %s
 
 ; Make sure that inst-combine fuses the multiply add in the addressing mode of
 ; the load.
Index: llvm/test/CodeGen/AArch64/loop-micro-op-buffer-size-t110.ll
===
--- /dev/null
+++ llvm/test/CodeGen/AArch64/loop-micro-op-buffer-size-t110.ll
@@ -0,0 +1,124 @@
+; REQUIRES: asserts
+; RUN: opt -mcpu=thunderx3t110 -loop-unroll --debug-only=loop-unroll --debug-only=basicblock-utils -S -unroll-allow-partial < %s 2>&1 | FileCheck %s
+
+target triple = "aarch64-unknown-linux-gnu"
+
+; CHECK: Loop Unroll: F[foo] Loop %loop.2.header
+; CHECK: Loop Size = 19
+; CHECK: Trip Count = 512
+; CHECK: Trip Multiple = 512
+; CHECK: UNROLLING loop %loop.2.header by 4 with a breakout at trip 0
+; CHECK: Merging:
+; CHECK: Loop Unroll: F[foo] Loop %loop.header
+; CHECK:   Loop Size = 18
+; CHECK:   Trip Count = 512
+; CHECK:   Trip Multiple = 512
+; CHECK: UNROLLING loop %loop.header by 4 with a breakout at trip 0
+; CHECK: Merging:
+; CHECK: %counter = phi i32 [ 0, %entry ], [ %inc.3, %loop.inc.3 ]
+; CHECK: %val = add nuw nsw i32 %counter, 5
+; CHECK: %val1 = add nuw nsw i32 %counter, 6
+; CHECK: %val2 = add nuw nsw i32 %counter, 7
+; CHECK: %val3 = add nuw nsw i32 %counter, 8
+; CHECK: %val4 = add nuw nsw i32 %counter, 9
+; CHECK: %val5 = add nuw nsw i32 %counter, 10
+; CHECK-NOT: %val = add i32 %counter, 5
+; CHECK-NOT: %val = add i32 %counter, 6
+; CHECK-NOT: %val = add i32 %counter, 7
+; CHECK-NOT: %val = add i32 %counter, 8
+; CHECK-NOT: %val =

[PATCH] D78129: Add Marvell ThunderX3T110 support

2020-04-14 Thread Wei Zhao via Phabricator via cfe-commits 
wxz2020 created this revision.
wxz2020 added reviewers: joelkevinjones, pankajgode.
Herald added subscribers: cfe-commits, jfb, hiraditya.
Herald added a project: clang.

This is the first checkin to support Marvell ThunderX3T110.

Initial definition of the micro-ops of the instructions in ThunderX3T110 is 
included.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D78129

Files:
  clang/lib/Driver/ToolChains/Arch/AArch64.cpp
  llvm/include/llvm/Support/AArch64TargetParser.def
  llvm/lib/Target/AArch64/AArch64.td
  llvm/lib/Target/AArch64/AArch64InstrInfo.td
  llvm/lib/Target/AArch64/AArch64SchedA53.td
  llvm/lib/Target/AArch64/AArch64SchedA57.td
  llvm/lib/Target/AArch64/AArch64SchedCyclone.td
  llvm/lib/Target/AArch64/AArch64SchedExynosM3.td
  llvm/lib/Target/AArch64/AArch64SchedExynosM4.td
  llvm/lib/Target/AArch64/AArch64SchedExynosM5.td
  llvm/lib/Target/AArch64/AArch64SchedFalkor.td
  llvm/lib/Target/AArch64/AArch64SchedKryo.td
  llvm/lib/Target/AArch64/AArch64SchedThunderX.td
  llvm/lib/Target/AArch64/AArch64SchedThunderX2T99.td
  llvm/lib/Target/AArch64/AArch64SchedThunderX3T110.td
  llvm/lib/Target/AArch64/AArch64Subtarget.cpp
  llvm/lib/Target/AArch64/AArch64Subtarget.h
  llvm/test/CodeGen/AArch64/aarch64-combine-fmul-fsub.mir
  llvm/test/CodeGen/AArch64/cpus.ll
  llvm/test/CodeGen/AArch64/loop-micro-op-buffer-size-t110.ll
  llvm/test/CodeGen/AArch64/machine-combiner-madd.ll
  llvm/test/CodeGen/AArch64/preferred-function-alignment.ll
  llvm/test/CodeGen/AArch64/remat.ll

Index: llvm/test/CodeGen/AArch64/remat.ll
===
--- llvm/test/CodeGen/AArch64/remat.ll
+++ llvm/test/CodeGen/AArch64/remat.ll
@@ -19,6 +19,7 @@
 ; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=thunderx2t99 -o - %s | FileCheck %s
 ; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=tsv110 -o - %s | FileCheck %s
 ; RUN: llc -mtriple=aarch64-linux-gnuabi -mattr=+custom-cheap-as-move -o - %s | FileCheck %s
+; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=thunderx3t110 -o - %s | FileCheck %s
 
 %X = type { i64, i64, i64 }
 declare void @f(%X*)
Index: llvm/test/CodeGen/AArch64/preferred-function-alignment.ll
===
--- llvm/test/CodeGen/AArch64/preferred-function-alignment.ll
+++ llvm/test/CodeGen/AArch64/preferred-function-alignment.ll
@@ -19,6 +19,7 @@
 ; RUN: llc -mtriple=aarch64-unknown-linux -mcpu=thunderxt83 < %s | FileCheck --check-prefixes=ALIGN3,CHECK %s
 ; RUN: llc -mtriple=aarch64-unknown-linux -mcpu=thunderxt88 < %s | FileCheck --check-prefixes=ALIGN3,CHECK %s
 ; RUN: llc -mtriple=aarch64-unknown-linux -mcpu=thunderx2t99 < %s | FileCheck --check-prefixes=ALIGN3,CHECK %s
+; RUN: llc -mtriple=aarch64-unknown-linux -mcpu=thunderx3t110 < %s | FileCheck --check-prefixes=ALIGN4,CHECK %s
 ; RUN: llc -mtriple=aarch64-unknown-linux -mcpu=exynos-m3 < %s | FileCheck --check-prefixes=ALIGN5,CHECK %s
 
 define void @test() {
Index: llvm/test/CodeGen/AArch64/machine-combiner-madd.ll
===
--- llvm/test/CodeGen/AArch64/machine-combiner-madd.ll
+++ llvm/test/CodeGen/AArch64/machine-combiner-madd.ll
@@ -6,6 +6,7 @@
 ; RUN: llc -mtriple=aarch64-linux-gnu -mcpu=exynos-m3  < %s | FileCheck %s
 ; RUN: llc -mtriple=aarch64-linux-gnu -mcpu=kryo   < %s | FileCheck %s
 ; RUN: llc -mtriple=aarch64-linux-gnu -mcpu=thunderx2t99 < %s | FileCheck %s
+; RUN: llc -mtriple=aarch64-linux-gnu -mcpu=thunderx3t110 < %s | FileCheck %s
 
 ; Make sure that inst-combine fuses the multiply add in the addressing mode of
 ; the load.
Index: llvm/test/CodeGen/AArch64/loop-micro-op-buffer-size-t110.ll
===
--- llvm/test/CodeGen/AArch64/loop-micro-op-buffer-size-t110.ll
+++ llvm/test/CodeGen/AArch64/loop-micro-op-buffer-size-t110.ll
@@ -0,0 +1,124 @@
+; REQUIRES: asserts
+; RUN: opt -mcpu=thunderx3t110 -loop-unroll --debug-only=loop-unroll --debug-only=basicblock-utils -S -unroll-allow-partial < %s 2>&1 | FileCheck %s
+
+target triple = "aarch64-unknown-linux-gnu"
+
+; CHECK: Loop Unroll: F[foo] Loop %loop.2.header
+; CHECK: Loop Size = 19
+; CHECK: Trip Count = 512
+; CHECK: Trip Multiple = 512
+; CHECK: UNROLLING loop %loop.2.header by 4 with a breakout at trip 0
+; CHECK: Merging:
+; CHECK: Loop Unroll: F[foo] Loop %loop.header
+; CHECK:   Loop Size = 18
+; CHECK:   Trip Count = 512
+; CHECK:   Trip Multiple = 512
+; CHECK: UNROLLING loop %loop.header by 4 with a breakout at trip 0
+; CHECK: Merging:
+; CHECK: %counter = phi i32 [ 0, %entry ], [ %inc.3, %loop.inc.3 ]
+; CHECK: %val = add nuw nsw i32 %counter, 5
+; CHECK: %val1 = add nuw nsw i32 %counter, 6
+; CHECK: %val2 = add nuw nsw i32 %counter, 7
+; CHECK: %val3 = add nuw nsw i32 %counter, 8
+; CHECK: %val4 = add nuw nsw i32 %counter, 9
+; CHECK: %val5 = add nuw nsw i32 %counter, 10
+; CHECK-NOT: %val = add i32 %counter, 5
+; CHECK-NOT: %val = add i32