[PATCH] D103501: [clang][AIX] Enable inlined quadword atomic operations

2022-03-24 Thread Kai Luo via Phabricator via cfe-commits 
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Most are covered by https://reviews.llvm.org/D122377 already.


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[PATCH] D103501: [clang][AIX] Enable inlined quadword atomic operations

2021-06-23 Thread Hubert Tong via Phabricator via cfe-commits 
hubert.reinterpretcast added inline comments.



Comment at: clang/test/CodeGen/ppc64-quadword-atomics.c:10
+
+// CHECK-NOT: call void @__atomic_exchange
+// CHECK: +quadword-atomics

lkail wrote:
> hubert.reinterpretcast wrote:
> > Can you add a link to something that demonstrates that the implementation 
> > of `__atomic_exchange` is also lock-free when running on `pwr8` and up?
> https://reviews.llvm.org/D103614#C2646926NL5 All related lock-free codegen is 
> in the parent revision.
That change is for the compiler. I am looking for something that makes the 
libatomic implementation correspondingly lock-free for this type (even if 
libatomic needs to be deployable on `pwr7`).


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[PATCH] D103501: [clang][AIX] Enable inlined quadword atomic operations

2021-06-22 Thread Kai Luo via Phabricator via cfe-commits 
lkail added inline comments.



Comment at: clang/test/CodeGen/ppc64-quadword-atomics.c:10
+
+// CHECK-NOT: call void @__atomic_exchange
+// CHECK: +quadword-atomics

hubert.reinterpretcast wrote:
> Can you add a link to something that demonstrates that the implementation of 
> `__atomic_exchange` is also lock-free when running on `pwr8` and up?
https://reviews.llvm.org/D103614#C2646926NL5 All related lock-free codegen is 
in the parent revision.


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[PATCH] D103501: [clang][AIX] Enable inlined quadword atomic operations

2021-06-22 Thread Hubert Tong via Phabricator via cfe-commits 
hubert.reinterpretcast added inline comments.



Comment at: clang/test/CodeGen/ppc64-quadword-atomics.c:10
+
+// CHECK-NOT: call void @__atomic_exchange
+// CHECK: +quadword-atomics

Can you add a link to something that demonstrates that the implementation of 
`__atomic_exchange` is also lock-free when running on `pwr8` and up?


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[PATCH] D103501: [clang][AIX] Enable inlined quadword atomic operations

2021-06-20 Thread Kai Luo via Phabricator via cfe-commits 
lkail added inline comments.



Comment at: clang/lib/Basic/Targets/PPC.cpp:336
 .Default(false);
+  Features["quadword-atomics"] = llvm::StringSwitch(CPU)
+ .Case("pwr10", true)

qiucf wrote:
> What about `ppc64`?
> 
> Also, seems there's no need to add `pwr10` here.
> What about ppc64?


Instructions needed for inline quadword atomics like `lqarx` and `stqcx` are 
only user-space viable in pwr8 and above. However, pwr6 and pwr7 also feature 
ppc64.


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[PATCH] D103501: [clang][AIX] Enable inlined quadword atomic operations

2021-06-20 Thread Kai Luo via Phabricator via cfe-commits 
lkail updated this revision to Diff 353268.
lkail added a comment.

Address comments.


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Files:
  clang/lib/Basic/Targets/PPC.cpp
  clang/lib/Basic/Targets/PPC.h
  clang/test/CodeGen/ppc64-quadword-atomics.c


Index: clang/test/CodeGen/ppc64-quadword-atomics.c
===
--- /dev/null
+++ clang/test/CodeGen/ppc64-quadword-atomics.c
@@ -0,0 +1,16 @@
+// RUN: %clang -target powerpc64-ibm-aix-xcoff -mcpu=pwr8 -S -emit-llvm -o - \
+// RUN:   %s | FileCheck %s
+// RUN: %clang -target powerpc64-ibm-aix-xcoff -mcpu=pwr9 -S -emit-llvm -o - \
+// RUN:   %s | FileCheck %s
+// RUN: %clang -target powerpc64-ibm-aix-xcoff -mcpu=pwr10 -S -emit-llvm -o - \
+// RUN:   %s | FileCheck %s
+
+struct Quadword { long long a[2]; } __attribute__((aligned (16)));
+
+// CHECK-NOT: call void @__atomic_exchange
+// CHECK: +quadword-atomics
+struct Quadword test_xchg(struct Quadword *ptr, struct Quadword new) {
+  struct Quadword old;
+  __atomic_exchange(ptr, , , __ATOMIC_SEQ_CST);
+  return old;
+}
Index: clang/lib/Basic/Targets/PPC.h
===
--- clang/lib/Basic/Targets/PPC.h
+++ clang/lib/Basic/Targets/PPC.h
@@ -74,6 +74,7 @@
   bool HasP10Vector = false;
   bool HasPCRelativeMemops = false;
   bool HasPrefixInstrs = false;
+  bool HasQuadwordAtomics = false;
 
 protected:
   std::string ABI;
@@ -437,6 +438,12 @@
 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
   }
 
+  void setMaxAtomicWidth() override {
+// FIXME: Current only support quadword inline atomics on AIX.
+if (getTriple().isOSAIX() && hasFeature("quadword-atomics"))
+  MaxAtomicInlineWidth = 128;
+  }
+
   BuiltinVaListKind getBuiltinVaListKind() const override {
 return TargetInfo::CharPtrBuiltinVaList;
   }
Index: clang/lib/Basic/Targets/PPC.cpp
===
--- clang/lib/Basic/Targets/PPC.cpp
+++ clang/lib/Basic/Targets/PPC.cpp
@@ -73,6 +73,8 @@
   HasROPProtect = true;
 } else if (Feature == "+privileged") {
   HasPrivileged = true;
+} else if (Feature == "+quadword-atomics") {
+  HasQuadwordAtomics = true;
 }
 // TODO: Finish this list and add an assert that we've handled them
 // all.
@@ -352,6 +354,11 @@
 .Case("pwr9", true)
 .Case("pwr8", true)
 .Default(false);
+  Features["quadword-atomics"] =
+  getTriple().isArch64Bit() && llvm::StringSwitch(CPU)
+   .Case("pwr9", true)
+   .Case("pwr8", true)
+   .Default(false);
 
   // ROP Protect is off by default.
   Features["rop-protect"] = false;
@@ -449,6 +456,7 @@
   .Case("mma", HasMMA)
   .Case("rop-protect", HasROPProtect)
   .Case("privileged", HasPrivileged)
+  .Case("quadword-atomics", HasQuadwordAtomics)
   .Default(false);
 }
 


Index: clang/test/CodeGen/ppc64-quadword-atomics.c
===
--- /dev/null
+++ clang/test/CodeGen/ppc64-quadword-atomics.c
@@ -0,0 +1,16 @@
+// RUN: %clang -target powerpc64-ibm-aix-xcoff -mcpu=pwr8 -S -emit-llvm -o - \
+// RUN:   %s | FileCheck %s
+// RUN: %clang -target powerpc64-ibm-aix-xcoff -mcpu=pwr9 -S -emit-llvm -o - \
+// RUN:   %s | FileCheck %s
+// RUN: %clang -target powerpc64-ibm-aix-xcoff -mcpu=pwr10 -S -emit-llvm -o - \
+// RUN:   %s | FileCheck %s
+
+struct Quadword { long long a[2]; } __attribute__((aligned (16)));
+
+// CHECK-NOT: call void @__atomic_exchange
+// CHECK: +quadword-atomics
+struct Quadword test_xchg(struct Quadword *ptr, struct Quadword new) {
+  struct Quadword old;
+  __atomic_exchange(ptr, , , __ATOMIC_SEQ_CST);
+  return old;
+}
Index: clang/lib/Basic/Targets/PPC.h
===
--- clang/lib/Basic/Targets/PPC.h
+++ clang/lib/Basic/Targets/PPC.h
@@ -74,6 +74,7 @@
   bool HasP10Vector = false;
   bool HasPCRelativeMemops = false;
   bool HasPrefixInstrs = false;
+  bool HasQuadwordAtomics = false;
 
 protected:
   std::string ABI;
@@ -437,6 +438,12 @@
 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
   }
 
+  void setMaxAtomicWidth() override {
+// FIXME: Current only support quadword inline atomics on AIX.
+if (getTriple().isOSAIX() && hasFeature("quadword-atomics"))
+  MaxAtomicInlineWidth = 128;
+  }
+
   BuiltinVaListKind getBuiltinVaListKind() const override {
 return TargetInfo::CharPtrBuiltinVaList;
   }
Index: clang/lib/Basic/Targets/PPC.cpp
===
--- clang/lib/Basic/Targets/PPC.cpp
+++ clang/lib/Basic/Targets/PPC.cpp
@@ -73,6 +73,8 @@
   HasROPProtect = true;
 } else if

[PATCH] D103501: [clang][AIX] Enable inlined quadword atomic operations

2021-06-07 Thread Qiu Chaofan via Phabricator via cfe-commits 
qiucf added inline comments.



Comment at: clang/lib/Basic/Targets/PPC.cpp:336
 .Default(false);
+  Features["quadword-atomics"] = llvm::StringSwitch(CPU)
+ .Case("pwr10", true)

What about `ppc64`?

Also, seems there's no need to add `pwr10` here.



Comment at: clang/lib/Basic/Targets/PPC.h:442
+  void setMaxAtomicWidth() override {
+if (getTriple().isOSAIX() && getTriple().isArch64Bit() &&
+hasFeature("quadword-atomics"))

We don't need this at all for Linux?


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[PATCH] D103501: [clang][AIX] Enable inlined quadword atomic operations

2021-06-01 Thread Kai Luo via Phabricator via cfe-commits 
lkail created this revision.
lkail added reviewers: nemanjai, jsji, xingxue, hubert.reinterpretcast, 
cebowleratibm, PowerPC.
Herald added subscribers: jfb, kbarton.
Herald added a reviewer: jfb.
lkail requested review of this revision.
Herald added a project: clang.
Herald added a subscriber: cfe-commits.

If target cpu is pwr8+, we can generate inlined quadword lock free atomic 
operations, thus no need to generate libcalls into libatomic.


Repository:
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Files:
  clang/lib/Basic/Targets/PPC.cpp
  clang/lib/Basic/Targets/PPC.h
  clang/test/CodeGen/ppc64-quadword-atomics.c


Index: clang/test/CodeGen/ppc64-quadword-atomics.c
===
--- /dev/null
+++ clang/test/CodeGen/ppc64-quadword-atomics.c
@@ -0,0 +1,16 @@
+// RUN: %clang -target powerpc64-ibm-aix-xcoff -mcpu=pwr8 -S -emit-llvm -o - \
+// RUN:   %s | FileCheck %s
+// RUN: %clang -target powerpc64-ibm-aix-xcoff -mcpu=pwr9 -S -emit-llvm -o - \
+// RUN:   %s | FileCheck %s
+// RUN: %clang -target powerpc64-ibm-aix-xcoff -mcpu=pwr10 -S -emit-llvm -o - \
+// RUN:   %s | FileCheck %s
+
+struct Quadword { long long a[2]; } __attribute__((aligned (16)));
+
+// CHECK-NOT: call void @__atomic_exchange
+// CHECK: +quadword-atomics
+struct Quadword test_xchg(struct Quadword *ptr, struct Quadword new) {
+  struct Quadword old;
+  __atomic_exchange(ptr, , , __ATOMIC_SEQ_CST);
+  return old;
+}
Index: clang/lib/Basic/Targets/PPC.h
===
--- clang/lib/Basic/Targets/PPC.h
+++ clang/lib/Basic/Targets/PPC.h
@@ -74,6 +74,7 @@
   bool HasP10Vector = false;
   bool HasPCRelativeMemops = false;
   bool HasPrefixInstrs = false;
+  bool HasQuadwordAtomics = false;
 
 protected:
   std::string ABI;
@@ -437,6 +438,12 @@
 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
   }
 
+  void setMaxAtomicWidth() override {
+if (getTriple().isOSAIX() && getTriple().isArch64Bit() &&
+hasFeature("quadword-atomics"))
+  MaxAtomicInlineWidth = 128;
+  }
+
   BuiltinVaListKind getBuiltinVaListKind() const override {
 return TargetInfo::CharPtrBuiltinVaList;
   }
Index: clang/lib/Basic/Targets/PPC.cpp
===
--- clang/lib/Basic/Targets/PPC.cpp
+++ clang/lib/Basic/Targets/PPC.cpp
@@ -73,6 +73,8 @@
   HasROPProtect = true;
 } else if (Feature == "+privileged") {
   HasPrivileged = true;
+} else if (Feature == "+quadword-atomics") {
+  HasQuadwordAtomics = true;
 }
 // TODO: Finish this list and add an assert that we've handled them
 // all.
@@ -331,6 +333,11 @@
 .Case("pwr9", true)
 .Case("pwr8", true)
 .Default(false);
+  Features["quadword-atomics"] = llvm::StringSwitch(CPU)
+ .Case("pwr10", true)
+ .Case("pwr9", true)
+ .Case("pwr8", true)
+ .Default(false);
 
   // ROP Protect is off by default.
   Features["rop-protect"] = false;
@@ -428,6 +435,7 @@
   .Case("mma", HasMMA)
   .Case("rop-protect", HasROPProtect)
   .Case("privileged", HasPrivileged)
+  .Case("quadword-atomics", HasQuadwordAtomics)
   .Default(false);
 }
 


Index: clang/test/CodeGen/ppc64-quadword-atomics.c
===
--- /dev/null
+++ clang/test/CodeGen/ppc64-quadword-atomics.c
@@ -0,0 +1,16 @@
+// RUN: %clang -target powerpc64-ibm-aix-xcoff -mcpu=pwr8 -S -emit-llvm -o - \
+// RUN:   %s | FileCheck %s
+// RUN: %clang -target powerpc64-ibm-aix-xcoff -mcpu=pwr9 -S -emit-llvm -o - \
+// RUN:   %s | FileCheck %s
+// RUN: %clang -target powerpc64-ibm-aix-xcoff -mcpu=pwr10 -S -emit-llvm -o - \
+// RUN:   %s | FileCheck %s
+
+struct Quadword { long long a[2]; } __attribute__((aligned (16)));
+
+// CHECK-NOT: call void @__atomic_exchange
+// CHECK: +quadword-atomics
+struct Quadword test_xchg(struct Quadword *ptr, struct Quadword new) {
+  struct Quadword old;
+  __atomic_exchange(ptr, , , __ATOMIC_SEQ_CST);
+  return old;
+}
Index: clang/lib/Basic/Targets/PPC.h
===
--- clang/lib/Basic/Targets/PPC.h
+++ clang/lib/Basic/Targets/PPC.h
@@ -74,6 +74,7 @@
   bool HasP10Vector = false;
   bool HasPCRelativeMemops = false;
   bool HasPrefixInstrs = false;
+  bool HasQuadwordAtomics = false;
 
 protected:
   std::string ABI;
@@ -437,6 +438,12 @@
 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
   }
 
+  void setMaxAtomicWidth() override {
+if (getTriple().isOSAIX() && getTriple().isArch64Bit() &&
+hasFeature("quadword-atomics"))
+  MaxAtomicInlineWidth = 128;
+  }
+
   BuiltinVaListKind getBuiltinVaListKind() const override {
 return TargetInfo::CharPtrBuiltinVaList;