[PATCH] D105268: [X86] AVX512FP16 instructions enabling 5/6
This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rGc728bd5bbaab: [X86] AVX512FP16 instructions enabling 5/6 (authored by pengfei). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D105268/new/ https://reviews.llvm.org/D105268 Files: clang/include/clang/Basic/BuiltinsX86.def clang/lib/CodeGen/CGBuiltin.cpp clang/lib/Headers/avx512fp16intrin.h clang/lib/Headers/avx512vlfp16intrin.h clang/lib/Sema/SemaChecking.cpp clang/test/CodeGen/X86/avx512fp16-builtins.c clang/test/CodeGen/X86/avx512vlfp16-builtins.c llvm/include/llvm/IR/IntrinsicsX86.td llvm/lib/Target/X86/X86ISelLowering.cpp llvm/lib/Target/X86/X86InstrAVX512.td llvm/lib/Target/X86/X86InstrFMA3Info.cpp llvm/lib/Target/X86/X86InstrFoldTables.cpp llvm/lib/Target/X86/X86InstrFormats.td llvm/lib/Target/X86/X86InstrInfo.cpp llvm/lib/Target/X86/X86IntrinsicsInfo.h llvm/test/CodeGen/X86/avx512fp16-fma-commute.ll llvm/test/CodeGen/X86/avx512fp16-fma-intrinsics.ll llvm/test/CodeGen/X86/avx512fp16vl-fma-intrinsics.ll llvm/test/CodeGen/X86/fp-strict-scalar-fp16.ll llvm/test/CodeGen/X86/stack-folding-fp-avx512fp16-fma.ll llvm/test/CodeGen/X86/stack-folding-fp-avx512fp16vl-fma.ll llvm/test/CodeGen/X86/vec-strict-128-fp16.ll llvm/test/CodeGen/X86/vec-strict-256-fp16.ll llvm/test/CodeGen/X86/vec-strict-512-fp16.ll llvm/test/MC/Disassembler/X86/avx512fp16.txt llvm/test/MC/Disassembler/X86/avx512fp16vl.txt llvm/test/MC/X86/avx512fp16.s llvm/test/MC/X86/avx512fp16vl.s llvm/test/MC/X86/intel-syntax-avx512fp16.s llvm/test/MC/X86/intel-syntax-avx512fp16vl.s ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D105268: [X86] AVX512FP16 instructions enabling 5/6
LuoYuanke accepted this revision. LuoYuanke added a comment. This revision is now accepted and ready to land. LGTM, may wait 1 or 2 days for comments from others. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D105268/new/ https://reviews.llvm.org/D105268 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D105268: [X86] AVX512FP16 instructions enabling 5/6
pengfei added inline comments.
Comment at: clang/include/clang/Basic/BuiltinsX86.def:2010
+TARGET_BUILTIN(__builtin_ia32_vfmaddph, "V8xV8xV8xV8x", "ncV:128:",
"avx512fp16,avx512vl")
+TARGET_BUILTIN(__builtin_ia32_vfmaddph256, "V16xV16xV16xV16x", "ncV:256:",
"avx512fp16,avx512vl")
+
LuoYuanke wrote:
> Can we arrange the vfmaddph variant together? Move it to line 1997?
> Why there is no mask version for 128 and 256?
We followed what're ps/pd doing. As Craig explained, this is history's legacy.
We should fix them in future.
Comment at: llvm/test/CodeGen/X86/vec-strict-128-fp16.ll:105
+define <8 x half> @f13(<8 x half> %a, <8 x half> %b, <8 x half> %c) #0 {
+; CHECK-LABEL: f13:
LuoYuanke wrote:
> Is it necessary to test 132, 231 version?
213 is the preferred version due to its order in `SelectCode` table. We can
test others by using memory input, but they are covered in
stack-folding-fp-avx512fp16vl-fma.ll. I don't think it's necessary to test here.
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[PATCH] D105268: [X86] AVX512FP16 instructions enabling 5/6
pengfei updated this revision to Diff 367957. pengfei marked 8 inline comments as done. pengfei added a comment. Address Yuanke's comments. Thanks Yuanke and Craig. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D105268/new/ https://reviews.llvm.org/D105268 Files: clang/include/clang/Basic/BuiltinsX86.def clang/lib/CodeGen/CGBuiltin.cpp clang/lib/Headers/avx512fp16intrin.h clang/lib/Headers/avx512vlfp16intrin.h clang/lib/Sema/SemaChecking.cpp clang/test/CodeGen/X86/avx512fp16-builtins.c clang/test/CodeGen/X86/avx512vlfp16-builtins.c llvm/include/llvm/IR/IntrinsicsX86.td llvm/lib/Target/X86/X86ISelLowering.cpp llvm/lib/Target/X86/X86InstrAVX512.td llvm/lib/Target/X86/X86InstrFMA3Info.cpp llvm/lib/Target/X86/X86InstrFoldTables.cpp llvm/lib/Target/X86/X86InstrFormats.td llvm/lib/Target/X86/X86InstrInfo.cpp llvm/lib/Target/X86/X86IntrinsicsInfo.h llvm/test/CodeGen/X86/avx512fp16-fma-commute.ll llvm/test/CodeGen/X86/avx512fp16-fma-intrinsics.ll llvm/test/CodeGen/X86/avx512fp16vl-fma-intrinsics.ll llvm/test/CodeGen/X86/fp-strict-scalar-fp16.ll llvm/test/CodeGen/X86/stack-folding-fp-avx512fp16-fma.ll llvm/test/CodeGen/X86/stack-folding-fp-avx512fp16vl-fma.ll llvm/test/CodeGen/X86/vec-strict-128-fp16.ll llvm/test/CodeGen/X86/vec-strict-256-fp16.ll llvm/test/CodeGen/X86/vec-strict-512-fp16.ll llvm/test/MC/Disassembler/X86/avx512fp16.txt llvm/test/MC/Disassembler/X86/avx512fp16vl.txt llvm/test/MC/X86/avx512fp16.s llvm/test/MC/X86/avx512fp16vl.s llvm/test/MC/X86/intel-syntax-avx512fp16.s llvm/test/MC/X86/intel-syntax-avx512fp16vl.s ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D105268: [X86] AVX512FP16 instructions enabling 5/6
LuoYuanke added a comment. I understand now. Thanks, Craig. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D105268/new/ https://reviews.llvm.org/D105268 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D105268: [X86] AVX512FP16 instructions enabling 5/6
craig.topper added inline comments.
Comment at: clang/include/clang/Basic/BuiltinsX86.def:2014
+
+TARGET_BUILTIN(__builtin_ia32_vfmaddsh3_mask, "V8xV8xV8xV8xUcIi", "ncV:128:",
"avx512fp16")
+TARGET_BUILTIN(__builtin_ia32_vfmaddsh3_maskz, "V8xV8xV8xV8xUcIi", "ncV:128:",
"avx512fp16")
LuoYuanke wrote:
> What does "3" stand for?
The 3 is there because AMD's 4 operand fma used vfmaddss/vfmaddsd. So Intel's 3
operand used vfmaddss3/vfmaddsd3. That naming is being carried forward here.
Comment at: clang/lib/Headers/avx512vlfp16intrin.h:1385
+ __m128h __C)
{
+ return (__m128h)__builtin_ia32_selectph_128(
+ (__mmask8)__U,
LuoYuanke wrote:
> Sorry, I'm confused sometimes we use mask builtin, sometimes we use select
> builtin. Any guideline on it?
Ideally FP should never use select because it doesn't convey that exceptions
should be masked for strictfp. But the mistake was already made for
add/sub/mul/div/fma/etc years ago before strictfp support existed in llvm. fp16
is intentionally following float/double for consistency.
Comment at: llvm/include/llvm/IR/IntrinsicsX86.td:5709
+
+ def int_x86_avx512fp16_vfmadd_ph_512
+ : Intrinsic<[ llvm_v32f16_ty ],
LuoYuanke wrote:
> I notice there is no builtin bound to this intrinsic. What is it used for?
It is manually selected in CGBuiltin.cpp
Comment at: llvm/include/llvm/IR/IntrinsicsX86.td:5727
+ [ IntrNoMem, ImmArg> ]>;
+ def int_x86_avx512fp16_vfmadd_f16
+ : Intrinsic<[ llvm_half_ty ],
LuoYuanke wrote:
> ph?
It's scalar so it shouldn't be ph. This matches int_x86_avx512_vfmadd_f32 and
int_x86_avx512_vfmadd_f64. They don't use ss/sd because the ss/sd names are
usually used for intrinsics that 128-bit operands and only modify the lower
element. int_x86_avx512_vfmadd_f32 and int_x86_avx512_vfmadd_f64 have
float/double inputs and produce float/double results.
Comment at: llvm/test/CodeGen/X86/avx512fp16-fma-commute.ll:9
+
+define half @fma_123_f16(half %x, half %y, half %z) {
+; CHECK-LABEL: fma_123_f16:
LuoYuanke wrote:
> The name 123 is not the same with the generated instruction (213sh). Is it
> expected?
123 represents how the 3 arguments to the fucntion are mapped to the 3
intrinsic arguments that it calls. There are 6 possible permutations which are
all tested here, but only 3 instruction mnemonics.
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[PATCH] D105268: [X86] AVX512FP16 instructions enabling 5/6
LuoYuanke added inline comments.
Comment at: clang/include/clang/Basic/BuiltinsX86.def:2010
+TARGET_BUILTIN(__builtin_ia32_vfmaddph, "V8xV8xV8xV8x", "ncV:128:",
"avx512fp16,avx512vl")
+TARGET_BUILTIN(__builtin_ia32_vfmaddph256, "V16xV16xV16xV16x", "ncV:256:",
"avx512fp16,avx512vl")
+
Can we arrange the vfmaddph variant together? Move it to line 1997?
Why there is no mask version for 128 and 256?
Comment at: clang/include/clang/Basic/BuiltinsX86.def:2014
+
+TARGET_BUILTIN(__builtin_ia32_vfmaddsh3_mask, "V8xV8xV8xV8xUcIi", "ncV:128:",
"avx512fp16")
+TARGET_BUILTIN(__builtin_ia32_vfmaddsh3_maskz, "V8xV8xV8xV8xUcIi", "ncV:128:",
"avx512fp16")
What does "3" stand for?
Comment at: clang/lib/Headers/avx512vlfp16intrin.h:1385
+ __m128h __C)
{
+ return (__m128h)__builtin_ia32_selectph_128(
+ (__mmask8)__U,
Sorry, I'm confused sometimes we use mask builtin, sometimes we use select
builtin. Any guideline on it?
Comment at: llvm/include/llvm/IR/IntrinsicsX86.td:5709
+
+ def int_x86_avx512fp16_vfmadd_ph_512
+ : Intrinsic<[ llvm_v32f16_ty ],
I notice there is no builtin bound to this intrinsic. What is it used for?
Comment at: llvm/include/llvm/IR/IntrinsicsX86.td:5727
+ [ IntrNoMem, ImmArg> ]>;
+ def int_x86_avx512fp16_vfmadd_f16
+ : Intrinsic<[ llvm_half_ty ],
ph?
Comment at: llvm/lib/Target/X86/X86InstrFMA3Info.cpp:148
+
+#define FP16_FMA3GROUP_PACKED_AVX512(Name, Suf, Attrs)
\
+ FMA3GROUP_PACKED_AVX512_WIDTHS(Name, PH, Suf, Attrs)
Can we integrate it to FMA3GROUP_PACKED_AVX512() with PH extended?
Comment at: llvm/lib/Target/X86/X86InstrFMA3Info.cpp:151
+
+#define FP16_FMA3GROUP_PACKED_AVX512_ROUND(Name, Suf, Attrs)
\
+ FMA3GROUP_MASKED(Name, PHZ##Suf, Attrs)
Ditto.
Comment at: llvm/lib/Target/X86/X86InstrFMA3Info.cpp:154
+
+#define FP16_FMA3GROUP_SCALAR_AVX512_ROUND(Name, Suf, Attrs)
\
+ FMA3GROUP(Name, SHZ##Suf, Attrs)
\
Ditto.
Comment at: llvm/lib/Target/X86/X86InstrFMA3Info.cpp:158
+
+static const X86InstrFMA3Group FP16BroadcastGroups[] = {
+ FP16_FMA3GROUP_PACKED_AVX512(VFMADD, mb, 0)
Ditto.
Comment at: llvm/lib/Target/X86/X86InstrFMA3Info.cpp:167
+
+static const X86InstrFMA3Group FP16RoundGroups[] = {
+ FP16_FMA3GROUP_PACKED_AVX512_ROUND(VFMADD, rb, 0)
Ditto.
Comment at: llvm/lib/Target/X86/X86InstrFMA3Info.cpp:208
(BaseOpcode >= 0xB6 && BaseOpcode <= 0xBF));
+ bool IsFMA3H = (TSFlags & X86II::EncodingMask) == X86II::EVEX &&
+ (TSFlags & X86II::OpMapMask) == X86II::T_MAP6 &&
Looks some redundant logic. Only X86II::EVEX and X86II::T_MAP6 is special for
FP16?
Comment at: llvm/lib/Target/X86/X86InstrFMA3Info.cpp:235
+else
+ Table = makeArrayRef(FP16Groups);
+ }
Seems we only need FP16Groups be separate table.
Comment at: llvm/test/CodeGen/X86/avx512fp16-fma-commute.ll:9
+
+define half @fma_123_f16(half %x, half %y, half %z) {
+; CHECK-LABEL: fma_123_f16:
The name 123 is not the same with the generated instruction (213sh). Is it
expected?
Comment at: llvm/test/CodeGen/X86/vec-strict-128-fp16.ll:105
+define <8 x half> @f13(<8 x half> %a, <8 x half> %b, <8 x half> %c) #0 {
+; CHECK-LABEL: f13:
Is it necessary to test 132, 231 version?
Comment at: llvm/test/CodeGen/X86/vec-strict-256-fp16.ll:105
+; CHECK: # %bb.0:
+; CHECK-NEXT:vfmadd213ph %ymm2, %ymm1, %ymm0
+; CHECK-NEXT:ret{{[l|q]}}
Ditto.
Comment at: llvm/test/CodeGen/X86/vec-strict-512-fp16.ll:104
+; CHECK: # %bb.0:
+; CHECK-NEXT:vfmadd213ph %zmm2, %zmm1, %zmm0
+; CHECK-NEXT:ret{{[l|q]}}
Ditto.
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[PATCH] D105268: [X86] AVX512FP16 instructions enabling 5/6
pengfei added inline comments. Comment at: clang/lib/Headers/avx512fp16intrin.h:2373 + (__v32hf)(__m512h)(A), (__v32hf)(__m512h)(B), (__v32hf)(__m512h)(C), \ + (__mmask32)-1, (int)(R)) + RKSimon wrote: > Add outer brackets to all the defines to prevent precedence issues: > ``` > #define _mm512_fmadd_round_ph(A, B, C, R) > \ > ((__m512h) __builtin_ia32_vfmaddph512_mask( > \ > (__v32hf)(__m512h)(A), (__v32hf)(__m512h)(B), (__v32hf)(__m512h)(C), > \ > (__mmask32)-1, (int)(R))) > ``` Thanks Simon. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D105268/new/ https://reviews.llvm.org/D105268 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D105268: [X86] AVX512FP16 instructions enabling 5/6
pengfei updated this revision to Diff 366873. pengfei added a comment. Rebased. Add extra parentheses for macro. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D105268/new/ https://reviews.llvm.org/D105268 Files: clang/include/clang/Basic/BuiltinsX86.def clang/lib/CodeGen/CGBuiltin.cpp clang/lib/Headers/avx512fp16intrin.h clang/lib/Headers/avx512vlfp16intrin.h clang/lib/Sema/SemaChecking.cpp clang/test/CodeGen/X86/avx512fp16-builtins.c clang/test/CodeGen/X86/avx512vlfp16-builtins.c llvm/include/llvm/IR/IntrinsicsX86.td llvm/lib/Target/X86/X86ISelLowering.cpp llvm/lib/Target/X86/X86InstrAVX512.td llvm/lib/Target/X86/X86InstrFMA3Info.cpp llvm/lib/Target/X86/X86InstrFoldTables.cpp llvm/lib/Target/X86/X86InstrFormats.td llvm/lib/Target/X86/X86InstrInfo.cpp llvm/lib/Target/X86/X86IntrinsicsInfo.h llvm/test/CodeGen/X86/avx512fp16-fma-commute.ll llvm/test/CodeGen/X86/avx512fp16-fma-intrinsics.ll llvm/test/CodeGen/X86/avx512fp16vl-fma-intrinsics.ll llvm/test/CodeGen/X86/fp-strict-scalar-fp16.ll llvm/test/CodeGen/X86/stack-folding-fp-avx512fp16-fma.ll llvm/test/CodeGen/X86/stack-folding-fp-avx512fp16vl-fma.ll llvm/test/CodeGen/X86/vec-strict-128-fp16.ll llvm/test/CodeGen/X86/vec-strict-256-fp16.ll llvm/test/CodeGen/X86/vec-strict-512-fp16.ll llvm/test/MC/Disassembler/X86/avx512fp16.txt llvm/test/MC/Disassembler/X86/avx512fp16vl.txt llvm/test/MC/X86/avx512fp16.s llvm/test/MC/X86/avx512fp16vl.s llvm/test/MC/X86/intel-syntax-avx512fp16.s llvm/test/MC/X86/intel-syntax-avx512fp16vl.s ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D105268: [X86] AVX512FP16 instructions enabling 5/6
RKSimon added inline comments. Comment at: clang/lib/Headers/avx512fp16intrin.h:2373 + (__v32hf)(__m512h)(A), (__v32hf)(__m512h)(B), (__v32hf)(__m512h)(C), \ + (__mmask32)-1, (int)(R)) + Add outer brackets to all the defines to prevent precedence issues: ``` #define _mm512_fmadd_round_ph(A, B, C, R) \ ((__m512h) __builtin_ia32_vfmaddph512_mask( \ (__v32hf)(__m512h)(A), (__v32hf)(__m512h)(B), (__v32hf)(__m512h)(C), \ (__mmask32)-1, (int)(R))) ``` Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D105268/new/ https://reviews.llvm.org/D105268 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D105268: [X86] AVX512FP16 instructions enabling 5/6
pengfei updated this revision to Diff 356585. pengfei added a comment. Fix the capitalization mismatch in tests. Thanks Sanjay! Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D105268/new/ https://reviews.llvm.org/D105268 Files: clang/include/clang/Basic/BuiltinsX86.def clang/lib/CodeGen/CGBuiltin.cpp clang/lib/Headers/avx512fp16intrin.h clang/lib/Headers/avx512vlfp16intrin.h clang/lib/Sema/SemaChecking.cpp clang/test/CodeGen/X86/avx512fp16-builtins.c clang/test/CodeGen/X86/avx512vlfp16-builtins.c llvm/include/llvm/IR/IntrinsicsX86.td llvm/lib/Target/X86/X86ISelLowering.cpp llvm/lib/Target/X86/X86InstrAVX512.td llvm/lib/Target/X86/X86InstrFMA3Info.cpp llvm/lib/Target/X86/X86InstrFoldTables.cpp llvm/lib/Target/X86/X86InstrFormats.td llvm/lib/Target/X86/X86InstrInfo.cpp llvm/lib/Target/X86/X86IntrinsicsInfo.h llvm/test/CodeGen/X86/avx512fp16-fma-commute.ll llvm/test/CodeGen/X86/avx512fp16-fma-intrinsics.ll llvm/test/CodeGen/X86/avx512fp16vl-fma-intrinsics.ll llvm/test/CodeGen/X86/fp-strict-scalar-fp16.ll llvm/test/CodeGen/X86/stack-folding-fp-avx512fp16-fma.ll llvm/test/CodeGen/X86/stack-folding-fp-avx512fp16vl-fma.ll llvm/test/CodeGen/X86/vec-strict-128-fp16.ll llvm/test/CodeGen/X86/vec-strict-256-fp16.ll llvm/test/CodeGen/X86/vec-strict-512-fp16.ll llvm/test/MC/Disassembler/X86/avx512fp16.txt llvm/test/MC/Disassembler/X86/avx512fp16vl.txt llvm/test/MC/X86/avx512fp16.s llvm/test/MC/X86/avx512fp16vl.s llvm/test/MC/X86/intel-syntax-avx512fp16.s llvm/test/MC/X86/intel-syntax-avx512fp16vl.s ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D105268: [X86] AVX512FP16 instructions enabling 5/6
pengfei added inline comments.
Comment at: llvm/test/CodeGen/X86/stack-folding-fp-avx512fp16vl-fma.ll:193-194
+define <8 x half> @stack_fold_fmsub123ph(<8 x half> %a0, <8 x half> %a1, <8 x
half> %a2) {
+ ;check-label: stack_fold_fmsub123ph:
+ ;check: vfmsub213ph {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}},
{{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte folded reload
+ %1 = tail call <2 x i64> asm sideeffect "nop",
"=x,~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{xmm16},~{xmm17},~{xmm18},~{xmm19},~{xmm20},~{xmm21},~{xmm22},~{xmm23},~{xmm24},~{xmm25},~{xmm26},~{xmm27},~{xmm28},~{xmm29},~{xmm30},~{xmm31},~{flags}"()
spatel wrote:
> I was just scanning through this patch and noticed the capitalization
> mismatch on these lines and others. This test has no valid checks as written?
Good catch! Yes, these two tests were manually written and lit doesn't report
fail for such mismatch.
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[PATCH] D105268: [X86] AVX512FP16 instructions enabling 5/6
spatel added inline comments.
Comment at: llvm/test/CodeGen/X86/stack-folding-fp-avx512fp16vl-fma.ll:193-194
+define <8 x half> @stack_fold_fmsub123ph(<8 x half> %a0, <8 x half> %a1, <8 x
half> %a2) {
+ ;check-label: stack_fold_fmsub123ph:
+ ;check: vfmsub213ph {{-?[0-9]*}}(%rsp), {{%xmm[0-9][0-9]*}},
{{%xmm[0-9][0-9]*}} {{.*#+}} 16-byte folded reload
+ %1 = tail call <2 x i64> asm sideeffect "nop",
"=x,~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{xmm16},~{xmm17},~{xmm18},~{xmm19},~{xmm20},~{xmm21},~{xmm22},~{xmm23},~{xmm24},~{xmm25},~{xmm26},~{xmm27},~{xmm28},~{xmm29},~{xmm30},~{xmm31},~{flags}"()
I was just scanning through this patch and noticed the capitalization mismatch
on these lines and others. This test has no valid checks as written?
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D105268/new/
https://reviews.llvm.org/D105268
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[PATCH] D105268: [X86] AVX512FP16 instructions enabling 5/6
pengfei created this revision. pengfei added reviewers: craig.topper, RKSimon, spatel, LiuChen3, FreddyYe, yubing, LuoYuanke. Herald added a subscriber: hiraditya. pengfei requested review of this revision. Herald added projects: clang, LLVM. Herald added subscribers: llvm-commits, cfe-commits. Enable FP16 FMA instructions. Repository: rG LLVM Github Monorepo https://reviews.llvm.org/D105268 Files: clang/include/clang/Basic/BuiltinsX86.def clang/lib/CodeGen/CGBuiltin.cpp clang/lib/Headers/avx512fp16intrin.h clang/lib/Headers/avx512vlfp16intrin.h clang/lib/Sema/SemaChecking.cpp clang/test/CodeGen/X86/avx512fp16-builtins.c clang/test/CodeGen/X86/avx512vlfp16-builtins.c llvm/include/llvm/IR/IntrinsicsX86.td llvm/lib/Target/X86/X86ISelLowering.cpp llvm/lib/Target/X86/X86InstrAVX512.td llvm/lib/Target/X86/X86InstrFMA3Info.cpp llvm/lib/Target/X86/X86InstrFoldTables.cpp llvm/lib/Target/X86/X86InstrFormats.td llvm/lib/Target/X86/X86InstrInfo.cpp llvm/lib/Target/X86/X86IntrinsicsInfo.h llvm/test/CodeGen/X86/avx512fp16-fma-commute.ll llvm/test/CodeGen/X86/avx512fp16-fma-intrinsics.ll llvm/test/CodeGen/X86/avx512fp16vl-fma-intrinsics.ll llvm/test/CodeGen/X86/fp-strict-scalar-fp16.ll llvm/test/CodeGen/X86/stack-folding-fp-avx512fp16-fma.ll llvm/test/CodeGen/X86/stack-folding-fp-avx512fp16vl-fma.ll llvm/test/CodeGen/X86/vec-strict-128-fp16.ll llvm/test/CodeGen/X86/vec-strict-256-fp16.ll llvm/test/CodeGen/X86/vec-strict-512-fp16.ll llvm/test/MC/Disassembler/X86/avx512fp16.txt llvm/test/MC/Disassembler/X86/avx512fp16vl.txt llvm/test/MC/X86/avx512fp16.s llvm/test/MC/X86/avx512fp16vl.s llvm/test/MC/X86/intel-syntax-avx512fp16.s llvm/test/MC/X86/intel-syntax-avx512fp16vl.s ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
