[PATCH] D106409: [PowerPC] Truncate exponent parameter for vec_cts,vec_ctf

2023-07-11 Thread Zarko Todorovski via Phabricator via cfe-commits 
This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG14742f2a689c: [PowerPC] Truncate exponent parameter for 
vec_cts,vec_ctf (authored by ZarkoCA).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D106409/new/

https://reviews.llvm.org/D106409

Files:
  clang/lib/Headers/altivec.h
  clang/test/CodeGen/ppc-vec_ct-truncate.c

Index: clang/test/CodeGen/ppc-vec_ct-truncate.c
===
--- /dev/null
+++ clang/test/CodeGen/ppc-vec_ct-truncate.c
@@ -0,0 +1,80 @@
+// REQUIRES: powerpc-registered-target
+// RUN: %clang_cc1 -target-feature +altivec -target-feature +vsx \
+// RUN:   -flax-vector-conversions=all -triple powerpc64-ibm-aix-xcoff -emit-llvm %s -o - \
+// RUN:   -target-cpu pwr7 | FileCheck %s
+// RUN: %clang_cc1 -target-feature +altivec -target-feature +vsx \
+// RUN:   -flax-vector-conversions=all -triple powerpc64-unknown-linux-gnu -emit-llvm %s -o - \
+// RUN:   -target-cpu pwr8 | FileCheck %s
+// RUN: %clang_cc1 -target-feature +altivec -target-feature +vsx \
+// RUN:   -flax-vector-conversions=all -triple powerpc64le-unknown-linux-gnu -emit-llvm %s -o - \
+// RUN:   -target-cpu pwr8 | FileCheck %s
+// RUN: %clang_cc1 -target-feature +altivec -target-feature +vsx \
+// RUN:   -flax-vector-conversions=all -triple powerpc64-ibm-aix-xcoff -emit-llvm %s -o - \
+// RUN:   -D__XL_COMPAT_ALTIVEC__ -target-cpu pwr7 | FileCheck %s
+// RUN: %clang_cc1 -target-feature +altivec -target-feature +vsx \
+// RUN:   -flax-vector-conversions=all -triple powerpc64le-unknown-linux-gnu -emit-llvm %s -o - \
+// RUN:   -D__XL_COMPAT_ALTIVEC__ -target-cpu pwr8 | FileCheck %s
+
+#include 
+vector double a1 = {-1.234e-5, 1.2345};
+vector signed int res_vsi;
+vector float vf1 = {0.234, 1.234, 2.345, 3.456};
+vector signed int vsi1 = {1, 2, 3, 4};
+vector double res_vd;
+vector float res_vf;
+vector signed long long res_vsll;
+vector unsigned long long res_vull;
+void test(void) {
+  // CHECK-LABEL: @test(
+  // CHECK-NEXT:  entry:
+
+  res_vsi = vec_cts(a1, 31);
+  //  CHECK:   [[TMP0:%.*]] = load <2 x double>, ptr @a1, align 16
+  //  CHECK-NEXT:  fmul <2 x double> [[TMP0]], 
+
+  res_vsi = vec_cts(a1, 500);
+  // CHECK:[[TMP4:%.*]] = load <2 x double>, ptr @a1, align 16
+  // CHECK-NEXT:   fmul <2 x double> [[TMP4]], 
+
+  res_vsi = vec_ctu(vf1, 31);
+  // CHECK:[[TMP8:%.*]] = load <4 x float>, ptr @vf1, align 16
+  // CHECK-NEXT:   call <4 x i32> @llvm.ppc.altivec.vctuxs(<4 x float> [[TMP8]], i32 31)
+
+  res_vsi = vec_ctu(vf1, 500);
+  // CHECK:[[TMP10:%.*]] = load <4 x float>, ptr @vf1, align 16
+  // CHECK-NEXT:   call <4 x i32> @llvm.ppc.altivec.vctuxs(<4 x float> [[TMP10]], i32 20)
+
+  res_vull = vec_ctul(vf1, 31);
+  // CHECK:[[TMP12:%.*]] = load <4 x float>, ptr @vf1, align 16
+  // CHECK-NEXT:   fmul <4 x float> [[TMP12]], 
+
+  res_vull = vec_ctul(vf1, 500);
+  // CHECK:[[TMP21:%.*]] = load <4 x float>, ptr @vf1, align 16
+  // CHECK-NEXT:   fmul <4 x float> [[TMP21]], 
+
+  res_vsll = vec_ctsl(vf1, 31);
+  // CHECK:[[TMP30:%.*]] = load <4 x float>, ptr @vf1, align 16
+  // CHECK-NEXT:   fmul <4 x float> [[TMP30]], 
+
+  res_vsll = vec_ctsl(vf1, 500);
+  // CHECK:[[TMP39:%.*]] = load <4 x float>, ptr @vf1, align 16
+  // CHECK-NEXT:   fmul <4 x float> [[TMP39]], 
+
+  res_vf = vec_ctf(vsi1, 31);
+  // CHECK:[[TMP48:%.*]] = load <4 x i32>, ptr @vsi1, align 16
+  // CHECK-NEXT:   call <4 x float> @llvm.ppc.altivec.vcfsx(<4 x i32> [[TMP48]], i32 31)
+
+  res_vf = vec_ctf(vsi1, 500);
+  // CHECK:[[TMP50:%.*]] = load <4 x i32>, ptr @vsi1, align 16
+  // CHECK-NEXT:   call <4 x float> @llvm.ppc.altivec.vcfsx(<4 x i32> [[TMP50]], i32 20)
+
+  res_vd = vec_ctd(vsi1, 31);
+  // CHECK:[[TMP53:%.*]] = load <4 x i32>, ptr @vsi1, align 16
+  // CHECK:[[TMP83:%.*]] = call <2 x double> @llvm.ppc.vsx.xvcvsxwdp(<4 x i32> [[TMP82:%.*]])
+  // CHECK-NEXT:   fmul <2 x double> [[TMP83]], 
+
+  res_vd = vec_ctd(vsi1, 500);
+  // CHECK:[[TMP84:%.*]] = load <4 x i32>, ptr @vsi1, align 16
+  // CHECK:[[TMP115:%.*]] = call <2 x double> @llvm.ppc.vsx.xvcvsxwdp(<4 x i32> [[TMP114:%.*]])
+  // CHECK-NEXT:   fmul <2 x double> [[TMP115]], 
+}
Index: clang/lib/Headers/altivec.h
===
--- clang/lib/Headers/altivec.h
+++ clang/lib/Headers/altivec.h
@@ -3202,71 +3202,79 @@
 // the XL-compatible signatures are used for those functions.
 #ifdef __XL_COMPAT_ALTIVEC__
 #define vec_ctf(__a, __b)  \
-  _Generic(\
-  (__a), vector int\
-  : (vector float)__builtin_altivec_vcfsx((vector int)(__a), (__b)),   \

[PATCH] D106409: [PowerPC] Truncate exponent parameter for vec_cts,vec_ctf

2023-06-16 Thread Nemanja Ivanovic via Phabricator via cfe-commits 
nemanjai accepted this revision.
nemanjai added a comment.
This revision is now accepted and ready to land.

LGTM.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D106409/new/

https://reviews.llvm.org/D106409

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D106409: [PowerPC] Truncate exponent parameter for vec_cts,vec_ctf

2023-06-05 Thread Zarko Todorovski via Phabricator via cfe-commits 
ZarkoCA updated this revision to Diff 528492.
ZarkoCA marked an inline comment as done.
ZarkoCA removed a reviewer: jsji.
ZarkoCA added a comment.

Rebase and fix test.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D106409/new/

https://reviews.llvm.org/D106409

Files:
  clang/lib/Headers/altivec.h
  clang/test/CodeGen/ppc-vec_ct-truncate.c

Index: clang/test/CodeGen/ppc-vec_ct-truncate.c
===
--- /dev/null
+++ clang/test/CodeGen/ppc-vec_ct-truncate.c
@@ -0,0 +1,80 @@
+// REQUIRES: powerpc-registered-target
+// RUN: %clang_cc1 -target-feature +altivec -target-feature +vsx \
+// RUN:   -flax-vector-conversions=all -triple powerpc64-ibm-aix-xcoff -emit-llvm %s -o - \
+// RUN:   -target-cpu pwr7 | FileCheck %s
+// RUN: %clang_cc1 -target-feature +altivec -target-feature +vsx \
+// RUN:   -flax-vector-conversions=all -triple powerpc64-unknown-linux-gnu -emit-llvm %s -o - \
+// RUN:   -target-cpu pwr8 | FileCheck %s
+// RUN: %clang_cc1 -target-feature +altivec -target-feature +vsx \
+// RUN:   -flax-vector-conversions=all -triple powerpc64le-unknown-linux-gnu -emit-llvm %s -o - \
+// RUN:   -target-cpu pwr8 | FileCheck %s
+// RUN: %clang_cc1 -target-feature +altivec -target-feature +vsx \
+// RUN:   -flax-vector-conversions=all -triple powerpc64-ibm-aix-xcoff -emit-llvm %s -o - \
+// RUN:   -D__XL_COMPAT_ALTIVEC__ -target-cpu pwr7 | FileCheck %s
+// RUN: %clang_cc1 -target-feature +altivec -target-feature +vsx \
+// RUN:   -flax-vector-conversions=all -triple powerpc64le-unknown-linux-gnu -emit-llvm %s -o - \
+// RUN:   -D__XL_COMPAT_ALTIVEC__ -target-cpu pwr8 | FileCheck %s
+
+#include 
+vector double a1 = {-1.234e-5, 1.2345};
+vector signed int res_vsi;
+vector float vf1 = {0.234, 1.234, 2.345, 3.456};
+vector signed int vsi1 = {1, 2, 3, 4};
+vector double res_vd;
+vector float res_vf;
+vector signed long long res_vsll;
+vector unsigned long long res_vull;
+void test(void) {
+  // CHECK-LABEL: @test(
+  // CHECK-NEXT:  entry:
+
+  res_vsi = vec_cts(a1, 31);
+  //  CHECK:   [[TMP0:%.*]] = load <2 x double>, ptr @a1, align 16
+  //  CHECK-NEXT:  fmul <2 x double> [[TMP0]], 
+
+  res_vsi = vec_cts(a1, 500);
+  // CHECK:[[TMP4:%.*]] = load <2 x double>, ptr @a1, align 16
+  // CHECK-NEXT:   fmul <2 x double> [[TMP4]], 
+
+  res_vsi = vec_ctu(vf1, 31);
+  // CHECK:[[TMP8:%.*]] = load <4 x float>, ptr @vf1, align 16
+  // CHECK-NEXT:   call <4 x i32> @llvm.ppc.altivec.vctuxs(<4 x float> [[TMP8]], i32 31)
+
+  res_vsi = vec_ctu(vf1, 500);
+  // CHECK:[[TMP10:%.*]] = load <4 x float>, ptr @vf1, align 16
+  // CHECK-NEXT:   call <4 x i32> @llvm.ppc.altivec.vctuxs(<4 x float> [[TMP10]], i32 20)
+
+  res_vull = vec_ctul(vf1, 31);
+  // CHECK:[[TMP12:%.*]] = load <4 x float>, ptr @vf1, align 16
+  // CHECK-NEXT:   fmul <4 x float> [[TMP12]], 
+
+  res_vull = vec_ctul(vf1, 500);
+  // CHECK:[[TMP21:%.*]] = load <4 x float>, ptr @vf1, align 16
+  // CHECK-NEXT:   fmul <4 x float> [[TMP21]], 
+
+  res_vsll = vec_ctsl(vf1, 31);
+  // CHECK:[[TMP30:%.*]] = load <4 x float>, ptr @vf1, align 16
+  // CHECK-NEXT:   fmul <4 x float> [[TMP30]], 
+
+  res_vsll = vec_ctsl(vf1, 500);
+  // CHECK:[[TMP39:%.*]] = load <4 x float>, ptr @vf1, align 16
+  // CHECK-NEXT:   fmul <4 x float> [[TMP39]], 
+
+  res_vf = vec_ctf(vsi1, 31);
+  // CHECK:[[TMP48:%.*]] = load <4 x i32>, ptr @vsi1, align 16
+  // CHECK-NEXT:   call <4 x float> @llvm.ppc.altivec.vcfsx(<4 x i32> [[TMP48]], i32 31)
+
+  res_vf = vec_ctf(vsi1, 500);
+  // CHECK:[[TMP50:%.*]] = load <4 x i32>, ptr @vsi1, align 16
+  // CHECK-NEXT:   call <4 x float> @llvm.ppc.altivec.vcfsx(<4 x i32> [[TMP50]], i32 20)
+
+  res_vd = vec_ctd(vsi1, 31);
+  // CHECK:[[TMP53:%.*]] = load <4 x i32>, ptr @vsi1, align 16
+  // CHECK:[[TMP83:%.*]] = call <2 x double> @llvm.ppc.vsx.xvcvsxwdp(<4 x i32> [[TMP82:%.*]])
+  // CHECK-NEXT:   fmul <2 x double> [[TMP83]], 
+
+  res_vd = vec_ctd(vsi1, 500);
+  // CHECK:[[TMP84:%.*]] = load <4 x i32>, ptr @vsi1, align 16
+  // CHECK:[[TMP115:%.*]] = call <2 x double> @llvm.ppc.vsx.xvcvsxwdp(<4 x i32> [[TMP114:%.*]])
+  // CHECK-NEXT:   fmul <2 x double> [[TMP115]], 
+}
Index: clang/lib/Headers/altivec.h
===
--- clang/lib/Headers/altivec.h
+++ clang/lib/Headers/altivec.h
@@ -3202,71 +3202,79 @@
 // the XL-compatible signatures are used for those functions.
 #ifdef __XL_COMPAT_ALTIVEC__
 #define vec_ctf(__a, __b)  \
-  _Generic(\
-  (__a), vector int\
-  : (vector float)__builtin_altivec_vcfsx((vector int)(__a), (__b)),   \
-vector unsigned int

[PATCH] D106409: [PowerPC] Truncate exponent parameter for vec_cts,vec_ctf

2021-11-05 Thread Nemanja Ivanovic via Phabricator via cfe-commits 
nemanjai requested changes to this revision.
nemanjai added a comment.
This revision now requires changes to proceed.

I believe you are planning an update for this patch. Requesting changes to take 
it off the queue until you have uploaded the updated version.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D106409/new/

https://reviews.llvm.org/D106409

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D106409: [PowerPC] Truncate exponent parameter for vec_cts,vec_ctf

2021-10-01 Thread Zarko Todorovski via Phabricator via cfe-commits 
ZarkoCA marked an inline comment as done.
ZarkoCA added inline comments.



Comment at: clang/lib/Headers/altivec.h:3178
+  : (__builtin_vsx_xvcvuxdsp((vector unsigned long long)(__a)) *   
\
+ (vector float)(vector unsigned)((0x7f - (__b)) << 23 & 0x1F)),
\
+vector signed long long
\

nemanjai wrote:
> Hmm... aren't you truncating the wrong thing here (and for all the other 
> shifted ones? Shouldn't it be something like:
> ```
> (vector float)(vector unsigned)((0x7f - ((__b) & 0x1F)) << 23)),
> ```
Thanks, I wasn't doing the truncation correctly. Redid to what I think is 
correct now. 


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D106409/new/

https://reviews.llvm.org/D106409

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits