[PATCH] D107646: [PowerPC] Fix the frame addresss computing return address for `__builtin_return_address`

2021-08-12 Thread Victor Huang via Phabricator via cfe-commits 
This revision was automatically updated to reflect the committed changes.
Closed by commit rG99e00663d4cd: [PowerPC] Fix return address computation for 
"__builtin_return_address" (authored by NeHuang).

Repository:
  rG LLVM Github Monorepo

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Files:
  llvm/lib/Target/PowerPC/PPCISelLowering.cpp
  llvm/test/CodeGen/PowerPC/2010-05-03-retaddr1.ll
  llvm/test/CodeGen/PowerPC/retaddr_multi_levels.ll

Index: llvm/test/CodeGen/PowerPC/retaddr_multi_levels.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/retaddr_multi_levels.ll
@@ -0,0 +1,140 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64le-unknown-linux \
+; RUN:   -mcpu=pwr8 | FileCheck %s -check-prefix=CHECK-64B-LE
+; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux \
+; RUN:   -mcpu=pwr7 | FileCheck %s -check-prefix=CHECK-64B-BE
+; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-aix \
+; RUN:   -mcpu=pwr7 | FileCheck %s -check-prefix=CHECK-64B-BE
+; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc-unknown-aix \
+; RUN:   -mcpu=pwr7 | FileCheck %s -check-prefix=CHECK-32B-BE
+
+declare i8* @llvm.returnaddress(i32) nounwind readnone
+
+define i8* @test0() nounwind readnone {
+; CHECK-64B-LE-LABEL: test0:
+; CHECK-64B-LE:   # %bb.0: # %entry
+; CHECK-64B-LE-NEXT:mflr 0
+; CHECK-64B-LE-NEXT:std 0, 16(1)
+; CHECK-64B-LE-NEXT:stdu 1, -32(1)
+; CHECK-64B-LE-NEXT:ld 3, 48(1)
+; CHECK-64B-LE-NEXT:addi 1, 1, 32
+; CHECK-64B-LE-NEXT:ld 0, 16(1)
+; CHECK-64B-LE-NEXT:mtlr 0
+; CHECK-64B-LE-NEXT:blr
+;
+; CHECK-64B-BE-LABEL: test0:
+; CHECK-64B-BE:   # %bb.0: # %entry
+; CHECK-64B-BE-NEXT:mflr 0
+; CHECK-64B-BE-NEXT:std 0, 16(1)
+; CHECK-64B-BE-NEXT:stdu 1, -48(1)
+; CHECK-64B-BE-NEXT:ld 3, 64(1)
+; CHECK-64B-BE-NEXT:addi 1, 1, 48
+; CHECK-64B-BE-NEXT:ld 0, 16(1)
+; CHECK-64B-BE-NEXT:mtlr 0
+; CHECK-64B-BE-NEXT:blr
+;
+; CHECK-32B-BE-LABEL: test0:
+; CHECK-32B-BE:   # %bb.0: # %entry
+; CHECK-32B-BE-NEXT:mflr 0
+; CHECK-32B-BE-NEXT:stw 0, 8(1)
+; CHECK-32B-BE-NEXT:stwu 1, -32(1)
+; CHECK-32B-BE-NEXT:lwz 3, 40(1)
+; CHECK-32B-BE-NEXT:addi 1, 1, 32
+; CHECK-32B-BE-NEXT:lwz 0, 8(1)
+; CHECK-32B-BE-NEXT:mtlr 0
+; CHECK-32B-BE-NEXT:blr
+entry:
+  %0 = tail call i8* @llvm.returnaddress(i32 0);
+  ret i8* %0
+}
+
+define i8* @test1() nounwind readnone {
+; CHECK-64B-LE-LABEL: test1:
+; CHECK-64B-LE:   # %bb.0: # %entry
+; CHECK-64B-LE-NEXT:mflr 0
+; CHECK-64B-LE-NEXT:std 0, 16(1)
+; CHECK-64B-LE-NEXT:stdu 1, -32(1)
+; CHECK-64B-LE-NEXT:ld 3, 0(1)
+; CHECK-64B-LE-NEXT:ld 3, 0(3)
+; CHECK-64B-LE-NEXT:ld 3, 16(3)
+; CHECK-64B-LE-NEXT:addi 1, 1, 32
+; CHECK-64B-LE-NEXT:ld 0, 16(1)
+; CHECK-64B-LE-NEXT:mtlr 0
+; CHECK-64B-LE-NEXT:blr
+;
+; CHECK-64B-BE-LABEL: test1:
+; CHECK-64B-BE:   # %bb.0: # %entry
+; CHECK-64B-BE-NEXT:mflr 0
+; CHECK-64B-BE-NEXT:std 0, 16(1)
+; CHECK-64B-BE-NEXT:stdu 1, -48(1)
+; CHECK-64B-BE-NEXT:ld 3, 0(1)
+; CHECK-64B-BE-NEXT:ld 3, 0(3)
+; CHECK-64B-BE-NEXT:ld 3, 16(3)
+; CHECK-64B-BE-NEXT:addi 1, 1, 48
+; CHECK-64B-BE-NEXT:ld 0, 16(1)
+; CHECK-64B-BE-NEXT:mtlr 0
+; CHECK-64B-BE-NEXT:blr
+;
+; CHECK-32B-BE-LABEL: test1:
+; CHECK-32B-BE:   # %bb.0: # %entry
+; CHECK-32B-BE-NEXT:mflr 0
+; CHECK-32B-BE-NEXT:stw 0, 8(1)
+; CHECK-32B-BE-NEXT:stwu 1, -32(1)
+; CHECK-32B-BE-NEXT:lwz 3, 0(1)
+; CHECK-32B-BE-NEXT:lwz 3, 0(3)
+; CHECK-32B-BE-NEXT:lwz 3, 8(3)
+; CHECK-32B-BE-NEXT:addi 1, 1, 32
+; CHECK-32B-BE-NEXT:lwz 0, 8(1)
+; CHECK-32B-BE-NEXT:mtlr 0
+; CHECK-32B-BE-NEXT:blr
+entry:
+  %0 = tail call i8* @llvm.returnaddress(i32 1);
+  ret i8* %0
+}
+
+define i8* @test2() nounwind readnone {
+; CHECK-64B-LE-LABEL: test2:
+; CHECK-64B-LE:   # %bb.0: # %entry
+; CHECK-64B-LE-NEXT:mflr 0
+; CHECK-64B-LE-NEXT:std 0, 16(1)
+; CHECK-64B-LE-NEXT:stdu 1, -32(1)
+; CHECK-64B-LE-NEXT:ld 3, 0(1)
+; CHECK-64B-LE-NEXT:ld 3, 0(3)
+; CHECK-64B-LE-NEXT:ld 3, 0(3)
+; CHECK-64B-LE-NEXT:ld 3, 16(3)
+; CHECK-64B-LE-NEXT:addi 1, 1, 32
+; CHECK-64B-LE-NEXT:ld 0, 16(1)
+; CHECK-64B-LE-NEXT:mtlr 0
+; CHECK-64B-LE-NEXT:blr
+;
+; CHECK-64B-BE-LABEL: test2:
+; CHECK-64B-BE:   # %bb.0: # %entry
+; CHECK-64B-BE-NEXT:mflr 0
+; CHECK-64B-BE-NEXT:std 0, 16(1)
+; CHECK-64B-BE-NEXT:stdu 1, -48(1)
+; CHECK-64B-BE-NEXT:ld 3, 0(1)
+; CHECK-64B-BE-NEXT:ld 3, 0(3)
+; CHECK-64B-BE-NEXT:ld 3, 0(3)
+; CHECK-64B-BE-NEXT:ld 3, 16(3)
+; CHECK-64B-BE-NEXT:addi 1, 1, 48
+; CHECK-64B-BE-NEXT:ld 0, 16(1)
+; CHECK-64B-BE-NEXT:mtlr 0
+; CHECK-64B-BE-NEXT:blr
+;
+; CHECK-32B-BE-LABEL: test2:
+; CHE

[PATCH] D107646: [PowerPC] Fix the frame addresss computing return address for `__builtin_return_address`

2021-08-11 Thread Nemanja Ivanovic via Phabricator via cfe-commits 
nemanjai accepted this revision.
nemanjai added a comment.
This revision is now accepted and ready to land.

LGTM. Thanks for fixing this.


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[PATCH] D107646: [PowerPC] Fix the frame addresss computing return address for `__builtin_return_address`

2021-08-11 Thread Victor Huang via Phabricator via cfe-commits 
NeHuang updated this revision to Diff 365761.
NeHuang added a comment.

Address review comment from Nemanja.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D107646/new/

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Files:
  llvm/lib/Target/PowerPC/PPCISelLowering.cpp
  llvm/test/CodeGen/PowerPC/2010-05-03-retaddr1.ll
  llvm/test/CodeGen/PowerPC/retaddr_multi_levels.ll

Index: llvm/test/CodeGen/PowerPC/retaddr_multi_levels.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/retaddr_multi_levels.ll
@@ -0,0 +1,140 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64le-unknown-linux \
+; RUN:   -mcpu=pwr8 | FileCheck %s -check-prefix=CHECK-64B-LE
+; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux \
+; RUN:   -mcpu=pwr7 | FileCheck %s -check-prefix=CHECK-64B-BE
+; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-aix \
+; RUN:   -mcpu=pwr7 | FileCheck %s -check-prefix=CHECK-64B-BE
+; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc-unknown-aix \
+; RUN:   -mcpu=pwr7 | FileCheck %s -check-prefix=CHECK-32B-BE
+
+declare i8* @llvm.returnaddress(i32) nounwind readnone
+
+define i8* @test0() nounwind readnone {
+; CHECK-64B-LE-LABEL: test0:
+; CHECK-64B-LE:   # %bb.0: # %entry
+; CHECK-64B-LE-NEXT:mflr 0
+; CHECK-64B-LE-NEXT:std 0, 16(1)
+; CHECK-64B-LE-NEXT:stdu 1, -32(1)
+; CHECK-64B-LE-NEXT:ld 3, 48(1)
+; CHECK-64B-LE-NEXT:addi 1, 1, 32
+; CHECK-64B-LE-NEXT:ld 0, 16(1)
+; CHECK-64B-LE-NEXT:mtlr 0
+; CHECK-64B-LE-NEXT:blr
+;
+; CHECK-64B-BE-LABEL: test0:
+; CHECK-64B-BE:   # %bb.0: # %entry
+; CHECK-64B-BE-NEXT:mflr 0
+; CHECK-64B-BE-NEXT:std 0, 16(1)
+; CHECK-64B-BE-NEXT:stdu 1, -48(1)
+; CHECK-64B-BE-NEXT:ld 3, 64(1)
+; CHECK-64B-BE-NEXT:addi 1, 1, 48
+; CHECK-64B-BE-NEXT:ld 0, 16(1)
+; CHECK-64B-BE-NEXT:mtlr 0
+; CHECK-64B-BE-NEXT:blr
+;
+; CHECK-32B-BE-LABEL: test0:
+; CHECK-32B-BE:   # %bb.0: # %entry
+; CHECK-32B-BE-NEXT:mflr 0
+; CHECK-32B-BE-NEXT:stw 0, 8(1)
+; CHECK-32B-BE-NEXT:stwu 1, -32(1)
+; CHECK-32B-BE-NEXT:lwz 3, 40(1)
+; CHECK-32B-BE-NEXT:addi 1, 1, 32
+; CHECK-32B-BE-NEXT:lwz 0, 8(1)
+; CHECK-32B-BE-NEXT:mtlr 0
+; CHECK-32B-BE-NEXT:blr
+entry:
+  %0 = tail call i8* @llvm.returnaddress(i32 0);
+  ret i8* %0
+}
+
+define i8* @test1() nounwind readnone {
+; CHECK-64B-LE-LABEL: test1:
+; CHECK-64B-LE:   # %bb.0: # %entry
+; CHECK-64B-LE-NEXT:mflr 0
+; CHECK-64B-LE-NEXT:std 0, 16(1)
+; CHECK-64B-LE-NEXT:stdu 1, -32(1)
+; CHECK-64B-LE-NEXT:ld 3, 0(1)
+; CHECK-64B-LE-NEXT:ld 3, 0(3)
+; CHECK-64B-LE-NEXT:ld 3, 16(3)
+; CHECK-64B-LE-NEXT:addi 1, 1, 32
+; CHECK-64B-LE-NEXT:ld 0, 16(1)
+; CHECK-64B-LE-NEXT:mtlr 0
+; CHECK-64B-LE-NEXT:blr
+;
+; CHECK-64B-BE-LABEL: test1:
+; CHECK-64B-BE:   # %bb.0: # %entry
+; CHECK-64B-BE-NEXT:mflr 0
+; CHECK-64B-BE-NEXT:std 0, 16(1)
+; CHECK-64B-BE-NEXT:stdu 1, -48(1)
+; CHECK-64B-BE-NEXT:ld 3, 0(1)
+; CHECK-64B-BE-NEXT:ld 3, 0(3)
+; CHECK-64B-BE-NEXT:ld 3, 16(3)
+; CHECK-64B-BE-NEXT:addi 1, 1, 48
+; CHECK-64B-BE-NEXT:ld 0, 16(1)
+; CHECK-64B-BE-NEXT:mtlr 0
+; CHECK-64B-BE-NEXT:blr
+;
+; CHECK-32B-BE-LABEL: test1:
+; CHECK-32B-BE:   # %bb.0: # %entry
+; CHECK-32B-BE-NEXT:mflr 0
+; CHECK-32B-BE-NEXT:stw 0, 8(1)
+; CHECK-32B-BE-NEXT:stwu 1, -32(1)
+; CHECK-32B-BE-NEXT:lwz 3, 0(1)
+; CHECK-32B-BE-NEXT:lwz 3, 0(3)
+; CHECK-32B-BE-NEXT:lwz 3, 8(3)
+; CHECK-32B-BE-NEXT:addi 1, 1, 32
+; CHECK-32B-BE-NEXT:lwz 0, 8(1)
+; CHECK-32B-BE-NEXT:mtlr 0
+; CHECK-32B-BE-NEXT:blr
+entry:
+  %0 = tail call i8* @llvm.returnaddress(i32 1);
+  ret i8* %0
+}
+
+define i8* @test2() nounwind readnone {
+; CHECK-64B-LE-LABEL: test2:
+; CHECK-64B-LE:   # %bb.0: # %entry
+; CHECK-64B-LE-NEXT:mflr 0
+; CHECK-64B-LE-NEXT:std 0, 16(1)
+; CHECK-64B-LE-NEXT:stdu 1, -32(1)
+; CHECK-64B-LE-NEXT:ld 3, 0(1)
+; CHECK-64B-LE-NEXT:ld 3, 0(3)
+; CHECK-64B-LE-NEXT:ld 3, 0(3)
+; CHECK-64B-LE-NEXT:ld 3, 16(3)
+; CHECK-64B-LE-NEXT:addi 1, 1, 32
+; CHECK-64B-LE-NEXT:ld 0, 16(1)
+; CHECK-64B-LE-NEXT:mtlr 0
+; CHECK-64B-LE-NEXT:blr
+;
+; CHECK-64B-BE-LABEL: test2:
+; CHECK-64B-BE:   # %bb.0: # %entry
+; CHECK-64B-BE-NEXT:mflr 0
+; CHECK-64B-BE-NEXT:std 0, 16(1)
+; CHECK-64B-BE-NEXT:stdu 1, -48(1)
+; CHECK-64B-BE-NEXT:ld 3, 0(1)
+; CHECK-64B-BE-NEXT:ld 3, 0(3)
+; CHECK-64B-BE-NEXT:ld 3, 0(3)
+; CHECK-64B-BE-NEXT:ld 3, 16(3)
+; CHECK-64B-BE-NEXT:addi 1, 1, 48
+; CHECK-64B-BE-NEXT:ld 0, 16(1)
+; CHECK-64B-BE-NEXT:mtlr 0
+; CHECK-64B-BE-NEXT:blr
+;
+; CHECK-32B-BE-LABEL: test2:
+; CHECK-32B-BE:   # %bb.0: # %entry
+; CHECK-32B-BE-NEXT:mflr 0
+; CHECK-32B-BE-NEXT:s

[PATCH] D107646: [PowerPC] Fix the frame addresss computing return address for `__builtin_return_address`

2021-08-10 Thread Nemanja Ivanovic via Phabricator via cfe-commits 
nemanjai added inline comments.



Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.cpp:15962
 
   if (Depth > 0) {
+SDValue FrameAddr =

Please add a comment:
```
// The link register (return address) is saved in the caller's frame
// not the callee's stack frame. So we must get the caller's frame
// address and load the return address at the LR offset from there.
```



Comment at: llvm/test/CodeGen/PowerPC/2010-05-03-retaddr1.ll:1
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc-unknown-linux-gnu  | 
FileCheck %s

It is very hard to see what the actual differences are when you have changed 
the codegen as well as how the checks are produced in the same review. Could 
you please use the script to produce the checks and pre-commit that? Then this 
will show just the differences due to this patch.


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[PATCH] D107646: [PowerPC] Fix the frame addresss computing return address for `__builtin_return_address`

2021-08-10 Thread Victor Huang via Phabricator via cfe-commits 
NeHuang updated this revision to Diff 365470.
NeHuang added a comment.

Address review comments on the test case.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D107646/new/

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Files:
  llvm/lib/Target/PowerPC/PPCISelLowering.cpp
  llvm/test/CodeGen/PowerPC/2010-05-03-retaddr1.ll
  llvm/test/CodeGen/PowerPC/retaddr_multi_levels.ll

Index: llvm/test/CodeGen/PowerPC/retaddr_multi_levels.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/retaddr_multi_levels.ll
@@ -0,0 +1,140 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64le-unknown-linux \
+; RUN:   -mcpu=pwr8 | FileCheck %s -check-prefix=CHECK-64B-LE
+; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux \
+; RUN:   -mcpu=pwr7 | FileCheck %s -check-prefix=CHECK-64B-BE
+; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-aix \
+; RUN:   -mcpu=pwr7 | FileCheck %s -check-prefix=CHECK-64B-BE
+; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc-unknown-aix \
+; RUN:   -mcpu=pwr7 | FileCheck %s -check-prefix=CHECK-32B-BE
+
+declare i8* @llvm.returnaddress(i32) nounwind readnone
+
+define i8* @test0() nounwind readnone {
+; CHECK-64B-LE-LABEL: test0:
+; CHECK-64B-LE:   # %bb.0: # %entry
+; CHECK-64B-LE-NEXT:mflr 0
+; CHECK-64B-LE-NEXT:std 0, 16(1)
+; CHECK-64B-LE-NEXT:stdu 1, -32(1)
+; CHECK-64B-LE-NEXT:ld 3, 48(1)
+; CHECK-64B-LE-NEXT:addi 1, 1, 32
+; CHECK-64B-LE-NEXT:ld 0, 16(1)
+; CHECK-64B-LE-NEXT:mtlr 0
+; CHECK-64B-LE-NEXT:blr
+;
+; CHECK-64B-BE-LABEL: test0:
+; CHECK-64B-BE:   # %bb.0: # %entry
+; CHECK-64B-BE-NEXT:mflr 0
+; CHECK-64B-BE-NEXT:std 0, 16(1)
+; CHECK-64B-BE-NEXT:stdu 1, -48(1)
+; CHECK-64B-BE-NEXT:ld 3, 64(1)
+; CHECK-64B-BE-NEXT:addi 1, 1, 48
+; CHECK-64B-BE-NEXT:ld 0, 16(1)
+; CHECK-64B-BE-NEXT:mtlr 0
+; CHECK-64B-BE-NEXT:blr
+;
+; CHECK-32B-BE-LABEL: test0:
+; CHECK-32B-BE:   # %bb.0: # %entry
+; CHECK-32B-BE-NEXT:mflr 0
+; CHECK-32B-BE-NEXT:stw 0, 8(1)
+; CHECK-32B-BE-NEXT:stwu 1, -32(1)
+; CHECK-32B-BE-NEXT:lwz 3, 40(1)
+; CHECK-32B-BE-NEXT:addi 1, 1, 32
+; CHECK-32B-BE-NEXT:lwz 0, 8(1)
+; CHECK-32B-BE-NEXT:mtlr 0
+; CHECK-32B-BE-NEXT:blr
+entry:
+  %0 = tail call i8* @llvm.returnaddress(i32 0);
+  ret i8* %0
+}
+
+define i8* @test1() nounwind readnone {
+; CHECK-64B-LE-LABEL: test1:
+; CHECK-64B-LE:   # %bb.0: # %entry
+; CHECK-64B-LE-NEXT:mflr 0
+; CHECK-64B-LE-NEXT:std 0, 16(1)
+; CHECK-64B-LE-NEXT:stdu 1, -32(1)
+; CHECK-64B-LE-NEXT:ld 3, 0(1)
+; CHECK-64B-LE-NEXT:ld 3, 0(3)
+; CHECK-64B-LE-NEXT:ld 3, 16(3)
+; CHECK-64B-LE-NEXT:addi 1, 1, 32
+; CHECK-64B-LE-NEXT:ld 0, 16(1)
+; CHECK-64B-LE-NEXT:mtlr 0
+; CHECK-64B-LE-NEXT:blr
+;
+; CHECK-64B-BE-LABEL: test1:
+; CHECK-64B-BE:   # %bb.0: # %entry
+; CHECK-64B-BE-NEXT:mflr 0
+; CHECK-64B-BE-NEXT:std 0, 16(1)
+; CHECK-64B-BE-NEXT:stdu 1, -48(1)
+; CHECK-64B-BE-NEXT:ld 3, 0(1)
+; CHECK-64B-BE-NEXT:ld 3, 0(3)
+; CHECK-64B-BE-NEXT:ld 3, 16(3)
+; CHECK-64B-BE-NEXT:addi 1, 1, 48
+; CHECK-64B-BE-NEXT:ld 0, 16(1)
+; CHECK-64B-BE-NEXT:mtlr 0
+; CHECK-64B-BE-NEXT:blr
+;
+; CHECK-32B-BE-LABEL: test1:
+; CHECK-32B-BE:   # %bb.0: # %entry
+; CHECK-32B-BE-NEXT:mflr 0
+; CHECK-32B-BE-NEXT:stw 0, 8(1)
+; CHECK-32B-BE-NEXT:stwu 1, -32(1)
+; CHECK-32B-BE-NEXT:lwz 3, 0(1)
+; CHECK-32B-BE-NEXT:lwz 3, 0(3)
+; CHECK-32B-BE-NEXT:lwz 3, 8(3)
+; CHECK-32B-BE-NEXT:addi 1, 1, 32
+; CHECK-32B-BE-NEXT:lwz 0, 8(1)
+; CHECK-32B-BE-NEXT:mtlr 0
+; CHECK-32B-BE-NEXT:blr
+entry:
+  %0 = tail call i8* @llvm.returnaddress(i32 1);
+  ret i8* %0
+}
+
+define i8* @test2() nounwind readnone {
+; CHECK-64B-LE-LABEL: test2:
+; CHECK-64B-LE:   # %bb.0: # %entry
+; CHECK-64B-LE-NEXT:mflr 0
+; CHECK-64B-LE-NEXT:std 0, 16(1)
+; CHECK-64B-LE-NEXT:stdu 1, -32(1)
+; CHECK-64B-LE-NEXT:ld 3, 0(1)
+; CHECK-64B-LE-NEXT:ld 3, 0(3)
+; CHECK-64B-LE-NEXT:ld 3, 0(3)
+; CHECK-64B-LE-NEXT:ld 3, 16(3)
+; CHECK-64B-LE-NEXT:addi 1, 1, 32
+; CHECK-64B-LE-NEXT:ld 0, 16(1)
+; CHECK-64B-LE-NEXT:mtlr 0
+; CHECK-64B-LE-NEXT:blr
+;
+; CHECK-64B-BE-LABEL: test2:
+; CHECK-64B-BE:   # %bb.0: # %entry
+; CHECK-64B-BE-NEXT:mflr 0
+; CHECK-64B-BE-NEXT:std 0, 16(1)
+; CHECK-64B-BE-NEXT:stdu 1, -48(1)
+; CHECK-64B-BE-NEXT:ld 3, 0(1)
+; CHECK-64B-BE-NEXT:ld 3, 0(3)
+; CHECK-64B-BE-NEXT:ld 3, 0(3)
+; CHECK-64B-BE-NEXT:ld 3, 16(3)
+; CHECK-64B-BE-NEXT:addi 1, 1, 48
+; CHECK-64B-BE-NEXT:ld 0, 16(1)
+; CHECK-64B-BE-NEXT:mtlr 0
+; CHECK-64B-BE-NEXT:blr
+;
+; CHECK-32B-BE-LABEL: test2:
+; CHECK-32B-BE:   # %bb.0: # %entry
+; CHECK-32B-BE-NEXT:mflr 0
+; CHECK-32B-BE-NEXT:

[PATCH] D107646: [PowerPC] Fix the frame addresss computing return address for `__builtin_return_address`

2021-08-09 Thread Amy Kwan via Phabricator via cfe-commits 
amyk added inline comments.



Comment at: llvm/test/CodeGen/PowerPC/retaddr_multi_levels.ll:2
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64le-unknown-linux 
-mcpu=pwr8 | FileCheck %s -check-prefix=CHECK-64B-LE
+; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux 
-mcpu=pwr7 | FileCheck %s -check-prefix=CHECK-64B-BE

nit: The RUN lines look a bit too long in this test.



Comment at: llvm/test/CodeGen/PowerPC/retaddr_multi_levels.ll:21
+;
+; CHECK-64B-BE-LABEL: test0:
+; CHECK-64B-BE:   # %bb.0: # %entry

At a glance, it looks like `CHECK-64B-BE` and `CHECK-64B-AIX` looks like 
they're the same CHECKs.
Do you think it's a good idea to combine them into a single check/use 
check-prefixes? 


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D107646/new/

https://reviews.llvm.org/D107646

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[PATCH] D107646: [PowerPC] Fix the frame addresss computing return address for `__builtin_return_address`

2021-08-06 Thread Victor Huang via Phabricator via cfe-commits 
NeHuang updated this revision to Diff 364856.
NeHuang added a comment.

- Rebased with ToT
- Clang-format


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D107646/new/

https://reviews.llvm.org/D107646

Files:
  llvm/lib/Target/PowerPC/PPCISelLowering.cpp
  llvm/test/CodeGen/PowerPC/2010-05-03-retaddr1.ll
  llvm/test/CodeGen/PowerPC/retaddr_multi_levels.ll

Index: llvm/test/CodeGen/PowerPC/retaddr_multi_levels.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/retaddr_multi_levels.ll
@@ -0,0 +1,174 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64le-unknown-linux -mcpu=pwr8 | FileCheck %s -check-prefix=CHECK-64B-LE
+; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux -mcpu=pwr7 | FileCheck %s -check-prefix=CHECK-64B-BE
+; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-aix -mcpu=pwr7 | FileCheck %s -check-prefix=CHECK-64B-AIX
+; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc-unknown-aix -mcpu=pwr7 | FileCheck %s -check-prefix=CHECK-32B-AIX
+
+declare i8* @llvm.returnaddress(i32) nounwind readnone
+
+define i8* @test0() nounwind readnone {
+; CHECK-64B-LE-LABEL: test0:
+; CHECK-64B-LE:   # %bb.0: # %entry
+; CHECK-64B-LE-NEXT:mflr 0
+; CHECK-64B-LE-NEXT:std 0, 16(1)
+; CHECK-64B-LE-NEXT:stdu 1, -32(1)
+; CHECK-64B-LE-NEXT:ld 3, 48(1)
+; CHECK-64B-LE-NEXT:addi 1, 1, 32
+; CHECK-64B-LE-NEXT:ld 0, 16(1)
+; CHECK-64B-LE-NEXT:mtlr 0
+; CHECK-64B-LE-NEXT:blr
+;
+; CHECK-64B-BE-LABEL: test0:
+; CHECK-64B-BE:   # %bb.0: # %entry
+; CHECK-64B-BE-NEXT:mflr 0
+; CHECK-64B-BE-NEXT:std 0, 16(1)
+; CHECK-64B-BE-NEXT:stdu 1, -48(1)
+; CHECK-64B-BE-NEXT:ld 3, 64(1)
+; CHECK-64B-BE-NEXT:addi 1, 1, 48
+; CHECK-64B-BE-NEXT:ld 0, 16(1)
+; CHECK-64B-BE-NEXT:mtlr 0
+; CHECK-64B-BE-NEXT:blr
+;
+; CHECK-64B-AIX-LABEL: test0:
+; CHECK-64B-AIX:   # %bb.0: # %entry
+; CHECK-64B-AIX-NEXT:mflr 0
+; CHECK-64B-AIX-NEXT:std 0, 16(1)
+; CHECK-64B-AIX-NEXT:stdu 1, -48(1)
+; CHECK-64B-AIX-NEXT:ld 3, 64(1)
+; CHECK-64B-AIX-NEXT:addi 1, 1, 48
+; CHECK-64B-AIX-NEXT:ld 0, 16(1)
+; CHECK-64B-AIX-NEXT:mtlr 0
+; CHECK-64B-AIX-NEXT:blr
+;
+; CHECK-32B-AIX-LABEL: test0:
+; CHECK-32B-AIX:   # %bb.0: # %entry
+; CHECK-32B-AIX-NEXT:mflr 0
+; CHECK-32B-AIX-NEXT:stw 0, 8(1)
+; CHECK-32B-AIX-NEXT:stwu 1, -32(1)
+; CHECK-32B-AIX-NEXT:lwz 3, 40(1)
+; CHECK-32B-AIX-NEXT:addi 1, 1, 32
+; CHECK-32B-AIX-NEXT:lwz 0, 8(1)
+; CHECK-32B-AIX-NEXT:mtlr 0
+; CHECK-32B-AIX-NEXT:blr
+entry:
+  %0 = tail call i8* @llvm.returnaddress(i32 0);
+  ret i8* %0
+}
+
+define i8* @test1() nounwind readnone {
+; CHECK-64B-LE-LABEL: test1:
+; CHECK-64B-LE:   # %bb.0: # %entry
+; CHECK-64B-LE-NEXT:mflr 0
+; CHECK-64B-LE-NEXT:std 0, 16(1)
+; CHECK-64B-LE-NEXT:stdu 1, -32(1)
+; CHECK-64B-LE-NEXT:ld 3, 0(1)
+; CHECK-64B-LE-NEXT:ld 3, 0(3)
+; CHECK-64B-LE-NEXT:ld 3, 16(3)
+; CHECK-64B-LE-NEXT:addi 1, 1, 32
+; CHECK-64B-LE-NEXT:ld 0, 16(1)
+; CHECK-64B-LE-NEXT:mtlr 0
+; CHECK-64B-LE-NEXT:blr
+;
+; CHECK-64B-BE-LABEL: test1:
+; CHECK-64B-BE:   # %bb.0: # %entry
+; CHECK-64B-BE-NEXT:mflr 0
+; CHECK-64B-BE-NEXT:std 0, 16(1)
+; CHECK-64B-BE-NEXT:stdu 1, -48(1)
+; CHECK-64B-BE-NEXT:ld 3, 0(1)
+; CHECK-64B-BE-NEXT:ld 3, 0(3)
+; CHECK-64B-BE-NEXT:ld 3, 16(3)
+; CHECK-64B-BE-NEXT:addi 1, 1, 48
+; CHECK-64B-BE-NEXT:ld 0, 16(1)
+; CHECK-64B-BE-NEXT:mtlr 0
+; CHECK-64B-BE-NEXT:blr
+;
+; CHECK-64B-AIX-LABEL: test1:
+; CHECK-64B-AIX:   # %bb.0: # %entry
+; CHECK-64B-AIX-NEXT:mflr 0
+; CHECK-64B-AIX-NEXT:std 0, 16(1)
+; CHECK-64B-AIX-NEXT:stdu 1, -48(1)
+; CHECK-64B-AIX-NEXT:ld 3, 0(1)
+; CHECK-64B-AIX-NEXT:ld 3, 0(3)
+; CHECK-64B-AIX-NEXT:ld 3, 16(3)
+; CHECK-64B-AIX-NEXT:addi 1, 1, 48
+; CHECK-64B-AIX-NEXT:ld 0, 16(1)
+; CHECK-64B-AIX-NEXT:mtlr 0
+; CHECK-64B-AIX-NEXT:blr
+;
+; CHECK-32B-AIX-LABEL: test1:
+; CHECK-32B-AIX:   # %bb.0: # %entry
+; CHECK-32B-AIX-NEXT:mflr 0
+; CHECK-32B-AIX-NEXT:stw 0, 8(1)
+; CHECK-32B-AIX-NEXT:stwu 1, -32(1)
+; CHECK-32B-AIX-NEXT:lwz 3, 0(1)
+; CHECK-32B-AIX-NEXT:lwz 3, 0(3)
+; CHECK-32B-AIX-NEXT:lwz 3, 8(3)
+; CHECK-32B-AIX-NEXT:addi 1, 1, 32
+; CHECK-32B-AIX-NEXT:lwz 0, 8(1)
+; CHECK-32B-AIX-NEXT:mtlr 0
+; CHECK-32B-AIX-NEXT:blr
+entry:
+  %0 = tail call i8* @llvm.returnaddress(i32 1);
+  ret i8* %0
+}
+
+define i8* @test2() nounwind readnone {
+; CHECK-64B-LE-LABEL: test2:
+; CHECK-64B-LE:   # %bb.0: # %entry
+; CHECK-64B-LE-NEXT:mflr 0
+; CHECK-64B-LE-NEXT:std 0, 16(1)
+; CHECK-64B-LE-NEXT:stdu 1, -32(1)
+; CHECK-64B-LE-NEXT:ld 3, 0(1)
+; CHECK-64B-LE-NEXT:ld 3, 0(3)
+; CHECK-64B-LE-NEXT:

[PATCH] D107646: [PowerPC] Fix the frame addresss computing return address for `__builtin_return_address`

2021-08-06 Thread Victor Huang via Phabricator via cfe-commits 
NeHuang created this revision.
NeHuang added reviewers: nemanjai, stefanp, PowerPC.
NeHuang added a project: LLVM.
Herald added subscribers: shchenz, kbarton, hiraditya.
NeHuang requested review of this revision.

When depth > 0, callee frame address is used to compute the return address of 
callee producing improper return address. This patch adds the fix to use caller 
frame address to compute the return address of callee.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D107646

Files:
  llvm/lib/Target/PowerPC/PPCISelLowering.cpp
  llvm/test/CodeGen/PowerPC/2010-05-03-retaddr1.ll
  llvm/test/CodeGen/PowerPC/retaddr_multi_levels.ll

Index: llvm/test/CodeGen/PowerPC/retaddr_multi_levels.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/retaddr_multi_levels.ll
@@ -0,0 +1,174 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64le-unknown-linux -mcpu=pwr8 | FileCheck %s -check-prefix=CHECK-64B-LE
+; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux -mcpu=pwr7 | FileCheck %s -check-prefix=CHECK-64B-BE
+; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-aix -mcpu=pwr7 | FileCheck %s -check-prefix=CHECK-64B-AIX
+; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc-unknown-aix -mcpu=pwr7 | FileCheck %s -check-prefix=CHECK-32B-AIX
+
+declare i8* @llvm.returnaddress(i32) nounwind readnone
+
+define i8* @test0() nounwind readnone {
+; CHECK-64B-LE-LABEL: test0:
+; CHECK-64B-LE:   # %bb.0: # %entry
+; CHECK-64B-LE-NEXT:mflr 0
+; CHECK-64B-LE-NEXT:std 0, 16(1)
+; CHECK-64B-LE-NEXT:stdu 1, -32(1)
+; CHECK-64B-LE-NEXT:ld 3, 48(1)
+; CHECK-64B-LE-NEXT:addi 1, 1, 32
+; CHECK-64B-LE-NEXT:ld 0, 16(1)
+; CHECK-64B-LE-NEXT:mtlr 0
+; CHECK-64B-LE-NEXT:blr
+;
+; CHECK-64B-BE-LABEL: test0:
+; CHECK-64B-BE:   # %bb.0: # %entry
+; CHECK-64B-BE-NEXT:mflr 0
+; CHECK-64B-BE-NEXT:std 0, 16(1)
+; CHECK-64B-BE-NEXT:stdu 1, -48(1)
+; CHECK-64B-BE-NEXT:ld 3, 64(1)
+; CHECK-64B-BE-NEXT:addi 1, 1, 48
+; CHECK-64B-BE-NEXT:ld 0, 16(1)
+; CHECK-64B-BE-NEXT:mtlr 0
+; CHECK-64B-BE-NEXT:blr
+;
+; CHECK-64B-AIX-LABEL: test0:
+; CHECK-64B-AIX:   # %bb.0: # %entry
+; CHECK-64B-AIX-NEXT:mflr 0
+; CHECK-64B-AIX-NEXT:std 0, 16(1)
+; CHECK-64B-AIX-NEXT:stdu 1, -48(1)
+; CHECK-64B-AIX-NEXT:ld 3, 64(1)
+; CHECK-64B-AIX-NEXT:addi 1, 1, 48
+; CHECK-64B-AIX-NEXT:ld 0, 16(1)
+; CHECK-64B-AIX-NEXT:mtlr 0
+; CHECK-64B-AIX-NEXT:blr
+;
+; CHECK-32B-AIX-LABEL: test0:
+; CHECK-32B-AIX:   # %bb.0: # %entry
+; CHECK-32B-AIX-NEXT:mflr 0
+; CHECK-32B-AIX-NEXT:stw 0, 8(1)
+; CHECK-32B-AIX-NEXT:stwu 1, -32(1)
+; CHECK-32B-AIX-NEXT:lwz 3, 40(1)
+; CHECK-32B-AIX-NEXT:addi 1, 1, 32
+; CHECK-32B-AIX-NEXT:lwz 0, 8(1)
+; CHECK-32B-AIX-NEXT:mtlr 0
+; CHECK-32B-AIX-NEXT:blr
+entry:
+  %0 = tail call i8* @llvm.returnaddress(i32 0);
+  ret i8* %0
+}
+
+define i8* @test1() nounwind readnone {
+; CHECK-64B-LE-LABEL: test1:
+; CHECK-64B-LE:   # %bb.0: # %entry
+; CHECK-64B-LE-NEXT:mflr 0
+; CHECK-64B-LE-NEXT:std 0, 16(1)
+; CHECK-64B-LE-NEXT:stdu 1, -32(1)
+; CHECK-64B-LE-NEXT:ld 3, 0(1)
+; CHECK-64B-LE-NEXT:ld 3, 0(3)
+; CHECK-64B-LE-NEXT:ld 3, 16(3)
+; CHECK-64B-LE-NEXT:addi 1, 1, 32
+; CHECK-64B-LE-NEXT:ld 0, 16(1)
+; CHECK-64B-LE-NEXT:mtlr 0
+; CHECK-64B-LE-NEXT:blr
+;
+; CHECK-64B-BE-LABEL: test1:
+; CHECK-64B-BE:   # %bb.0: # %entry
+; CHECK-64B-BE-NEXT:mflr 0
+; CHECK-64B-BE-NEXT:std 0, 16(1)
+; CHECK-64B-BE-NEXT:stdu 1, -48(1)
+; CHECK-64B-BE-NEXT:ld 3, 0(1)
+; CHECK-64B-BE-NEXT:ld 3, 0(3)
+; CHECK-64B-BE-NEXT:ld 3, 16(3)
+; CHECK-64B-BE-NEXT:addi 1, 1, 48
+; CHECK-64B-BE-NEXT:ld 0, 16(1)
+; CHECK-64B-BE-NEXT:mtlr 0
+; CHECK-64B-BE-NEXT:blr
+;
+; CHECK-64B-AIX-LABEL: test1:
+; CHECK-64B-AIX:   # %bb.0: # %entry
+; CHECK-64B-AIX-NEXT:mflr 0
+; CHECK-64B-AIX-NEXT:std 0, 16(1)
+; CHECK-64B-AIX-NEXT:stdu 1, -48(1)
+; CHECK-64B-AIX-NEXT:ld 3, 0(1)
+; CHECK-64B-AIX-NEXT:ld 3, 0(3)
+; CHECK-64B-AIX-NEXT:ld 3, 16(3)
+; CHECK-64B-AIX-NEXT:addi 1, 1, 48
+; CHECK-64B-AIX-NEXT:ld 0, 16(1)
+; CHECK-64B-AIX-NEXT:mtlr 0
+; CHECK-64B-AIX-NEXT:blr
+;
+; CHECK-32B-AIX-LABEL: test1:
+; CHECK-32B-AIX:   # %bb.0: # %entry
+; CHECK-32B-AIX-NEXT:mflr 0
+; CHECK-32B-AIX-NEXT:stw 0, 8(1)
+; CHECK-32B-AIX-NEXT:stwu 1, -32(1)
+; CHECK-32B-AIX-NEXT:lwz 3, 0(1)
+; CHECK-32B-AIX-NEXT:lwz 3, 0(3)
+; CHECK-32B-AIX-NEXT:lwz 3, 8(3)
+; CHECK-32B-AIX-NEXT:addi 1, 1, 32
+; CHECK-32B-AIX-NEXT:lwz 0, 8(1)
+; CHECK-32B-AIX-NEXT:mtlr 0
+; CHECK-32B-AIX-NEXT:blr
+entry:
+  %0 = tail call i8* @llvm.returnaddress(i32 1);
+  ret i8* %0
+}
+
+define i8* @test2() nounwind readnone {
+; CHECK-64B-LE-LABEL: