[PATCH] D107850: [asan] Implemented custom calling convention similar to the one used by HWASan for X86.

[Evgenii Stepanov via Phabricator via cfe-commits]

eugenis added inline comments.



Comment at: llvm/include/llvm/IR/Intrinsics.td:1640
 
+def int_asan_check_memaccess :
+  Intrinsic<[],[llvm_ptr_ty, llvm_i8_ty, llvm_i8_ty],

vitalybuka wrote:
> kstoimenov wrote:
> > vitalybuka wrote:
> > > vitalybuka wrote:
> > > > PTAL at lvm.read_register.i32
> > > > 
> > > > How about:
> > > > 
> > > > llvm.asan.check.memaccess ->
> > > >   lvm.asan.check_read
> > > >   lvm.asan.check_write
> > > >   lvm.asan.kernel.check_read
> > > >   lvm.asan.kernel.check_write
> > > > 
> > > > Even better
> > > >   lvm.asan.check_read.{i8, i16, i32, ...}
> > > >   lvm.asan.check_write.{i8, i16, i32, ...}
> > > >   lvm.asan.kernel.check_read.{i8, i16, i32, ...}
> > > >   lvm.asan.kernel.check_write.{i8, i16, i32, ...}
> > > > 
> > > Looks like underscore is not used in intrinsic names, so essentially the 
> > > same with dots.
> > Sounds good to me. I do the full expansion so there will be 20 intrinsics 
> > altogether. I will update the code and ping you when done. 
> @pcc @eugenis 
> WDYT, I think later we can do the same for HWASAN?
I don't see what these multiple intrinsics give us that a single memaccess one 
does not provide?

As long as access type and similar arguments are immediates.




Comment at: llvm/include/llvm/IR/Intrinsics.td:1642
+  Intrinsic<[],[llvm_ptr_ty, llvm_i8_ty, llvm_i8_ty],
+[IntrInaccessibleMemOnly, ImmArg>, 
ImmArg>]>;
+

We've just removed IntrInaccessibleMemOnly from hwasan. This needs to alias 
shadow updates.



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[PATCH] D107850: [asan] Implemented custom calling convention similar to the one used by HWASan for X86.

[Kirill Stoimenov via Phabricator via cfe-commits]

kstoimenov updated this revision to Diff 367575.
kstoimenov added a comment.

Update before expanding intrinsics.


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Files:
  llvm/include/llvm/IR/Intrinsics.td
  llvm/lib/Target/X86/X86AsmPrinter.cpp
  llvm/lib/Target/X86/X86AsmPrinter.h
  llvm/lib/Target/X86/X86InstrCompiler.td
  llvm/lib/Target/X86/X86MCInstLower.cpp
  llvm/lib/Target/X86/X86RegisterInfo.td
  llvm/test/CodeGen/X86/asan-check-memaccess-add.ll
  llvm/test/CodeGen/X86/asan-check-memaccess-or.ll

Index: llvm/test/CodeGen/X86/asan-check-memaccess-or.ll
===
--- /dev/null
+++ llvm/test/CodeGen/X86/asan-check-memaccess-or.ll
@@ -0,0 +1,234 @@
+; RUN: llc < %s | FileCheck %s
+
+target triple = "x86_64-unknown-linux-gnu"
+
+define void @load1(i8* nocapture readonly %x) {
+; CHECK:  callq   __asan_check_load1_rn[[RN1:.*]]
+; CHECK:  callq   __asan_check_store1_rn[[RN1]]
+; CHECK-NEXT: retq
+  call void @llvm.asan.check.memaccess(i8* %x, i64 2147450880, i32 0,
+   i32 0, i32 3, i32 1)
+  call void @llvm.asan.check.memaccess(i8* %x, i64 2147450880, i32 1,
+   i32 0, i32 3, i32 1)
+  ret void
+}
+
+define void @load2(i16* nocapture readonly %x) {
+; CHECK:  callq   __asan_check_load2_rn[[RN2:.*]]
+; CHECK:  callq   __asan_check_store2_rn[[RN2]]
+; CHECK-NEXT: retq
+  %1 = ptrtoint i16* %x to i64
+  %2 = bitcast i16* %x to i8*
+  call void @llvm.asan.check.memaccess(i8* %2, i64 2147450880, i32 0,
+   i32 1, i32 3, i32 1)
+  call void @llvm.asan.check.memaccess(i8* %2, i64 2147450880, i32 1,
+   i32 1, i32 3, i32 1)
+  ret void
+}
+
+define void @load4(i32* nocapture readonly %x) {
+; CHECK:  callq   __asan_check_load4_rn[[RN4:.*]]
+; CHECK:  callq   __asan_check_store4_rn[[RN4]]
+; CHECK-NEXT: retq
+  %1 = ptrtoint i32* %x to i64
+  %2 = bitcast i32* %x to i8*
+  call void @llvm.asan.check.memaccess(i8* %2, i64 2147450880, i32 0,
+   i32 2, i32 3, i32 1)
+  call void @llvm.asan.check.memaccess(i8* %2, i64 2147450880, i32 1,
+   i32 2, i32 3, i32 1)
+  ret void
+}
+define void @load8(i64* nocapture readonly %x) {
+; CHECK:  callq   __asan_check_load8_rn[[RN8:.*]]
+; CHECK:  callq   __asan_check_store8_rn[[RN8]]
+; CHECK-NEXT: retq
+  %1 = ptrtoint i64* %x to i64
+  %2 = bitcast i64* %x to i8*
+  call void @llvm.asan.check.memaccess(i8* %2, i64 2147450880, i32 0,
+   i32 3, i32 3, i32 1)
+  call void @llvm.asan.check.memaccess(i8* %2, i64 2147450880, i32 1,
+   i32 3, i32 3, i32 1)
+  ret void
+}
+
+define void @load16(i128* nocapture readonly %x) {
+; CHECK:  callq   __asan_check_load16_rn[[RN16:.*]]
+; CHECK:  callq   __asan_check_store16_rn[[RN16]]
+; CHECK-NEXT: retq
+  %1 = ptrtoint i128* %x to i64
+  %2 = bitcast i128* %x to i8*
+  call void @llvm.asan.check.memaccess(i8* %2, i64 2147450880, i32 0,
+   i32 4, i32 3, i32 1)
+  call void @llvm.asan.check.memaccess(i8* %2, i64 2147450880, i32 1,
+   i32 4, i32 3, i32 1)
+  ret void
+}
+
+; CHECK:  __asan_check_load1_rn[[RN1]]:
+; CHECK-NEXT: movq[[REG:.*]], %r8
+; CHECK-NEXT: shrq$3, %r8
+; CHECK-NEXT: orq $2147450880, %r8{{.*}}
+; CHECK-NEXT: movb(%r8), %r8b
+; CHECK-NEXT: testb   %r8b, %r8b
+; CHECK-NEXT: jne [[EXTRA:.*]]
+; CHECK-NEXT: [[RET:.*]]:
+; CHECK-NEXT: retq
+; CHECK-NEXT: [[EXTRA]]:
+; CHECK-NEXT: pushq   %rcx
+; CHECK-NEXT: movq[[REG]], %rcx
+; CHECK-NEXT: andl$7, %ecx
+; CHECK-NEXT: cmpl%r8d, %ecx
+; CHECK-NEXT: popq%rcx
+; CHECK-NEXT: jl  [[RET]]
+; CHECK-NEXT: movq[[REG:.*]], %rdi
+; CHECK-NEXT: jmp __asan_report_load1
+
+; CHECK:  __asan_check_load2_rn[[RN2]]:
+; CHECK-NEXT: movq[[REG:.*]], %r8
+; CHECK-NEXT: shrq$3, %r8
+; CHECK-NEXT: orq $2147450880, %r8{{.*}}
+; CHECK-NEXT: movb(%r8), %r8b
+; CHECK-NEXT: testb   %r8b, %r8b
+; CHECK-NEXT: jne [[EXTRA:.*]]
+; CHECK-NEXT: [[RET:.*]]:
+; CHECK-NEXT: retq
+; CHECK-NEXT: [[EXTRA]]:
+; CHECK-NEXT: pushq   %rcx
+; CHECK-NEXT: movq[[REG]], %rcx
+; CHECK-NEXT: andl$7, %ecx
+; CHECK-NEXT: addl$1, %ecx
+; CHECK-NEXT: cmpl%r8d, %ecx
+; CHECK-NEXT: popq%rcx
+; CHECK-NEXT: jl  [[RET]]
+; CHECK-NEXT: mo

[PATCH] D107850: [asan] Implemented custom calling convention similar to the one used by HWASan for X86.

[Vitaly Buka via Phabricator via cfe-commits]

vitalybuka added a subscriber: eugenis.
vitalybuka added inline comments.



Comment at: llvm/include/llvm/IR/Intrinsics.td:1640
 
+def int_asan_check_memaccess :
+  Intrinsic<[],[llvm_ptr_ty, llvm_i8_ty, llvm_i8_ty],

kstoimenov wrote:
> vitalybuka wrote:
> > vitalybuka wrote:
> > > PTAL at lvm.read_register.i32
> > > 
> > > How about:
> > > 
> > > llvm.asan.check.memaccess ->
> > >   lvm.asan.check_read
> > >   lvm.asan.check_write
> > >   lvm.asan.kernel.check_read
> > >   lvm.asan.kernel.check_write
> > > 
> > > Even better
> > >   lvm.asan.check_read.{i8, i16, i32, ...}
> > >   lvm.asan.check_write.{i8, i16, i32, ...}
> > >   lvm.asan.kernel.check_read.{i8, i16, i32, ...}
> > >   lvm.asan.kernel.check_write.{i8, i16, i32, ...}
> > > 
> > Looks like underscore is not used in intrinsic names, so essentially the 
> > same with dots.
> Sounds good to me. I do the full expansion so there will be 20 intrinsics 
> altogether. I will update the code and ping you when done. 
@pcc @eugenis 
WDYT, I think later we can do the same for HWASAN?


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[PATCH] D107850: [asan] Implemented custom calling convention similar to the one used by HWASan for X86.

[Kirill Stoimenov via Phabricator via cfe-commits]

kstoimenov marked an inline comment as done.
kstoimenov added inline comments.



Comment at: llvm/include/llvm/IR/Intrinsics.td:1640
 
+def int_asan_check_memaccess :
+  Intrinsic<[],[llvm_ptr_ty, llvm_i8_ty, llvm_i8_ty],

vitalybuka wrote:
> vitalybuka wrote:
> > PTAL at lvm.read_register.i32
> > 
> > How about:
> > 
> > llvm.asan.check.memaccess ->
> >   lvm.asan.check_read
> >   lvm.asan.check_write
> >   lvm.asan.kernel.check_read
> >   lvm.asan.kernel.check_write
> > 
> > Even better
> >   lvm.asan.check_read.{i8, i16, i32, ...}
> >   lvm.asan.check_write.{i8, i16, i32, ...}
> >   lvm.asan.kernel.check_read.{i8, i16, i32, ...}
> >   lvm.asan.kernel.check_write.{i8, i16, i32, ...}
> > 
> Looks like underscore is not used in intrinsic names, so essentially the same 
> with dots.
Sounds good to me. I do the full expansion so there will be 20 intrinsics 
altogether. I will update the code and ping you when done. 


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[PATCH] D107850: [asan] Implemented custom calling convention similar to the one used by HWASan for X86.

[Vitaly Buka via Phabricator via cfe-commits]

vitalybuka added inline comments.



Comment at: llvm/include/llvm/IR/Intrinsics.td:1640
 
+def int_asan_check_memaccess :
+  Intrinsic<[],[llvm_ptr_ty, llvm_i8_ty, llvm_i8_ty],

vitalybuka wrote:
> PTAL at lvm.read_register.i32
> 
> How about:
> 
> llvm.asan.check.memaccess ->
>   lvm.asan.check_read
>   lvm.asan.check_write
>   lvm.asan.kernel.check_read
>   lvm.asan.kernel.check_write
> 
> Even better
>   lvm.asan.check_read.{i8, i16, i32, ...}
>   lvm.asan.check_write.{i8, i16, i32, ...}
>   lvm.asan.kernel.check_read.{i8, i16, i32, ...}
>   lvm.asan.kernel.check_write.{i8, i16, i32, ...}
> 
Looks like underscore is not used in intrinsic names, so essentially the same 
with dots.


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[PATCH] D107850: [asan] Implemented custom calling convention similar to the one used by HWASan for X86.

[Vitaly Buka via Phabricator via cfe-commits]

vitalybuka added inline comments.



Comment at: llvm/include/llvm/IR/Intrinsics.td:1640
 
+def int_asan_check_memaccess :
+  Intrinsic<[],[llvm_ptr_ty, llvm_i8_ty, llvm_i8_ty],

PTAL at lvm.read_register.i32

How about:

llvm.asan.check.memaccess ->
  lvm.asan.check_read
  lvm.asan.check_write
  lvm.asan.kernel.check_read
  lvm.asan.kernel.check_write

Even better
  lvm.asan.check_read.{i8, i16, i32, ...}
  lvm.asan.check_write.{i8, i16, i32, ...}
  lvm.asan.kernel.check_read.{i8, i16, i32, ...}
  lvm.asan.kernel.check_write.{i8, i16, i32, ...}



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[PATCH] D107850: [asan] Implemented custom calling convention similar to the one used by HWASan for X86.

[Kirill Stoimenov via Phabricator via cfe-commits]

kstoimenov marked 7 inline comments as done.
kstoimenov added a comment.

Added getAddressSanitizerParams to pull the constants out. Let me know if this 
is what you had in mind. Also struggled a little bit with git and rebase, but I 
think I have figured it out now.




Comment at: llvm/lib/Target/X86/X86MCInstLower.cpp:1340-1341
+  MCSymbol *&Sym = AsanMemaccessSymbols[{
+  Reg, ShadowBase, IsWrite, AccessSizeIndex, MI.getOperand(4).getImm(),
+  MI.getOperand(5).getImm()}];
+  if (!Sym) {

vitalybuka wrote:
> vitalybuka wrote:
> > Why shadow is an argument? Both runtime and instrumented code know the 
> > shadow.
> could you please unpack these to into local variables for consistency?
Removed the variables as we have discussed. 


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[PATCH] D107850: [asan] Implemented custom calling convention similar to the one used by HWASan for X86.

[Kirill Stoimenov via Phabricator via cfe-commits]

kstoimenov updated this revision to Diff 367507.
kstoimenov added a comment.

Fixed after rebase.


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Files:
  llvm/include/llvm/IR/Intrinsics.td
  llvm/lib/Target/X86/X86AsmPrinter.cpp
  llvm/lib/Target/X86/X86AsmPrinter.h
  llvm/lib/Target/X86/X86InstrCompiler.td
  llvm/lib/Target/X86/X86MCInstLower.cpp
  llvm/lib/Target/X86/X86RegisterInfo.td
  llvm/test/CodeGen/X86/asan-check-memaccess-add.ll
  llvm/test/CodeGen/X86/asan-check-memaccess-or.ll

Index: llvm/test/CodeGen/X86/asan-check-memaccess-or.ll
===
--- /dev/null
+++ llvm/test/CodeGen/X86/asan-check-memaccess-or.ll
@@ -0,0 +1,234 @@
+; RUN: llc < %s | FileCheck %s
+
+target triple = "x86_64-unknown-linux-gnu"
+
+define void @load1(i8* nocapture readonly %x) {
+; CHECK:  callq   __asan_check_load1_rn[[RN1:.*]]
+; CHECK:  callq   __asan_check_store1_rn[[RN1]]
+; CHECK-NEXT: retq
+  call void @llvm.asan.check.memaccess(i8* %x, i64 2147450880, i32 0,
+   i32 0, i32 3, i32 1)
+  call void @llvm.asan.check.memaccess(i8* %x, i64 2147450880, i32 1,
+   i32 0, i32 3, i32 1)
+  ret void
+}
+
+define void @load2(i16* nocapture readonly %x) {
+; CHECK:  callq   __asan_check_load2_rn[[RN2:.*]]
+; CHECK:  callq   __asan_check_store2_rn[[RN2]]
+; CHECK-NEXT: retq
+  %1 = ptrtoint i16* %x to i64
+  %2 = bitcast i16* %x to i8*
+  call void @llvm.asan.check.memaccess(i8* %2, i64 2147450880, i32 0,
+   i32 1, i32 3, i32 1)
+  call void @llvm.asan.check.memaccess(i8* %2, i64 2147450880, i32 1,
+   i32 1, i32 3, i32 1)
+  ret void
+}
+
+define void @load4(i32* nocapture readonly %x) {
+; CHECK:  callq   __asan_check_load4_rn[[RN4:.*]]
+; CHECK:  callq   __asan_check_store4_rn[[RN4]]
+; CHECK-NEXT: retq
+  %1 = ptrtoint i32* %x to i64
+  %2 = bitcast i32* %x to i8*
+  call void @llvm.asan.check.memaccess(i8* %2, i64 2147450880, i32 0,
+   i32 2, i32 3, i32 1)
+  call void @llvm.asan.check.memaccess(i8* %2, i64 2147450880, i32 1,
+   i32 2, i32 3, i32 1)
+  ret void
+}
+define void @load8(i64* nocapture readonly %x) {
+; CHECK:  callq   __asan_check_load8_rn[[RN8:.*]]
+; CHECK:  callq   __asan_check_store8_rn[[RN8]]
+; CHECK-NEXT: retq
+  %1 = ptrtoint i64* %x to i64
+  %2 = bitcast i64* %x to i8*
+  call void @llvm.asan.check.memaccess(i8* %2, i64 2147450880, i32 0,
+   i32 3, i32 3, i32 1)
+  call void @llvm.asan.check.memaccess(i8* %2, i64 2147450880, i32 1,
+   i32 3, i32 3, i32 1)
+  ret void
+}
+
+define void @load16(i128* nocapture readonly %x) {
+; CHECK:  callq   __asan_check_load16_rn[[RN16:.*]]
+; CHECK:  callq   __asan_check_store16_rn[[RN16]]
+; CHECK-NEXT: retq
+  %1 = ptrtoint i128* %x to i64
+  %2 = bitcast i128* %x to i8*
+  call void @llvm.asan.check.memaccess(i8* %2, i64 2147450880, i32 0,
+   i32 4, i32 3, i32 1)
+  call void @llvm.asan.check.memaccess(i8* %2, i64 2147450880, i32 1,
+   i32 4, i32 3, i32 1)
+  ret void
+}
+
+; CHECK:  __asan_check_load1_rn[[RN1]]:
+; CHECK-NEXT: movq[[REG:.*]], %r8
+; CHECK-NEXT: shrq$3, %r8
+; CHECK-NEXT: orq $2147450880, %r8{{.*}}
+; CHECK-NEXT: movb(%r8), %r8b
+; CHECK-NEXT: testb   %r8b, %r8b
+; CHECK-NEXT: jne [[EXTRA:.*]]
+; CHECK-NEXT: [[RET:.*]]:
+; CHECK-NEXT: retq
+; CHECK-NEXT: [[EXTRA]]:
+; CHECK-NEXT: pushq   %rcx
+; CHECK-NEXT: movq[[REG]], %rcx
+; CHECK-NEXT: andl$7, %ecx
+; CHECK-NEXT: cmpl%r8d, %ecx
+; CHECK-NEXT: popq%rcx
+; CHECK-NEXT: jl  [[RET]]
+; CHECK-NEXT: movq[[REG:.*]], %rdi
+; CHECK-NEXT: jmp __asan_report_load1
+
+; CHECK:  __asan_check_load2_rn[[RN2]]:
+; CHECK-NEXT: movq[[REG:.*]], %r8
+; CHECK-NEXT: shrq$3, %r8
+; CHECK-NEXT: orq $2147450880, %r8{{.*}}
+; CHECK-NEXT: movb(%r8), %r8b
+; CHECK-NEXT: testb   %r8b, %r8b
+; CHECK-NEXT: jne [[EXTRA:.*]]
+; CHECK-NEXT: [[RET:.*]]:
+; CHECK-NEXT: retq
+; CHECK-NEXT: [[EXTRA]]:
+; CHECK-NEXT: pushq   %rcx
+; CHECK-NEXT: movq[[REG]], %rcx
+; CHECK-NEXT: andl$7, %ecx
+; CHECK-NEXT: addl$1, %ecx
+; CHECK-NEXT: cmpl%r8d, %ecx
+; CHECK-NEXT: popq%rcx
+; CHECK-NEXT: jl  [[RET]]
+; CHECK-NEXT: movq[[REG:.*]]

[PATCH] D107850: [asan] Implemented custom calling convention similar to the one used by HWASan for X86.

[Kirill Stoimenov via Phabricator via cfe-commits]

kstoimenov updated this revision to Diff 367505.
kstoimenov added a comment.

Pulled constants like shadow base, etc out of the intrinsic.


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Files:
  clang/test/CodeGen/asan-use-callbacks.cpp
  llvm/include/llvm/Transforms/Instrumentation/AddressSanitizer.h
  llvm/include/llvm/Transforms/Instrumentation/AddressSanitizerCommon.h
  llvm/lib/Transforms/Instrumentation/AddressSanitizer.cpp

Index: llvm/lib/Transforms/Instrumentation/AddressSanitizer.cpp
===
--- llvm/lib/Transforms/Instrumentation/AddressSanitizer.cpp
+++ llvm/lib/Transforms/Instrumentation/AddressSanitizer.cpp
@@ -348,6 +348,10 @@
 static cl::opt ClOpt("asan-opt", cl::desc("Optimize instrumentation"),
cl::Hidden, cl::init(true));
 
+static cl::opt ClOptimizeCallbacks("asan-optimize-callbacks",
+ cl::desc("Optimize callbacks"),
+ cl::Hidden, cl::init(false));
+
 static cl::opt ClOptSameTemp(
 "asan-opt-same-temp", cl::desc("Instrument the same temp just once"),
 cl::Hidden, cl::init(true));
@@ -559,6 +563,17 @@
   return Mapping;
 }
 
+void getAddressSanitizerParams(Module &M, uint64_t *ShadowBase,
+   int *MappingScale, bool *OrShadowOffset) {
+  Triple TargetTriple = Triple(M.getTargetTriple());
+  auto Mapping =
+  getShadowMapping(TargetTriple, M.getDataLayout().getPointerSizeInBits(),
+   ClEnableKasan.getNumOccurrences() > 0);
+  *ShadowBase = Mapping.Offset;
+  *MappingScale = Mapping.Scale;
+  *OrShadowOffset = Mapping.OrShadowOffset;
+}
+
 static uint64_t getRedzoneSizeForScale(int MappingScale) {
   // Redzone used for stack and globals is at least 32 bytes.
   // For scales 6 and 7, the redzone has to be 64 and 128 bytes respectively.
@@ -623,6 +638,7 @@
 C = &(M.getContext());
 LongSize = M.getDataLayout().getPointerSizeInBits();
 IntptrTy = Type::getIntNTy(*C, LongSize);
+Int8PtrTy = Type::getInt8PtrTy(*C);
 TargetTriple = Triple(M.getTargetTriple());
 
 Mapping = getShadowMapping(TargetTriple, LongSize, this->CompileKernel);
@@ -673,6 +689,7 @@
  Value *SizeArgument, uint32_t Exp);
   void instrumentMemIntrinsic(MemIntrinsic *MI);
   Value *memToShadow(Value *Shadow, IRBuilder<> &IRB);
+  void encodeMemToShadowInfo(int64_t *AccessInfo);
   bool suppressInstrumentationSiteForDebug(int &Instrumented);
   bool instrumentFunction(Function &F, const TargetLibraryInfo *TLI);
   bool maybeInsertAsanInitAtFunctionEntry(Function &F);
@@ -713,6 +730,7 @@
   bool UseAfterScope;
   AsanDetectStackUseAfterReturnMode UseAfterReturn;
   Type *IntptrTy;
+  Type *Int8PtrTy;
   ShadowMapping Mapping;
   FunctionCallee AsanHandleNoReturnFunc;
   FunctionCallee AsanPtrCmpFunction, AsanPtrSubFunction;
@@ -1742,12 +1760,21 @@
   size_t AccessSizeIndex = TypeSizeToSizeIndex(TypeSize);
 
   if (UseCalls) {
-if (Exp == 0)
-  IRB.CreateCall(AsanMemoryAccessCallback[IsWrite][0][AccessSizeIndex],
- AddrLong);
-else
-  IRB.CreateCall(AsanMemoryAccessCallback[IsWrite][1][AccessSizeIndex],
- {AddrLong, ConstantInt::get(IRB.getInt32Ty(), Exp)});
+if (ClOptimizeCallbacks) {
+  Value *Ptr8 = IRB.CreatePointerCast(Addr, Int8PtrTy);
+  Module *M = IRB.GetInsertBlock()->getParent()->getParent();
+  IRB.CreateCall(
+  Intrinsic::getDeclaration(M, Intrinsic::asan_check_memaccess),
+  {Ptr8, ConstantInt::get(IRB.getInt8Ty(), IsWrite),
+   ConstantInt::get(IRB.getInt8Ty(), AccessSizeIndex)});
+} else {
+  if (Exp == 0)
+IRB.CreateCall(AsanMemoryAccessCallback[IsWrite][0][AccessSizeIndex],
+   AddrLong);
+  else
+IRB.CreateCall(AsanMemoryAccessCallback[IsWrite][1][AccessSizeIndex],
+   {AddrLong, ConstantInt::get(IRB.getInt32Ty(), Exp)});
+}
 return;
   }
 
Index: llvm/include/llvm/Transforms/Instrumentation/AddressSanitizerCommon.h
===
--- llvm/include/llvm/Transforms/Instrumentation/AddressSanitizerCommon.h
+++ llvm/include/llvm/Transforms/Instrumentation/AddressSanitizerCommon.h
@@ -87,6 +87,8 @@
   return true;
 }
 
+void getASanShadowMapping(int *Scale, uint64_t *Offset, bool *OrShadowOffset);
+
 } // namespace llvm
 
 #endif
Index: llvm/include/llvm/Transforms/Instrumentation/AddressSanitizer.h
===
--- llvm/include/llvm/Transforms/Instrumentation/AddressSanitizer.h
+++ llvm/include/llvm/Transforms/Instrumentation/AddressSanitizer.h
@@ -147,6 +147,10 @@
 bool UseOdrIndicator = true,
 AsanDtorKind DestructorKind = AsanDtorKind::Global);
 
+// Get

[PATCH] D107850: [asan] Implemented custom calling convention similar to the one used by HWASan for X86.

[Kirill Stoimenov via Phabricator via cfe-commits]

kstoimenov updated this revision to Diff 367501.
kstoimenov added a comment.

Pulled constants like shadow base, etc out of the intrinsic.


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Files:
  clang/test/CodeGen/asan-use-callbacks.cpp
  llvm/include/llvm/Transforms/Instrumentation/AddressSanitizer.h
  llvm/include/llvm/Transforms/Instrumentation/AddressSanitizerCommon.h
  llvm/lib/Transforms/Instrumentation/AddressSanitizer.cpp

Index: llvm/lib/Transforms/Instrumentation/AddressSanitizer.cpp
===
--- llvm/lib/Transforms/Instrumentation/AddressSanitizer.cpp
+++ llvm/lib/Transforms/Instrumentation/AddressSanitizer.cpp
@@ -348,6 +348,10 @@
 static cl::opt ClOpt("asan-opt", cl::desc("Optimize instrumentation"),
cl::Hidden, cl::init(true));
 
+static cl::opt ClOptimizeCallbacks("asan-optimize-callbacks",
+ cl::desc("Optimize callbacks"),
+ cl::Hidden, cl::init(false));
+
 static cl::opt ClOptSameTemp(
 "asan-opt-same-temp", cl::desc("Instrument the same temp just once"),
 cl::Hidden, cl::init(true));
@@ -559,6 +563,17 @@
   return Mapping;
 }
 
+void getAddressSanitizerParams(Module &M, uint64_t *ShadowBase,
+   int *MappingScale, bool *OrShadowOffset) {
+  Triple TargetTriple = Triple(M.getTargetTriple());
+  auto Mapping =
+  getShadowMapping(TargetTriple, M.getDataLayout().getPointerSizeInBits(),
+   ClEnableKasan.getNumOccurrences() > 0);
+  *ShadowBase = Mapping.Offset;
+  *MappingScale = Mapping.Scale;
+  *OrShadowOffset = Mapping.OrShadowOffset;
+}
+
 static uint64_t getRedzoneSizeForScale(int MappingScale) {
   // Redzone used for stack and globals is at least 32 bytes.
   // For scales 6 and 7, the redzone has to be 64 and 128 bytes respectively.
@@ -623,6 +638,7 @@
 C = &(M.getContext());
 LongSize = M.getDataLayout().getPointerSizeInBits();
 IntptrTy = Type::getIntNTy(*C, LongSize);
+Int8PtrTy = Type::getInt8PtrTy(*C);
 TargetTriple = Triple(M.getTargetTriple());
 
 Mapping = getShadowMapping(TargetTriple, LongSize, this->CompileKernel);
@@ -673,6 +689,7 @@
  Value *SizeArgument, uint32_t Exp);
   void instrumentMemIntrinsic(MemIntrinsic *MI);
   Value *memToShadow(Value *Shadow, IRBuilder<> &IRB);
+  void encodeMemToShadowInfo(int64_t *AccessInfo);
   bool suppressInstrumentationSiteForDebug(int &Instrumented);
   bool instrumentFunction(Function &F, const TargetLibraryInfo *TLI);
   bool maybeInsertAsanInitAtFunctionEntry(Function &F);
@@ -713,6 +730,7 @@
   bool UseAfterScope;
   AsanDetectStackUseAfterReturnMode UseAfterReturn;
   Type *IntptrTy;
+  Type *Int8PtrTy;
   ShadowMapping Mapping;
   FunctionCallee AsanHandleNoReturnFunc;
   FunctionCallee AsanPtrCmpFunction, AsanPtrSubFunction;
@@ -1742,12 +1760,21 @@
   size_t AccessSizeIndex = TypeSizeToSizeIndex(TypeSize);
 
   if (UseCalls) {
-if (Exp == 0)
-  IRB.CreateCall(AsanMemoryAccessCallback[IsWrite][0][AccessSizeIndex],
- AddrLong);
-else
-  IRB.CreateCall(AsanMemoryAccessCallback[IsWrite][1][AccessSizeIndex],
- {AddrLong, ConstantInt::get(IRB.getInt32Ty(), Exp)});
+if (ClOptimizeCallbacks) {
+  Value *Ptr8 = IRB.CreatePointerCast(Addr, Int8PtrTy);
+  Module *M = IRB.GetInsertBlock()->getParent()->getParent();
+  IRB.CreateCall(
+  Intrinsic::getDeclaration(M, Intrinsic::asan_check_memaccess),
+  {Ptr8, ConstantInt::get(IRB.getInt8Ty(), IsWrite),
+   ConstantInt::get(IRB.getInt8Ty(), AccessSizeIndex)});
+} else {
+  if (Exp == 0)
+IRB.CreateCall(AsanMemoryAccessCallback[IsWrite][0][AccessSizeIndex],
+   AddrLong);
+  else
+IRB.CreateCall(AsanMemoryAccessCallback[IsWrite][1][AccessSizeIndex],
+   {AddrLong, ConstantInt::get(IRB.getInt32Ty(), Exp)});
+}
 return;
   }
 
Index: llvm/include/llvm/Transforms/Instrumentation/AddressSanitizerCommon.h
===
--- llvm/include/llvm/Transforms/Instrumentation/AddressSanitizerCommon.h
+++ llvm/include/llvm/Transforms/Instrumentation/AddressSanitizerCommon.h
@@ -87,6 +87,8 @@
   return true;
 }
 
+void getASanShadowMapping(int *Scale, uint64_t *Offset, bool *OrShadowOffset);
+
 } // namespace llvm
 
 #endif
Index: llvm/include/llvm/Transforms/Instrumentation/AddressSanitizer.h
===
--- llvm/include/llvm/Transforms/Instrumentation/AddressSanitizer.h
+++ llvm/include/llvm/Transforms/Instrumentation/AddressSanitizer.h
@@ -147,6 +147,10 @@
 bool UseOdrIndicator = true,
 AsanDtorKind DestructorKind = AsanDtorKind::Global);
 
+// Get

[PATCH] D107850: [asan] Implemented custom calling convention similar to the one used by HWASan for X86.

[Vitaly Buka via Phabricator via cfe-commits]

vitalybuka added a comment.

In D107850#2952641 , @kstoimenov 
wrote:

> I know it seems redundant to pass the constants with every function call, but 
> otherwise the code generation code will have to take dependency on 
> AddressSanitizerCommon.h, which I am not sure is ideal. I spent some time 
> looking into it and > becomes quite messy. For example the tests now need a 
> way to set the values for those variables. I think the main downside of this 
> approach is the bloat in the IR code, but it is cleaner than exposing 
> internal asan details.

Bloat in IR is bigger concert than include of AddressSanitizerCommon.h. And I 
don't see anything messy about that.
Similar AArch64/AArch64AsmPrinter.cpp does not hesitate to #include 
"llvm/Transforms/Instrumentation/HWAddressSanitizer.h"

> One other option I have looked into is to pass this info using the Module. 
> For example using the addModuleFlag function, but again there is a problem of 
> the tests. We could have a quick chat to discuss this if you want.

It will extend the language, we should try to avoid that if possible. So far 
all values directly calculated from target triple.


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[PATCH] D107850: [asan] Implemented custom calling convention similar to the one used by HWASan for X86.

[Kirill Stoimenov via Phabricator via cfe-commits]

kstoimenov added a comment.

I know it seems redundant to pass the constants with every function call, but 
otherwise the code generation code will have to take dependency on 
AddressSanitizerCommon.h, which I am not sure is ideal. I spent some time 
looking into it and becomes quite messy. For example the tests now need a way 
to set the values for those variables. I think the main downside of this 
approach is the bloat in the IR code, but it is cleaner than exposing internal 
asan details.

One other option I have looked into is to pass this info using the Module. For 
example using the addModuleFlag function, but again there is a problem of the 
tests. We could have a quick chat to discuss this if you want.




Comment at: llvm/lib/Target/X86/X86MCInstLower.cpp:1334
+
+  unsigned Reg = MI.getOperand(0).getReg().id();
+  uint64_t ShadowBase = MI.getOperand(1).getImm();

vitalybuka wrote:
> Why this called reg when it's address?
Because it is the id of the register which is used to pass the address. For 
example for X86::RDI it will be 53. 


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[PATCH] D107850: [asan] Implemented custom calling convention similar to the one used by HWASan for X86.

[Kirill Stoimenov via Phabricator via cfe-commits]

kstoimenov updated this revision to Diff 367013.
kstoimenov added a comment.

Removed unused include.


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Files:
  llvm/include/llvm/IR/Intrinsics.td
  llvm/lib/Target/X86/X86AsmPrinter.cpp
  llvm/lib/Target/X86/X86AsmPrinter.h
  llvm/lib/Target/X86/X86InstrCompiler.td
  llvm/lib/Target/X86/X86MCInstLower.cpp
  llvm/lib/Target/X86/X86RegisterInfo.td
  llvm/test/CodeGen/X86/asan-check-memaccess-add.ll
  llvm/test/CodeGen/X86/asan-check-memaccess-or.ll

Index: llvm/test/CodeGen/X86/asan-check-memaccess-or.ll
===
--- /dev/null
+++ llvm/test/CodeGen/X86/asan-check-memaccess-or.ll
@@ -0,0 +1,234 @@
+; RUN: llc < %s | FileCheck %s
+
+target triple = "x86_64-unknown-linux-gnu"
+
+define void @load1(i8* nocapture readonly %x) {
+; CHECK:  callq   __asan_check_load1_rn[[RN1:.*]]
+; CHECK:  callq   __asan_check_store1_rn[[RN1]]
+; CHECK-NEXT: retq
+  call void @llvm.asan.check.memaccess(i8* %x, i64 2147450880, i32 0,
+   i32 0, i32 3, i32 1)
+  call void @llvm.asan.check.memaccess(i8* %x, i64 2147450880, i32 1,
+   i32 0, i32 3, i32 1)
+  ret void
+}
+
+define void @load2(i16* nocapture readonly %x) {
+; CHECK:  callq   __asan_check_load2_rn[[RN2:.*]]
+; CHECK:  callq   __asan_check_store2_rn[[RN2]]
+; CHECK-NEXT: retq
+  %1 = ptrtoint i16* %x to i64
+  %2 = bitcast i16* %x to i8*
+  call void @llvm.asan.check.memaccess(i8* %2, i64 2147450880, i32 0,
+   i32 1, i32 3, i32 1)
+  call void @llvm.asan.check.memaccess(i8* %2, i64 2147450880, i32 1,
+   i32 1, i32 3, i32 1)
+  ret void
+}
+
+define void @load4(i32* nocapture readonly %x) {
+; CHECK:  callq   __asan_check_load4_rn[[RN4:.*]]
+; CHECK:  callq   __asan_check_store4_rn[[RN4]]
+; CHECK-NEXT: retq
+  %1 = ptrtoint i32* %x to i64
+  %2 = bitcast i32* %x to i8*
+  call void @llvm.asan.check.memaccess(i8* %2, i64 2147450880, i32 0,
+   i32 2, i32 3, i32 1)
+  call void @llvm.asan.check.memaccess(i8* %2, i64 2147450880, i32 1,
+   i32 2, i32 3, i32 1)
+  ret void
+}
+define void @load8(i64* nocapture readonly %x) {
+; CHECK:  callq   __asan_check_load8_rn[[RN8:.*]]
+; CHECK:  callq   __asan_check_store8_rn[[RN8]]
+; CHECK-NEXT: retq
+  %1 = ptrtoint i64* %x to i64
+  %2 = bitcast i64* %x to i8*
+  call void @llvm.asan.check.memaccess(i8* %2, i64 2147450880, i32 0,
+   i32 3, i32 3, i32 1)
+  call void @llvm.asan.check.memaccess(i8* %2, i64 2147450880, i32 1,
+   i32 3, i32 3, i32 1)
+  ret void
+}
+
+define void @load16(i128* nocapture readonly %x) {
+; CHECK:  callq   __asan_check_load16_rn[[RN16:.*]]
+; CHECK:  callq   __asan_check_store16_rn[[RN16]]
+; CHECK-NEXT: retq
+  %1 = ptrtoint i128* %x to i64
+  %2 = bitcast i128* %x to i8*
+  call void @llvm.asan.check.memaccess(i8* %2, i64 2147450880, i32 0,
+   i32 4, i32 3, i32 1)
+  call void @llvm.asan.check.memaccess(i8* %2, i64 2147450880, i32 1,
+   i32 4, i32 3, i32 1)
+  ret void
+}
+
+; CHECK:  __asan_check_load1_rn[[RN1]]:
+; CHECK-NEXT: movq[[REG:.*]], %r8
+; CHECK-NEXT: shrq$3, %r8
+; CHECK-NEXT: orq $2147450880, %r8{{.*}}
+; CHECK-NEXT: movb(%r8), %r8b
+; CHECK-NEXT: testb   %r8b, %r8b
+; CHECK-NEXT: jne [[EXTRA:.*]]
+; CHECK-NEXT: [[RET:.*]]:
+; CHECK-NEXT: retq
+; CHECK-NEXT: [[EXTRA]]:
+; CHECK-NEXT: pushq   %rcx
+; CHECK-NEXT: movq[[REG]], %rcx
+; CHECK-NEXT: andl$7, %ecx
+; CHECK-NEXT: cmpl%r8d, %ecx
+; CHECK-NEXT: popq%rcx
+; CHECK-NEXT: jl  [[RET]]
+; CHECK-NEXT: movq[[REG:.*]], %rdi
+; CHECK-NEXT: jmp __asan_report_load1
+
+; CHECK:  __asan_check_load2_rn[[RN2]]:
+; CHECK-NEXT: movq[[REG:.*]], %r8
+; CHECK-NEXT: shrq$3, %r8
+; CHECK-NEXT: orq $2147450880, %r8{{.*}}
+; CHECK-NEXT: movb(%r8), %r8b
+; CHECK-NEXT: testb   %r8b, %r8b
+; CHECK-NEXT: jne [[EXTRA:.*]]
+; CHECK-NEXT: [[RET:.*]]:
+; CHECK-NEXT: retq
+; CHECK-NEXT: [[EXTRA]]:
+; CHECK-NEXT: pushq   %rcx
+; CHECK-NEXT: movq[[REG]], %rcx
+; CHECK-NEXT: andl$7, %ecx
+; CHECK-NEXT: addl$1, %ecx
+; CHECK-NEXT: cmpl%r8d, %ecx
+; CHECK-NEXT: popq%rcx
+; CHECK-NEXT: jl  [[RET]]
+; CHECK-NEXT: movq[[REG:

[PATCH] D107850: [asan] Implemented custom calling convention similar to the one used by HWASan for X86.

[Kirill Stoimenov via Phabricator via cfe-commits]

kstoimenov updated this revision to Diff 367011.
kstoimenov edited the summary of this revision.
kstoimenov added a comment.

Instead of packing and bit shifting arguments passing them as individual 
intrinsic arguments.


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Files:
  llvm/include/llvm/IR/Intrinsics.td
  llvm/lib/Target/X86/X86AsmPrinter.cpp
  llvm/lib/Target/X86/X86AsmPrinter.h
  llvm/lib/Target/X86/X86InstrCompiler.td
  llvm/lib/Target/X86/X86MCInstLower.cpp
  llvm/lib/Target/X86/X86RegisterInfo.td
  llvm/test/CodeGen/X86/asan-check-memaccess-add.ll
  llvm/test/CodeGen/X86/asan-check-memaccess-or.ll

Index: llvm/test/CodeGen/X86/asan-check-memaccess-or.ll
===
--- /dev/null
+++ llvm/test/CodeGen/X86/asan-check-memaccess-or.ll
@@ -0,0 +1,234 @@
+; RUN: llc < %s | FileCheck %s
+
+target triple = "x86_64-unknown-linux-gnu"
+
+define void @load1(i8* nocapture readonly %x) {
+; CHECK:  callq   __asan_check_load1_rn[[RN1:.*]]
+; CHECK:  callq   __asan_check_store1_rn[[RN1]]
+; CHECK-NEXT: retq
+  call void @llvm.asan.check.memaccess(i8* %x, i64 2147450880, i32 0,
+   i32 0, i32 3, i32 1)
+  call void @llvm.asan.check.memaccess(i8* %x, i64 2147450880, i32 1,
+   i32 0, i32 3, i32 1)
+  ret void
+}
+
+define void @load2(i16* nocapture readonly %x) {
+; CHECK:  callq   __asan_check_load2_rn[[RN2:.*]]
+; CHECK:  callq   __asan_check_store2_rn[[RN2]]
+; CHECK-NEXT: retq
+  %1 = ptrtoint i16* %x to i64
+  %2 = bitcast i16* %x to i8*
+  call void @llvm.asan.check.memaccess(i8* %2, i64 2147450880, i32 0,
+   i32 1, i32 3, i32 1)
+  call void @llvm.asan.check.memaccess(i8* %2, i64 2147450880, i32 1,
+   i32 1, i32 3, i32 1)
+  ret void
+}
+
+define void @load4(i32* nocapture readonly %x) {
+; CHECK:  callq   __asan_check_load4_rn[[RN4:.*]]
+; CHECK:  callq   __asan_check_store4_rn[[RN4]]
+; CHECK-NEXT: retq
+  %1 = ptrtoint i32* %x to i64
+  %2 = bitcast i32* %x to i8*
+  call void @llvm.asan.check.memaccess(i8* %2, i64 2147450880, i32 0,
+   i32 2, i32 3, i32 1)
+  call void @llvm.asan.check.memaccess(i8* %2, i64 2147450880, i32 1,
+   i32 2, i32 3, i32 1)
+  ret void
+}
+define void @load8(i64* nocapture readonly %x) {
+; CHECK:  callq   __asan_check_load8_rn[[RN8:.*]]
+; CHECK:  callq   __asan_check_store8_rn[[RN8]]
+; CHECK-NEXT: retq
+  %1 = ptrtoint i64* %x to i64
+  %2 = bitcast i64* %x to i8*
+  call void @llvm.asan.check.memaccess(i8* %2, i64 2147450880, i32 0,
+   i32 3, i32 3, i32 1)
+  call void @llvm.asan.check.memaccess(i8* %2, i64 2147450880, i32 1,
+   i32 3, i32 3, i32 1)
+  ret void
+}
+
+define void @load16(i128* nocapture readonly %x) {
+; CHECK:  callq   __asan_check_load16_rn[[RN16:.*]]
+; CHECK:  callq   __asan_check_store16_rn[[RN16]]
+; CHECK-NEXT: retq
+  %1 = ptrtoint i128* %x to i64
+  %2 = bitcast i128* %x to i8*
+  call void @llvm.asan.check.memaccess(i8* %2, i64 2147450880, i32 0,
+   i32 4, i32 3, i32 1)
+  call void @llvm.asan.check.memaccess(i8* %2, i64 2147450880, i32 1,
+   i32 4, i32 3, i32 1)
+  ret void
+}
+
+; CHECK:  __asan_check_load1_rn[[RN1]]:
+; CHECK-NEXT: movq[[REG:.*]], %r8
+; CHECK-NEXT: shrq$3, %r8
+; CHECK-NEXT: orq $2147450880, %r8{{.*}}
+; CHECK-NEXT: movb(%r8), %r8b
+; CHECK-NEXT: testb   %r8b, %r8b
+; CHECK-NEXT: jne [[EXTRA:.*]]
+; CHECK-NEXT: [[RET:.*]]:
+; CHECK-NEXT: retq
+; CHECK-NEXT: [[EXTRA]]:
+; CHECK-NEXT: pushq   %rcx
+; CHECK-NEXT: movq[[REG]], %rcx
+; CHECK-NEXT: andl$7, %ecx
+; CHECK-NEXT: cmpl%r8d, %ecx
+; CHECK-NEXT: popq%rcx
+; CHECK-NEXT: jl  [[RET]]
+; CHECK-NEXT: movq[[REG:.*]], %rdi
+; CHECK-NEXT: jmp __asan_report_load1
+
+; CHECK:  __asan_check_load2_rn[[RN2]]:
+; CHECK-NEXT: movq[[REG:.*]], %r8
+; CHECK-NEXT: shrq$3, %r8
+; CHECK-NEXT: orq $2147450880, %r8{{.*}}
+; CHECK-NEXT: movb(%r8), %r8b
+; CHECK-NEXT: testb   %r8b, %r8b
+; CHECK-NEXT: jne [[EXTRA:.*]]
+; CHECK-NEXT: [[RET:.*]]:
+; CHECK-NEXT: retq
+; CHECK-NEXT: [[EXTRA]]:
+; CHECK-NEXT: pushq   %rcx
+; CHECK-NEXT: movq[[REG]], %rcx
+; CHECK-NEXT: andl$7, %ecx
+; CHECK-NEXT: addl$1, %ecx
+; CHECK-NEXT: cmpl%r8d

[PATCH] D107850: [asan] Implemented custom calling convention similar to the one used by HWASan for X86.

[Kirill Stoimenov via Phabricator via cfe-commits]

kstoimenov added a comment.

Never mind, this won't compile. Let me fix it and I will let you know when it 
is ready for review.


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[PATCH] D107850: [asan] Implemented custom calling convention similar to the one used by HWASan for X86.

[Kirill Stoimenov via Phabricator via cfe-commits]

kstoimenov added a comment.

Amended this patch to be the x86 only patch. PTAL.

In D107850#2949939 , @vitalybuka 
wrote:

> This can be split into 3 patches in the following order:
>
> 1. x86
> 2. Instrumentation
> 3. clang
>
> Each of them needs tests, Instrumentation changes are not tested.




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[PATCH] D107850: [asan] Implemented custom calling convention similar to the one used by HWASan for X86.

[Kirill Stoimenov via Phabricator via cfe-commits]

kstoimenov updated this revision to Diff 366970.
kstoimenov retitled this revision from "[asan] Implemented custom calling 
convention similar to the one used by HWASan for X86. " to "[asan] Implemented 
custom calling convention similar to the one used by HWASan for X86.".
kstoimenov added a comment.

X86 only patch.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D107850/new/

https://reviews.llvm.org/D107850

Files:
  llvm/include/llvm/IR/Intrinsics.td
  llvm/lib/Target/X86/X86AsmPrinter.cpp
  llvm/lib/Target/X86/X86AsmPrinter.h
  llvm/lib/Target/X86/X86InstrCompiler.td
  llvm/lib/Target/X86/X86MCInstLower.cpp
  llvm/lib/Target/X86/X86RegisterInfo.td
  llvm/test/CodeGen/X86/asan-check-memaccess-add.ll
  llvm/test/CodeGen/X86/asan-check-memaccess-or.ll

Index: llvm/test/CodeGen/X86/asan-check-memaccess-or.ll
===
--- /dev/null
+++ llvm/test/CodeGen/X86/asan-check-memaccess-or.ll
@@ -0,0 +1,223 @@
+; RUN: llc < %s | FileCheck %s
+
+target triple = "x86_64-unknown-linux-gnu"
+
+define void @load1(i8* nocapture readonly %x) {
+; CHECK:  callq   __asan_check_load1_rn[[RN1:.*]]
+; CHECK:  callq   __asan_check_store1_rn[[RN1]]
+; CHECK-NEXT: retq
+  call void @llvm.asan.check.memaccess(i8* %x, i64 2147450880, i32 608)
+  call void @llvm.asan.check.memaccess(i8* %x, i64 2147450880, i32 624)
+  ret void
+}
+
+define void @load2(i16* nocapture readonly %x) {
+; CHECK:  callq   __asan_check_load2_rn[[RN2:.*]]
+; CHECK:  callq   __asan_check_store2_rn[[RN2]]
+; CHECK-NEXT: retq
+  %1 = ptrtoint i16* %x to i64
+  %2 = bitcast i16* %x to i8*
+  call void @llvm.asan.check.memaccess(i8* %2, i64 2147450880, i32 609)
+  call void @llvm.asan.check.memaccess(i8* %2, i64 2147450880, i32 625)
+  ret void
+}
+
+define void @load4(i32* nocapture readonly %x) {
+; CHECK:  callq   __asan_check_load4_rn[[RN4:.*]]
+; CHECK:  callq   __asan_check_store4_rn[[RN4]]
+; CHECK-NEXT: retq
+  %1 = ptrtoint i32* %x to i64
+  %2 = bitcast i32* %x to i8*
+  call void @llvm.asan.check.memaccess(i8* %2, i64 2147450880, i32 610)
+  call void @llvm.asan.check.memaccess(i8* %2, i64 2147450880, i32 626)
+  ret void
+}
+define void @load8(i64* nocapture readonly %x) {
+; CHECK:  callq   __asan_check_load8_rn[[RN8:.*]]
+; CHECK:  callq   __asan_check_store8_rn[[RN8]]
+; CHECK-NEXT: retq
+  %1 = ptrtoint i64* %x to i64
+  %2 = bitcast i64* %x to i8*
+  call void @llvm.asan.check.memaccess(i8* %2, i64 2147450880, i32 611)
+  call void @llvm.asan.check.memaccess(i8* %2, i64 2147450880, i32 627)
+  ret void
+}
+
+define void @load16(i128* nocapture readonly %x) {
+; CHECK:  callq   __asan_check_load16_rn[[RN16:.*]]
+; CHECK:  callq   __asan_check_store16_rn[[RN16]]
+; CHECK-NEXT: retq
+  %1 = ptrtoint i128* %x to i64
+  %2 = bitcast i128* %x to i8*
+  call void @llvm.asan.check.memaccess(i8* %2, i64 2147450880, i32 612)
+  call void @llvm.asan.check.memaccess(i8* %2, i64 2147450880, i32 628)
+  ret void
+}
+
+; CHECK:  __asan_check_load1_rn[[RN1]]:
+; CHECK-NEXT: movq[[REG:.*]], %r8
+; CHECK-NEXT: shrq$3, %r8
+; CHECK-NEXT: orq $2147450880, %r8
+; CHECK-NEXT: movb(%r8), %r8b
+; CHECK-NEXT: testb   %r8b, %r8b
+; CHECK-NEXT: jne [[EXTRA:.*]]
+; CHECK-NEXT: [[RET:.*]]:
+; CHECK-NEXT: retq
+; CHECK-NEXT: [[EXTRA]]:
+; CHECK-NEXT: pushq   %rcx
+; CHECK-NEXT: movq[[REG]], %rcx
+; CHECK-NEXT: andl$7, %ecx
+; CHECK-NEXT: cmpl%r8d, %ecx
+; CHECK-NEXT: popq%rcx
+; CHECK-NEXT: jl  [[RET]]
+; CHECK-NEXT: movq[[REG:.*]], %rdi
+; CHECK-NEXT: jmp __asan_report_load1
+
+; CHECK:  __asan_check_load2_rn[[RN2]]:
+; CHECK-NEXT: movq[[REG:.*]], %r8
+; CHECK-NEXT: shrq$3, %r8
+; CHECK-NEXT: orq $2147450880, %r8
+; CHECK-NEXT: movb(%r8), %r8b
+; CHECK-NEXT: testb   %r8b, %r8b
+; CHECK-NEXT: jne [[EXTRA:.*]]
+; CHECK-NEXT: [[RET:.*]]:
+; CHECK-NEXT: retq
+; CHECK-NEXT: [[EXTRA]]:
+; CHECK-NEXT: pushq   %rcx
+; CHECK-NEXT: movq[[REG]], %rcx
+; CHECK-NEXT: andl$7, %ecx
+; CHECK-NEXT: addl$1, %ecx
+; CHECK-NEXT: cmpl%r8d, %ecx
+; CHECK-NEXT: popq%rcx
+; CHECK-NEXT: jl  [[RET]]
+; CHECK-NEXT: movq[[REG:.*]], %rdi
+; CHECK-NEXT: jmp __asan_report_load2
+
+; CHECK:  __asan_check_load4_rn[[RN4]]:
+; CHECK-NEXT: movq[[REG:.*]], %r8
+; CHECK-NEXT: shrq$3, %r8
+; CHECK-NEXT: orq $2147450880, %r8
+; CHECK-NEXT: movb(%r8), %r8b
+; CHECK-NEXT: testb   %r8b, %r8b
+; CHECK-NEXT: jne [[EXTRA:.*]]
+; CHECK-NEX

[PATCH] D107850: [asan] Implemented custom calling convention similar to the one used by HWASan for X86.

[Vitaly Buka via Phabricator via cfe-commits]

vitalybuka added a comment.

This can be split into 3 patches in the following order:

1. x86
2. Instrumentation
3. clang

Each of them needs tests, Intrtumentation changes are not tested.




Comment at: llvm/include/llvm/Transforms/Instrumentation/AddressSanitizer.h:150
 
+namespace AsanAccessInfo {
+

It's not how enums described here 
https://llvm.org/docs/CodingStandards.html#id43
Also it's common to use enum class nowerdays.


However this one does not need to be enum and just "constexpr size_t"


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D107850/new/

https://reviews.llvm.org/D107850

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