[PATCH] D108624: [Clang][RISCV] Implement getConstraintRegister for RISC-V

[Luís Marques via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG34e055d33e37: [Clang][RISCV] Implement getConstraintRegister 
for RISC-V (authored by luismarques).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D108624/new/

https://reviews.llvm.org/D108624

Files:
  clang/lib/Basic/Targets/RISCV.h
  clang/test/Sema/inline-asm-validate-riscv.c


Index: clang/test/Sema/inline-asm-validate-riscv.c
===
--- clang/test/Sema/inline-asm-validate-riscv.c
+++ clang/test/Sema/inline-asm-validate-riscv.c
@@ -21,3 +21,11 @@
   asm volatile ("" :: "K"(BelowMin)); // expected-error{{value '-1' out of 
range for constraint 'K'}}
   asm volatile ("" :: "K"(AboveMax)); // expected-error{{value '32' out of 
range for constraint 'K'}}
 }
+
+void test_clobber_conflict(void) {
+  register long x10 asm("x10");
+  asm volatile("" :: "r"(x10) : "x10"); // expected-error {{conflicts with asm 
clobber list}}
+  asm volatile("" :: "r"(x10) : "a0"); // expected-error {{conflicts with asm 
clobber list}}
+  asm volatile("" : "=r"(x10) :: "x10"); // expected-error {{conflicts with 
asm clobber list}}
+  asm volatile("" : "=r"(x10) :: "a0"); // expected-error {{conflicts with asm 
clobber list}}
+}
Index: clang/lib/Basic/Targets/RISCV.h
===
--- clang/lib/Basic/Targets/RISCV.h
+++ clang/lib/Basic/Targets/RISCV.h
@@ -82,6 +82,11 @@
 
   const char *getClobbers() const override { return ""; }
 
+  StringRef getConstraintRegister(StringRef Constraint,
+  StringRef Expression) const override {
+return Expression;
+  }
+
   ArrayRef getGCCRegNames() const override;
 
   int getEHDataRegisterNumber(unsigned RegNo) const override {


Index: clang/test/Sema/inline-asm-validate-riscv.c
===
--- clang/test/Sema/inline-asm-validate-riscv.c
+++ clang/test/Sema/inline-asm-validate-riscv.c
@@ -21,3 +21,11 @@
   asm volatile ("" :: "K"(BelowMin)); // expected-error{{value '-1' out of range for constraint 'K'}}
   asm volatile ("" :: "K"(AboveMax)); // expected-error{{value '32' out of range for constraint 'K'}}
 }
+
+void test_clobber_conflict(void) {
+  register long x10 asm("x10");
+  asm volatile("" :: "r"(x10) : "x10"); // expected-error {{conflicts with asm clobber list}}
+  asm volatile("" :: "r"(x10) : "a0"); // expected-error {{conflicts with asm clobber list}}
+  asm volatile("" : "=r"(x10) :: "x10"); // expected-error {{conflicts with asm clobber list}}
+  asm volatile("" : "=r"(x10) :: "a0"); // expected-error {{conflicts with asm clobber list}}
+}
Index: clang/lib/Basic/Targets/RISCV.h
===
--- clang/lib/Basic/Targets/RISCV.h
+++ clang/lib/Basic/Targets/RISCV.h
@@ -82,6 +82,11 @@
 
   const char *getClobbers() const override { return ""; }
 
+  StringRef getConstraintRegister(StringRef Constraint,
+  StringRef Expression) const override {
+return Expression;
+  }
+
   ArrayRef getGCCRegNames() const override;
 
   int getEHDataRegisterNumber(unsigned RegNo) const override {
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D108624: [Clang][RISCV] Implement getConstraintRegister for RISC-V

[Alex Bradbury via Phabricator via cfe-commits]

asb accepted this revision.
asb added a comment.
This revision is now accepted and ready to land.

Looks good to me - I'm surprised only Arm, AArch64, and X86 implement this!


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D108624/new/

https://reviews.llvm.org/D108624

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D108624: [Clang][RISCV] Implement getConstraintRegister for RISC-V

[Luís Marques via Phabricator via cfe-commits]

luismarques added inline comments.



Comment at: clang/test/Sema/inline-asm-validate-riscv.c:27-28
+  register long x10 asm("x10");
+  asm volatile("" :: "r"(x10) : "x10"); // expected-error {{conflicts with asm 
clobber list}}
+  asm volatile("" :: "r"(x10) : "a0"); // expected-error {{conflicts with asm 
clobber list}}
+  asm volatile("" : "=r"(x10) :: "x10"); // expected-error {{conflicts with 
asm clobber list}}

I don't really understand the point of erroring-out in these two cases where 
the register is an input and is also clobbered. In fact, I've run into a case 
where that would be useful and accurately reflected the situation. But GCC's 
documentation explicitly prohibits that. I'm not sure if there's a fundamental 
reason for that, or if it's just an implementation quirk.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D108624/new/

https://reviews.llvm.org/D108624

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D108624: [Clang][RISCV] Implement getConstraintRegister for RISC-V

[Luís Marques via Phabricator via cfe-commits]

luismarques updated this revision to Diff 368323.
luismarques added a comment.

Nit: remove nop.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D108624/new/

https://reviews.llvm.org/D108624

Files:
  clang/lib/Basic/Targets/RISCV.h
  clang/test/Sema/inline-asm-validate-riscv.c


Index: clang/test/Sema/inline-asm-validate-riscv.c
===
--- clang/test/Sema/inline-asm-validate-riscv.c
+++ clang/test/Sema/inline-asm-validate-riscv.c
@@ -21,3 +21,11 @@
   asm volatile ("" :: "K"(BelowMin)); // expected-error{{value '-1' out of 
range for constraint 'K'}}
   asm volatile ("" :: "K"(AboveMax)); // expected-error{{value '32' out of 
range for constraint 'K'}}
 }
+
+void test_clobber_conflict(void) {
+  register long x10 asm("x10");
+  asm volatile("" :: "r"(x10) : "x10"); // expected-error {{conflicts with asm 
clobber list}}
+  asm volatile("" :: "r"(x10) : "a0"); // expected-error {{conflicts with asm 
clobber list}}
+  asm volatile("" : "=r"(x10) :: "x10"); // expected-error {{conflicts with 
asm clobber list}}
+  asm volatile("" : "=r"(x10) :: "a0"); // expected-error {{conflicts with asm 
clobber list}}
+}
Index: clang/lib/Basic/Targets/RISCV.h
===
--- clang/lib/Basic/Targets/RISCV.h
+++ clang/lib/Basic/Targets/RISCV.h
@@ -82,6 +82,11 @@
 
   const char *getClobbers() const override { return ""; }
 
+  StringRef getConstraintRegister(StringRef Constraint,
+  StringRef Expression) const override {
+return Expression;
+  }
+
   ArrayRef getGCCRegNames() const override;
 
   int getEHDataRegisterNumber(unsigned RegNo) const override {


Index: clang/test/Sema/inline-asm-validate-riscv.c
===
--- clang/test/Sema/inline-asm-validate-riscv.c
+++ clang/test/Sema/inline-asm-validate-riscv.c
@@ -21,3 +21,11 @@
   asm volatile ("" :: "K"(BelowMin)); // expected-error{{value '-1' out of range for constraint 'K'}}
   asm volatile ("" :: "K"(AboveMax)); // expected-error{{value '32' out of range for constraint 'K'}}
 }
+
+void test_clobber_conflict(void) {
+  register long x10 asm("x10");
+  asm volatile("" :: "r"(x10) : "x10"); // expected-error {{conflicts with asm clobber list}}
+  asm volatile("" :: "r"(x10) : "a0"); // expected-error {{conflicts with asm clobber list}}
+  asm volatile("" : "=r"(x10) :: "x10"); // expected-error {{conflicts with asm clobber list}}
+  asm volatile("" : "=r"(x10) :: "a0"); // expected-error {{conflicts with asm clobber list}}
+}
Index: clang/lib/Basic/Targets/RISCV.h
===
--- clang/lib/Basic/Targets/RISCV.h
+++ clang/lib/Basic/Targets/RISCV.h
@@ -82,6 +82,11 @@
 
   const char *getClobbers() const override { return ""; }
 
+  StringRef getConstraintRegister(StringRef Constraint,
+  StringRef Expression) const override {
+return Expression;
+  }
+
   ArrayRef getGCCRegNames() const override;
 
   int getEHDataRegisterNumber(unsigned RegNo) const override {
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D108624: [Clang][RISCV] Implement getConstraintRegister for RISC-V

[Luís Marques via Phabricator via cfe-commits]

luismarques created this revision.
luismarques added reviewers: asb, thopre.
Herald added subscribers: vkmr, frasercrmck, evandro, apazos, sameer.abuasal, 
s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, 
rogfer01, edward-jones, zzheng, jrtc27, shiva0217, kito-cheng, niosHD, 
sabuasal, simoncook, johnrusso, rbar.
luismarques requested review of this revision.
Herald added subscribers: cfe-commits, MaskRay.
Herald added a project: clang.

The getConstraintRegister method is used by semantic checking of inline 
assembly statements in order to diagnose conflicts between clobber list and 
input/output lists. By overriding getConstraintRegister we get those 
diagnostics and we match RISC-V GCC's behavior. The implementation is trivial 
due to the lack of single-register RISC-V-specific constraints.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D108624

Files:
  clang/lib/Basic/Targets/RISCV.h
  clang/test/Sema/inline-asm-validate-riscv.c


Index: clang/test/Sema/inline-asm-validate-riscv.c
===
--- clang/test/Sema/inline-asm-validate-riscv.c
+++ clang/test/Sema/inline-asm-validate-riscv.c
@@ -21,3 +21,11 @@
   asm volatile ("" :: "K"(BelowMin)); // expected-error{{value '-1' out of 
range for constraint 'K'}}
   asm volatile ("" :: "K"(AboveMax)); // expected-error{{value '32' out of 
range for constraint 'K'}}
 }
+
+void test_clobber_conflict(void) {
+  register long x10 asm("x10");
+  asm volatile("nop" :: "r"(x10) : "x10"); // expected-error {{conflicts with 
asm clobber list}}
+  asm volatile("nop" :: "r"(x10) : "a0"); // expected-error {{conflicts with 
asm clobber list}}
+  asm volatile("nop" : "=r"(x10) :: "x10"); // expected-error {{conflicts with 
asm clobber list}}
+  asm volatile("nop" : "=r"(x10) :: "a0"); // expected-error {{conflicts with 
asm clobber list}}
+}
Index: clang/lib/Basic/Targets/RISCV.h
===
--- clang/lib/Basic/Targets/RISCV.h
+++ clang/lib/Basic/Targets/RISCV.h
@@ -82,6 +82,11 @@
 
   const char *getClobbers() const override { return ""; }
 
+  StringRef getConstraintRegister(StringRef Constraint,
+  StringRef Expression) const override {
+return Expression;
+  }
+
   ArrayRef getGCCRegNames() const override;
 
   int getEHDataRegisterNumber(unsigned RegNo) const override {


Index: clang/test/Sema/inline-asm-validate-riscv.c
===
--- clang/test/Sema/inline-asm-validate-riscv.c
+++ clang/test/Sema/inline-asm-validate-riscv.c
@@ -21,3 +21,11 @@
   asm volatile ("" :: "K"(BelowMin)); // expected-error{{value '-1' out of range for constraint 'K'}}
   asm volatile ("" :: "K"(AboveMax)); // expected-error{{value '32' out of range for constraint 'K'}}
 }
+
+void test_clobber_conflict(void) {
+  register long x10 asm("x10");
+  asm volatile("nop" :: "r"(x10) : "x10"); // expected-error {{conflicts with asm clobber list}}
+  asm volatile("nop" :: "r"(x10) : "a0"); // expected-error {{conflicts with asm clobber list}}
+  asm volatile("nop" : "=r"(x10) :: "x10"); // expected-error {{conflicts with asm clobber list}}
+  asm volatile("nop" : "=r"(x10) :: "a0"); // expected-error {{conflicts with asm clobber list}}
+}
Index: clang/lib/Basic/Targets/RISCV.h
===
--- clang/lib/Basic/Targets/RISCV.h
+++ clang/lib/Basic/Targets/RISCV.h
@@ -82,6 +82,11 @@
 
   const char *getClobbers() const override { return ""; }
 
+  StringRef getConstraintRegister(StringRef Constraint,
+  StringRef Expression) const override {
+return Expression;
+  }
+
   ArrayRef getGCCRegNames() const override;
 
   int getEHDataRegisterNumber(unsigned RegNo) const override {
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits