[PATCH] D109825: [AArch64]Enabling Cortex-A510 Support

2021-10-15 Thread Sam Elliott via Phabricator via cfe-commits 
lenary added a comment.

In D109825#3066853 , @jansvoboda11 
wrote:

> This seems to be breaking the macOS bot, can you take a look? 
> https://green.lab.llvm.org/green/job/clang-stage1-RA/24735/

Will do.


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[PATCH] D109825: [AArch64]Enabling Cortex-A510 Support

2021-10-15 Thread Jan Svoboda via Phabricator via cfe-commits 
jansvoboda11 added a comment.

This seems to be breaking the macOS bot, can you take a look? 
https://green.lab.llvm.org/green/job/clang-stage1-RA/24735/


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[PATCH] D109825: [AArch64]Enabling Cortex-A510 Support

2021-10-15 Thread Sam Elliott via Phabricator via cfe-commits 
This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG97809c828f8e: [AArch64]Enabling Cortex-A510 Support 
(authored by mubashar_, committed by lenary).

Repository:
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Files:
  clang/docs/ReleaseNotes.rst
  clang/test/Driver/aarch64-cpus.c
  llvm/include/llvm/Support/AArch64TargetParser.def
  llvm/lib/Target/AArch64/AArch64.td
  llvm/lib/Target/AArch64/AArch64Subtarget.cpp
  llvm/lib/Target/AArch64/AArch64Subtarget.h
  llvm/unittests/Support/TargetParserTest.cpp

Index: llvm/unittests/Support/TargetParserTest.cpp
===
--- llvm/unittests/Support/TargetParserTest.cpp
+++ llvm/unittests/Support/TargetParserTest.cpp
@@ -898,6 +898,17 @@
  AArch64::AEK_RDM | AArch64::AEK_FP16 |
  AArch64::AEK_DOTPROD | AArch64::AEK_RCPC,
  "8.2-A"),
+ARMCPUTestParams("cortex-a510", "armv9-a", "neon-fp-armv8",
+ AArch64::AEK_CRC | AArch64::AEK_FP |
+ AArch64::AEK_SIMD | AArch64::AEK_RAS |
+ AArch64::AEK_LSE | AArch64::AEK_RDM |
+ AArch64::AEK_RCPC | AArch64::AEK_DOTPROD |
+ AArch64::AEK_SVE2 | AArch64::AEK_BF16 |
+ AArch64::AEK_I8MM | AArch64::AEK_SVE2BITPERM |
+ AArch64::AEK_PAUTH | AArch64::AEK_MTE |
+ AArch64::AEK_SSBS | AArch64::AEK_FP16FML |
+ AArch64::AEK_SB,
+ "9-A"),
 ARMCPUTestParams("cortex-a57", "armv8-a", "crypto-neon-fp-armv8",
  AArch64::AEK_CRC | AArch64::AEK_CRYPTO |
  AArch64::AEK_FP | AArch64::AEK_SIMD,
@@ -1178,7 +1189,7 @@
  AArch64::AEK_LSE | AArch64::AEK_RDM,
  "8.2-A")));
 
-static constexpr unsigned NumAArch64CPUArchs = 48;
+static constexpr unsigned NumAArch64CPUArchs = 49;
 
 TEST(TargetParserTest, testAArch64CPUArchList) {
   SmallVector List;
Index: llvm/lib/Target/AArch64/AArch64Subtarget.h
===
--- llvm/lib/Target/AArch64/AArch64Subtarget.h
+++ llvm/lib/Target/AArch64/AArch64Subtarget.h
@@ -50,6 +50,7 @@
 CortexA35,
 CortexA53,
 CortexA55,
+CortexA510,
 CortexA57,
 CortexA65,
 CortexA72,
Index: llvm/lib/Target/AArch64/AArch64Subtarget.cpp
===
--- llvm/lib/Target/AArch64/AArch64Subtarget.cpp
+++ llvm/lib/Target/AArch64/AArch64Subtarget.cpp
@@ -78,6 +78,7 @@
 break;
   case CortexA53:
   case CortexA55:
+  case CortexA510:
 PrefFunctionLogAlignment = 4;
 break;
   case CortexA57:
Index: llvm/lib/Target/AArch64/AArch64.td
===
--- llvm/lib/Target/AArch64/AArch64.td
+++ llvm/lib/Target/AArch64/AArch64.td
@@ -634,6 +634,22 @@
FeatureFuseAddress,
]>;
 
+def ProcA510: SubtargetFeature<"a510", "ARMProcFamily", "CortexA510",
+   "Cortex-A510 ARM processors", [
+   HasV9_0aOps,
+   FeatureNEON,
+   FeaturePerfMon,
+   FeatureMatMulInt8,
+   FeatureBF16,
+   FeatureAM,
+   FeatureMTE,
+   FeatureETE,
+   FeatureSVE2BitPerm,
+   FeatureFP16FML,
+   FeatureFuseAES,
+   FeaturePostRAScheduler
+   ]>;
+
 def ProcA57 : SubtargetFeature<"a57", "ARMProcFamily", "CortexA57",
"Cortex-A57 ARM processors", [
FeatureBalanceFPOps,
@@ -1190,6 +1206,7 @@
 def : ProcessorModel<"cortex-a34", CortexA53Model, [ProcA35]>;
 def : ProcessorModel<"cortex-a53", CortexA53Model, [ProcA53]>;
 def : ProcessorModel<"cortex-a55", CortexA55Model, [ProcA55]>;
+def : ProcessorModel<"cortex-a510", CortexA55Model, [ProcA510]>;
 def : ProcessorModel<"cortex-a57", CortexA57Model, [ProcA57]>;
 def : ProcessorModel<"cortex-a65", CortexA53Model, [ProcA65]>;
 def : ProcessorModel<"cortex-a65ae", CortexA53Model, [ProcA65]>;
Index: llvm/include/llvm/Support/AArch64TargetParser.def
===
---

[PATCH] D109825: [AArch64]Enabling Cortex-A510 Support

2021-10-15 Thread Sam Elliott via Phabricator via cfe-commits 
lenary added inline comments.



Comment at: clang/docs/ReleaseNotes.rst:86
 
+- Support has been added for the following processors (command-line 
identifiers in parentheses):
+  - Arm Cortex-A510 (cortex-a510)

dmgreen wrote:
> dmgreen wrote:
> > Can you add an Arm section below and move this to it.
> This still needs doing. Also please add a line to the arm section saying 
> "Added support for the Armv9-A, Armv9.1-A and Armv9.2-A architectures."
> 
> It looks like there are some llvm release notes in llvm/docs/ReleaseNotes.rst 
> too, that could have a line added.
I'll do armv9 in a separate NFC commit


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[PATCH] D109825: [AArch64]Enabling Cortex-A510 Support

2021-10-14 Thread Dave Green via Phabricator via cfe-commits 
dmgreen accepted this revision.
dmgreen added a comment.
This revision is now accepted and ready to land.

Thanks for the changes. Nice working pulling this into shape.

LGTM




Comment at: llvm/include/llvm/Support/AArch64TargetParser.def:149
+ (AArch64::AEK_BF16 | AArch64::AEK_I8MM | 
AArch64::AEK_SVE2BITPERM |
+  AArch64::AEK_PAUTH | AArch64::AEK_PAUTH | AArch64::AEK_MTE |
+  AArch64::AEK_SSBS | AArch64::AEK_SB | AArch64::AEK_FP16FML))

dmgreen wrote:
> AEK_PAUTH is twice here.
Can you make sure you remove the second PAUTH here before committing.


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[PATCH] D109825: [AArch64]Enabling Cortex-A510 Support

2021-10-14 Thread Mubashar Ahmad via Phabricator via cfe-commits 
mubashar_ marked an inline comment as done.
mubashar_ added inline comments.



Comment at: clang/docs/ReleaseNotes.rst:86
 
+- Support has been added for the following processors (command-line 
identifiers in parentheses):
+  - Arm Cortex-A510 (cortex-a510)

dmgreen wrote:
> dmgreen wrote:
> > Can you add an Arm section below and move this to it.
> This still needs doing. Also please add a line to the arm section saying 
> "Added support for the Armv9-A, Armv9.1-A and Armv9.2-A architectures."
> 
> It looks like there are some llvm release notes in llvm/docs/ReleaseNotes.rst 
> too, that could have a line added.
I didn't add support for these architectures. This may already be in its own 
commit.


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[PATCH] D109825: [AArch64]Enabling Cortex-A510 Support

2021-10-14 Thread Mubashar Ahmad via Phabricator via cfe-commits 
mubashar_ updated this revision to Diff 379717.
mubashar_ marked an inline comment as done.
mubashar_ added a comment.

Corrected PAUTH duplication mistake.


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Files:
  clang/docs/ReleaseNotes.rst
  clang/test/Driver/aarch64-cpus.c
  llvm/include/llvm/Support/AArch64TargetParser.def
  llvm/lib/Target/AArch64/AArch64.td
  llvm/lib/Target/AArch64/AArch64Subtarget.cpp
  llvm/lib/Target/AArch64/AArch64Subtarget.h
  llvm/unittests/Support/TargetParserTest.cpp

Index: llvm/unittests/Support/TargetParserTest.cpp
===
--- llvm/unittests/Support/TargetParserTest.cpp
+++ llvm/unittests/Support/TargetParserTest.cpp
@@ -898,6 +898,17 @@
  AArch64::AEK_RDM | AArch64::AEK_FP16 |
  AArch64::AEK_DOTPROD | AArch64::AEK_RCPC,
  "8.2-A"),
+ARMCPUTestParams("cortex-a510", "armv9-a", "neon-fp-armv8",
+ AArch64::AEK_CRC | AArch64::AEK_FP |
+ AArch64::AEK_SIMD | AArch64::AEK_RAS |
+ AArch64::AEK_LSE | AArch64::AEK_RDM |
+ AArch64::AEK_RCPC | AArch64::AEK_DOTPROD |
+ AArch64::AEK_SVE2 | AArch64::AEK_BF16 |
+ AArch64::AEK_I8MM | AArch64::AEK_SVE2BITPERM |
+ AArch64::AEK_PAUTH | AArch64::AEK_MTE |
+ AArch64::AEK_SSBS | AArch64::AEK_FP16FML |
+ AArch64::AEK_SB,
+ "9-A"),
 ARMCPUTestParams("cortex-a57", "armv8-a", "crypto-neon-fp-armv8",
  AArch64::AEK_CRC | AArch64::AEK_CRYPTO |
  AArch64::AEK_FP | AArch64::AEK_SIMD,
@@ -1178,7 +1189,7 @@
  AArch64::AEK_LSE | AArch64::AEK_RDM,
  "8.2-A")));
 
-static constexpr unsigned NumAArch64CPUArchs = 48;
+static constexpr unsigned NumAArch64CPUArchs = 49;
 
 TEST(TargetParserTest, testAArch64CPUArchList) {
   SmallVector List;
Index: llvm/lib/Target/AArch64/AArch64Subtarget.h
===
--- llvm/lib/Target/AArch64/AArch64Subtarget.h
+++ llvm/lib/Target/AArch64/AArch64Subtarget.h
@@ -50,6 +50,7 @@
 CortexA35,
 CortexA53,
 CortexA55,
+CortexA510,
 CortexA57,
 CortexA65,
 CortexA72,
Index: llvm/lib/Target/AArch64/AArch64Subtarget.cpp
===
--- llvm/lib/Target/AArch64/AArch64Subtarget.cpp
+++ llvm/lib/Target/AArch64/AArch64Subtarget.cpp
@@ -78,6 +78,7 @@
 break;
   case CortexA53:
   case CortexA55:
+  case CortexA510:
 PrefFunctionLogAlignment = 4;
 break;
   case CortexA57:
Index: llvm/lib/Target/AArch64/AArch64.td
===
--- llvm/lib/Target/AArch64/AArch64.td
+++ llvm/lib/Target/AArch64/AArch64.td
@@ -630,6 +630,22 @@
FeatureFuseAddress,
]>;
 
+def ProcA510: SubtargetFeature<"a510", "ARMProcFamily", "CortexA510",
+   "Cortex-A510 ARM processors", [
+   HasV9_0aOps,
+   FeatureNEON,
+   FeaturePerfMon,
+   FeatureMatMulInt8,
+   FeatureBF16,
+   FeatureAM,
+   FeatureMTE,
+   FeatureETE,
+   FeatureSVE2BitPerm,
+   FeatureFP16FML,
+   FeatureFuseAES,
+   FeaturePostRAScheduler
+   ]>;
+
 def ProcA57 : SubtargetFeature<"a57", "ARMProcFamily", "CortexA57",
"Cortex-A57 ARM processors", [
FeatureBalanceFPOps,
@@ -1186,6 +1202,7 @@
 def : ProcessorModel<"cortex-a34", CortexA53Model, [ProcA35]>;
 def : ProcessorModel<"cortex-a53", CortexA53Model, [ProcA53]>;
 def : ProcessorModel<"cortex-a55", CortexA55Model, [ProcA55]>;
+def : ProcessorModel<"cortex-a510", CortexA55Model, [ProcA510]>;
 def : ProcessorModel<"cortex-a57", CortexA57Model, [ProcA57]>;
 def : ProcessorModel<"cortex-a65", CortexA53Model, [ProcA65]>;
 def : ProcessorModel<"cortex-a65ae", CortexA53Model, [ProcA65]>;
Index: llvm/include/llvm/Support/AArch64TargetParser.def
===
--- llvm/include/llvm/Support/AArch64TargetParser.def
+++ llvm/include/llvm/Support/AArch64TargetParser.def
@@ -144,6 +144,10 @@
  (AArch64::AEK_CRC))

[PATCH] D109825: [AArch64]Enabling Cortex-A510 Support

2021-10-14 Thread Mubashar Ahmad via Phabricator via cfe-commits 
mubashar_ updated this revision to Diff 379713.
mubashar_ marked 2 inline comments as done.
mubashar_ added a comment.

Added crypto and no-crypto tests for -mcpu and added new section for Arm and 
AArch64 support in release notes.


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Files:
  clang/docs/ReleaseNotes.rst
  clang/test/Driver/aarch64-cpus.c
  llvm/include/llvm/Support/AArch64TargetParser.def
  llvm/lib/Target/AArch64/AArch64.td
  llvm/lib/Target/AArch64/AArch64Subtarget.cpp
  llvm/lib/Target/AArch64/AArch64Subtarget.h
  llvm/unittests/Support/TargetParserTest.cpp

Index: llvm/unittests/Support/TargetParserTest.cpp
===
--- llvm/unittests/Support/TargetParserTest.cpp
+++ llvm/unittests/Support/TargetParserTest.cpp
@@ -898,6 +898,17 @@
  AArch64::AEK_RDM | AArch64::AEK_FP16 |
  AArch64::AEK_DOTPROD | AArch64::AEK_RCPC,
  "8.2-A"),
+ARMCPUTestParams("cortex-a510", "armv9-a", "neon-fp-armv8",
+ AArch64::AEK_CRC | AArch64::AEK_FP |
+ AArch64::AEK_SIMD | AArch64::AEK_RAS |
+ AArch64::AEK_LSE | AArch64::AEK_RDM |
+ AArch64::AEK_RCPC | AArch64::AEK_DOTPROD |
+ AArch64::AEK_SVE2 | AArch64::AEK_BF16 |
+ AArch64::AEK_I8MM | AArch64::AEK_SVE2BITPERM |
+ AArch64::AEK_PAUTH | AArch64::AEK_MTE |
+ AArch64::AEK_SSBS | AArch64::AEK_FP16FML |
+ AArch64::AEK_SB,
+ "9-A"),
 ARMCPUTestParams("cortex-a57", "armv8-a", "crypto-neon-fp-armv8",
  AArch64::AEK_CRC | AArch64::AEK_CRYPTO |
  AArch64::AEK_FP | AArch64::AEK_SIMD,
@@ -1178,7 +1189,7 @@
  AArch64::AEK_LSE | AArch64::AEK_RDM,
  "8.2-A")));
 
-static constexpr unsigned NumAArch64CPUArchs = 48;
+static constexpr unsigned NumAArch64CPUArchs = 49;
 
 TEST(TargetParserTest, testAArch64CPUArchList) {
   SmallVector List;
Index: llvm/lib/Target/AArch64/AArch64Subtarget.h
===
--- llvm/lib/Target/AArch64/AArch64Subtarget.h
+++ llvm/lib/Target/AArch64/AArch64Subtarget.h
@@ -50,6 +50,7 @@
 CortexA35,
 CortexA53,
 CortexA55,
+CortexA510,
 CortexA57,
 CortexA65,
 CortexA72,
Index: llvm/lib/Target/AArch64/AArch64Subtarget.cpp
===
--- llvm/lib/Target/AArch64/AArch64Subtarget.cpp
+++ llvm/lib/Target/AArch64/AArch64Subtarget.cpp
@@ -78,6 +78,7 @@
 break;
   case CortexA53:
   case CortexA55:
+  case CortexA510:
 PrefFunctionLogAlignment = 4;
 break;
   case CortexA57:
Index: llvm/lib/Target/AArch64/AArch64.td
===
--- llvm/lib/Target/AArch64/AArch64.td
+++ llvm/lib/Target/AArch64/AArch64.td
@@ -630,6 +630,22 @@
FeatureFuseAddress,
]>;
 
+def ProcA510: SubtargetFeature<"a510", "ARMProcFamily", "CortexA510",
+   "Cortex-A510 ARM processors", [
+   HasV9_0aOps,
+   FeatureNEON,
+   FeaturePerfMon,
+   FeatureMatMulInt8,
+   FeatureBF16,
+   FeatureAM,
+   FeatureMTE,
+   FeatureETE,
+   FeatureSVE2BitPerm,
+   FeatureFP16FML,
+   FeatureFuseAES,
+   FeaturePostRAScheduler
+   ]>;
+
 def ProcA57 : SubtargetFeature<"a57", "ARMProcFamily", "CortexA57",
"Cortex-A57 ARM processors", [
FeatureBalanceFPOps,
@@ -1186,6 +1202,7 @@
 def : ProcessorModel<"cortex-a34", CortexA53Model, [ProcA35]>;
 def : ProcessorModel<"cortex-a53", CortexA53Model, [ProcA53]>;
 def : ProcessorModel<"cortex-a55", CortexA55Model, [ProcA55]>;
+def : ProcessorModel<"cortex-a510", CortexA55Model, [ProcA510]>;
 def : ProcessorModel<"cortex-a57", CortexA57Model, [ProcA57]>;
 def : ProcessorModel<"cortex-a65", CortexA53Model, [ProcA65]>;
 def : ProcessorModel<"cortex-a65ae", CortexA53Model, [ProcA65]>;
Index: llvm/include/llvm/Support/AArch64TargetParser.def
===
--- llvm/include/llvm/Support/AArch64TargetParser.def
+++

[PATCH] D109825: [AArch64]Enabling Cortex-A510 Support

2021-10-14 Thread Dave Green via Phabricator via cfe-commits 
dmgreen added a comment.

In D109825#3060796 , @mubashar_ wrote:

> Added crypto and non-crypto related tests for mcpu in aarch64-cpus.c

Thanks, but did this change miss being updated in the review?




Comment at: clang/docs/ReleaseNotes.rst:86
 
+- Support has been added for the following processors (command-line 
identifiers in parentheses):
+  - Arm Cortex-A510 (cortex-a510)

dmgreen wrote:
> Can you add an Arm section below and move this to it.
This still needs doing. Also please add a line to the arm section saying "Added 
support for the Armv9-A, Armv9.1-A and Armv9.2-A architectures."

It looks like there are some llvm release notes in llvm/docs/ReleaseNotes.rst 
too, that could have a line added.



Comment at: llvm/include/llvm/Support/AArch64TargetParser.def:149
+ (AArch64::AEK_BF16 | AArch64::AEK_I8MM | 
AArch64::AEK_SVE2BITPERM |
+  AArch64::AEK_PAUTH | AArch64::AEK_PAUTH | AArch64::AEK_MTE |
+  AArch64::AEK_SSBS | AArch64::AEK_SB | AArch64::AEK_FP16FML))

AEK_PAUTH is twice here.


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[PATCH] D109825: [AArch64]Enabling Cortex-A510 Support

2021-10-13 Thread Mubashar Ahmad via Phabricator via cfe-commits 
mubashar_ updated this revision to Diff 379321.
mubashar_ added a comment.

Added crypto and non-crypto related tests for mcpu in aarch64-cpus.c


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Files:
  clang/docs/ReleaseNotes.rst
  clang/test/Driver/aarch64-cpus.c
  llvm/include/llvm/Support/AArch64TargetParser.def
  llvm/lib/Target/AArch64/AArch64.td
  llvm/lib/Target/AArch64/AArch64Subtarget.cpp
  llvm/lib/Target/AArch64/AArch64Subtarget.h
  llvm/unittests/Support/TargetParserTest.cpp

Index: llvm/unittests/Support/TargetParserTest.cpp
===
--- llvm/unittests/Support/TargetParserTest.cpp
+++ llvm/unittests/Support/TargetParserTest.cpp
@@ -898,6 +898,17 @@
  AArch64::AEK_RDM | AArch64::AEK_FP16 |
  AArch64::AEK_DOTPROD | AArch64::AEK_RCPC,
  "8.2-A"),
+ARMCPUTestParams("cortex-a510", "armv9-a", "neon-fp-armv8",
+ AArch64::AEK_CRC | AArch64::AEK_FP |
+ AArch64::AEK_SIMD | AArch64::AEK_RAS |
+ AArch64::AEK_LSE | AArch64::AEK_RDM |
+ AArch64::AEK_RCPC | AArch64::AEK_DOTPROD |
+ AArch64::AEK_SVE2 | AArch64::AEK_BF16 |
+ AArch64::AEK_I8MM | AArch64::AEK_SVE2BITPERM |
+ AArch64::AEK_PAUTH | AArch64::AEK_MTE |
+ AArch64::AEK_SSBS | AArch64::AEK_FP16FML |
+ AArch64::AEK_SB,
+ "9-A"),
 ARMCPUTestParams("cortex-a57", "armv8-a", "crypto-neon-fp-armv8",
  AArch64::AEK_CRC | AArch64::AEK_CRYPTO |
  AArch64::AEK_FP | AArch64::AEK_SIMD,
@@ -1178,7 +1189,7 @@
  AArch64::AEK_LSE | AArch64::AEK_RDM,
  "8.2-A")));
 
-static constexpr unsigned NumAArch64CPUArchs = 48;
+static constexpr unsigned NumAArch64CPUArchs = 49;
 
 TEST(TargetParserTest, testAArch64CPUArchList) {
   SmallVector List;
Index: llvm/lib/Target/AArch64/AArch64Subtarget.h
===
--- llvm/lib/Target/AArch64/AArch64Subtarget.h
+++ llvm/lib/Target/AArch64/AArch64Subtarget.h
@@ -50,6 +50,7 @@
 CortexA35,
 CortexA53,
 CortexA55,
+CortexA510,
 CortexA57,
 CortexA65,
 CortexA72,
Index: llvm/lib/Target/AArch64/AArch64Subtarget.cpp
===
--- llvm/lib/Target/AArch64/AArch64Subtarget.cpp
+++ llvm/lib/Target/AArch64/AArch64Subtarget.cpp
@@ -78,6 +78,7 @@
 break;
   case CortexA53:
   case CortexA55:
+  case CortexA510:
 PrefFunctionLogAlignment = 4;
 break;
   case CortexA57:
Index: llvm/lib/Target/AArch64/AArch64.td
===
--- llvm/lib/Target/AArch64/AArch64.td
+++ llvm/lib/Target/AArch64/AArch64.td
@@ -630,6 +630,22 @@
FeatureFuseAddress,
]>;
 
+def ProcA510: SubtargetFeature<"a510", "ARMProcFamily", "CortexA510",
+   "Cortex-A510 ARM processors", [
+   HasV9_0aOps,
+   FeatureNEON,
+   FeaturePerfMon,
+   FeatureMatMulInt8,
+   FeatureBF16,
+   FeatureAM,
+   FeatureMTE,
+   FeatureETE,
+   FeatureSVE2BitPerm,
+   FeatureFP16FML,
+   FeatureFuseAES,
+   FeaturePostRAScheduler
+   ]>;
+
 def ProcA57 : SubtargetFeature<"a57", "ARMProcFamily", "CortexA57",
"Cortex-A57 ARM processors", [
FeatureBalanceFPOps,
@@ -1186,6 +1202,7 @@
 def : ProcessorModel<"cortex-a34", CortexA53Model, [ProcA35]>;
 def : ProcessorModel<"cortex-a53", CortexA53Model, [ProcA53]>;
 def : ProcessorModel<"cortex-a55", CortexA55Model, [ProcA55]>;
+def : ProcessorModel<"cortex-a510", CortexA55Model, [ProcA510]>;
 def : ProcessorModel<"cortex-a57", CortexA57Model, [ProcA57]>;
 def : ProcessorModel<"cortex-a65", CortexA53Model, [ProcA65]>;
 def : ProcessorModel<"cortex-a65ae", CortexA53Model, [ProcA65]>;
Index: llvm/include/llvm/Support/AArch64TargetParser.def
===
--- llvm/include/llvm/Support/AArch64TargetParser.def
+++ llvm/include/llvm/Support/AArch64TargetParser.def
@@ -144,6 +144,10 @@
  (AArch64::AEK_CRC))

[PATCH] D109825: [AArch64]Enabling Cortex-A510 Support

2021-10-11 Thread Dave Green via Phabricator via cfe-commits 
dmgreen added a comment.

Thanks for the updates.

In D109825#3055264 , @lenary wrote:

> In D109825#3055142 , @xgupta wrote:
>
>> It misses llvm/test/CodeGen/AArch64 and llvm/test/MC/AArch64 testcases 
>> changes, see for example https://reviews.llvm.org/D36667 (Cortex-A55 
>> support).
>
> I'm not convinced this is required - those tests are to ensure that the 
> extensions (rcpc, dotprod) can be enabled either from a `-march`, or from a 
> `-mcpu=` with a cpu that contains that extension -- they are not testing 
> that the extension is enabled from *all* cpus that contain said extension.

Yeah I agree. It would be useful to add some tests for -mcpu=cortex-a510+crypto 
and -mcpu=cortex-a510+nocrypto, to make sure they do what is expected.




Comment at: clang/docs/ReleaseNotes.rst:86
 
+- Support has been added for the following processors (command-line 
identifiers in parentheses):
+  - Arm Cortex-A510 (cortex-a510)

Can you add an Arm section below and move this to it.


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[PATCH] D109825: [AArch64]Enabling Cortex-A510 Support

2021-10-11 Thread Shivam Gupta via Phabricator via cfe-commits 
xgupta added a comment.

oh thanks for the clarification, I am not aware of it.


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[PATCH] D109825: [AArch64]Enabling Cortex-A510 Support

2021-10-11 Thread Sam Elliott via Phabricator via cfe-commits 
lenary added a comment.

In D109825#3055142 , @xgupta wrote:

> It misses llvm/test/CodeGen/AArch64 and llvm/test/MC/AArch64 testcases 
> changes, see for example https://reviews.llvm.org/D36667 (Cortex-A55 support).

I'm not convinced this is required - those tests are to ensure that the 
extensions (rcpc, dotprod) can be enabled either from a `-march`, or from a 
`-mcpu=` with a cpu that contains that extension -- they are not testing 
that the extension is enabled from *all* cpus that contain said extension.


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[PATCH] D109825: [AArch64]Enabling Cortex-A510 Support

2021-10-11 Thread Shivam Gupta via Phabricator via cfe-commits 
xgupta added a comment.

It misses llvm/test/CodeGen/AArch64 and llvm/test/MC/AArch64 testcases changes, 
see for example https://reviews.llvm.org/D36667 (Cortex-A55 support).


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[PATCH] D109825: [AArch64]Enabling Cortex-A510 Support

2021-10-11 Thread Mubashar Ahmad via Phabricator via cfe-commits 
mubashar_ updated this revision to Diff 378645.
mubashar_ added a comment.

Added files that were missing from previous diff.


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Files:
  clang/docs/ReleaseNotes.rst
  clang/test/Driver/aarch64-cpus.c
  llvm/include/llvm/Support/AArch64TargetParser.def
  llvm/lib/Target/AArch64/AArch64.td
  llvm/lib/Target/AArch64/AArch64Subtarget.cpp
  llvm/lib/Target/AArch64/AArch64Subtarget.h
  llvm/unittests/Support/TargetParserTest.cpp

Index: llvm/unittests/Support/TargetParserTest.cpp
===
--- llvm/unittests/Support/TargetParserTest.cpp
+++ llvm/unittests/Support/TargetParserTest.cpp
@@ -898,6 +898,17 @@
  AArch64::AEK_RDM | AArch64::AEK_FP16 |
  AArch64::AEK_DOTPROD | AArch64::AEK_RCPC,
  "8.2-A"),
+ARMCPUTestParams("cortex-a510", "armv9-a", "neon-fp-armv8",
+ AArch64::AEK_CRC | AArch64::AEK_FP |
+ AArch64::AEK_SIMD | AArch64::AEK_RAS |
+ AArch64::AEK_LSE | AArch64::AEK_RDM |
+ AArch64::AEK_RCPC | AArch64::AEK_DOTPROD |
+ AArch64::AEK_SVE2 | AArch64::AEK_BF16 |
+ AArch64::AEK_I8MM | AArch64::AEK_SVE2BITPERM |
+ AArch64::AEK_PAUTH | AArch64::AEK_MTE |
+ AArch64::AEK_SSBS | AArch64::AEK_FP16FML |
+ AArch64::AEK_SB,
+ "9-A"),
 ARMCPUTestParams("cortex-a57", "armv8-a", "crypto-neon-fp-armv8",
  AArch64::AEK_CRC | AArch64::AEK_CRYPTO |
  AArch64::AEK_FP | AArch64::AEK_SIMD,
@@ -1178,7 +1189,7 @@
  AArch64::AEK_LSE | AArch64::AEK_RDM,
  "8.2-A")));
 
-static constexpr unsigned NumAArch64CPUArchs = 48;
+static constexpr unsigned NumAArch64CPUArchs = 49;
 
 TEST(TargetParserTest, testAArch64CPUArchList) {
   SmallVector List;
Index: llvm/lib/Target/AArch64/AArch64Subtarget.h
===
--- llvm/lib/Target/AArch64/AArch64Subtarget.h
+++ llvm/lib/Target/AArch64/AArch64Subtarget.h
@@ -50,6 +50,7 @@
 CortexA35,
 CortexA53,
 CortexA55,
+CortexA510,
 CortexA57,
 CortexA65,
 CortexA72,
Index: llvm/lib/Target/AArch64/AArch64Subtarget.cpp
===
--- llvm/lib/Target/AArch64/AArch64Subtarget.cpp
+++ llvm/lib/Target/AArch64/AArch64Subtarget.cpp
@@ -78,6 +78,7 @@
 break;
   case CortexA53:
   case CortexA55:
+  case CortexA510:
 PrefFunctionLogAlignment = 4;
 break;
   case CortexA57:
Index: llvm/lib/Target/AArch64/AArch64.td
===
--- llvm/lib/Target/AArch64/AArch64.td
+++ llvm/lib/Target/AArch64/AArch64.td
@@ -630,6 +630,22 @@
FeatureFuseAddress,
]>;
 
+def ProcA510: SubtargetFeature<"a510", "ARMProcFamily", "CortexA510",
+   "Cortex-A510 ARM processors", [
+   HasV9_0aOps,
+   FeatureNEON,
+   FeaturePerfMon,
+   FeatureMatMulInt8,
+   FeatureBF16,
+   FeatureAM,
+   FeatureMTE,
+   FeatureETE,
+   FeatureSVE2BitPerm,
+   FeatureFP16FML,
+   FeatureFuseAES,
+   FeaturePostRAScheduler
+   ]>;
+
 def ProcA57 : SubtargetFeature<"a57", "ARMProcFamily", "CortexA57",
"Cortex-A57 ARM processors", [
FeatureBalanceFPOps,
@@ -1186,6 +1202,7 @@
 def : ProcessorModel<"cortex-a34", CortexA53Model, [ProcA35]>;
 def : ProcessorModel<"cortex-a53", CortexA53Model, [ProcA53]>;
 def : ProcessorModel<"cortex-a55", CortexA55Model, [ProcA55]>;
+def : ProcessorModel<"cortex-a510", CortexA55Model, [ProcA510]>;
 def : ProcessorModel<"cortex-a57", CortexA57Model, [ProcA57]>;
 def : ProcessorModel<"cortex-a65", CortexA53Model, [ProcA65]>;
 def : ProcessorModel<"cortex-a65ae", CortexA53Model, [ProcA65]>;
Index: llvm/include/llvm/Support/AArch64TargetParser.def
===
--- llvm/include/llvm/Support/AArch64TargetParser.def
+++ llvm/include/llvm/Support/AArch64TargetParser.def
@@ -144,6 +144,10 @@
  (AArch64::AEK_CRC))
 AARCH64_CPU_NAME("cortex-a55", ARMV8_2A,

[PATCH] D109825: [AArch64]Enabling Cortex-A510 Support

2021-10-08 Thread Mubashar Ahmad via Phabricator via cfe-commits 
mubashar_ added a comment.

@xgupta I followed the request review via web interface section of that page. 
Let me look into it.


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[PATCH] D109825: [AArch64]Enabling Cortex-A510 Support

2021-10-08 Thread Shivam Gupta via Phabricator via cfe-commits 
xgupta added a comment.

Yeah, those changes are in history, But we need them in the present to commit :)

The patch is incorrectly updated, did you followed 
https://llvm.org/docs/Phabricator.html#requesting-a-review-via-the-command-line?


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[PATCH] D109825: [AArch64]Enabling Cortex-A510 Support

2021-10-08 Thread Mubashar Ahmad via Phabricator via cfe-commits 
mubashar_ added a comment.

@xgupta those would be under the history tab.


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[PATCH] D109825: [AArch64]Enabling Cortex-A510 Support

2021-10-08 Thread Shivam Gupta via Phabricator via cfe-commits 
xgupta added a comment.

Where are the other patches? Or diff is not uploaded correctly.


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[PATCH] D109825: [AArch64]Enabling Cortex-A510 Support

2021-10-08 Thread Mubashar Ahmad via Phabricator via cfe-commits 
mubashar_ updated this revision to Diff 378216.
mubashar_ marked 3 inline comments as done.

Repository:
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Files:
  llvm/include/llvm/Support/AArch64TargetParser.def
  llvm/lib/Target/AArch64/AArch64.td
  llvm/unittests/Support/TargetParserTest.cpp


Index: llvm/unittests/Support/TargetParserTest.cpp
===
--- llvm/unittests/Support/TargetParserTest.cpp
+++ llvm/unittests/Support/TargetParserTest.cpp
@@ -898,14 +898,16 @@
  AArch64::AEK_RDM | AArch64::AEK_FP16 |
  AArch64::AEK_DOTPROD | AArch64::AEK_RCPC,
  "8.2-A"),
-ARMCPUTestParams("cortex-a510", "armv9-a", "crypto-neon-fp-armv8",
+ARMCPUTestParams("cortex-a510", "armv9-a", "neon-fp-armv8",
  AArch64::AEK_CRC | AArch64::AEK_FP |
  AArch64::AEK_SIMD | AArch64::AEK_RAS |
- AArch64::AEK_I8MM | AArch64::AEK_BF16 |
- AArch64::AEK_SVE2 | AArch64::AEK_SVE |
- AArch64::AEK_SVE2BITPERM | AArch64::AEK_SSBS |
- AArch64::AEK_BT | AArch64::AEK_MTE |
- AArch64::AEK_DOTPROD,
+ AArch64::AEK_LSE | AArch64::AEK_RDM |
+ AArch64::AEK_RCPC | AArch64::AEK_DOTPROD |
+ AArch64::AEK_SVE2 | AArch64::AEK_BF16 |
+ AArch64::AEK_I8MM | AArch64::AEK_SVE2BITPERM |
+ AArch64::AEK_PAUTH | AArch64::AEK_MTE |
+ AArch64::AEK_SSBS | AArch64::AEK_FP16FML |
+ AArch64::AEK_SB,
  "9-A"),
 ARMCPUTestParams("cortex-a57", "armv8-a", "crypto-neon-fp-armv8",
  AArch64::AEK_CRC | AArch64::AEK_CRYPTO |
Index: llvm/lib/Target/AArch64/AArch64.td
===
--- llvm/lib/Target/AArch64/AArch64.td
+++ llvm/lib/Target/AArch64/AArch64.td
@@ -632,23 +632,18 @@
 
 def ProcA510: SubtargetFeature<"a510", "ARMProcFamily", "CortexA510",
"Cortex-A510 ARM processors", [
- HasV9aOps,
- FeatureCrypto,
- FeatureFPARMv8,
- FeatureFuseAES,
- FeatureNEON,
- FeaturePerfMon,
- FeaturePostRAScheduler,
- FeatureSPE,
- FeatureAM,
- FeatureMPAM,
- FeatureETE,
- FeatureMTE,
- FeatureSVE2,
- FeatureSVE2BitPerm,
- FeatureFullFP16,
- FeatureFP16FML,
- FeatureDotProd
+   HasV9_0aOps,
+   FeatureNEON,
+   FeaturePerfMon,
+   FeatureMatMulInt8,
+   FeatureBF16,
+   FeatureAM,
+   FeatureMTE,
+   FeatureETE,
+   FeatureSVE2BitPerm,
+   FeatureFP16FML,
+   FeatureFuseAES,
+   FeaturePostRAScheduler
]>;
 
 def ProcA57 : SubtargetFeature<"a57", "ARMProcFamily", "CortexA57",
Index: llvm/include/llvm/Support/AArch64TargetParser.def
===
--- llvm/include/llvm/Support/AArch64TargetParser.def
+++ llvm/include/llvm/Support/AArch64TargetParser.def
@@ -144,11 +144,10 @@
  (AArch64::AEK_CRC))
 AARCH64_CPU_NAME("cortex-a55", ARMV8_2A, FK_CRYPTO_NEON_FP_ARMV8, false,
  (AArch64::AEK_FP16 | AArch64::AEK_DOTPROD | 
AArch64::AEK_RCPC))
-AARCH64_CPU_NAME("cortex=a510", ARMV9A,FK_CRYPTO_NEON_FP_ARMV8, false,
- (AArch64::AEK_CRC | AArch64::AEK_FP | AArch64::AEK_SIMD |
-  AArch64::AEK_RAS | AArch64::AEK_I8MM | AArch64::AEK_BF16 |
-  AArch64::AEK_SVE2 | AArch64::AEK_SVE | 
AArch64::AEK_SVE2BITPERM |
-  AArch64::AEK_SSBS | AArch64::AEK_BT | AArch64::AEK_MTE))
+AARCH64_CPU_NAME("cortex-a510", ARMV9A, FK_NEON_FP_ARMV8, false,
+ (AArch64::AEK_BF16 |

[PATCH] D109825: [AArch64]Enabling Cortex-A510 Support

2021-09-15 Thread Mark Murray via Phabricator via cfe-commits 
MarkMurrayARM added a comment.

In D109825#3001622 , @dmgreen wrote:

>> As I did the downstream work for this, I'm happy with it to go in in this 
>> form.
>
> This doesn't seem.. wise. Please make sure the reviews you do are at a 
> sufficient quality, and it is probably best not to review patches you write 
> yourself.

Very good point!

I reduce this to the claim that it has been stable downstream for a couple of 
weeks now.


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[PATCH] D109825: [AArch64]Enabling Cortex-A510 Support

2021-09-15 Thread Mubashar Ahmad via Phabricator via cfe-commits 
mubashar_ updated this revision to Diff 372698.
mubashar_ added a comment.

Updated release notes to solve a merge conflict.


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Files:
  clang/docs/ReleaseNotes.rst
  clang/test/Driver/aarch64-cpus.c
  llvm/include/llvm/Support/AArch64TargetParser.def
  llvm/lib/Target/AArch64/AArch64.td
  llvm/lib/Target/AArch64/AArch64Subtarget.cpp
  llvm/lib/Target/AArch64/AArch64Subtarget.h
  llvm/unittests/Support/TargetParserTest.cpp

Index: llvm/unittests/Support/TargetParserTest.cpp
===
--- llvm/unittests/Support/TargetParserTest.cpp
+++ llvm/unittests/Support/TargetParserTest.cpp
@@ -983,6 +983,14 @@
  AArch64::AEK_DOTPROD | AArch64::AEK_RCPC |
  AArch64::AEK_SSBS,
  "8.2-A"),
+ARMCPUTestParams("cortex-a510", "armv8.3-a", "crypto-neon-fp-armv8",
+ AArch64::AEK_CRC | AArch64::AEK_CRYPTO |
+ AArch64::AEK_FP | AArch64::AEK_SIMD |
+ AArch64::AEK_RAS | AArch64::AEK_LSE |
+ AArch64::AEK_RDM | AArch64::AEK_RCPC |
+ AArch64::AEK_SVE2 | AArch64::AEK_SVE2BITPERM |
+ AArch64::AEK_DOTPROD | AArch64::AEK_MTE,
+ "8.3-A"),
 ARMCPUTestParams("cyclone", "armv8-a", "crypto-neon-fp-armv8",
  AArch64::AEK_NONE | AArch64::AEK_CRYPTO |
  AArch64::AEK_FP | AArch64::AEK_SIMD,
@@ -1164,7 +1172,7 @@
  AArch64::AEK_LSE | AArch64::AEK_RDM,
  "8.2-A")));
 
-static constexpr unsigned NumAArch64CPUArchs = 48;
+static constexpr unsigned NumAArch64CPUArchs = 49;
 
 TEST(TargetParserTest, testAArch64CPUArchList) {
   SmallVector List;
Index: llvm/lib/Target/AArch64/AArch64Subtarget.h
===
--- llvm/lib/Target/AArch64/AArch64Subtarget.h
+++ llvm/lib/Target/AArch64/AArch64Subtarget.h
@@ -59,6 +59,7 @@
 CortexA77,
 CortexA78,
 CortexA78C,
+CortexA510,
 CortexR82,
 CortexX1,
 ExynosM3,
Index: llvm/lib/Target/AArch64/AArch64Subtarget.cpp
===
--- llvm/lib/Target/AArch64/AArch64Subtarget.cpp
+++ llvm/lib/Target/AArch64/AArch64Subtarget.cpp
@@ -193,6 +193,9 @@
 // FIXME: remove this to enable 64-bit SLP if performance looks good.
 MinVectorRegisterBitWidth = 128;
 break;
+  case CortexA510:
+PrefFunctionLogAlignment = 4;
+break;
   }
 }
 
Index: llvm/lib/Target/AArch64/AArch64.td
===
--- llvm/lib/Target/AArch64/AArch64.td
+++ llvm/lib/Target/AArch64/AArch64.td
@@ -1048,6 +1048,26 @@
   FeatureSSBS,
   FeatureSVE]>;
 
+def ProcCortexA510 : SubtargetFeature<"cortex-a510", "ARMProcFamily",
+  "CortexA510", "Cortex-A510 ARM processors", [
+  HasV8_3aOps,
+  FeatureCrypto,
+  FeatureFPARMv8,
+  FeatureFuseAES,
+  FeatureNEON,
+  FeaturePerfMon,
+  FeaturePostRAScheduler,
+  FeatureSPE,
+  FeatureAM,
+  FeatureMPAM,
+  FeatureETE,
+  FeatureMTE,
+  FeatureSVE2,
+  FeatureSVE2BitPerm,
+  FeatureFullFP16,
+  FeatureFP16FML,
+  FeatureDotProd]>;
+
 def ProcSaphira  : SubtargetFeature<"saphira", "ARMProcFamily", "Saphira",
"Qualcomm Saphira processors", [
FeatureCrypto,
@@ -1187,6 +1207,7 @@
 def : ProcessorModel<"neoverse-n1", CortexA57Model, [ProcNeoverseN1]>;
 def : ProcessorModel<"neoverse-n2", CortexA57Model, [ProcNeoverseN2]>;
 def : ProcessorModel<"neoverse-v1", CortexA57Model, [ProcNeoverseV1]>;
+def : ProcessorModel<"cortex-a510", CortexA57Model, [ProcCortexA510]>;
 def : ProcessorModel<"exynos-m3", ExynosM3Model, [ProcExynosM3]>;
 def : ProcessorModel<"exynos-m4", ExynosM4Model, [ProcExynosM4]>;
 def : ProcessorModel<"exynos-m5", ExynosM5Model, [ProcExynosM4]>;
Index: llvm/include/llvm/Support/AArch64TargetParser.def
===
---

[PATCH] D109825: [AArch64]Enabling Cortex-A510 Support

2021-09-15 Thread Dave Green via Phabricator via cfe-commits 
dmgreen requested changes to this revision.
dmgreen added a comment.
This revision now requires changes to proceed.

> As I did the downstream work for this, I'm happy with it to go in in this 
> form.

This doesn't seem.. wise. Please make sure the reviews you do are at a 
sufficient quality, and it is probably best not to review patches you write 
yourself.




Comment at: llvm/include/llvm/Support/AArch64TargetParser.def:179
   AArch64::AEK_DOTPROD ))
+AARCH64_CPU_NAME("cortex-a510", ARMV8_3A, FK_CRYPTO_NEON_FP_ARMV8, false,
+ (AArch64::AEK_MTE | AArch64::AEK_SVE2 |

Why is this 8.3? The TRM 
(https://developer.arm.com/documentation/101604/0003/The-Cortex-A510--core) 
describes it as implementing the 9.0-A architecture.



Comment at: llvm/lib/Target/AArch64/AArch64.td:1055
 
+def ProcCortexA510 : SubtargetFeature<"cortex-a510", "ARMProcFamily",
+  "CortexA510", "Cortex-A510 ARM 
processors", [

This should be in some sort of order, next to the Cortex-A55. It should 
probably be called ProcA510 for consistency too.



Comment at: llvm/lib/Target/AArch64/AArch64.td:1214
 def : ProcessorModel<"neoverse-v1", CortexA57Model, [ProcNeoverseV1]>;
+def : ProcessorModel<"cortex-a510", CortexA57Model, [ProcCortexA510]>;
 def : ProcessorModel<"exynos-m3", ExynosM3Model, [ProcExynosM3]>;

Ordering. Please use the CortexA55Model. This is not an out of order core like 
the A57.



Comment at: llvm/lib/Target/AArch64/AArch64Subtarget.cpp:196
 break;
+  case CortexA510:
+PrefFunctionLogAlignment = 4;

This can be the same case block as the A53 and A55.


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  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D109825/new/

https://reviews.llvm.org/D109825

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[PATCH] D109825: [AArch64]Enabling Cortex-A510 Support

2021-09-15 Thread Mark Murray via Phabricator via cfe-commits 
MarkMurrayARM accepted this revision.
MarkMurrayARM added a comment.
This revision is now accepted and ready to land.

As I did the downstream work for this, I'm happy with it to go in in this form.


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[PATCH] D109825: [AArch64]Enabling Cortex-A510 Support

2021-09-15 Thread Mubashar Ahmad via Phabricator via cfe-commits 
mubashar_ created this revision.
mubashar_ added a reviewer: MarkMurrayARM.
Herald added subscribers: hiraditya, kristof.beyls.
mubashar_ requested review of this revision.
Herald added projects: clang, LLVM.
Herald added subscribers: llvm-commits, cfe-commits.

This patch enables support for Cortex-A510 CPUs.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D109825

Files:
  clang/docs/ReleaseNotes.rst
  clang/test/Driver/aarch64-cpus.c
  llvm/include/llvm/Support/AArch64TargetParser.def
  llvm/lib/Target/AArch64/AArch64.td
  llvm/lib/Target/AArch64/AArch64Subtarget.cpp
  llvm/lib/Target/AArch64/AArch64Subtarget.h
  llvm/unittests/Support/TargetParserTest.cpp

Index: llvm/unittests/Support/TargetParserTest.cpp
===
--- llvm/unittests/Support/TargetParserTest.cpp
+++ llvm/unittests/Support/TargetParserTest.cpp
@@ -983,6 +983,14 @@
  AArch64::AEK_DOTPROD | AArch64::AEK_RCPC |
  AArch64::AEK_SSBS,
  "8.2-A"),
+ARMCPUTestParams("cortex-a510", "armv8.3-a", "crypto-neon-fp-armv8",
+ AArch64::AEK_CRC | AArch64::AEK_CRYPTO |
+ AArch64::AEK_FP | AArch64::AEK_SIMD |
+ AArch64::AEK_RAS | AArch64::AEK_LSE |
+ AArch64::AEK_RDM | AArch64::AEK_RCPC |
+ AArch64::AEK_SVE2 | AArch64::AEK_SVE2BITPERM |
+ AArch64::AEK_DOTPROD | AArch64::AEK_MTE,
+ "8.3-A"),
 ARMCPUTestParams("cyclone", "armv8-a", "crypto-neon-fp-armv8",
  AArch64::AEK_NONE | AArch64::AEK_CRYPTO |
  AArch64::AEK_FP | AArch64::AEK_SIMD,
@@ -1164,7 +1172,7 @@
  AArch64::AEK_LSE | AArch64::AEK_RDM,
  "8.2-A")));
 
-static constexpr unsigned NumAArch64CPUArchs = 48;
+static constexpr unsigned NumAArch64CPUArchs = 49;
 
 TEST(TargetParserTest, testAArch64CPUArchList) {
   SmallVector List;
Index: llvm/lib/Target/AArch64/AArch64Subtarget.h
===
--- llvm/lib/Target/AArch64/AArch64Subtarget.h
+++ llvm/lib/Target/AArch64/AArch64Subtarget.h
@@ -59,6 +59,7 @@
 CortexA77,
 CortexA78,
 CortexA78C,
+CortexA510,
 CortexR82,
 CortexX1,
 ExynosM3,
Index: llvm/lib/Target/AArch64/AArch64Subtarget.cpp
===
--- llvm/lib/Target/AArch64/AArch64Subtarget.cpp
+++ llvm/lib/Target/AArch64/AArch64Subtarget.cpp
@@ -193,6 +193,9 @@
 // FIXME: remove this to enable 64-bit SLP if performance looks good.
 MinVectorRegisterBitWidth = 128;
 break;
+  case CortexA510:
+PrefFunctionLogAlignment = 4;
+break;
   }
 }
 
Index: llvm/lib/Target/AArch64/AArch64.td
===
--- llvm/lib/Target/AArch64/AArch64.td
+++ llvm/lib/Target/AArch64/AArch64.td
@@ -1052,6 +1052,26 @@
   FeatureSSBS,
   FeatureSVE]>;
 
+def ProcCortexA510 : SubtargetFeature<"cortex-a510", "ARMProcFamily",
+  "CortexA510", "Cortex-A510 ARM processors", [
+  HasV8_3aOps,
+  FeatureCrypto,
+  FeatureFPARMv8,
+  FeatureFuseAES,
+  FeatureNEON,
+  FeaturePerfMon,
+  FeaturePostRAScheduler,
+  FeatureSPE,
+  FeatureAM,
+  FeatureMPAM,
+  FeatureETE,
+  FeatureMTE,
+  FeatureSVE2,
+  FeatureSVE2BitPerm,
+  FeatureFullFP16,
+  FeatureFP16FML,
+  FeatureDotProd]>;
+
 def ProcSaphira  : SubtargetFeature<"saphira", "ARMProcFamily", "Saphira",
"Qualcomm Saphira processors", [
FeatureCrypto,
@@ -1191,6 +1211,7 @@
 def : ProcessorModel<"neoverse-n1", CortexA57Model, [ProcNeoverseN1]>;
 def : ProcessorModel<"neoverse-n2", CortexA57Model, [ProcNeoverseN2]>;
 def : ProcessorModel<"neoverse-v1", CortexA57Model, [ProcNeoverseV1]>;
+def : ProcessorModel<"cortex-a510", CortexA57Model, [ProcCortexA510]>;
 def : ProcessorModel<"exynos-m3", ExynosM3Model, [ProcExynosM3]>;
 def : ProcessorModel<"exynos-m4", ExynosM4Model, [ProcExynosM4]>;
 def : ProcessorModel<"exynos-m5", ExynosM5Model, [ProcExynosM4]>;