[PATCH] D111258: [PowerPC] Emit dcbt and dcbtst in place of their extended mnemonics on AIX

2021-10-12 Thread Albion Fung via Phabricator via cfe-commits 
This revision was automatically updated to reflect the committed changes.
Closed by commit rGb4b9f9b4b3cf: [PowerPC] Emit dcbt and dcbtst in place of 
their extended mnemonics on AIX (authored by Conanap).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D111258/new/

https://reviews.llvm.org/D111258

Files:
  llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-prefetch.ll


Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-prefetch.ll
===
--- llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-prefetch.ll
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-prefetch.ll
@@ -26,14 +26,14 @@
 ; CHECK-AIX:   # %bb.0: # %entry
 ; CHECK-AIX-NEXT:lwz 3, L..C0(2) # @vpa
 ; CHECK-AIX-NEXT:lwz 3, 0(3)
-; CHECK-AIX-NEXT:dcbtstt 0, 3
+; CHECK-AIX-NEXT:dcbtst 0, 3, 16
 ; CHECK-AIX-NEXT:blr
 ;
 ; CHECK-AIX64-LABEL: test_dcbtstt:
 ; CHECK-AIX64:   # %bb.0: # %entry
 ; CHECK-AIX64-NEXT:ld 3, L..C0(2) # @vpa
 ; CHECK-AIX64-NEXT:ld 3, 0(3)
-; CHECK-AIX64-NEXT:dcbtstt 0, 3
+; CHECK-AIX64-NEXT:dcbtst 0, 3, 16
 ; CHECK-AIX64-NEXT:blr
 entry:
   %0 = load i8*, i8** @vpa, align 8
@@ -55,14 +55,14 @@
 ; CHECK-AIX:   # %bb.0: # %entry
 ; CHECK-AIX-NEXT:lwz 3, L..C0(2) # @vpa
 ; CHECK-AIX-NEXT:lwz 3, 0(3)
-; CHECK-AIX-NEXT:dcbtt 0, 3
+; CHECK-AIX-NEXT:dcbt 0, 3, 16
 ; CHECK-AIX-NEXT:blr
 ;
 ; CHECK-AIX64-LABEL: test_dcbtt:
 ; CHECK-AIX64:   # %bb.0: # %entry
 ; CHECK-AIX64-NEXT:ld 3, L..C0(2) # @vpa
 ; CHECK-AIX64-NEXT:ld 3, 0(3)
-; CHECK-AIX64-NEXT:dcbtt 0, 3
+; CHECK-AIX64-NEXT:dcbt 0, 3, 16
 ; CHECK-AIX64-NEXT:blr
 entry:
   %0 = load i8*, i8** @vpa, align 8
Index: llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp
===
--- llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp
+++ llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp
@@ -158,7 +158,10 @@
   //dcbt ra, rb, th [server]
   //dcbt th, ra, rb [embedded]
   //  where th can be omitted when it is 0. dcbtst is the same.
-  if (MI->getOpcode() == PPC::DCBT || MI->getOpcode() == PPC::DCBTST) {
+  // On AIX, only emit the extended mnemonics for dcbt and dcbtst if
+  // the "modern assembler" is available.
+  if ((MI->getOpcode() == PPC::DCBT || MI->getOpcode() == PPC::DCBTST) &&
+  (!TT.isOSAIX() || STI.getFeatureBits()[PPC::FeatureModernAIXAs])) {
 unsigned char TH = MI->getOperand(0).getImm();
 O << "\tdcbt";
 if (MI->getOpcode() == PPC::DCBTST)


Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-prefetch.ll
===
--- llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-prefetch.ll
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-prefetch.ll
@@ -26,14 +26,14 @@
 ; CHECK-AIX:   # %bb.0: # %entry
 ; CHECK-AIX-NEXT:lwz 3, L..C0(2) # @vpa
 ; CHECK-AIX-NEXT:lwz 3, 0(3)
-; CHECK-AIX-NEXT:dcbtstt 0, 3
+; CHECK-AIX-NEXT:dcbtst 0, 3, 16
 ; CHECK-AIX-NEXT:blr
 ;
 ; CHECK-AIX64-LABEL: test_dcbtstt:
 ; CHECK-AIX64:   # %bb.0: # %entry
 ; CHECK-AIX64-NEXT:ld 3, L..C0(2) # @vpa
 ; CHECK-AIX64-NEXT:ld 3, 0(3)
-; CHECK-AIX64-NEXT:dcbtstt 0, 3
+; CHECK-AIX64-NEXT:dcbtst 0, 3, 16
 ; CHECK-AIX64-NEXT:blr
 entry:
   %0 = load i8*, i8** @vpa, align 8
@@ -55,14 +55,14 @@
 ; CHECK-AIX:   # %bb.0: # %entry
 ; CHECK-AIX-NEXT:lwz 3, L..C0(2) # @vpa
 ; CHECK-AIX-NEXT:lwz 3, 0(3)
-; CHECK-AIX-NEXT:dcbtt 0, 3
+; CHECK-AIX-NEXT:dcbt 0, 3, 16
 ; CHECK-AIX-NEXT:blr
 ;
 ; CHECK-AIX64-LABEL: test_dcbtt:
 ; CHECK-AIX64:   # %bb.0: # %entry
 ; CHECK-AIX64-NEXT:ld 3, L..C0(2) # @vpa
 ; CHECK-AIX64-NEXT:ld 3, 0(3)
-; CHECK-AIX64-NEXT:dcbtt 0, 3
+; CHECK-AIX64-NEXT:dcbt 0, 3, 16
 ; CHECK-AIX64-NEXT:blr
 entry:
   %0 = load i8*, i8** @vpa, align 8
Index: llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp
===
--- llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp
+++ llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp
@@ -158,7 +158,10 @@
   //dcbt ra, rb, th [server]
   //dcbt th, ra, rb [embedded]
   //  where th can be omitted when it is 0. dcbtst is the same.
-  if (MI->getOpcode() == PPC::DCBT || MI->getOpcode() == PPC::DCBTST) {
+  // On AIX, only emit the extended mnemonics for dcbt and dcbtst if
+  // the "modern assembler" is available.
+  if ((MI->getOpcode() == PPC::DCBT || MI->getOpcode() == PPC::DCBTST) &&
+  (!TT.isOSAIX() || STI.getFeatureBits()[PPC::FeatureModernAIXAs])) {
 unsigned char TH = MI->getOperand(0).getImm();
 O << "\tdcbt";
 if (MI->getOpcode() == PPC::DCBTST)
___
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[PATCH] D111258: [PowerPC] Emit dcbt and dcbtst in place of their extended mnemonics on AIX

2021-10-08 Thread Nemanja Ivanovic via Phabricator via cfe-commits 
nemanjai accepted this revision.
nemanjai added a comment.

LGTM. This is already approved, but just wanted to indicate that I think the 
comments were addressed adequately.


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[PATCH] D111258: [PowerPC] Emit dcbt and dcbtst in place of their extended mnemonics on AIX

2021-10-07 Thread Albion Fung via Phabricator via cfe-commits 
Conanap updated this revision to Diff 378015.
Conanap marked 2 inline comments as done.
Conanap added a comment.

Added mordern assembler check


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D111258/new/

https://reviews.llvm.org/D111258

Files:
  llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-prefetch.ll


Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-prefetch.ll
===
--- llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-prefetch.ll
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-prefetch.ll
@@ -26,14 +26,14 @@
 ; CHECK-AIX:   # %bb.0: # %entry
 ; CHECK-AIX-NEXT:lwz 3, L..C0(2) # @vpa
 ; CHECK-AIX-NEXT:lwz 3, 0(3)
-; CHECK-AIX-NEXT:dcbtstt 0, 3
+; CHECK-AIX-NEXT:dcbtst 0, 3, 16
 ; CHECK-AIX-NEXT:blr
 ;
 ; CHECK-AIX64-LABEL: test_dcbtstt:
 ; CHECK-AIX64:   # %bb.0: # %entry
 ; CHECK-AIX64-NEXT:ld 3, L..C0(2) # @vpa
 ; CHECK-AIX64-NEXT:ld 3, 0(3)
-; CHECK-AIX64-NEXT:dcbtstt 0, 3
+; CHECK-AIX64-NEXT:dcbtst 0, 3, 16
 ; CHECK-AIX64-NEXT:blr
 entry:
   %0 = load i8*, i8** @vpa, align 8
@@ -55,14 +55,14 @@
 ; CHECK-AIX:   # %bb.0: # %entry
 ; CHECK-AIX-NEXT:lwz 3, L..C0(2) # @vpa
 ; CHECK-AIX-NEXT:lwz 3, 0(3)
-; CHECK-AIX-NEXT:dcbtt 0, 3
+; CHECK-AIX-NEXT:dcbt 0, 3, 16
 ; CHECK-AIX-NEXT:blr
 ;
 ; CHECK-AIX64-LABEL: test_dcbtt:
 ; CHECK-AIX64:   # %bb.0: # %entry
 ; CHECK-AIX64-NEXT:ld 3, L..C0(2) # @vpa
 ; CHECK-AIX64-NEXT:ld 3, 0(3)
-; CHECK-AIX64-NEXT:dcbtt 0, 3
+; CHECK-AIX64-NEXT:dcbt 0, 3, 16
 ; CHECK-AIX64-NEXT:blr
 entry:
   %0 = load i8*, i8** @vpa, align 8
Index: llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp
===
--- llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp
+++ llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp
@@ -158,7 +158,10 @@
   //dcbt ra, rb, th [server]
   //dcbt th, ra, rb [embedded]
   //  where th can be omitted when it is 0. dcbtst is the same.
-  if (MI->getOpcode() == PPC::DCBT || MI->getOpcode() == PPC::DCBTST) {
+  // On AIX, only emit the extended mnemonics for dcbt and dcbtst if
+  // the "modern assembler" is available.
+  if ((MI->getOpcode() == PPC::DCBT || MI->getOpcode() == PPC::DCBTST) &&
+  (!TT.isOSAIX() || STI.getFeatureBits()[PPC::FeatureModernAIXAs])) {
 unsigned char TH = MI->getOperand(0).getImm();
 O << "\tdcbt";
 if (MI->getOpcode() == PPC::DCBTST)


Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-prefetch.ll
===
--- llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-prefetch.ll
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-prefetch.ll
@@ -26,14 +26,14 @@
 ; CHECK-AIX:   # %bb.0: # %entry
 ; CHECK-AIX-NEXT:lwz 3, L..C0(2) # @vpa
 ; CHECK-AIX-NEXT:lwz 3, 0(3)
-; CHECK-AIX-NEXT:dcbtstt 0, 3
+; CHECK-AIX-NEXT:dcbtst 0, 3, 16
 ; CHECK-AIX-NEXT:blr
 ;
 ; CHECK-AIX64-LABEL: test_dcbtstt:
 ; CHECK-AIX64:   # %bb.0: # %entry
 ; CHECK-AIX64-NEXT:ld 3, L..C0(2) # @vpa
 ; CHECK-AIX64-NEXT:ld 3, 0(3)
-; CHECK-AIX64-NEXT:dcbtstt 0, 3
+; CHECK-AIX64-NEXT:dcbtst 0, 3, 16
 ; CHECK-AIX64-NEXT:blr
 entry:
   %0 = load i8*, i8** @vpa, align 8
@@ -55,14 +55,14 @@
 ; CHECK-AIX:   # %bb.0: # %entry
 ; CHECK-AIX-NEXT:lwz 3, L..C0(2) # @vpa
 ; CHECK-AIX-NEXT:lwz 3, 0(3)
-; CHECK-AIX-NEXT:dcbtt 0, 3
+; CHECK-AIX-NEXT:dcbt 0, 3, 16
 ; CHECK-AIX-NEXT:blr
 ;
 ; CHECK-AIX64-LABEL: test_dcbtt:
 ; CHECK-AIX64:   # %bb.0: # %entry
 ; CHECK-AIX64-NEXT:ld 3, L..C0(2) # @vpa
 ; CHECK-AIX64-NEXT:ld 3, 0(3)
-; CHECK-AIX64-NEXT:dcbtt 0, 3
+; CHECK-AIX64-NEXT:dcbt 0, 3, 16
 ; CHECK-AIX64-NEXT:blr
 entry:
   %0 = load i8*, i8** @vpa, align 8
Index: llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp
===
--- llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp
+++ llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp
@@ -158,7 +158,10 @@
   //dcbt ra, rb, th [server]
   //dcbt th, ra, rb [embedded]
   //  where th can be omitted when it is 0. dcbtst is the same.
-  if (MI->getOpcode() == PPC::DCBT || MI->getOpcode() == PPC::DCBTST) {
+  // On AIX, only emit the extended mnemonics for dcbt and dcbtst if
+  // the "modern assembler" is available.
+  if ((MI->getOpcode() == PPC::DCBT || MI->getOpcode() == PPC::DCBTST) &&
+  (!TT.isOSAIX() || STI.getFeatureBits()[PPC::FeatureModernAIXAs])) {
 unsigned char TH = MI->getOperand(0).getImm();
 O << "\tdcbt";
 if (MI->getOpcode() == PPC::DCBTST)
___
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[PATCH] D111258: [PowerPC] Emit dcbt and dcbtst in place of their extended mnemonics on AIX

2021-10-06 Thread Nemanja Ivanovic via Phabricator via cfe-commits 
nemanjai added a comment.

Please change the condition as Jinsong suggested and change the leading comment 
to:

  // On AIX, only emit the extended mnemonics for dcbt and dcbtst if
  // the "modern assembler" is available.


Repository:
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[PATCH] D111258: [PowerPC] Emit dcbt and dcbtst in place of their extended mnemonics on AIX

2021-10-06 Thread Jinsong Ji via Phabricator via cfe-commits 
jsji accepted this revision as: jsji.
jsji added a comment.
This revision is now accepted and ready to land.

Thanks for working on this.




Comment at: llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp:161
   //  where th can be omitted when it is 0. dcbtst is the same.
-  if (MI->getOpcode() == PPC::DCBT || MI->getOpcode() == PPC::DCBTST) {
+  // TODO: AIX still requires dcbtt and dcbtstt implementation,
+  // remove AIX OS check when dcbtt and dcbtstt become available.

What do you mean by `still requires dcbtt and dcbtstt implementation`?



Comment at: llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp:164
+  if ((MI->getOpcode() == PPC::DCBT || MI->getOpcode() == PPC::DCBTST) &&
+  !TT.isOSAIX()) {
 unsigned char TH = MI->getOperand(0).getImm();

I think it is better to use the same condition as `ModernAs` Predicate , so 
that we may be able to enable it with feature bit if needed.
```
(!TT.isOSAIX() || STI.getFeatureBits()[PPC::HasModernAIXAs])
```


Repository:
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[PATCH] D111258: [PowerPC] Emit dcbt and dcbtst in place of their extended mnemonics on AIX

2021-10-06 Thread Albion Fung via Phabricator via cfe-commits 
Conanap created this revision.
Conanap added reviewers: nemanjai, jsji, PowerPC.
Conanap added projects: clang, LLVM, PowerPC.
Herald added subscribers: kbarton, hiraditya.
Conanap requested review of this revision.

On AIX, the system assembler does not support the extended mnemonics
`dcbtt` and `dcbtstt`. This patch stops them from being emitted on
AIX and emits the base mnemonics instead, `dcbt X, X, 16` and
`dcbtstt X, X, 16` respectively.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D111258

Files:
  llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-prefetch.ll


Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-prefetch.ll
===
--- llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-prefetch.ll
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-prefetch.ll
@@ -26,14 +26,14 @@
 ; CHECK-AIX:   # %bb.0: # %entry
 ; CHECK-AIX-NEXT:lwz 3, L..C0(2) # @vpa
 ; CHECK-AIX-NEXT:lwz 3, 0(3)
-; CHECK-AIX-NEXT:dcbtstt 0, 3
+; CHECK-AIX-NEXT:dcbtst 0, 3, 16
 ; CHECK-AIX-NEXT:blr
 ;
 ; CHECK-AIX64-LABEL: test_dcbtstt:
 ; CHECK-AIX64:   # %bb.0: # %entry
 ; CHECK-AIX64-NEXT:ld 3, L..C0(2) # @vpa
 ; CHECK-AIX64-NEXT:ld 3, 0(3)
-; CHECK-AIX64-NEXT:dcbtstt 0, 3
+; CHECK-AIX64-NEXT:dcbtst 0, 3, 16
 ; CHECK-AIX64-NEXT:blr
 entry:
   %0 = load i8*, i8** @vpa, align 8
@@ -55,14 +55,14 @@
 ; CHECK-AIX:   # %bb.0: # %entry
 ; CHECK-AIX-NEXT:lwz 3, L..C0(2) # @vpa
 ; CHECK-AIX-NEXT:lwz 3, 0(3)
-; CHECK-AIX-NEXT:dcbtt 0, 3
+; CHECK-AIX-NEXT:dcbt 0, 3, 16
 ; CHECK-AIX-NEXT:blr
 ;
 ; CHECK-AIX64-LABEL: test_dcbtt:
 ; CHECK-AIX64:   # %bb.0: # %entry
 ; CHECK-AIX64-NEXT:ld 3, L..C0(2) # @vpa
 ; CHECK-AIX64-NEXT:ld 3, 0(3)
-; CHECK-AIX64-NEXT:dcbtt 0, 3
+; CHECK-AIX64-NEXT:dcbt 0, 3, 16
 ; CHECK-AIX64-NEXT:blr
 entry:
   %0 = load i8*, i8** @vpa, align 8
Index: llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp
===
--- llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp
+++ llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp
@@ -158,7 +158,10 @@
   //dcbt ra, rb, th [server]
   //dcbt th, ra, rb [embedded]
   //  where th can be omitted when it is 0. dcbtst is the same.
-  if (MI->getOpcode() == PPC::DCBT || MI->getOpcode() == PPC::DCBTST) {
+  // TODO: AIX still requires dcbtt and dcbtstt implementation,
+  // remove AIX OS check when dcbtt and dcbtstt become available.
+  if ((MI->getOpcode() == PPC::DCBT || MI->getOpcode() == PPC::DCBTST) &&
+  !TT.isOSAIX()) {
 unsigned char TH = MI->getOperand(0).getImm();
 O << "\tdcbt";
 if (MI->getOpcode() == PPC::DCBTST)


Index: llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-prefetch.ll
===
--- llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-prefetch.ll
+++ llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-prefetch.ll
@@ -26,14 +26,14 @@
 ; CHECK-AIX:   # %bb.0: # %entry
 ; CHECK-AIX-NEXT:lwz 3, L..C0(2) # @vpa
 ; CHECK-AIX-NEXT:lwz 3, 0(3)
-; CHECK-AIX-NEXT:dcbtstt 0, 3
+; CHECK-AIX-NEXT:dcbtst 0, 3, 16
 ; CHECK-AIX-NEXT:blr
 ;
 ; CHECK-AIX64-LABEL: test_dcbtstt:
 ; CHECK-AIX64:   # %bb.0: # %entry
 ; CHECK-AIX64-NEXT:ld 3, L..C0(2) # @vpa
 ; CHECK-AIX64-NEXT:ld 3, 0(3)
-; CHECK-AIX64-NEXT:dcbtstt 0, 3
+; CHECK-AIX64-NEXT:dcbtst 0, 3, 16
 ; CHECK-AIX64-NEXT:blr
 entry:
   %0 = load i8*, i8** @vpa, align 8
@@ -55,14 +55,14 @@
 ; CHECK-AIX:   # %bb.0: # %entry
 ; CHECK-AIX-NEXT:lwz 3, L..C0(2) # @vpa
 ; CHECK-AIX-NEXT:lwz 3, 0(3)
-; CHECK-AIX-NEXT:dcbtt 0, 3
+; CHECK-AIX-NEXT:dcbt 0, 3, 16
 ; CHECK-AIX-NEXT:blr
 ;
 ; CHECK-AIX64-LABEL: test_dcbtt:
 ; CHECK-AIX64:   # %bb.0: # %entry
 ; CHECK-AIX64-NEXT:ld 3, L..C0(2) # @vpa
 ; CHECK-AIX64-NEXT:ld 3, 0(3)
-; CHECK-AIX64-NEXT:dcbtt 0, 3
+; CHECK-AIX64-NEXT:dcbt 0, 3, 16
 ; CHECK-AIX64-NEXT:blr
 entry:
   %0 = load i8*, i8** @vpa, align 8
Index: llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp
===
--- llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp
+++ llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp
@@ -158,7 +158,10 @@
   //dcbt ra, rb, th [server]
   //dcbt th, ra, rb [embedded]
   //  where th can be omitted when it is 0. dcbtst is the same.
-  if (MI->getOpcode() == PPC::DCBT || MI->getOpcode() == PPC::DCBTST) {
+  // TODO: AIX still requires dcbtt and dcbtstt implementation,
+  // remove AIX OS check when dcbtt and dcbtstt become available.
+  if ((MI->getOpcode() == PPC::DCBT || MI->getOpcode() == PPC::DCBTST) &&
+  !TT.isOSAIX()) {
 unsigned char TH = MI->getOperand(0).getImm();
 O << "\tdcbt";
 if (MI->getOpcode() == PPC::DCBTST)