[PATCH] D111434: [PowerPC] PPC backend optimization on conditional trap intrustions
This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rGae27ca9a6783: [PowerPC] PPC backend optimization on conditional trap intrustions (authored by NeHuang). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D111434/new/ https://reviews.llvm.org/D111434 Files: llvm/lib/Target/PowerPC/PPCMIPeephole.cpp llvm/test/CodeGen/PowerPC/mi-peepholes-trap-opt.mir Index: llvm/test/CodeGen/PowerPC/mi-peepholes-trap-opt.mir === --- /dev/null +++ llvm/test/CodeGen/PowerPC/mi-peepholes-trap-opt.mir @@ -0,0 +1,747 @@ +# RUN: llc -mtriple powerpc64le-unknown-linux-gnu -mcpu=pwr8 -x mir < %s \ +# RUN: -verify-machineinstrs -start-before=ppc-mi-peepholes | FileCheck %s + +--- +name:conditional_trap_opt_reg_implicit_def +alignment: 16 +tracksRegLiveness: true +body: | + bb.0.entry: +%0:gprc = IMPLICIT_DEF +%1:gprc = IMPLICIT_DEF +%2:g8rc = IMPLICIT_DEF +%3:g8rc = IMPLICIT_DEF +TW 8, %0, %1 +TD 8, %2, %3 +TWI 24, %0, 0 +TDI 24, %2, 0 +BLR8 implicit $lr8, implicit $rm +... + # CHECK-LABEL: conditional_trap_opt_reg_implicit_def + # CHECK: # %bb.0: # %entry + # CHECK-NEXT: twgt3, 3 + # CHECK-NEXT: tdgt3, 3 + # CHECK-NEXT: twnei 3, 0 + # CHECK-NEXT: tdnei 3, 0 + # CHECK-NEXT: blr + +--- +name:conditional_trap_opt_TW_31 +alignment: 16 +tracksRegLiveness: true +body: | + bb.0.entry: +%0:gprc = LI 3 +%1:gprc = LI 0 +TW 31, %1, %0 +BLR8 implicit $lr8, implicit $rm +... + # CHECK-LABEL: conditional_trap_opt_TW_31 + # CHECK: # %bb.0: # %entry + # CHECK-NEXT: trap + # CHECK-NEXT: blr + +--- +name:conditional_trap_opt_TW_24 +alignment: 16 +tracksRegLiveness: true +body: | + bb.0.entry: +%0:gprc = LI 3 +%1:gprc = LI 0 +TW 24, %1, %0 +BLR8 implicit $lr8, implicit $rm +... + # CHECK-LABEL: conditional_trap_opt_TW_24 + # CHECK: # %bb.0: # %entry + # CHECK-NEXT: trap + # CHECK-NEXT: blr + +--- +name:conditional_trap_opt_no_trap_TW_24 +alignment: 16 +tracksRegLiveness: true +body: | + bb.0.entry: +%0:gprc = LI 3 +%1:gprc = LI 3 +TW 24, %1, %0 +BLR8 implicit $lr8, implicit $rm +... + # CHECK-LABEL: conditional_trap_opt_no_trap_TW_24 + # CHECK: # %bb.0: # %entry + # CHECK-NEXT: blr + +--- +name:conditional_trap_opt_TW_20 +alignment: 16 +tracksRegLiveness: true +body: | + bb.0.entry: +%0:gprc = LI 3 +%1:gprc = LI 3 +TW 20, %1, %0 +BLR8 implicit $lr8, implicit $rm +... + # CHECK-LABEL: conditional_trap_opt_TW_20 + # CHECK: # %bb.0: # %entry + # CHECK-NEXT: trap + # CHECK-NEXT: blr + +--- +name:conditional_trap_opt_no_trap_TW_20 +alignment: 16 +tracksRegLiveness: true +body: | + bb.0.entry: +%0:gprc = LI 3 +%1:gprc = LI 5 +TW 20, %1, %0 +BLR8 implicit $lr8, implicit $rm +... + # CHECK-LABEL: conditional_trap_opt_no_trap_TW_20 + # CHECK: # %bb.0: # %entry + # CHECK-NEXT: blr + +--- +name:conditional_trap_opt_no_trap_TW_16 +alignment: 16 +tracksRegLiveness: true +body: | + bb.0.entry: +%0:gprc = LI 5 +%1:gprc = LI 1 +TW 16, %0, %1 +BLR8 implicit $lr8, implicit $rm +... + # CHECK-LABEL: conditional_trap_opt_no_trap_TW_16 + # CHECK: # %bb.0: # %entry + # CHECK-NEXT: blr + +--- +name:conditional_trap_opt_TW_16 +alignment: 16 +tracksRegLiveness: true +body: | + bb.0.entry: +%0:gprc = LI 5 +%1:gprc = LI 1 +TW 16, %1, %0 +TW 16, %0, %1 +BLR8 implicit $lr8, implicit $rm +... + # CHECK-LABEL: conditional_trap_opt_TW_16 + # CHECK: # %bb.0: # %entry + # CHECK-NEXT: trap + # CHECK-NEXT: blr + +--- +name:conditional_trap_opt_TW_8 +alignment: 16 +tracksRegLiveness: true +body: | + bb.0.entry: +%0:gprc = LI -1 +%1:gprc = LI 10 +TW 8, %1, %0 +TW 8, %0, %1 +BLR8 implicit $lr8, implicit $rm +... + # CHECK-LABEL: conditional_trap_opt_TW_8 + # CHECK: # %bb.0: # %entry + # CHECK-NEXT: trap + # CHECK-NEXT: blr + +--- +name:conditional_trap_opt_TW_2 +alignment: 16 +tracksRegLiveness: true +body: | + bb.0.entry: +%0:gprc = LI -1 +%1:gprc = LI 2 +TW 2, %1, %0 +TW 2, %0, %1 +BLR8 implicit $lr8, implicit $rm +... + # CHECK-LABEL: conditional_trap_opt_TW_2 + # CHECK: # %bb.0: # %entry + # CHECK-NEXT: trap + # CHECK-NEXT: blr + +--- +name:conditional_trap_opt_TW_1 +alignment: 16 +tracksRegLiveness: true +body: | + bb.0.entry: +%0:gprc = LI -3 +%1:gprc = LI 4 +TW 1, %1, %0 +TW 1, %0, %1 +BLR8 implicit $lr8, implicit $rm +... + # CHECK-LABEL:
[PATCH] D111434: [PowerPC] PPC backend optimization on conditional trap intrustions
amyk accepted this revision. amyk added a comment. Thanks for addressing the review comments and answering my question. This LGTM. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D111434/new/ https://reviews.llvm.org/D111434 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D111434: [PowerPC] PPC backend optimization on conditional trap intrustions
NeHuang updated this revision to Diff 387652. NeHuang added a comment. Addressed review comments Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D111434/new/ https://reviews.llvm.org/D111434 Files: llvm/lib/Target/PowerPC/PPCMIPeephole.cpp llvm/test/CodeGen/PowerPC/mi-peepholes-trap-opt.mir Index: llvm/test/CodeGen/PowerPC/mi-peepholes-trap-opt.mir === --- /dev/null +++ llvm/test/CodeGen/PowerPC/mi-peepholes-trap-opt.mir @@ -0,0 +1,747 @@ +# RUN: llc -mtriple powerpc64le-unknown-linux-gnu -mcpu=pwr8 -x mir < %s \ +# RUN: -verify-machineinstrs -start-before=ppc-mi-peepholes | FileCheck %s + +--- +name:conditional_trap_opt_reg_implicit_def +alignment: 16 +tracksRegLiveness: true +body: | + bb.0.entry: +%0:gprc = IMPLICIT_DEF +%1:gprc = IMPLICIT_DEF +%2:g8rc = IMPLICIT_DEF +%3:g8rc = IMPLICIT_DEF +TW 8, %0, %1 +TD 8, %2, %3 +TWI 24, %0, 0 +TDI 24, %2, 0 +BLR8 implicit $lr8, implicit $rm +... + # CHECK-LABEL: conditional_trap_opt_reg_implicit_def + # CHECK: # %bb.0: # %entry + # CHECK-NEXT: twgt3, 3 + # CHECK-NEXT: tdgt3, 3 + # CHECK-NEXT: twnei 3, 0 + # CHECK-NEXT: tdnei 3, 0 + # CHECK-NEXT: blr + +--- +name:conditional_trap_opt_TW_31 +alignment: 16 +tracksRegLiveness: true +body: | + bb.0.entry: +%0:gprc = LI 3 +%1:gprc = LI 0 +TW 31, %1, %0 +BLR8 implicit $lr8, implicit $rm +... + # CHECK-LABEL: conditional_trap_opt_TW_31 + # CHECK: # %bb.0: # %entry + # CHECK-NEXT: trap + # CHECK-NEXT: blr + +--- +name:conditional_trap_opt_TW_24 +alignment: 16 +tracksRegLiveness: true +body: | + bb.0.entry: +%0:gprc = LI 3 +%1:gprc = LI 0 +TW 24, %1, %0 +BLR8 implicit $lr8, implicit $rm +... + # CHECK-LABEL: conditional_trap_opt_TW_24 + # CHECK: # %bb.0: # %entry + # CHECK-NEXT: trap + # CHECK-NEXT: blr + +--- +name:conditional_trap_opt_no_trap_TW_24 +alignment: 16 +tracksRegLiveness: true +body: | + bb.0.entry: +%0:gprc = LI 3 +%1:gprc = LI 3 +TW 24, %1, %0 +BLR8 implicit $lr8, implicit $rm +... + # CHECK-LABEL: conditional_trap_opt_no_trap_TW_24 + # CHECK: # %bb.0: # %entry + # CHECK-NEXT: blr + +--- +name:conditional_trap_opt_TW_20 +alignment: 16 +tracksRegLiveness: true +body: | + bb.0.entry: +%0:gprc = LI 3 +%1:gprc = LI 3 +TW 20, %1, %0 +BLR8 implicit $lr8, implicit $rm +... + # CHECK-LABEL: conditional_trap_opt_TW_20 + # CHECK: # %bb.0: # %entry + # CHECK-NEXT: trap + # CHECK-NEXT: blr + +--- +name:conditional_trap_opt_no_trap_TW_20 +alignment: 16 +tracksRegLiveness: true +body: | + bb.0.entry: +%0:gprc = LI 3 +%1:gprc = LI 5 +TW 20, %1, %0 +BLR8 implicit $lr8, implicit $rm +... + # CHECK-LABEL: conditional_trap_opt_no_trap_TW_20 + # CHECK: # %bb.0: # %entry + # CHECK-NEXT: blr + +--- +name:conditional_trap_opt_no_trap_TW_16 +alignment: 16 +tracksRegLiveness: true +body: | + bb.0.entry: +%0:gprc = LI 5 +%1:gprc = LI 1 +TW 16, %0, %1 +BLR8 implicit $lr8, implicit $rm +... + # CHECK-LABEL: conditional_trap_opt_no_trap_TW_16 + # CHECK: # %bb.0: # %entry + # CHECK-NEXT: blr + +--- +name:conditional_trap_opt_TW_16 +alignment: 16 +tracksRegLiveness: true +body: | + bb.0.entry: +%0:gprc = LI 5 +%1:gprc = LI 1 +TW 16, %1, %0 +TW 16, %0, %1 +BLR8 implicit $lr8, implicit $rm +... + # CHECK-LABEL: conditional_trap_opt_TW_16 + # CHECK: # %bb.0: # %entry + # CHECK-NEXT: trap + # CHECK-NEXT: blr + +--- +name:conditional_trap_opt_TW_8 +alignment: 16 +tracksRegLiveness: true +body: | + bb.0.entry: +%0:gprc = LI -1 +%1:gprc = LI 10 +TW 8, %1, %0 +TW 8, %0, %1 +BLR8 implicit $lr8, implicit $rm +... + # CHECK-LABEL: conditional_trap_opt_TW_8 + # CHECK: # %bb.0: # %entry + # CHECK-NEXT: trap + # CHECK-NEXT: blr + +--- +name:conditional_trap_opt_TW_2 +alignment: 16 +tracksRegLiveness: true +body: | + bb.0.entry: +%0:gprc = LI -1 +%1:gprc = LI 2 +TW 2, %1, %0 +TW 2, %0, %1 +BLR8 implicit $lr8, implicit $rm +... + # CHECK-LABEL: conditional_trap_opt_TW_2 + # CHECK: # %bb.0: # %entry + # CHECK-NEXT: trap + # CHECK-NEXT: blr + +--- +name:conditional_trap_opt_TW_1 +alignment: 16 +tracksRegLiveness: true +body: | + bb.0.entry: +%0:gprc = LI -3 +%1:gprc = LI 4 +TW 1, %1, %0 +TW 1, %0, %1 +BLR8 implicit $lr8, implicit $rm +... + # CHECK-LABEL: conditional_trap_opt_TW_1 + # CHECK: # %bb.0: # %entry + # CHECK-NEXT: trap + # CHECK-NEXT: blr + +--- +name:conditional_trap_opt_TW_4 +alignment:
[PATCH] D111434: [PowerPC] PPC backend optimization on conditional trap intrustions
NeHuang marked 7 inline comments as done. NeHuang added inline comments. Comment at: llvm/lib/Target/PowerPC/PPCMIPeephole.cpp:1020 +// We can only do the optimization for the "reg + reg" form. +if (!(LiMI1 && (Opcode1 == PPC::LI || Opcode1 == PPC::LI8))) + break; amyk wrote: > Do we still need to take into account of the lis+ori that Nemanja mentioned? IIUC, the optimization will be triggered if the immediate is a s16Immediate. We had the similar check and conversion in this patch https://reviews.llvm.org/D112285 Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D111434/new/ https://reviews.llvm.org/D111434 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D111434: [PowerPC] PPC backend optimization on conditional trap intrustions
nemanjai accepted this revision. nemanjai added a comment. This revision is now accepted and ready to land. LGTM. There are some very minor nits that can be addressed on the commit. Comment at: llvm/lib/Target/PowerPC/PPCMIPeephole.cpp:1018 +unsigned Opcode2 = LiMI2->getOpcode(); +bool isOperand2Immeidate = MI.getOperand(2).isImm(); +// We can only do the optimization for the "reg + reg" form. amyk wrote: > Nit: naming convention - variables start with uppercase letters. Comment at: llvm/lib/Target/PowerPC/PPCMIPeephole.cpp:1019 +bool isOperand2Immeidate = MI.getOperand(2).isImm(); +// We can only do the optimization for the "reg + reg" form. +if (!(LiMI1 && (Opcode1 == PPC::LI || Opcode1 == PPC::LI8))) I don't understand this comment. You say we can only do the optimization for the "reg + reg" form but the second condition is actually for the "reg + imm" form. Comment at: llvm/test/CodeGen/PowerPC/mi-peepholes-trap-opt.mir:5 +--- +name:conditional_trap_opt_reg_implicit_def +alignment: 16 Please add a couple more tests: 1. Test case where we delete the instruction because it won't trap 2. Test case(s) where we do some combination of comparisons (NE(24): `<>`, LE(20): `<=`, etc.) Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D111434/new/ https://reviews.llvm.org/D111434 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D111434: [PowerPC] PPC backend optimization on conditional trap intrustions
amyk added inline comments. Comment at: llvm/lib/Target/PowerPC/PPCMIPeephole.cpp:1018 +unsigned Opcode2 = LiMI2->getOpcode(); +bool isOperand2Immeidate = MI.getOperand(2).isImm(); +// We can only do the optimization for the "reg + reg" form. Comment at: llvm/lib/Target/PowerPC/PPCMIPeephole.cpp:1020 +// We can only do the optimization for the "reg + reg" form. +if (!(LiMI1 && (Opcode1 == PPC::LI || Opcode1 == PPC::LI8))) + break; Do we still need to take into account of the lis+ori that Nemanja mentioned? Comment at: llvm/lib/Target/PowerPC/PPCMIPeephole.cpp:1022 + break; +if (!isOperand2Immeidate && +!(LiMI2 && (Opcode2 == PPC::LI || Opcode2 == PPC::LI8))) Comment at: llvm/lib/Target/PowerPC/PPCMIPeephole.cpp:1028 +auto ImmOperand1 = LiMI1->getOperand(1).getImm(); +auto ImmOperand2 = isOperand2Immeidate ? MI.getOperand(2).getImm() + : LiMI2->getOperand(1).getImm(); Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D111434/new/ https://reviews.llvm.org/D111434 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D111434: [PowerPC] PPC backend optimization on conditional trap intrustions
NeHuang updated this revision to Diff 385282. NeHuang marked 3 inline comments as done. NeHuang added a comment. Address review comments Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D111434/new/ https://reviews.llvm.org/D111434 Files: llvm/lib/Target/PowerPC/PPCMIPeephole.cpp llvm/test/CodeGen/PowerPC/mi-peepholes-trap-opt.mir Index: llvm/test/CodeGen/PowerPC/mi-peepholes-trap-opt.mir === --- /dev/null +++ llvm/test/CodeGen/PowerPC/mi-peepholes-trap-opt.mir @@ -0,0 +1,448 @@ +# RUN: llc -mtriple powerpc64le-unknown-linux-gnu -mcpu=pwr8 -x mir < %s \ +# RUN: -verify-machineinstrs -start-before=ppc-mi-peepholes | FileCheck %s + +--- +name:conditional_trap_opt_reg_implicit_def +alignment: 16 +tracksRegLiveness: true +body: | + bb.0.entry: +%0:gprc = IMPLICIT_DEF +%1:gprc = IMPLICIT_DEF +%2:g8rc = IMPLICIT_DEF +%3:g8rc = IMPLICIT_DEF +TW 8, %0, %1 +TD 8, %2, %3 +TWI 24, %0, 0 +TDI 24, %2, 0 +BLR8 implicit $lr8, implicit $rm +... + # CHECK-LABEL: conditional_trap_opt_reg_implicit_def + # CHECK: # %bb.0: # %entry + # CHECK-NEXT: twgt3, 3 + # CHECK-NEXT: tdgt3, 3 + # CHECK-NEXT: twnei 3, 0 + # CHECK-NEXT: tdnei 3, 0 + # CHECK-NEXT: blr +--- +name:conditional_trap_opt_TW_31 +alignment: 16 +tracksRegLiveness: true +body: | + bb.0.entry: +%0:gprc = LI 3 +%1:gprc = LI 0 +TW 31, %1, %0 +BLR8 implicit $lr8, implicit $rm +... + # CHECK-LABEL: conditional_trap_opt_TW_31 + # CHECK: # %bb.0: # %entry + # CHECK-NEXT: trap + # CHECK-NEXT: blr + +--- +name:conditional_trap_opt_TW_16 +alignment: 16 +tracksRegLiveness: true +body: | + bb.0.entry: +%0:gprc = LI 5 +%1:gprc = LI 1 +TW 16, %1, %0 +TW 16, %0, %1 +BLR8 implicit $lr8, implicit $rm +... + # CHECK-LABEL: conditional_trap_opt_TW_16 + # CHECK: # %bb.0: # %entry + # CHECK-NEXT: trap + # CHECK-NEXT: blr + +--- +name:conditional_trap_opt_TW_8 +alignment: 16 +tracksRegLiveness: true +body: | + bb.0.entry: +%0:gprc = LI -1 +%1:gprc = LI 10 +TW 8, %1, %0 +TW 8, %0, %1 +BLR8 implicit $lr8, implicit $rm +... + # CHECK-LABEL: conditional_trap_opt_TW_8 + # CHECK: # %bb.0: # %entry + # CHECK-NEXT: trap + # CHECK-NEXT: blr + +--- +name:conditional_trap_opt_TW_2 +alignment: 16 +tracksRegLiveness: true +body: | + bb.0.entry: +%0:gprc = LI -1 +%1:gprc = LI 2 +TW 2, %1, %0 +TW 2, %0, %1 +BLR8 implicit $lr8, implicit $rm +... + # CHECK-LABEL: conditional_trap_opt_TW_2 + # CHECK: # %bb.0: # %entry + # CHECK-NEXT: trap + # CHECK-NEXT: blr + +--- +name:conditional_trap_opt_TW_1 +alignment: 16 +tracksRegLiveness: true +body: | + bb.0.entry: +%0:gprc = LI -3 +%1:gprc = LI 4 +TW 1, %1, %0 +TW 1, %0, %1 +BLR8 implicit $lr8, implicit $rm +... + # CHECK-LABEL: conditional_trap_opt_TW_1 + # CHECK: # %bb.0: # %entry + # CHECK-NEXT: trap + # CHECK-NEXT: blr + +--- +name:conditional_trap_opt_TW_4 +alignment: 16 +tracksRegLiveness: true +body: | + bb.0.entry: +%0:gprc = LI 5 +%1:gprc = LI 1 +TW 4, %1, %0 +TW 4, %1, %1 +BLR8 implicit $lr8, implicit $rm +... + # CHECK-LABEL: conditional_trap_opt_TW_4 + # CHECK: # %bb.0: # %entry + # CHECK-NEXT: trap + # CHECK-NEXT: blr + +--- +name:conditional_trap_opt_TWI_31 +alignment: 16 +tracksRegLiveness: true +body: | + bb.0.entry: +%0:gprc = LI 3 +TWI 31, %0, 0 +BLR8 implicit $lr8, implicit $rm +... + # CHECK-LABEL: conditional_trap_opt_TWI_31 + # CHECK: # %bb.0: # %entry + # CHECK-NEXT: trap + # CHECK-NEXT: blr + +--- +name:conditional_trap_opt_TWI_16 +alignment: 16 +tracksRegLiveness: true +body: | + bb.0.entry: +%0:gprc = LI 5 +%1:gprc = LI 1 +TWI 16, %1, 5 +TWI 16, %0, 1 +BLR8 implicit $lr8, implicit $rm +... + # CHECK-LABEL: conditional_trap_opt_TWI_16 + # CHECK: # %bb.0: # %entry + # CHECK-NEXT: trap + # CHECK-NEXT: blr + +--- +name:conditional_trap_opt_TWI_8 +alignment: 16 +tracksRegLiveness: true +body: | + bb.0.entry: +%0:gprc = LI -1 +%1:gprc = LI 10 +TWI 8, %1, -1 +TWI 8, %0, 10 +BLR8 implicit $lr8, implicit $rm +... + # CHECK-LABEL: conditional_trap_opt_TWI_8 + # CHECK: # %bb.0: # %entry + # CHECK-NEXT: trap + # CHECK-NEXT: blr + +--- +name:conditional_trap_opt_TWI_2 +alignment: 16 +tracksRegLiveness: true +body: | + bb.0.entry: +%0:gprc = LI -1 +%1:gprc = LI 2 +TWI 2, %1, -1 +TWI 2, %0, 2 +BLR8 implicit $lr8, implicit $rm +... + # CHECK-LABEL: conditional_trap_opt_TWI_2 + # CHECK: # %bb.0: #
[PATCH] D111434: [PowerPC] PPC backend optimization on conditional trap intrustions
amyk added inline comments.
Comment at: llvm/lib/Target/PowerPC/PPCMIPeephole.cpp:1011
+ case PPC::TDI:
+ case PPC::TWI: {
+MachineInstr *LiMIA = getVRegDefOrNull((1), MRI);
nemanjai wrote:
> Seems that we should be able to handle all 4 in the same block:
> - Check that both operands are `LI[8]`/`LI[S][8]+ORI[8]` or an immediate
> - Set the variables for the three constants
> - Determine if this is an unconditional trap or never trap
> - Emit the correct instruction
+1
Comment at: llvm/lib/Target/PowerPC/PPCMIPeephole.cpp:1013
+MachineInstr *LiMIA = getVRegDefOrNull((1), MRI);
+// will not optimize if no value set
+if (!(LiMIA && (LiMIA->getOpcode() == PPC::LI ||
nit: Capitalize and add a period (and for all other comments).
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[PATCH] D111434: [PowerPC] PPC backend optimization on conditional trap intrustions
nemanjai added inline comments.
Comment at: llvm/lib/Target/PowerPC/PPCMIPeephole.cpp:1011
+ case PPC::TDI:
+ case PPC::TWI: {
+MachineInstr *LiMIA = getVRegDefOrNull((1), MRI);
Seems that we should be able to handle all 4 in the same block:
- Check that both operands are `LI[8]`/`LI[S][8]+ORI[8]` or an immediate
- Set the variables for the three constants
- Determine if this is an unconditional trap or never trap
- Emit the correct instruction
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[PATCH] D111434: [PowerPC] PPC backend optimization on conditional trap intrustions
NeHuang added a comment. gentle ping Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D111434/new/ https://reviews.llvm.org/D111434 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D111434: [PowerPC] PPC backend optimization on conditional trap intrustions
NeHuang added a comment. gentle ping Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D111434/new/ https://reviews.llvm.org/D111434 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D111434: [PowerPC] PPC backend optimization on conditional trap intrustions
NeHuang updated this revision to Diff 378284. NeHuang added a comment. clang-format Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D111434/new/ https://reviews.llvm.org/D111434 Files: llvm/lib/Target/PowerPC/PPCMIPeephole.cpp llvm/test/CodeGen/PowerPC/mi-peepholes-trap-opt.mir Index: llvm/test/CodeGen/PowerPC/mi-peepholes-trap-opt.mir === --- /dev/null +++ llvm/test/CodeGen/PowerPC/mi-peepholes-trap-opt.mir @@ -0,0 +1,448 @@ +# RUN: llc -mtriple powerpc64le-unknown-linux-gnu -mcpu=pwr8 -x mir < %s \ +# RUN: -verify-machineinstrs -start-before=ppc-mi-peepholes | FileCheck %s + +--- +name:conditional_trap_opt_reg_implicit_def +alignment: 16 +tracksRegLiveness: true +body: | + bb.0.entry: +%0:gprc = IMPLICIT_DEF +%1:gprc = IMPLICIT_DEF +%2:g8rc = IMPLICIT_DEF +%3:g8rc = IMPLICIT_DEF +TW 8, %0, %1 +TD 8, %2, %3 +TWI 24, %0, 0 +TDI 24, %2, 0 +BLR8 implicit $lr8, implicit $rm +... + # CHECK-LABEL: conditional_trap_opt_reg_implicit_def + # CHECK: # %bb.0: # %entry + # CHECK-NEXT: twgt3, 3 + # CHECK-NEXT: tdgt3, 3 + # CHECK-NEXT: twnei 3, 0 + # CHECK-NEXT: tdnei 3, 0 + # CHECK-NEXT: blr +--- +name:conditional_trap_opt_TW_31 +alignment: 16 +tracksRegLiveness: true +body: | + bb.0.entry: +%0:gprc = LI 3 +%1:gprc = LI 0 +TW 31, %1, %0 +BLR8 implicit $lr8, implicit $rm +... + # CHECK-LABEL: conditional_trap_opt_TW_31 + # CHECK: # %bb.0: # %entry + # CHECK-NEXT: trap + # CHECK-NEXT: blr + +--- +name:conditional_trap_opt_TW_16 +alignment: 16 +tracksRegLiveness: true +body: | + bb.0.entry: +%0:gprc = LI 5 +%1:gprc = LI 1 +TW 16, %1, %0 +TW 16, %0, %1 +BLR8 implicit $lr8, implicit $rm +... + # CHECK-LABEL: conditional_trap_opt_TW_16 + # CHECK: # %bb.0: # %entry + # CHECK-NEXT: trap + # CHECK-NEXT: blr + +--- +name:conditional_trap_opt_TW_8 +alignment: 16 +tracksRegLiveness: true +body: | + bb.0.entry: +%0:gprc = LI -1 +%1:gprc = LI 10 +TW 8, %1, %0 +TW 8, %0, %1 +BLR8 implicit $lr8, implicit $rm +... + # CHECK-LABEL: conditional_trap_opt_TW_8 + # CHECK: # %bb.0: # %entry + # CHECK-NEXT: trap + # CHECK-NEXT: blr + +--- +name:conditional_trap_opt_TW_2 +alignment: 16 +tracksRegLiveness: true +body: | + bb.0.entry: +%0:gprc = LI -1 +%1:gprc = LI 2 +TW 2, %1, %0 +TW 2, %0, %1 +BLR8 implicit $lr8, implicit $rm +... + # CHECK-LABEL: conditional_trap_opt_TW_2 + # CHECK: # %bb.0: # %entry + # CHECK-NEXT: trap + # CHECK-NEXT: blr + +--- +name:conditional_trap_opt_TW_1 +alignment: 16 +tracksRegLiveness: true +body: | + bb.0.entry: +%0:gprc = LI -3 +%1:gprc = LI 4 +TW 1, %1, %0 +TW 1, %0, %1 +BLR8 implicit $lr8, implicit $rm +... + # CHECK-LABEL: conditional_trap_opt_TW_1 + # CHECK: # %bb.0: # %entry + # CHECK-NEXT: trap + # CHECK-NEXT: blr + +--- +name:conditional_trap_opt_TW_4 +alignment: 16 +tracksRegLiveness: true +body: | + bb.0.entry: +%0:gprc = LI 5 +%1:gprc = LI 1 +TW 4, %1, %0 +TW 4, %1, %1 +BLR8 implicit $lr8, implicit $rm +... + # CHECK-LABEL: conditional_trap_opt_TW_4 + # CHECK: # %bb.0: # %entry + # CHECK-NEXT: trap + # CHECK-NEXT: blr + +--- +name:conditional_trap_opt_TWI_31 +alignment: 16 +tracksRegLiveness: true +body: | + bb.0.entry: +%0:gprc = LI 3 +TWI 31, %0, 0 +BLR8 implicit $lr8, implicit $rm +... + # CHECK-LABEL: conditional_trap_opt_TWI_31 + # CHECK: # %bb.0: # %entry + # CHECK-NEXT: trap + # CHECK-NEXT: blr + +--- +name:conditional_trap_opt_TWI_16 +alignment: 16 +tracksRegLiveness: true +body: | + bb.0.entry: +%0:gprc = LI 5 +%1:gprc = LI 1 +TWI 16, %1, 5 +TWI 16, %0, 1 +BLR8 implicit $lr8, implicit $rm +... + # CHECK-LABEL: conditional_trap_opt_TWI_16 + # CHECK: # %bb.0: # %entry + # CHECK-NEXT: trap + # CHECK-NEXT: blr + +--- +name:conditional_trap_opt_TWI_8 +alignment: 16 +tracksRegLiveness: true +body: | + bb.0.entry: +%0:gprc = LI -1 +%1:gprc = LI 10 +TWI 8, %1, -1 +TWI 8, %0, 10 +BLR8 implicit $lr8, implicit $rm +... + # CHECK-LABEL: conditional_trap_opt_TWI_8 + # CHECK: # %bb.0: # %entry + # CHECK-NEXT: trap + # CHECK-NEXT: blr + +--- +name:conditional_trap_opt_TWI_2 +alignment: 16 +tracksRegLiveness: true +body: | + bb.0.entry: +%0:gprc = LI -1 +%1:gprc = LI 2 +TWI 2, %1, -1 +TWI 2, %0, 2 +BLR8 implicit $lr8, implicit $rm +... + # CHECK-LABEL: conditional_trap_opt_TWI_2 + # CHECK: # %bb.0: # %entry + # CHECK-NEXT: trap + # CHECK-NEXT: blr + +---
[PATCH] D111434: [PowerPC] PPC backend optimization on conditional trap intrustions
NeHuang created this revision. NeHuang added reviewers: nemanjai, stefanp, PowerPC. NeHuang added projects: LLVM, PowerPC. Herald added subscribers: shchenz, JDevlieghere, kbarton, hiraditya. NeHuang requested review of this revision. This patch adds PPC back end optimization to analyze the arguments of a conditional trap instruction to execute one of the following - Delete it if the condition is never true - Replace it with an unconditional trap if the condition is always true - Otherwise keep it Repository: rG LLVM Github Monorepo https://reviews.llvm.org/D111434 Files: llvm/lib/Target/PowerPC/PPCMIPeephole.cpp llvm/test/CodeGen/PowerPC/mi-peepholes-trap-opt.mir Index: llvm/test/CodeGen/PowerPC/mi-peepholes-trap-opt.mir === --- /dev/null +++ llvm/test/CodeGen/PowerPC/mi-peepholes-trap-opt.mir @@ -0,0 +1,448 @@ +# RUN: llc -mtriple powerpc64le-unknown-linux-gnu -mcpu=pwr8 -x mir < %s \ +# RUN: -verify-machineinstrs -start-before=ppc-mi-peepholes | FileCheck %s + +--- +name:conditional_trap_opt_reg_implicit_def +alignment: 16 +tracksRegLiveness: true +body: | + bb.0.entry: +%0:gprc = IMPLICIT_DEF +%1:gprc = IMPLICIT_DEF +%2:g8rc = IMPLICIT_DEF +%3:g8rc = IMPLICIT_DEF +TW 8, %0, %1 +TD 8, %2, %3 +TWI 24, %0, 0 +TDI 24, %2, 0 +BLR8 implicit $lr8, implicit $rm +... + # CHECK-LABEL: conditional_trap_opt_reg_implicit_def + # CHECK: # %bb.0: # %entry + # CHECK-NEXT: twgt3, 3 + # CHECK-NEXT: tdgt3, 3 + # CHECK-NEXT: twnei 3, 0 + # CHECK-NEXT: tdnei 3, 0 + # CHECK-NEXT: blr +--- +name:conditional_trap_opt_TW_31 +alignment: 16 +tracksRegLiveness: true +body: | + bb.0.entry: +%0:gprc = LI 3 +%1:gprc = LI 0 +TW 31, %1, %0 +BLR8 implicit $lr8, implicit $rm +... + # CHECK-LABEL: conditional_trap_opt_TW_31 + # CHECK: # %bb.0: # %entry + # CHECK-NEXT: trap + # CHECK-NEXT: blr + +--- +name:conditional_trap_opt_TW_16 +alignment: 16 +tracksRegLiveness: true +body: | + bb.0.entry: +%0:gprc = LI 5 +%1:gprc = LI 1 +TW 16, %1, %0 +TW 16, %0, %1 +BLR8 implicit $lr8, implicit $rm +... + # CHECK-LABEL: conditional_trap_opt_TW_16 + # CHECK: # %bb.0: # %entry + # CHECK-NEXT: trap + # CHECK-NEXT: blr + +--- +name:conditional_trap_opt_TW_8 +alignment: 16 +tracksRegLiveness: true +body: | + bb.0.entry: +%0:gprc = LI -1 +%1:gprc = LI 10 +TW 8, %1, %0 +TW 8, %0, %1 +BLR8 implicit $lr8, implicit $rm +... + # CHECK-LABEL: conditional_trap_opt_TW_8 + # CHECK: # %bb.0: # %entry + # CHECK-NEXT: trap + # CHECK-NEXT: blr + +--- +name:conditional_trap_opt_TW_2 +alignment: 16 +tracksRegLiveness: true +body: | + bb.0.entry: +%0:gprc = LI -1 +%1:gprc = LI 2 +TW 2, %1, %0 +TW 2, %0, %1 +BLR8 implicit $lr8, implicit $rm +... + # CHECK-LABEL: conditional_trap_opt_TW_2 + # CHECK: # %bb.0: # %entry + # CHECK-NEXT: trap + # CHECK-NEXT: blr + +--- +name:conditional_trap_opt_TW_1 +alignment: 16 +tracksRegLiveness: true +body: | + bb.0.entry: +%0:gprc = LI -3 +%1:gprc = LI 4 +TW 1, %1, %0 +TW 1, %0, %1 +BLR8 implicit $lr8, implicit $rm +... + # CHECK-LABEL: conditional_trap_opt_TW_1 + # CHECK: # %bb.0: # %entry + # CHECK-NEXT: trap + # CHECK-NEXT: blr + +--- +name:conditional_trap_opt_TW_4 +alignment: 16 +tracksRegLiveness: true +body: | + bb.0.entry: +%0:gprc = LI 5 +%1:gprc = LI 1 +TW 4, %1, %0 +TW 4, %1, %1 +BLR8 implicit $lr8, implicit $rm +... + # CHECK-LABEL: conditional_trap_opt_TW_4 + # CHECK: # %bb.0: # %entry + # CHECK-NEXT: trap + # CHECK-NEXT: blr + +--- +name:conditional_trap_opt_TWI_31 +alignment: 16 +tracksRegLiveness: true +body: | + bb.0.entry: +%0:gprc = LI 3 +TWI 31, %0, 0 +BLR8 implicit $lr8, implicit $rm +... + # CHECK-LABEL: conditional_trap_opt_TWI_31 + # CHECK: # %bb.0: # %entry + # CHECK-NEXT: trap + # CHECK-NEXT: blr + +--- +name:conditional_trap_opt_TWI_16 +alignment: 16 +tracksRegLiveness: true +body: | + bb.0.entry: +%0:gprc = LI 5 +%1:gprc = LI 1 +TWI 16, %1, 5 +TWI 16, %0, 1 +BLR8 implicit $lr8, implicit $rm +... + # CHECK-LABEL: conditional_trap_opt_TWI_16 + # CHECK: # %bb.0: # %entry + # CHECK-NEXT: trap + # CHECK-NEXT: blr + +--- +name:conditional_trap_opt_TWI_8 +alignment: 16 +tracksRegLiveness: true +body: | + bb.0.entry: +%0:gprc = LI -1 +%1:gprc = LI 10 +TWI 8, %1, -1 +TWI 8, %0, 10 +BLR8 implicit $lr8, implicit $rm +... + # CHECK-LABEL: conditional_trap_opt_TWI_8 + # CHECK: # %bb.0: # %entry + # CHECK-NEXT: trap + # CHECK-NEXT: blr + +--- +name:
