[PATCH] D111517: [X86] Remove little support we had for MPX
This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rGc2d4fe51bb4f: [X86] Remove little support we had for MPX (authored by MaskRay). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D111517/new/ https://reviews.llvm.org/D111517 Files: clang/test/CodeGen/ms-inline-asm.c llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoder.h llvm/lib/Target/X86/X86InstrInfo.cpp llvm/lib/Target/X86/X86InstrInfo.td llvm/lib/Target/X86/X86InstrMPX.td llvm/lib/Target/X86/X86RegisterInfo.td llvm/test/CodeGen/X86/ipra-reg-usage.ll llvm/test/MC/X86/mpx-encodings.s llvm/unittests/tools/llvm-exegesis/X86/SnippetGeneratorTest.cpp Index: llvm/unittests/tools/llvm-exegesis/X86/SnippetGeneratorTest.cpp === --- llvm/unittests/tools/llvm-exegesis/X86/SnippetGeneratorTest.cpp +++ llvm/unittests/tools/llvm-exegesis/X86/SnippetGeneratorTest.cpp @@ -213,26 +213,6 @@ ASSERT_TRUE(BC.Key.Instructions[0].getOperand(3).isImm()); } -TEST_F(X86ParallelSnippetGeneratorTest, ParallelInstruction) { - // - BNDCL32rr - // - Op0 Explicit Use RegClass(BNDR) - // - Op1 Explicit Use RegClass(GR32) - // - Var0 [Op0] - // - Var1 [Op1] - const unsigned Opcode = X86::BNDCL32rr; - const auto CodeTemplates = checkAndGetCodeTemplates(Opcode); - ASSERT_THAT(CodeTemplates, SizeIs(1)); - const auto = CodeTemplates[0]; - EXPECT_THAT(CT.Info, HasSubstr("parallel")); - EXPECT_THAT(CT.Execution, ExecutionMode::UNKNOWN); - ASSERT_THAT(CT.Instructions, SizeIs(1)); - const InstructionTemplate = CT.Instructions[0]; - EXPECT_THAT(IT.getOpcode(), Opcode); - ASSERT_THAT(IT.getVariableValues(), SizeIs(2)); - EXPECT_THAT(IT.getVariableValues()[0], IsInvalid()); - EXPECT_THAT(IT.getVariableValues()[1], IsInvalid()); -} - TEST_F(X86ParallelSnippetGeneratorTest, SerialInstruction) { // - CDQ // - Op0 Implicit Def Reg(EAX) Index: llvm/test/MC/X86/mpx-encodings.s === --- llvm/test/MC/X86/mpx-encodings.s +++ /dev/null @@ -1,41 +0,0 @@ -// RUN: llvm-mc -triple x86_64-- --show-encoding %s |\ -// RUN: FileCheck %s --check-prefixes=CHECK,ENCODING - -// RUN: llvm-mc -triple x86_64-- -filetype=obj %s |\ -// RUN: llvm-objdump -d - | FileCheck %s - -// CHECK: bndmk (%rax), %bnd0 -// ENCODING: encoding: [0xf3,0x0f,0x1b,0x00] -bndmk (%rax), %bnd0 - -// CHECK: bndmk 1024(%rax), %bnd1 -// ENCODING: encoding: [0xf3,0x0f,0x1b,0x88,0x00,0x04,0x00,0x00] -bndmk 1024(%rax), %bnd1 - -// CHECK: bndmov %bnd2, %bnd1 -// ENCODING: encoding: [0x66,0x0f,0x1a,0xca] -bndmov %bnd2, %bnd1 - -// CHECK: bndmov %bnd1, 1024(%r9) -// ENCODING: encoding: [0x66,0x41,0x0f,0x1b,0x89,0x00,0x04,0x00,0x00] -bndmov %bnd1, 1024(%r9) - -// CHECK: bndstx %bnd1, 1024(%rax) -// ENCODING: encoding: [0x0f,0x1b,0x88,0x00,0x04,0x00,0x00] -bndstx %bnd1, 1024(%rax) - -// CHECK: bndldx 1024(%r8), %bnd1 -// ENCODING: encoding: [0x41,0x0f,0x1a,0x88,0x00,0x04,0x00,0x00] -bndldx 1024(%r8), %bnd1 - -// CHECK: bndcl 121(%r10), %bnd1 -// ENCODING: encoding: [0xf3,0x41,0x0f,0x1a,0x4a,0x79] -bndcl 121(%r10), %bnd1 - -// CHECK: bndcn 121(%rcx), %bnd3 -// ENCODING: encoding: [0xf2,0x0f,0x1b,0x59,0x79] -bndcn 121(%rcx), %bnd3 - -// CHECK: bndcu %rdx, %bnd3 -// ENCODING: encoding: [0xf2,0x0f,0x1a,0xda] -bndcu %rdx, %bnd3 Index: llvm/test/CodeGen/X86/ipra-reg-usage.ll === --- llvm/test/CodeGen/X86/ipra-reg-usage.ll +++ llvm/test/CodeGen/X86/ipra-reg-usage.ll @@ -3,7 +3,7 @@ target triple = "x86_64-unknown-unknown" declare void @bar1() define preserve_allcc void @foo()#0 { -; CHECK: foo Clobbered Registers: $cs $df $ds $eflags $eip $eiz $es $esp $fpcw $fpsw $fs $gs $hip $hsp $ip $mxcsr $rip $riz $rsp $sp $sph $spl $ss $ssp $tmmcfg $bnd0 $bnd1 $bnd2 $bnd3 $cr0 $cr1 $cr2 $cr3 $cr4 $cr5 $cr6 $cr7 $cr8 $cr9 $cr10 $cr11 $cr12 $cr13 $cr14 $cr15 $dr0 $dr1 $dr2 $dr3 $dr4 $dr5 $dr6 $dr7 $dr8 $dr9 $dr10 $dr11 $dr12 $dr13 $dr14 $dr15 $fp0 $fp1 $fp2 $fp3 $fp4 $fp5 $fp6 $fp7 $k0 $k1 $k2 $k3 $k4 $k5 $k6 $k7 $mm0 $mm1 $mm2 $mm3 $mm4 $mm5 $mm6 $mm7 $r11 $st0 $st1 $st2 $st3 $st4 $st5 $st6 $st7 $tmm0 $tmm1 $tmm2 $tmm3 $tmm4 $tmm5 $tmm6 $tmm7 $xmm16 $xmm17 $xmm18 $xmm19 $xmm20 $xmm21 $xmm22 $xmm23 $xmm24 $xmm25 $xmm26 $xmm27 $xmm28 $xmm29 $xmm30 $xmm31 $ymm0 $ymm1 $ymm2 $ymm3 $ymm4 $ymm5 $ymm6 $ymm7 $ymm8 $ymm9 $ymm10 $ymm11 $ymm12 $ymm13 $ymm14 $ymm15 $ymm16 $ymm17 $ymm18 $ymm19 $ymm20 $ymm21 $ymm22 $ymm23 $ymm24 $ymm25 $ymm26 $ymm27 $ymm28 $ymm29 $ymm30 $ymm31 $zmm0 $zmm1 $zmm2 $zmm3 $zmm4 $zmm5 $zmm6 $zmm7 $zmm8 $zmm9 $zmm10 $zmm11 $zmm12 $zmm13 $zmm14 $zmm15 $zmm16 $zmm17 $zmm18 $zmm19 $zmm20 $zmm21 $zmm22 $zmm23 $zmm24 $zmm25 $zmm26 $zmm27 $zmm28 $zmm29 $zmm30 $zmm31 $r11b $r11bh $r11d $r11w $r11wh $k0_k1 $k2_k3
[PATCH] D111517: [X86] Remove little support we had for MPX
skan accepted this revision. skan added a comment. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D111517/new/ https://reviews.llvm.org/D111517 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D111517: [X86] Remove little support we had for MPX
pengfei accepted this revision. pengfei added a comment. This revision is now accepted and ready to land. LGTM. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D111517/new/ https://reviews.llvm.org/D111517 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D111517: [X86] Remove little support we had for MPX
MaskRay updated this revision to Diff 378737. MaskRay added a comment. Herald added a project: clang. Herald added a subscriber: cfe-commits. fix tests Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D111517/new/ https://reviews.llvm.org/D111517 Files: clang/test/CodeGen/ms-inline-asm.c llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoder.h llvm/lib/Target/X86/X86InstrInfo.cpp llvm/lib/Target/X86/X86InstrInfo.td llvm/lib/Target/X86/X86InstrMPX.td llvm/lib/Target/X86/X86RegisterInfo.td llvm/test/CodeGen/X86/ipra-reg-usage.ll llvm/test/MC/X86/mpx-encodings.s llvm/unittests/tools/llvm-exegesis/X86/SnippetGeneratorTest.cpp Index: llvm/unittests/tools/llvm-exegesis/X86/SnippetGeneratorTest.cpp === --- llvm/unittests/tools/llvm-exegesis/X86/SnippetGeneratorTest.cpp +++ llvm/unittests/tools/llvm-exegesis/X86/SnippetGeneratorTest.cpp @@ -213,26 +213,6 @@ ASSERT_TRUE(BC.Key.Instructions[0].getOperand(3).isImm()); } -TEST_F(X86ParallelSnippetGeneratorTest, ParallelInstruction) { - // - BNDCL32rr - // - Op0 Explicit Use RegClass(BNDR) - // - Op1 Explicit Use RegClass(GR32) - // - Var0 [Op0] - // - Var1 [Op1] - const unsigned Opcode = X86::BNDCL32rr; - const auto CodeTemplates = checkAndGetCodeTemplates(Opcode); - ASSERT_THAT(CodeTemplates, SizeIs(1)); - const auto = CodeTemplates[0]; - EXPECT_THAT(CT.Info, HasSubstr("parallel")); - EXPECT_THAT(CT.Execution, ExecutionMode::UNKNOWN); - ASSERT_THAT(CT.Instructions, SizeIs(1)); - const InstructionTemplate = CT.Instructions[0]; - EXPECT_THAT(IT.getOpcode(), Opcode); - ASSERT_THAT(IT.getVariableValues(), SizeIs(2)); - EXPECT_THAT(IT.getVariableValues()[0], IsInvalid()); - EXPECT_THAT(IT.getVariableValues()[1], IsInvalid()); -} - TEST_F(X86ParallelSnippetGeneratorTest, SerialInstruction) { // - CDQ // - Op0 Implicit Def Reg(EAX) Index: llvm/test/MC/X86/mpx-encodings.s === --- llvm/test/MC/X86/mpx-encodings.s +++ /dev/null @@ -1,41 +0,0 @@ -// RUN: llvm-mc -triple x86_64-- --show-encoding %s |\ -// RUN: FileCheck %s --check-prefixes=CHECK,ENCODING - -// RUN: llvm-mc -triple x86_64-- -filetype=obj %s |\ -// RUN: llvm-objdump -d - | FileCheck %s - -// CHECK: bndmk (%rax), %bnd0 -// ENCODING: encoding: [0xf3,0x0f,0x1b,0x00] -bndmk (%rax), %bnd0 - -// CHECK: bndmk 1024(%rax), %bnd1 -// ENCODING: encoding: [0xf3,0x0f,0x1b,0x88,0x00,0x04,0x00,0x00] -bndmk 1024(%rax), %bnd1 - -// CHECK: bndmov %bnd2, %bnd1 -// ENCODING: encoding: [0x66,0x0f,0x1a,0xca] -bndmov %bnd2, %bnd1 - -// CHECK: bndmov %bnd1, 1024(%r9) -// ENCODING: encoding: [0x66,0x41,0x0f,0x1b,0x89,0x00,0x04,0x00,0x00] -bndmov %bnd1, 1024(%r9) - -// CHECK: bndstx %bnd1, 1024(%rax) -// ENCODING: encoding: [0x0f,0x1b,0x88,0x00,0x04,0x00,0x00] -bndstx %bnd1, 1024(%rax) - -// CHECK: bndldx 1024(%r8), %bnd1 -// ENCODING: encoding: [0x41,0x0f,0x1a,0x88,0x00,0x04,0x00,0x00] -bndldx 1024(%r8), %bnd1 - -// CHECK: bndcl 121(%r10), %bnd1 -// ENCODING: encoding: [0xf3,0x41,0x0f,0x1a,0x4a,0x79] -bndcl 121(%r10), %bnd1 - -// CHECK: bndcn 121(%rcx), %bnd3 -// ENCODING: encoding: [0xf2,0x0f,0x1b,0x59,0x79] -bndcn 121(%rcx), %bnd3 - -// CHECK: bndcu %rdx, %bnd3 -// ENCODING: encoding: [0xf2,0x0f,0x1a,0xda] -bndcu %rdx, %bnd3 Index: llvm/test/CodeGen/X86/ipra-reg-usage.ll === --- llvm/test/CodeGen/X86/ipra-reg-usage.ll +++ llvm/test/CodeGen/X86/ipra-reg-usage.ll @@ -3,7 +3,7 @@ target triple = "x86_64-unknown-unknown" declare void @bar1() define preserve_allcc void @foo()#0 { -; CHECK: foo Clobbered Registers: $cs $df $ds $eflags $eip $eiz $es $esp $fpcw $fpsw $fs $gs $hip $hsp $ip $mxcsr $rip $riz $rsp $sp $sph $spl $ss $ssp $tmmcfg $bnd0 $bnd1 $bnd2 $bnd3 $cr0 $cr1 $cr2 $cr3 $cr4 $cr5 $cr6 $cr7 $cr8 $cr9 $cr10 $cr11 $cr12 $cr13 $cr14 $cr15 $dr0 $dr1 $dr2 $dr3 $dr4 $dr5 $dr6 $dr7 $dr8 $dr9 $dr10 $dr11 $dr12 $dr13 $dr14 $dr15 $fp0 $fp1 $fp2 $fp3 $fp4 $fp5 $fp6 $fp7 $k0 $k1 $k2 $k3 $k4 $k5 $k6 $k7 $mm0 $mm1 $mm2 $mm3 $mm4 $mm5 $mm6 $mm7 $r11 $st0 $st1 $st2 $st3 $st4 $st5 $st6 $st7 $tmm0 $tmm1 $tmm2 $tmm3 $tmm4 $tmm5 $tmm6 $tmm7 $xmm16 $xmm17 $xmm18 $xmm19 $xmm20 $xmm21 $xmm22 $xmm23 $xmm24 $xmm25 $xmm26 $xmm27 $xmm28 $xmm29 $xmm30 $xmm31 $ymm0 $ymm1 $ymm2 $ymm3 $ymm4 $ymm5 $ymm6 $ymm7 $ymm8 $ymm9 $ymm10 $ymm11 $ymm12 $ymm13 $ymm14 $ymm15 $ymm16 $ymm17 $ymm18 $ymm19 $ymm20 $ymm21 $ymm22 $ymm23 $ymm24 $ymm25 $ymm26 $ymm27 $ymm28 $ymm29 $ymm30 $ymm31 $zmm0 $zmm1 $zmm2 $zmm3 $zmm4 $zmm5 $zmm6 $zmm7 $zmm8 $zmm9 $zmm10 $zmm11 $zmm12 $zmm13 $zmm14 $zmm15 $zmm16 $zmm17 $zmm18 $zmm19 $zmm20 $zmm21 $zmm22 $zmm23 $zmm24 $zmm25 $zmm26 $zmm27 $zmm28 $zmm29 $zmm30 $zmm31 $r11b $r11bh $r11d $r11w $r11wh $k0_k1 $k2_k3 $k4_k5 $k6_k7 +; CHECK: foo Clobbered Registers: $cs $df $ds $eflags $eip $eiz