[PATCH] D116735: [RISCV] Adjust RV64I data layout by using n32:64 in layout string

2022-10-28 Thread Craig Topper via Phabricator via cfe-commits 
This revision was automatically updated to reflect the committed changes.
Closed by commit rG974e2e690b40: [RISCV] Adjust RV64I data layout by using 
n32:64 in layout string (authored by craig.topper).

Changed prior to commit:
  https://reviews.llvm.org/D116735?vs=471385=471564#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D116735/new/

https://reviews.llvm.org/D116735

Files:
  clang/lib/Basic/Targets/RISCV.h
  llvm/docs/ReleaseNotes.rst
  llvm/lib/IR/AutoUpgrade.cpp
  llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
  llvm/test/CodeGen/RISCV/aext-to-sext.ll
  llvm/test/CodeGen/RISCV/loop-strength-reduce-add-cheaper-than-mul.ll
  llvm/test/CodeGen/RISCV/loop-strength-reduce-loop-invar.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vector-strided-load-store-asm.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll
  llvm/unittests/Bitcode/DataLayoutUpgradeTest.cpp

Index: llvm/unittests/Bitcode/DataLayoutUpgradeTest.cpp
===
--- llvm/unittests/Bitcode/DataLayoutUpgradeTest.cpp
+++ llvm/unittests/Bitcode/DataLayoutUpgradeTest.cpp
@@ -31,6 +31,11 @@
   // Check that AMDGPU targets add -G1 if it's not present.
   EXPECT_EQ(UpgradeDataLayoutString("e-p:32:32", "r600"), "e-p:32:32-G1");
   EXPECT_EQ(UpgradeDataLayoutString("e-p:64:64", "amdgcn"), "e-p:64:64-G1");
+
+  // Check that RISCV64 upgrades -n64 to -n32:64.
+  EXPECT_EQ(UpgradeDataLayoutString("e-m:e-p:64:64-i64:64-i128:128-n64-S128",
+"riscv64"),
+"e-m:e-p:64:64-i64:64-i128:128-n32:64-S128");
 }
 
 TEST(DataLayoutUpgradeTest, NoDataLayoutUpgrade) {
Index: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll
===
--- llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll
+++ llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll
@@ -286,14 +286,12 @@
 ; RV64-NEXT:addi a1, a1, %lo(.LCPI12_0)
 ; RV64-NEXT:vsetivli zero, 4, e32, m1, ta, ma
 ; RV64-NEXT:vlse32.v v8, (a1), zero
-; RV64-NEXT:li a1, 0
-; RV64-NEXT:li a2, 1024
+; RV64-NEXT:li a1, 1024
 ; RV64-NEXT:  .LBB12_1: # =>This Inner Loop Header: Depth=1
-; RV64-NEXT:slli a3, a1, 2
-; RV64-NEXT:add a3, a0, a3
-; RV64-NEXT:addiw a1, a1, 4
-; RV64-NEXT:vse32.v v8, (a3)
-; RV64-NEXT:bne a1, a2, .LBB12_1
+; RV64-NEXT:vse32.v v8, (a0)
+; RV64-NEXT:addiw a1, a1, -4
+; RV64-NEXT:addi a0, a0, 16
+; RV64-NEXT:bnez a1, .LBB12_1
 ; RV64-NEXT:  # %bb.2:
 ; RV64-NEXT:ret
   br label %2
Index: llvm/test/CodeGen/RISCV/rvv/fixed-vector-strided-load-store-asm.ll
===
--- llvm/test/CodeGen/RISCV/rvv/fixed-vector-strided-load-store-asm.ll
+++ llvm/test/CodeGen/RISCV/rvv/fixed-vector-strided-load-store-asm.ll
@@ -794,20 +794,20 @@
 ; CHECK-NEXT:  # %bb.4:
 ; CHECK-NEXT:beq a4, a5, .LBB12_7
 ; CHECK-NEXT:  .LBB12_5:
-; CHECK-NEXT:slli a2, a3, 2
-; CHECK-NEXT:add a2, a2, a3
-; CHECK-NEXT:add a1, a1, a2
-; CHECK-NEXT:li a2, 1024
+; CHECK-NEXT:addiw a2, a3, -1024
+; CHECK-NEXT:add a0, a0, a3
+; CHECK-NEXT:slli a4, a3, 2
+; CHECK-NEXT:add a3, a4, a3
+; CHECK-NEXT:add a1, a1, a3
 ; CHECK-NEXT:  .LBB12_6: # =>This Inner Loop Header: Depth=1
-; CHECK-NEXT:lb a4, 0(a1)
-; CHECK-NEXT:add a5, a0, a3
-; CHECK-NEXT:lb a6, 0(a5)
-; CHECK-NEXT:addw a4, a6, a4
-; CHECK-NEXT:sb a4, 0(a5)
-; CHECK-NEXT:addiw a4, a3, 1
-; CHECK-NEXT:addi a3, a3, 1
+; CHECK-NEXT:lb a3, 0(a1)
+; CHECK-NEXT:lb a4, 0(a0)
+; CHECK-NEXT:addw a3, a4, a3
+; CHECK-NEXT:sb a3, 0(a0)
+; CHECK-NEXT:addiw a2, a2, 1
+; CHECK-NEXT:addi a0, a0, 1
 ; CHECK-NEXT:addi a1, a1, 5
-; CHECK-NEXT:bne a4, a2, .LBB12_6
+; CHECK-NEXT:bnez a2, .LBB12_6
 ; CHECK-NEXT:  .LBB12_7:
 ; CHECK-NEXT:ret
   %4 = icmp eq i32 %2, 1024
Index: llvm/test/CodeGen/RISCV/loop-strength-reduce-loop-invar.ll
===
--- llvm/test/CodeGen/RISCV/loop-strength-reduce-loop-invar.ll
+++ llvm/test/CodeGen/RISCV/loop-strength-reduce-loop-invar.ll
@@ -53,25 +53,24 @@
 ; RV64:   # %bb.0: # %entry
 ; RV64-NEXT:blez a1, .LBB0_3
 ; RV64-NEXT:  # %bb.1: # %cond_true.preheader
-; RV64-NEXT:li a4, 0
+; RV64-NEXT:li a2, 0
 ; RV64-NEXT:slli a0, a0, 6
-; RV64-NEXT:lui a2, %hi(A)
-; RV64-NEXT:addi a2, a2, %lo(A)
-; RV64-NEXT:add a0, a2, a0
-; RV64-NEXT:li a2, 4
-; RV64-NEXT:li a3, 5
+; RV64-NEXT:lui a3, %hi(A)
+; RV64-NEXT:addi a3, a3, %lo(A)
+; RV64-NEXT:add a0, a3, a0
+; RV64-NEXT:addi a3, a0, 4
+; RV64-NEXT:li a4, 4
+; RV64-NEXT:li a5, 5
 ; RV64-NEXT:  .LBB0_2: # %cond_true
 ; RV64-NEXT:# =>This Inner Loop Header: Depth=1
-; RV64-NEXT:addiw a5, a4, 1
-; RV64-NEXT:slli a6, a5, 2
+; RV64-NEXT:sw a4, 0(a3)
+; RV64-NEXT:addiw

[PATCH] D116735: [RISCV] Adjust RV64I data layout by using n32:64 in layout string

2022-10-28 Thread Fraser Cormack via Phabricator via cfe-commits 
frasercrmck accepted this revision.
frasercrmck added a comment.

LGTM other than a nit, but I concur that a comment in AutoUpgrade would be nice.




Comment at: llvm/docs/ReleaseNotes.rst:123
+* i32 is now a native type in the datalayout string. This enables
+  LoopStrengthReduce for loops with i32 induction variables. And other
+  optimizations.

something like `, among other optimizations` to avoid full stop + "and"?


Repository:
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[PATCH] D116735: [RISCV] Adjust RV64I data layout by using n32:64 in layout string

2022-10-27 Thread Craig Topper via Phabricator via cfe-commits 
craig.topper updated this revision to Diff 471385.
craig.topper added a comment.

Refine ReleaseNotes


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D116735/new/

https://reviews.llvm.org/D116735

Files:
  clang/lib/Basic/Targets/RISCV.h
  llvm/docs/ReleaseNotes.rst
  llvm/lib/IR/AutoUpgrade.cpp
  llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
  llvm/test/CodeGen/RISCV/aext-to-sext.ll
  llvm/test/CodeGen/RISCV/loop-strength-reduce-add-cheaper-than-mul.ll
  llvm/test/CodeGen/RISCV/loop-strength-reduce-loop-invar.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vector-strided-load-store-asm.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll
  llvm/unittests/Bitcode/DataLayoutUpgradeTest.cpp

Index: llvm/unittests/Bitcode/DataLayoutUpgradeTest.cpp
===
--- llvm/unittests/Bitcode/DataLayoutUpgradeTest.cpp
+++ llvm/unittests/Bitcode/DataLayoutUpgradeTest.cpp
@@ -31,6 +31,11 @@
   // Check that AMDGPU targets add -G1 if it's not present.
   EXPECT_EQ(UpgradeDataLayoutString("e-p:32:32", "r600"), "e-p:32:32-G1");
   EXPECT_EQ(UpgradeDataLayoutString("e-p:64:64", "amdgcn"), "e-p:64:64-G1");
+
+  // Check that RISCV64 upgrades -n64 to -n32:64.
+  EXPECT_EQ(UpgradeDataLayoutString("e-m:e-p:64:64-i64:64-i128:128-n64-S128",
+"riscv64"),
+"e-m:e-p:64:64-i64:64-i128:128-n32:64-S128");
 }
 
 TEST(DataLayoutUpgradeTest, NoDataLayoutUpgrade) {
Index: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll
===
--- llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll
+++ llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll
@@ -286,14 +286,12 @@
 ; RV64-NEXT:addi a1, a1, %lo(.LCPI12_0)
 ; RV64-NEXT:vsetivli zero, 4, e32, m1, ta, ma
 ; RV64-NEXT:vlse32.v v8, (a1), zero
-; RV64-NEXT:li a1, 0
-; RV64-NEXT:li a2, 1024
+; RV64-NEXT:li a1, 1024
 ; RV64-NEXT:  .LBB12_1: # =>This Inner Loop Header: Depth=1
-; RV64-NEXT:slli a3, a1, 2
-; RV64-NEXT:add a3, a0, a3
-; RV64-NEXT:addiw a1, a1, 4
-; RV64-NEXT:vse32.v v8, (a3)
-; RV64-NEXT:bne a1, a2, .LBB12_1
+; RV64-NEXT:vse32.v v8, (a0)
+; RV64-NEXT:addiw a1, a1, -4
+; RV64-NEXT:addi a0, a0, 16
+; RV64-NEXT:bnez a1, .LBB12_1
 ; RV64-NEXT:  # %bb.2:
 ; RV64-NEXT:ret
   br label %2
Index: llvm/test/CodeGen/RISCV/rvv/fixed-vector-strided-load-store-asm.ll
===
--- llvm/test/CodeGen/RISCV/rvv/fixed-vector-strided-load-store-asm.ll
+++ llvm/test/CodeGen/RISCV/rvv/fixed-vector-strided-load-store-asm.ll
@@ -794,20 +794,20 @@
 ; CHECK-NEXT:  # %bb.4:
 ; CHECK-NEXT:beq a4, a5, .LBB12_7
 ; CHECK-NEXT:  .LBB12_5:
-; CHECK-NEXT:slli a2, a3, 2
-; CHECK-NEXT:add a2, a2, a3
-; CHECK-NEXT:add a1, a1, a2
-; CHECK-NEXT:li a2, 1024
+; CHECK-NEXT:addiw a2, a3, -1024
+; CHECK-NEXT:add a0, a0, a3
+; CHECK-NEXT:slli a4, a3, 2
+; CHECK-NEXT:add a3, a4, a3
+; CHECK-NEXT:add a1, a1, a3
 ; CHECK-NEXT:  .LBB12_6: # =>This Inner Loop Header: Depth=1
-; CHECK-NEXT:lb a4, 0(a1)
-; CHECK-NEXT:add a5, a0, a3
-; CHECK-NEXT:lb a6, 0(a5)
-; CHECK-NEXT:addw a4, a6, a4
-; CHECK-NEXT:sb a4, 0(a5)
-; CHECK-NEXT:addiw a4, a3, 1
-; CHECK-NEXT:addi a3, a3, 1
+; CHECK-NEXT:lb a3, 0(a1)
+; CHECK-NEXT:lb a4, 0(a0)
+; CHECK-NEXT:addw a3, a4, a3
+; CHECK-NEXT:sb a3, 0(a0)
+; CHECK-NEXT:addiw a2, a2, 1
+; CHECK-NEXT:addi a0, a0, 1
 ; CHECK-NEXT:addi a1, a1, 5
-; CHECK-NEXT:bne a4, a2, .LBB12_6
+; CHECK-NEXT:bnez a2, .LBB12_6
 ; CHECK-NEXT:  .LBB12_7:
 ; CHECK-NEXT:ret
   %4 = icmp eq i32 %2, 1024
Index: llvm/test/CodeGen/RISCV/loop-strength-reduce-loop-invar.ll
===
--- llvm/test/CodeGen/RISCV/loop-strength-reduce-loop-invar.ll
+++ llvm/test/CodeGen/RISCV/loop-strength-reduce-loop-invar.ll
@@ -53,25 +53,24 @@
 ; RV64:   # %bb.0: # %entry
 ; RV64-NEXT:blez a1, .LBB0_3
 ; RV64-NEXT:  # %bb.1: # %cond_true.preheader
-; RV64-NEXT:li a4, 0
+; RV64-NEXT:li a2, 0
 ; RV64-NEXT:slli a0, a0, 6
-; RV64-NEXT:lui a2, %hi(A)
-; RV64-NEXT:addi a2, a2, %lo(A)
-; RV64-NEXT:add a0, a2, a0
-; RV64-NEXT:li a2, 4
-; RV64-NEXT:li a3, 5
+; RV64-NEXT:lui a3, %hi(A)
+; RV64-NEXT:addi a3, a3, %lo(A)
+; RV64-NEXT:add a0, a3, a0
+; RV64-NEXT:addi a3, a0, 4
+; RV64-NEXT:li a4, 4
+; RV64-NEXT:li a5, 5
 ; RV64-NEXT:  .LBB0_2: # %cond_true
 ; RV64-NEXT:# =>This Inner Loop Header: Depth=1
-; RV64-NEXT:addiw a5, a4, 1
-; RV64-NEXT:slli a6, a5, 2
+; RV64-NEXT:sw a4, 0(a3)
+; RV64-NEXT:addiw a6, a2, 2
+; RV64-NEXT:slli a6, a6, 2
 ; RV64-NEXT:add a6, a0, a6
-; RV64-NEXT:sw a2, 0(a6)
-; RV64-NEXT:addiw a4, a4, 2
-; RV64-NEXT:slli a4, a4, 2
-; RV64-NEXT:

[PATCH] D116735: [RISCV] Adjust RV64I data layout by using n32:64 in layout string

2022-10-27 Thread Jessica Clarke via Phabricator via cfe-commits 
jrtc27 added inline comments.



Comment at: llvm/docs/ReleaseNotes.rst:122
   been removed.
+* n32 was added to the RV64I datalayout string.
 

arichardson wrote:
> Without additional context I don't think this makes much sense to most 
> readers. Before looking at this patch description I would not have been and 
> to say what n is used for. 
> 
> Maybe something like "i32 has been marked as a legal integer type for RV64, 
> improving code generation for some benchmarks"?
"native integer type" not "legal integer type"; it still gets legalised during 
ISel


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[PATCH] D116735: [RISCV] Adjust RV64I data layout by using n32:64 in layout string

2022-10-27 Thread Alexander Richardson via Phabricator via cfe-commits 
arichardson added inline comments.



Comment at: llvm/docs/ReleaseNotes.rst:122
   been removed.
+* n32 was added to the RV64I datalayout string.
 

Without additional context I don't think this makes much sense to most readers. 
Before looking at this patch description I would not have been and to say what 
n is used for. 

Maybe something like "i32 has been marked as a legal integer type for RV64, 
improving code generation for some benchmarks"?


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