[PATCH] D125557: [APInt] Remove all uses of zextOrSelf, sextOrSelf and truncOrSelf

[Jay Foad via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG6bec3e9303d6: [APInt] Remove all uses of zextOrSelf, 
sextOrSelf and truncOrSelf (authored by foad).

Repository:
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Files:
  clang/lib/AST/ExprConstant.cpp
  clang/lib/AST/MicrosoftMangle.cpp
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/Sema/SemaDecl.cpp
  clang/lib/StaticAnalyzer/Core/LoopUnrolling.cpp
  llvm/lib/Analysis/BasicAliasAnalysis.cpp
  llvm/lib/Analysis/ConstantFolding.cpp
  llvm/lib/Analysis/LazyValueInfo.cpp
  llvm/lib/Analysis/MemoryBuiltins.cpp
  llvm/lib/Analysis/ScalarEvolution.cpp
  llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
  llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
  llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
  llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
  llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
  llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
  llvm/lib/IR/ConstantRange.cpp
  llvm/lib/Support/APFixedPoint.cpp
  llvm/lib/Support/APInt.cpp
  llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerCombiner.cpp
  llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
  llvm/lib/Target/Hexagon/HexagonConstPropagation.cpp
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/X86/X86ISelLowering.cpp
  llvm/lib/Target/X86/X86TargetTransformInfo.cpp
  llvm/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp
  llvm/lib/Transforms/Scalar/CorrelatedValuePropagation.cpp
  llvm/lib/Transforms/Vectorize/LoadStoreVectorizer.cpp
  llvm/test/TableGen/VarLenEncoder.td
  llvm/utils/TableGen/VarLenCodeEmitterGen.cpp
  polly/lib/CodeGen/IslExprBuilder.cpp

Index: polly/lib/CodeGen/IslExprBuilder.cpp
===
--- polly/lib/CodeGen/IslExprBuilder.cpp
+++ polly/lib/CodeGen/IslExprBuilder.cpp
@@ -765,7 +765,7 @@
   else
 T = Builder.getIntNTy(BitWidth);
 
-  APValue = APValue.sextOrSelf(T->getBitWidth());
+  APValue = APValue.sext(T->getBitWidth());
   V = ConstantInt::get(T, APValue);
 
   isl_ast_expr_free(Expr);
Index: llvm/utils/TableGen/VarLenCodeEmitterGen.cpp
===
--- llvm/utils/TableGen/VarLenCodeEmitterGen.cpp
+++ llvm/utils/TableGen/VarLenCodeEmitterGen.cpp
@@ -424,7 +424,7 @@
   raw_string_ostream SS(Case);
   // Resize the scratch buffer.
   if (BitWidth && !VLI.isFixedValueOnly())
-SS.indent(6) << "Scratch = Scratch.zextOrSelf(" << BitWidth << ");\n";
+SS.indent(6) << "Scratch = Scratch.zext(" << BitWidth << ");\n";
   // Populate based value.
   SS.indent(6) << "Inst = getInstBits(opcode);\n";
 
Index: llvm/test/TableGen/VarLenEncoder.td
===
--- llvm/test/TableGen/VarLenEncoder.td
+++ llvm/test/TableGen/VarLenEncoder.td
@@ -65,7 +65,7 @@
 // CHECK: UINT64_C(46848), // FOO32
 
 // CHECK-LABEL: case ::FOO16: {
-// CHECK: Scratch = Scratch.zextOrSelf(41);
+// CHECK: Scratch = Scratch.zext(41);
 // src.reg
 // CHECK: getMachineOpValue(MI, MI.getOperand(1), /*Pos=*/0, Scratch, Fixups, STI);
 // CHECK: Inst.insertBits(Scratch.extractBits(8, 0), 0);
@@ -83,7 +83,7 @@
 // CHECK: Inst.insertBits(Scratch.extractBits(2, 0), 39);
 
 // CHECK-LABEL: case ::FOO32: {
-// CHECK: Scratch = Scratch.zextOrSelf(57);
+// CHECK: Scratch = Scratch.zext(57);
 // src.reg
 // CHECK: getMachineOpValue(MI, MI.getOperand(1), /*Pos=*/0, Scratch, Fixups, STI);
 // CHECK: Inst.insertBits(Scratch.extractBits(8, 0), 0);
Index: llvm/lib/Transforms/Vectorize/LoadStoreVectorizer.cpp
===
--- llvm/lib/Transforms/Vectorize/LoadStoreVectorizer.cpp
+++ llvm/lib/Transforms/Vectorize/LoadStoreVectorizer.cpp
@@ -496,7 +496,7 @@
   if (PtrDelta.urem(Stride) != 0)
 return false;
   unsigned IdxBitWidth = OpA->getType()->getScalarSizeInBits();
-  APInt IdxDiff = PtrDelta.udiv(Stride).zextOrSelf(IdxBitWidth);
+  APInt IdxDiff = PtrDelta.udiv(Stride).zext(IdxBitWidth);
 
   // Only look through a ZExt/SExt.
   if (!isa(OpA) && !isa(OpA))
Index: llvm/lib/Transforms/Scalar/CorrelatedValuePropagation.cpp
===
--- llvm/lib/Transforms/Scalar/CorrelatedValuePropagation.cpp
+++ llvm/lib/Transforms/Scalar/CorrelatedValuePropagation.cpp
@@ -741,8 +741,7 @@
   // sdiv/srem is UB if divisor is -1 and divident is INT_MIN, so unless we can
   // prove that such a combination is impossible, we need to bump the bitwidth.
   if (CRs[1]->contains(APInt::getAllOnes(OrigWidth)) &&
-  CRs[0]->contains(
-  APInt::getSignedMinValue(MinSignedBits).sextOrSelf(OrigWidth)))
+  

[PATCH] D125557: [APInt] Remove all uses of zextOrSelf, sextOrSelf and truncOrSelf

[Chris Lattner via Phabricator via cfe-commits]

lattner added inline comments.



Comment at: llvm/lib/Analysis/ConstantFolding.cpp:2884
 if (IntrinsicID == Intrinsic::smul_fix_sat) {
-  APInt Max = APInt::getSignedMaxValue(Width).sextOrSelf(ExtendedWidth);
-  APInt Min = APInt::getSignedMinValue(Width).sextOrSelf(ExtendedWidth);
+  APInt Max = APInt::getSignedMaxValue(Width).sext(ExtendedWidth);
+  APInt Min = APInt::getSignedMinValue(Width).sext(ExtendedWidth);

foad wrote:
> lattner wrote:
> > I think this can be a zext given the top bit will be zero
> Sure the first one could be zext, but the second one can't be, so it feels 
> conceptually simpler (to me) to keep them both as sext.
likewise, I'm fine with this either way.  zext is slightly more "Strength 
reduced" than sext, but it doesn't matter.


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[PATCH] D125557: [APInt] Remove all uses of zextOrSelf, sextOrSelf and truncOrSelf

[Eli Friedman via Phabricator via cfe-commits]

efriedma added inline comments.



Comment at: llvm/lib/IR/ConstantRange.cpp:724
 auto BW = getBitWidth();
-APInt Min = APInt::getMinValue(BW).zextOrSelf(ResultBitWidth);
-APInt Max = APInt::getMaxValue(BW).zextOrSelf(ResultBitWidth);
+APInt Min = APInt::getMinValue(BW);
+APInt Max = APInt::getMaxValue(BW);

foad wrote:
> foad wrote:
> > efriedma wrote:
> > > efriedma wrote:
> > > > Making the bitwidth of the result here not equal to ResultBitWidth 
> > > > seems suspect.
> > > > 
> > > > I think there should just be an `if (ResultBitWidth < BW) return 
> > > > getFull(ResultBitWidth);` here.  Then a simple conversion just works.
> > > Actually, looking at D27294 again, maybe it is actually making the result 
> > > bitwidth intentionally inflate like this.
> > > 
> > > This could use a comment explaining what it's doing, in any case.
> > I agree it could use a comment but I don't feel qualified to write it - I 
> > am just trying to preserve the current behaviour.
> @efriedma do you have any objection to the patch as-is?
No objection.


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[PATCH] D125557: [APInt] Remove all uses of zextOrSelf, sextOrSelf and truncOrSelf

[Philip Reames via Phabricator via cfe-commits]

reames added a comment.

Coming into this late, but I'd have preferred to see this separated into at 
least two pieces.  One for each "non-obvious" adjustment, and one final one 
which just did the replace on the renaming sites.  This differs from feedback 
from other reviewers above, so don't feel bound by this in any way.  Just 
expressing the general preference.


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[PATCH] D125557: [APInt] Remove all uses of zextOrSelf, sextOrSelf and truncOrSelf

[Jay Foad via Phabricator via cfe-commits]

foad added inline comments.



Comment at: llvm/lib/IR/ConstantRange.cpp:724
 auto BW = getBitWidth();
-APInt Min = APInt::getMinValue(BW).zextOrSelf(ResultBitWidth);
-APInt Max = APInt::getMaxValue(BW).zextOrSelf(ResultBitWidth);
+APInt Min = APInt::getMinValue(BW);
+APInt Max = APInt::getMaxValue(BW);

foad wrote:
> efriedma wrote:
> > efriedma wrote:
> > > Making the bitwidth of the result here not equal to ResultBitWidth seems 
> > > suspect.
> > > 
> > > I think there should just be an `if (ResultBitWidth < BW) return 
> > > getFull(ResultBitWidth);` here.  Then a simple conversion just works.
> > Actually, looking at D27294 again, maybe it is actually making the result 
> > bitwidth intentionally inflate like this.
> > 
> > This could use a comment explaining what it's doing, in any case.
> I agree it could use a comment but I don't feel qualified to write it - I am 
> just trying to preserve the current behaviour.
@efriedma do you have any objection to the patch as-is?


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[PATCH] D125557: [APInt] Remove all uses of zextOrSelf, sextOrSelf and truncOrSelf

[Jay Foad via Phabricator via cfe-commits]

foad marked 2 inline comments as done.
foad added inline comments.



Comment at: llvm/lib/Analysis/ConstantFolding.cpp:2884
 if (IntrinsicID == Intrinsic::smul_fix_sat) {
-  APInt Max = APInt::getSignedMaxValue(Width).sextOrSelf(ExtendedWidth);
-  APInt Min = APInt::getSignedMinValue(Width).sextOrSelf(ExtendedWidth);
+  APInt Max = APInt::getSignedMaxValue(Width).sext(ExtendedWidth);
+  APInt Min = APInt::getSignedMinValue(Width).sext(ExtendedWidth);

lattner wrote:
> I think this can be a zext given the top bit will be zero
Sure the first one could be zext, but the second one can't be, so it feels 
conceptually simpler (to me) to keep them both as sext.



Comment at: llvm/lib/IR/ConstantRange.cpp:724
 auto BW = getBitWidth();
-APInt Min = APInt::getMinValue(BW).zextOrSelf(ResultBitWidth);
-APInt Max = APInt::getMaxValue(BW).zextOrSelf(ResultBitWidth);
+APInt Min = APInt::getMinValue(BW);
+APInt Max = APInt::getMaxValue(BW);

efriedma wrote:
> efriedma wrote:
> > Making the bitwidth of the result here not equal to ResultBitWidth seems 
> > suspect.
> > 
> > I think there should just be an `if (ResultBitWidth < BW) return 
> > getFull(ResultBitWidth);` here.  Then a simple conversion just works.
> Actually, looking at D27294 again, maybe it is actually making the result 
> bitwidth intentionally inflate like this.
> 
> This could use a comment explaining what it's doing, in any case.
I agree it could use a comment but I don't feel qualified to write it - I am 
just trying to preserve the current behaviour.


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[PATCH] D125557: [APInt] Remove all uses of zextOrSelf, sextOrSelf and truncOrSelf

[Jay Foad via Phabricator via cfe-commits]

foad updated this revision to Diff 429466.
foad added a comment.

Address some review comments.


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Files:
  clang/lib/AST/ExprConstant.cpp
  clang/lib/AST/MicrosoftMangle.cpp
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/Sema/SemaDecl.cpp
  clang/lib/StaticAnalyzer/Core/LoopUnrolling.cpp
  llvm/lib/Analysis/BasicAliasAnalysis.cpp
  llvm/lib/Analysis/ConstantFolding.cpp
  llvm/lib/Analysis/LazyValueInfo.cpp
  llvm/lib/Analysis/MemoryBuiltins.cpp
  llvm/lib/Analysis/ScalarEvolution.cpp
  llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
  llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
  llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
  llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
  llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
  llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
  llvm/lib/IR/ConstantRange.cpp
  llvm/lib/Support/APFixedPoint.cpp
  llvm/lib/Support/APInt.cpp
  llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerCombiner.cpp
  llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
  llvm/lib/Target/Hexagon/HexagonConstPropagation.cpp
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/X86/X86ISelLowering.cpp
  llvm/lib/Target/X86/X86TargetTransformInfo.cpp
  llvm/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp
  llvm/lib/Transforms/Scalar/CorrelatedValuePropagation.cpp
  llvm/lib/Transforms/Vectorize/LoadStoreVectorizer.cpp
  llvm/test/TableGen/VarLenEncoder.td
  llvm/utils/TableGen/VarLenCodeEmitterGen.cpp
  polly/lib/CodeGen/IslExprBuilder.cpp

Index: polly/lib/CodeGen/IslExprBuilder.cpp
===
--- polly/lib/CodeGen/IslExprBuilder.cpp
+++ polly/lib/CodeGen/IslExprBuilder.cpp
@@ -765,7 +765,7 @@
   else
 T = Builder.getIntNTy(BitWidth);
 
-  APValue = APValue.sextOrSelf(T->getBitWidth());
+  APValue = APValue.sext(T->getBitWidth());
   V = ConstantInt::get(T, APValue);
 
   isl_ast_expr_free(Expr);
Index: llvm/utils/TableGen/VarLenCodeEmitterGen.cpp
===
--- llvm/utils/TableGen/VarLenCodeEmitterGen.cpp
+++ llvm/utils/TableGen/VarLenCodeEmitterGen.cpp
@@ -424,7 +424,7 @@
   raw_string_ostream SS(Case);
   // Resize the scratch buffer.
   if (BitWidth && !VLI.isFixedValueOnly())
-SS.indent(6) << "Scratch = Scratch.zextOrSelf(" << BitWidth << ");\n";
+SS.indent(6) << "Scratch = Scratch.zext(" << BitWidth << ");\n";
   // Populate based value.
   SS.indent(6) << "Inst = getInstBits(opcode);\n";
 
Index: llvm/test/TableGen/VarLenEncoder.td
===
--- llvm/test/TableGen/VarLenEncoder.td
+++ llvm/test/TableGen/VarLenEncoder.td
@@ -65,7 +65,7 @@
 // CHECK: UINT64_C(46848), // FOO32
 
 // CHECK-LABEL: case ::FOO16: {
-// CHECK: Scratch = Scratch.zextOrSelf(41);
+// CHECK: Scratch = Scratch.zext(41);
 // src.reg
 // CHECK: getMachineOpValue(MI, MI.getOperand(1), /*Pos=*/0, Scratch, Fixups, STI);
 // CHECK: Inst.insertBits(Scratch.extractBits(8, 0), 0);
@@ -83,7 +83,7 @@
 // CHECK: Inst.insertBits(Scratch.extractBits(2, 0), 39);
 
 // CHECK-LABEL: case ::FOO32: {
-// CHECK: Scratch = Scratch.zextOrSelf(57);
+// CHECK: Scratch = Scratch.zext(57);
 // src.reg
 // CHECK: getMachineOpValue(MI, MI.getOperand(1), /*Pos=*/0, Scratch, Fixups, STI);
 // CHECK: Inst.insertBits(Scratch.extractBits(8, 0), 0);
Index: llvm/lib/Transforms/Vectorize/LoadStoreVectorizer.cpp
===
--- llvm/lib/Transforms/Vectorize/LoadStoreVectorizer.cpp
+++ llvm/lib/Transforms/Vectorize/LoadStoreVectorizer.cpp
@@ -496,7 +496,7 @@
   if (PtrDelta.urem(Stride) != 0)
 return false;
   unsigned IdxBitWidth = OpA->getType()->getScalarSizeInBits();
-  APInt IdxDiff = PtrDelta.udiv(Stride).zextOrSelf(IdxBitWidth);
+  APInt IdxDiff = PtrDelta.udiv(Stride).zext(IdxBitWidth);
 
   // Only look through a ZExt/SExt.
   if (!isa(OpA) && !isa(OpA))
Index: llvm/lib/Transforms/Scalar/CorrelatedValuePropagation.cpp
===
--- llvm/lib/Transforms/Scalar/CorrelatedValuePropagation.cpp
+++ llvm/lib/Transforms/Scalar/CorrelatedValuePropagation.cpp
@@ -741,8 +741,7 @@
   // sdiv/srem is UB if divisor is -1 and divident is INT_MIN, so unless we can
   // prove that such a combination is impossible, we need to bump the bitwidth.
   if (CRs[1]->contains(APInt::getAllOnes(OrigWidth)) &&
-  CRs[0]->contains(
-  APInt::getSignedMinValue(MinSignedBits).sextOrSelf(OrigWidth)))
+  CRs[0]->contains(APInt::getSignedMinValue(MinSignedBits).sext(OrigWidth)))
 ++MinSignedBits;
 
   // Don't shrink below 8 bits wide.
Index: 

[PATCH] D125557: [APInt] Remove all uses of zextOrSelf, sextOrSelf and truncOrSelf

[Chris Lattner via Phabricator via cfe-commits]

lattner accepted this revision.
lattner added a comment.
This revision is now accepted and ready to land.

nice cleanup!




Comment at: llvm/lib/Analysis/ConstantFolding.cpp:2884
 if (IntrinsicID == Intrinsic::smul_fix_sat) {
-  APInt Max = APInt::getSignedMaxValue(Width).sextOrSelf(ExtendedWidth);
-  APInt Min = APInt::getSignedMinValue(Width).sextOrSelf(ExtendedWidth);
+  APInt Max = APInt::getSignedMaxValue(Width).sext(ExtendedWidth);
+  APInt Min = APInt::getSignedMinValue(Width).sext(ExtendedWidth);

I think this can be a zext given the top bit will be zero



Comment at: llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerCombiner.cpp:138
 
-  const APInt ConstValue = Const->Value.sextOrSelf(Ty.getSizeInBits());
+  const APInt ConstValue = Const->Value.sext(Ty.getSizeInBits());
   // The following code is ported from AArch64ISelLowering.

plz drop the extraneous 'const' while here.



Comment at: llvm/lib/Target/Hexagon/HexagonConstPropagation.cpp:1220
   if (Cmp & Comparison::U) {
-const APInt Zx1 = A1.zextOrSelf(MaxW);
-const APInt Zx2 = A2.zextOrSelf(MaxW);
+const APInt Zx1 = A1.zext(MaxW);
+const APInt Zx2 = A2.zext(MaxW);

Here too :)


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[PATCH] D125557: [APInt] Remove all uses of zextOrSelf, sextOrSelf and truncOrSelf

[Eli Friedman via Phabricator via cfe-commits]

efriedma added subscribers: reames, efriedma.
efriedma added inline comments.



Comment at: llvm/lib/IR/ConstantRange.cpp:724
 auto BW = getBitWidth();
-APInt Min = APInt::getMinValue(BW).zextOrSelf(ResultBitWidth);
-APInt Max = APInt::getMaxValue(BW).zextOrSelf(ResultBitWidth);
+APInt Min = APInt::getMinValue(BW);
+APInt Max = APInt::getMaxValue(BW);

Making the bitwidth of the result here not equal to ResultBitWidth seems 
suspect.

I think there should just be an `if (ResultBitWidth < BW) return 
getFull(ResultBitWidth);` here.  Then a simple conversion just works.


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[PATCH] D125557: [APInt] Remove all uses of zextOrSelf, sextOrSelf and truncOrSelf

[Jay Foad via Phabricator via cfe-commits]

foad created this revision.
foad added reviewers: lattner, RKSimon, lebedev.ri, spatel.
Herald added subscribers: kosarev, jsilvanus, hsmhsm, jeroen.dobbelaere, 
frasercrmck, ecnelises, martong, kerbowa, luismarques, apazos, sameer.abuasal, 
pengfei, s.egerton, Jim, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, 
rogfer01, edward-jones, zzheng, jrtc27, niosHD, sabuasal, simoncook, johnrusso, 
rbar, asb, hiraditya, arichardson, nhaehnle, jvesely, arsenm.
Herald added a reviewer: bollu.
Herald added a project: All.
foad requested review of this revision.
Herald added subscribers: llvm-commits, cfe-commits, pcwang-thead, MaskRay.
Herald added projects: clang, LLVM.

Most clients only used these methods because they wanted to be able to
extend or truncate to the same bit width (which is a no-op). Now that
the standard zext, sext and trunc allow this, there is no reason to use
the OrSelf versions.

The OrSelf versions additionally have the strange behaviour of allowing
extending to a *smaller* width, or truncating to a *larger* width, which
are also treated as no-ops. A small amount of client code relied on this
(ConstantRange::castOp and MicrosoftCXXNameMangler::mangleNumber) and
needed rewriting.


Repository:
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https://reviews.llvm.org/D125557

Files:
  clang/lib/AST/ExprConstant.cpp
  clang/lib/AST/MicrosoftMangle.cpp
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/Sema/SemaDecl.cpp
  clang/lib/StaticAnalyzer/Core/LoopUnrolling.cpp
  llvm/lib/Analysis/BasicAliasAnalysis.cpp
  llvm/lib/Analysis/ConstantFolding.cpp
  llvm/lib/Analysis/LazyValueInfo.cpp
  llvm/lib/Analysis/MemoryBuiltins.cpp
  llvm/lib/Analysis/ScalarEvolution.cpp
  llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
  llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
  llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
  llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
  llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
  llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
  llvm/lib/IR/ConstantRange.cpp
  llvm/lib/Support/APFixedPoint.cpp
  llvm/lib/Support/APInt.cpp
  llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerCombiner.cpp
  llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
  llvm/lib/Target/Hexagon/HexagonConstPropagation.cpp
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/X86/X86ISelLowering.cpp
  llvm/lib/Target/X86/X86TargetTransformInfo.cpp
  llvm/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp
  llvm/lib/Transforms/Scalar/CorrelatedValuePropagation.cpp
  llvm/lib/Transforms/Vectorize/LoadStoreVectorizer.cpp
  llvm/test/TableGen/VarLenEncoder.td
  llvm/utils/TableGen/VarLenCodeEmitterGen.cpp
  polly/lib/CodeGen/IslExprBuilder.cpp

Index: polly/lib/CodeGen/IslExprBuilder.cpp
===
--- polly/lib/CodeGen/IslExprBuilder.cpp
+++ polly/lib/CodeGen/IslExprBuilder.cpp
@@ -765,7 +765,7 @@
   else
 T = Builder.getIntNTy(BitWidth);
 
-  APValue = APValue.sextOrSelf(T->getBitWidth());
+  APValue = APValue.sext(T->getBitWidth());
   V = ConstantInt::get(T, APValue);
 
   isl_ast_expr_free(Expr);
Index: llvm/utils/TableGen/VarLenCodeEmitterGen.cpp
===
--- llvm/utils/TableGen/VarLenCodeEmitterGen.cpp
+++ llvm/utils/TableGen/VarLenCodeEmitterGen.cpp
@@ -424,7 +424,7 @@
   raw_string_ostream SS(Case);
   // Resize the scratch buffer.
   if (BitWidth && !VLI.isFixedValueOnly())
-SS.indent(6) << "Scratch = Scratch.zextOrSelf(" << BitWidth << ");\n";
+SS.indent(6) << "Scratch = Scratch.zext(" << BitWidth << ");\n";
   // Populate based value.
   SS.indent(6) << "Inst = getInstBits(opcode);\n";
 
Index: llvm/test/TableGen/VarLenEncoder.td
===
--- llvm/test/TableGen/VarLenEncoder.td
+++ llvm/test/TableGen/VarLenEncoder.td
@@ -65,7 +65,7 @@
 // CHECK: UINT64_C(46848), // FOO32
 
 // CHECK-LABEL: case ::FOO16: {
-// CHECK: Scratch = Scratch.zextOrSelf(41);
+// CHECK: Scratch = Scratch.zext(41);
 // src.reg
 // CHECK: getMachineOpValue(MI, MI.getOperand(1), /*Pos=*/0, Scratch, Fixups, STI);
 // CHECK: Inst.insertBits(Scratch.extractBits(8, 0), 0);
@@ -83,7 +83,7 @@
 // CHECK: Inst.insertBits(Scratch.extractBits(2, 0), 39);
 
 // CHECK-LABEL: case ::FOO32: {
-// CHECK: Scratch = Scratch.zextOrSelf(57);
+// CHECK: Scratch = Scratch.zext(57);
 // src.reg
 // CHECK: getMachineOpValue(MI, MI.getOperand(1), /*Pos=*/0, Scratch, Fixups, STI);
 // CHECK: Inst.insertBits(Scratch.extractBits(8, 0), 0);
Index: llvm/lib/Transforms/Vectorize/LoadStoreVectorizer.cpp
===
--- llvm/lib/Transforms/Vectorize/LoadStoreVectorizer.cpp
+++ llvm/lib/Transforms/Vectorize/LoadStoreVectorizer.cpp
@@ -496,7 +496,7 @@
   if