[PATCH] D128612: RISC-V big-endian support implementation

2023-05-17 Thread Djordje Todorovic via Phabricator via cfe-commits 
djtodoro added a comment.

In D128612#4349291 , @asb wrote:

> In D128612#4349259 , @djtodoro 
> wrote:
>
>> In D128612#4345912 , @asb wrote:
>>
>>> In D128612#4337037 , @djtodoro 
>>> wrote:
>>>
 Hi! I am wondering if someone knows what is the status of this.
>>>
>>> I've not seen any further progress. I think it needs at a minimum a PR 
>>> against the psABI doc for big endian that we can review against.
>>
>> OK. Can you please share with me the GCC PR, so I can take a look how it 
>> should be done :)
>
> Based on comments here it sounds like GCC merged some level of support 
> without submitting corresponding changes to the psABI. I don't have those 
> patches to hand, but you can probably find them on the GCC patches list. I 
> think we've had enough unexpected compatibility issues by now that it's not 
> really justifiable to merge something that's meant to be a standard ABI 
> without having the corresponding psABI patch (even if it appears simple). I 
> don't think anyone has posted such a psABI patch but there is/was a tracking 
> issue for it on the psABI repo.

Yeah, if the https://github.com/riscv-non-isa/riscv-elf-psabi-doc is the repo, 
I was not able to find the PR for GCC. And I think the support within GCC is 
somewhat finished.

> @kito-cheng is the bigendian RISC-V work in GCC still active at all? I'm 
> wondering if there's a connection you could help make for Djordje.




Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D128612/new/

https://reviews.llvm.org/D128612

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D128612: RISC-V big-endian support implementation

2023-05-17 Thread Alex Bradbury via Phabricator via cfe-commits 
asb added a comment.

In D128612#4349259 , @djtodoro wrote:

> In D128612#4345912 , @asb wrote:
>
>> In D128612#4337037 , @djtodoro 
>> wrote:
>>
>>> Hi! I am wondering if someone knows what is the status of this.
>>
>> I've not seen any further progress. I think it needs at a minimum a PR 
>> against the psABI doc for big endian that we can review against.
>
> OK. Can you please share with me the GCC PR, so I can take a look how it 
> should be done :)

Based on comments here it sounds like GCC merged some level of support without 
submitting corresponding changes to the psABI. I don't have those patches to 
hand, but you can probably find them on the GCC patches list. I think we've had 
enough unexpected compatibility issues by now that it's not really justifiable 
to merge something that's meant to be a standard ABI without having the 
corresponding psABI patch (even if it appears simple). I don't think anyone has 
posted such a psABI patch but there is/was a tracking issue for it on the psABI 
repo.

@kito-cheng is the bigendian RISC-V work in GCC still active at all? I'm 
wondering if there's a connection you could help make for Djordje.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D128612/new/

https://reviews.llvm.org/D128612

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D128612: RISC-V big-endian support implementation

2023-05-17 Thread Djordje Todorovic via Phabricator via cfe-commits 
djtodoro added a comment.

In D128612#4345912 , @asb wrote:

> In D128612#4337037 , @djtodoro 
> wrote:
>
>> Hi! I am wondering if someone knows what is the status of this.
>
> I've not seen any further progress. I think it needs at a minimum a PR 
> against the psABI doc for big endian that we can review against.

OK. Can you please share with me the GCC PR, so I can take a look how it should 
be done :)


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D128612/new/

https://reviews.llvm.org/D128612

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D128612: RISC-V big-endian support implementation

2023-05-16 Thread Alex Bradbury via Phabricator via cfe-commits 
asb added a comment.

Thanks for this patch Guy. As just discussed in the RISC-V sync-up call, it 
would be helpful from a review perspective to write down at least a simple 
plain-text description of the changes to the psABI doc needed to reflect the BE 
ABI implemented by GCC (and soon LLVM), perhaps in an issue.

I think this patch is lacking some test coverage around things like fixup 
handling (e.g. the logic to swap fixups).

In D128612#4337037 , @djtodoro wrote:

> Hi! I am wondering if someone knows what is the status of this.

I've not seen any further progress. I think it needs at a minimum a PR against 
the psABI doc for big endian that we can review against.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D128612/new/

https://reviews.llvm.org/D128612

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D128612: RISC-V big-endian support implementation

2023-05-12 Thread Djordje Todorovic via Phabricator via cfe-commits 
djtodoro added a comment.
Herald added a subscriber: luke.

Hi! I wondering if someone knows what is the status of this.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D128612/new/

https://reviews.llvm.org/D128612

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D128612: RISC-V big-endian support implementation

2022-07-07 Thread Alex Bradbury via Phabricator via cfe-commits 
asb added a comment.

Thanks for this patch Guy. As just discussed in the RISC-V sync-up call, it 
would be helpful from a review perspective to write down at least a simple 
plain-text description of the changes to the psABI doc needed to reflect the BE 
ABI implemented by GCC (and soon LLVM), perhaps in an issue.

I think this patch is lacking some test coverage around things like fixup 
handling (e.g. the logic to swap fixups).


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D128612/new/

https://reviews.llvm.org/D128612

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D128612: RISC-V big-endian support implementation

2022-06-30 Thread Guy Benyei via Phabricator via cfe-commits 
gbenyei updated this revision to Diff 441410.
gbenyei added a comment.

Removed LLD and JIT related parts - JIT is out of my scope, and LLD will be in 
an additional patch.
Fixed additional remarks.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D128612/new/

https://reviews.llvm.org/D128612

Files:
  clang/include/clang/Basic/Attr.td
  clang/lib/Basic/Targets.cpp
  clang/lib/Basic/Targets/OSTargets.h
  clang/lib/Basic/Targets/RISCV.cpp
  clang/lib/Basic/Targets/RISCV.h
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/CodeGen/CodeGenModule.cpp
  clang/lib/CodeGen/TargetInfo.cpp
  clang/lib/Driver/Driver.cpp
  clang/lib/Driver/ToolChains/Arch/RISCV.cpp
  clang/lib/Driver/ToolChains/BareMetal.cpp
  clang/lib/Driver/ToolChains/Clang.cpp
  clang/lib/Driver/ToolChains/CommonArgs.cpp
  clang/lib/Driver/ToolChains/FreeBSD.cpp
  clang/lib/Driver/ToolChains/Gnu.cpp
  clang/lib/Driver/ToolChains/Linux.cpp
  clang/lib/Driver/ToolChains/RISCVToolchain.cpp
  clang/lib/Sema/SemaChecking.cpp
  clang/lib/Sema/SemaDeclAttr.cpp
  llvm/cmake/config.guess
  llvm/include/llvm/ADT/Triple.h
  llvm/include/llvm/Object/ELFObjectFile.h
  llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp
  llvm/lib/Object/RelocationResolver.cpp
  llvm/lib/Support/Triple.cpp
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.h
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCAsmInfo.cpp
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp
  llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
  llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
  llvm/lib/Target/RISCV/TargetInfo/RISCVTargetInfo.cpp
  llvm/lib/Target/RISCV/TargetInfo/RISCVTargetInfo.h
  llvm/lib/Transforms/Instrumentation/AddressSanitizer.cpp
  llvm/test/tools/llvm-objcopy/ELF/binary-output-target.test
  llvm/tools/llvm-objcopy/ObjcopyOptions.cpp
  llvm/unittests/Object/ELFObjectFileTest.cpp

Index: llvm/unittests/Object/ELFObjectFileTest.cpp
===
--- llvm/unittests/Object/ELFObjectFileTest.cpp
+++ llvm/unittests/Object/ELFObjectFileTest.cpp
@@ -186,10 +186,10 @@
 }
 
 TEST(ELFObjectFileTest, MachineTestForRISCV) {
-  std::array Formats = {"elf32-littleriscv", "elf32-littleriscv",
-  "elf64-littleriscv", "elf64-littleriscv"};
-  std::array Archs = {Triple::riscv32, Triple::riscv32,
-   Triple::riscv64, Triple::riscv64};
+  std::array Formats = {"elf32-littleriscv", "elf32-bigriscv",
+  "elf64-littleriscv", "elf64-bigriscv"};
+  std::array Archs = {Triple::riscv32, Triple::riscv32be,
+   Triple::riscv64, Triple::riscv64be};
   size_t I = 0;
   for (const DataForTest &D : generateData(ELF::EM_RISCV)) {
 checkFormatAndArch(D, Formats[I], Archs[I]);
Index: llvm/tools/llvm-objcopy/ObjcopyOptions.cpp
===
--- llvm/tools/llvm-objcopy/ObjcopyOptions.cpp
+++ llvm/tools/llvm-objcopy/ObjcopyOptions.cpp
@@ -301,6 +301,8 @@
 // RISC-V
 {"elf32-littleriscv", {ELF::EM_RISCV, false, true}},
 {"elf64-littleriscv", {ELF::EM_RISCV, true, true}},
+{"elf32-bigriscv", {ELF::EM_RISCV, false, false}},
+{"elf64-bigriscv", {ELF::EM_RISCV, true, false}},
 // PowerPC
 {"elf32-powerpc", {ELF::EM_PPC, false, false}},
 {"elf32-powerpcle", {ELF::EM_PPC, false, true}},
Index: llvm/test/tools/llvm-objcopy/ELF/binary-output-target.test
===
--- llvm/test/tools/llvm-objcopy/ELF/binary-output-target.test
+++ llvm/test/tools/llvm-objcopy/ELF/binary-output-target.test
@@ -33,6 +33,12 @@
 # RUN: llvm-objcopy -I binary -O elf64-littleriscv %t.txt %t.rv64.o
 # RUN: llvm-readobj --file-headers %t.rv64.o | FileCheck %s --check-prefixes=CHECK,LE,RISCV64,64
 
+# RUN: llvm-objcopy -I binary -O elf32-bigriscv %t.txt %t.rv32.o
+# RUN: llvm-readobj --file-headers %t.rv32.o | FileCheck %s --check-prefixes=CHECK,BE,RISCV32,32
+
+# RUN: llvm-objcopy -I binary -O elf64-bigriscv %t.txt %t.rv64.o
+# RUN: llvm-readobj --file-headers %t.rv64.o | FileCheck %s --check-prefixes=CHECK,BE,RISCV64,64
+
 # RUN: llvm-objcopy -I binary -O elf32-sparc %t.txt %t.sparc.o
 # RUN: llvm-readobj --file-headers %t.sparc.o | FileCheck %s --check-prefixes=CHECK,BE,SPARC,32
 
Index: llvm/lib/Transforms/Instrumentation/AddressSanitizer.cpp
===
--- llvm/lib/Transforms/Instrumentation/AddressSanitizer.cpp
+++ llvm/lib/Transforms/Instrumentation/AddressSanitizer.cpp
@@ -480,7 +480,8 @@
   bool IsMIPS64 = TargetTriple.isMIPS64();
   bool IsArmOrThumb = TargetTriple.isARM() || TargetTriple.isThumb();
   bool IsAArch64 = TargetTriple.getArc

[PATCH] D128612: RISC-V big-endian support implementation

2022-06-30 Thread Guy Benyei via Phabricator via cfe-commits 
gbenyei marked 3 inline comments as done.
gbenyei added inline comments.



Comment at: llvm/lib/ExecutionEngine/JITLink/ELF_riscv.cpp:554
 .buildGraph();
-  } else {
-assert((*ELFObj)->getArch() == Triple::riscv32 &&
-   "Invalid triple for RISCV ELF object file");
+  } else if ((*ELFObj)->getArch() == Triple::riscv64be) {
+auto &ELFObjFile = cast>(**ELFObj);

gbenyei wrote:
> jrtc27 wrote:
> > Why switch to this order when before you've used 32, 64, 32be, 64be as the 
> > order
> The order in the code before my changes is 64, 32. I guess for no good 
> reason, but I prefer not to re-order code while implementing a feature - it 
> trashes git history.
Removed this part anyway - JIT is out of scope for this commit. Thanks.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D128612/new/

https://reviews.llvm.org/D128612

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D128612: RISC-V big-endian support implementation

2022-06-29 Thread Fangrui Song via Phabricator via cfe-commits 
MaskRay added inline comments.



Comment at: clang/lib/Basic/Targets/RISCV.h:144
+
+StringRef LayoutEndianness = Triple.isLittleEndian() ? "e" : "E";
+

gbenyei wrote:
> MaskRay wrote:
> > You may use a `char` and possibly fold this into the expression below.
> Concatenating a conditional char and a string literal might be tricky, I'm 
> not sure there is a cleaner solution.
There is a constructor `Twine(char)`


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D128612/new/

https://reviews.llvm.org/D128612

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D128612: RISC-V big-endian support implementation

2022-06-29 Thread Guy Benyei via Phabricator via cfe-commits 
gbenyei marked 3 inline comments as done.
gbenyei added a comment.

In D128612#3620911 , @MaskRay wrote:

> In D128612#3618167 , @gbenyei wrote:
>
>> In D128612#3617955 , @MaskRay 
>> wrote:
>>
>>> lld/ELF change should be dropped from this change. Don't use 
>>> `config->endianness`.
>>> I feel sad that for little-endian users who don't use big-endian, every 
>>> write now is slightly slower due to a check ;-)
>>
>> Hi, I'm not sure I get it. How will we have a fully functional toolchain, if 
>> I don't implement the lld/ELF part?
>> In LLVM, unlike in GCC, target related decisions happen in runtime. I think 
>> it's a high level design decision. While I can understand the pain of LE 
>> developers getting a slightly slower linker due to endianness checking, I 
>> sure will feel the pain of a BE developer not having a linker...
>>
>> Please explain why I shouldn't use `config->endianness`?
>
> See PPC64.cpp. See D96188  how I added 
> aarch64_be support. A set of representative tests should be picked with be 
> tests.
> If llvm-project consensus is that we will add big-endian support, I can 
> handle lld/ELF part. I am mostly concerned with this scenarios that some 
> RISC-V folks click LGTM, and the change lands with no test in some areas, or 
> the code somewhat breaks local convention.
>
> Many of the changes in this patch probably should be split. llvm-objcopy and 
> JIT changes definitely needs appropriate tests and the suitable domain 
> reviewers.

Thanks, it makes more sense now. I'll split the LLD changes, and remove the JIT 
related stuff.




Comment at: clang/lib/Basic/Targets/RISCV.h:144
+
+StringRef LayoutEndianness = Triple.isLittleEndian() ? "e" : "E";
+

MaskRay wrote:
> You may use a `char` and possibly fold this into the expression below.
Concatenating a conditional char and a string literal might be tricky, I'm not 
sure there is a cleaner solution.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D128612/new/

https://reviews.llvm.org/D128612

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D128612: RISC-V big-endian support implementation

2022-06-29 Thread Fangrui Song via Phabricator via cfe-commits 
MaskRay added a comment.

In D128612#3618167 , @gbenyei wrote:

> In D128612#3617955 , @MaskRay wrote:
>
>> lld/ELF change should be dropped from this change. Don't use 
>> `config->endianness`.
>> I feel sad that for little-endian users who don't use big-endian, every 
>> write now is slightly slower due to a check ;-)
>
> Hi, I'm not sure I get it. How will we have a fully functional toolchain, if 
> I don't implement the lld/ELF part?
> In LLVM, unlike in GCC, target related decisions happen in runtime. I think 
> it's a high level design decision. While I can understand the pain of LE 
> developers getting a slightly slower linker due to endianness checking, I 
> sure will feel the pain of a BE developer not having a linker...
>
> Please explain why I shouldn't use `config->endianness`?

See PPC64.cpp. See D96188  how I added 
aarch64_be support. A set of representative tests should be picked with be 
tests.
If llvm-project consensus is that we will add big-endian support, I can handle 
lld/ELF part. I am mostly concerned with this scenarios that some RISC-V folks 
click LGTM, and the change lands with no test in some areas.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D128612/new/

https://reviews.llvm.org/D128612

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D128612: RISC-V big-endian support implementation

2022-06-29 Thread Guy Benyei via Phabricator via cfe-commits 
gbenyei added a comment.

In D128612#3617955 , @MaskRay wrote:

> lld/ELF change should be dropped from this change. Don't use 
> `config->endianness`.
> I feel sad that for little-endian users who don't use big-endian, every write 
> now is slightly slower due to a check ;-)

Hi, I'm not sure I get it. How will we have a fully functional toolchain, if I 
don't implement the lld/ELF part?
In LLVM, unlike in GCC, target related decisions happen in runtime. I think 
it's a high level design decision. While I can understand the pain of LE 
developers getting a slightly slower linker due to endianness checking, I sure 
will feel the pain of a BE developer not having a linker...

Please explain why I shouldn't use `config->endianness`?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D128612/new/

https://reviews.llvm.org/D128612

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D128612: RISC-V big-endian support implementation

2022-06-29 Thread Guy Benyei via Phabricator via cfe-commits 
gbenyei added a comment.

In D128612#3617906 , @jhenderson 
wrote:

> Objcopy aspects look good, thanks.

Thanks




Comment at: llvm/lib/ExecutionEngine/JITLink/ELF_riscv.cpp:554
 .buildGraph();
-  } else {
-assert((*ELFObj)->getArch() == Triple::riscv32 &&
-   "Invalid triple for RISCV ELF object file");
+  } else if ((*ELFObj)->getArch() == Triple::riscv64be) {
+auto &ELFObjFile = cast>(**ELFObj);

jrtc27 wrote:
> Why switch to this order when before you've used 32, 64, 32be, 64be as the 
> order
The order in the code before my changes is 64, 32. I guess for no good reason, 
but I prefer not to re-order code while implementing a feature - it trashes git 
history.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D128612/new/

https://reviews.llvm.org/D128612

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D128612: RISC-V big-endian support implementation

2022-06-29 Thread Fangrui Song via Phabricator via cfe-commits 
MaskRay added a comment.

lld/ELF change should be dropped from this change. Don't use 
`config->endianness`.
I feel sad that for little-endian users who don't use big-endian, every write 
now is slightly slower due to a check ;-)




Comment at: clang/lib/Basic/Targets/RISCV.cpp:124
   Builder.defineMacro("__riscv");
-  bool Is64Bit = getTriple().getArch() == llvm::Triple::riscv64;
+  bool Is64Bit = (getTriple().getArch() == llvm::Triple::riscv64 ||
+  getTriple().getArch() == llvm::Triple::riscv64be);

The convention doesn't add `()` in such an assignment.



Comment at: clang/lib/Basic/Targets/RISCV.cpp:220
 
-  if (getTriple().getArch() == llvm::Triple::riscv64) {
+  if (getTriple().getArch() == llvm::Triple::riscv64 ||
+  getTriple().getArch() == llvm::Triple::riscv64be) {

This can be simplified with something like `isRISCV64()`



Comment at: clang/lib/Basic/Targets/RISCV.h:144
+
+StringRef LayoutEndianness = Triple.isLittleEndian() ? "e" : "E";
+

You may use a `char` and possibly fold this into the expression below.



Comment at: clang/lib/Basic/Targets/RISCV.h:145
+StringRef LayoutEndianness = Triple.isLittleEndian() ? "e" : "E";
+
+resetDataLayout(

delete blank line


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D128612/new/

https://reviews.llvm.org/D128612

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D128612: RISC-V big-endian support implementation

2022-06-29 Thread James Henderson via Phabricator via cfe-commits 
jhenderson added a comment.

Objcopy aspects look good, thanks.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D128612/new/

https://reviews.llvm.org/D128612

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D128612: RISC-V big-endian support implementation

2022-06-28 Thread Guy Benyei via Phabricator via cfe-commits 
gbenyei updated this revision to Diff 440579.
gbenyei marked 7 inline comments as done.

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D128612/new/

https://reviews.llvm.org/D128612

Files:
  clang/include/clang/Basic/Attr.td
  clang/lib/Basic/Targets.cpp
  clang/lib/Basic/Targets/OSTargets.h
  clang/lib/Basic/Targets/RISCV.cpp
  clang/lib/Basic/Targets/RISCV.h
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/CodeGen/CodeGenModule.cpp
  clang/lib/CodeGen/TargetInfo.cpp
  clang/lib/Driver/Driver.cpp
  clang/lib/Driver/ToolChains/Arch/RISCV.cpp
  clang/lib/Driver/ToolChains/BareMetal.cpp
  clang/lib/Driver/ToolChains/Clang.cpp
  clang/lib/Driver/ToolChains/CommonArgs.cpp
  clang/lib/Driver/ToolChains/FreeBSD.cpp
  clang/lib/Driver/ToolChains/Gnu.cpp
  clang/lib/Driver/ToolChains/Linux.cpp
  clang/lib/Driver/ToolChains/RISCVToolchain.cpp
  clang/lib/Sema/SemaChecking.cpp
  clang/lib/Sema/SemaDeclAttr.cpp
  lld/ELF/Arch/RISCV.cpp
  lld/ELF/InputFiles.cpp
  lldb/source/Utility/ArchSpec.cpp
  llvm/cmake/config.guess
  llvm/include/llvm/ADT/Triple.h
  llvm/include/llvm/Object/ELFObjectFile.h
  llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp
  llvm/lib/ExecutionEngine/JITLink/ELF.cpp
  llvm/lib/ExecutionEngine/JITLink/ELF_riscv.cpp
  llvm/lib/ExecutionEngine/Orc/EPCIndirectionUtils.cpp
  llvm/lib/ExecutionEngine/Orc/IndirectionUtils.cpp
  llvm/lib/ExecutionEngine/Orc/LazyReexports.cpp
  llvm/lib/Object/RelocationResolver.cpp
  llvm/lib/Support/Triple.cpp
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.h
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCAsmInfo.cpp
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp
  llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
  llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
  llvm/lib/Target/RISCV/TargetInfo/RISCVTargetInfo.cpp
  llvm/lib/Target/RISCV/TargetInfo/RISCVTargetInfo.h
  llvm/lib/Transforms/Instrumentation/AddressSanitizer.cpp
  llvm/test/tools/llvm-objcopy/ELF/binary-output-target.test
  llvm/tools/llvm-objcopy/ObjcopyOptions.cpp
  llvm/unittests/Object/ELFObjectFileTest.cpp

Index: llvm/unittests/Object/ELFObjectFileTest.cpp
===
--- llvm/unittests/Object/ELFObjectFileTest.cpp
+++ llvm/unittests/Object/ELFObjectFileTest.cpp
@@ -186,10 +186,10 @@
 }
 
 TEST(ELFObjectFileTest, MachineTestForRISCV) {
-  std::array Formats = {"elf32-littleriscv", "elf32-littleriscv",
-  "elf64-littleriscv", "elf64-littleriscv"};
-  std::array Archs = {Triple::riscv32, Triple::riscv32,
-   Triple::riscv64, Triple::riscv64};
+  std::array Formats = {"elf32-littleriscv", "elf32-bigriscv",
+  "elf64-littleriscv", "elf64-bigriscv"};
+  std::array Archs = {Triple::riscv32, Triple::riscv32be,
+   Triple::riscv64, Triple::riscv64be};
   size_t I = 0;
   for (const DataForTest &D : generateData(ELF::EM_RISCV)) {
 checkFormatAndArch(D, Formats[I], Archs[I]);
Index: llvm/tools/llvm-objcopy/ObjcopyOptions.cpp
===
--- llvm/tools/llvm-objcopy/ObjcopyOptions.cpp
+++ llvm/tools/llvm-objcopy/ObjcopyOptions.cpp
@@ -301,6 +301,8 @@
 // RISC-V
 {"elf32-littleriscv", {ELF::EM_RISCV, false, true}},
 {"elf64-littleriscv", {ELF::EM_RISCV, true, true}},
+{"elf32-bigriscv", {ELF::EM_RISCV, false, false}},
+{"elf64-bigriscv", {ELF::EM_RISCV, true, false}},
 // PowerPC
 {"elf32-powerpc", {ELF::EM_PPC, false, false}},
 {"elf32-powerpcle", {ELF::EM_PPC, false, true}},
Index: llvm/test/tools/llvm-objcopy/ELF/binary-output-target.test
===
--- llvm/test/tools/llvm-objcopy/ELF/binary-output-target.test
+++ llvm/test/tools/llvm-objcopy/ELF/binary-output-target.test
@@ -33,6 +33,12 @@
 # RUN: llvm-objcopy -I binary -O elf64-littleriscv %t.txt %t.rv64.o
 # RUN: llvm-readobj --file-headers %t.rv64.o | FileCheck %s --check-prefixes=CHECK,LE,RISCV64,64
 
+# RUN: llvm-objcopy -I binary -O elf32-bigriscv %t.txt %t.rv32.o
+# RUN: llvm-readobj --file-headers %t.rv32.o | FileCheck %s --check-prefixes=CHECK,BE,RISCV32,32
+
+# RUN: llvm-objcopy -I binary -O elf64-bigriscv %t.txt %t.rv64.o
+# RUN: llvm-readobj --file-headers %t.rv64.o | FileCheck %s --check-prefixes=CHECK,BE,RISCV64,64
+
 # RUN: llvm-objcopy -I binary -O elf32-sparc %t.txt %t.sparc.o
 # RUN: llvm-readobj --file-headers %t.sparc.o | FileCheck %s --check-prefixes=CHECK,BE,SPARC,32
 
Index: llvm/lib/Transforms/Instrumentation/AddressSanitizer.cpp
===
--- llvm/lib/Transforms/Instrumentation/AddressSanitizer.cpp
+++ llvm/lib/T

[PATCH] D128612: RISC-V big-endian support implementation

2022-06-27 Thread Jessica Clarke via Phabricator via cfe-commits 
jrtc27 added inline comments.



Comment at: clang/lib/Basic/Targets/RISCV.h:113
+if (Triple.isLittleEndian())
+  resetDataLayout("e-m:e-p:32:32-i64:64-n32-S128");
+else

And please avoid repeating the whole data layout, just make the e/E a variable



Comment at: clang/lib/Driver/ToolChains/FreeBSD.cpp:235
+CmdArgs.push_back("-m");
+CmdArgs.push_back("elf32briscv");
+break;

-X to match LE. Or ditch these (and I can ditch riscv32...) since FreeBSD only 
supports riscv64.



Comment at: clang/lib/Driver/ToolChains/Gnu.cpp:1700
 {M.gccSuffix(),
  "/../../../../riscv64-unknown-elf/lib" + M.gccSuffix(),
  "/../../../../riscv32-unknown-elf/lib" + M.gccSuffix()});

Just shove a `+ Be +` in the middle of these two rather than introducing a 
whole new set and picking between them?



Comment at: llvm/cmake/config-ix.cmake:463
   set(LLVM_NATIVE_ARCH RISCV)
+elseif (LLVM_NATIVE_ARCH MATCHES "riscv32be")
+  set(LLVM_NATIVE_ARCH RISCV)

I believe these need to come before the unsuffixed versions to do anything, but 
also the unsuffixed versions already handle the suffixed versions correctly so 
this isn't needed?



Comment at: llvm/lib/ExecutionEngine/JITLink/ELF_riscv.cpp:554
 .buildGraph();
-  } else {
-assert((*ELFObj)->getArch() == Triple::riscv32 &&
-   "Invalid triple for RISCV ELF object file");
+  } else if ((*ELFObj)->getArch() == Triple::riscv64be) {
+auto &ELFObjFile = cast>(**ELFObj);

Why switch to this order when before you've used 32, 64, 32be, 64be as the order



Comment at: llvm/lib/Target/RISCV/RISCVTargetMachine.cpp:65
+
+return "E-m:e-p:64:64-i64:64-i128:128-n64-S128";
+  }

As with Clang


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D128612/new/

https://reviews.llvm.org/D128612

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D128612: RISC-V big-endian support implementation

2022-06-27 Thread Guy Benyei via Phabricator via cfe-commits 
gbenyei updated this revision to Diff 440196.
gbenyei added a comment.

Thanks, Craig. Updated the patch with your remarks.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D128612/new/

https://reviews.llvm.org/D128612

Files:
  clang/include/clang/Basic/Attr.td
  clang/lib/Basic/Targets.cpp
  clang/lib/Basic/Targets/OSTargets.h
  clang/lib/Basic/Targets/RISCV.cpp
  clang/lib/Basic/Targets/RISCV.h
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/CodeGen/CodeGenModule.cpp
  clang/lib/CodeGen/TargetInfo.cpp
  clang/lib/Driver/Driver.cpp
  clang/lib/Driver/ToolChains/Arch/RISCV.cpp
  clang/lib/Driver/ToolChains/BareMetal.cpp
  clang/lib/Driver/ToolChains/Clang.cpp
  clang/lib/Driver/ToolChains/CommonArgs.cpp
  clang/lib/Driver/ToolChains/FreeBSD.cpp
  clang/lib/Driver/ToolChains/Gnu.cpp
  clang/lib/Driver/ToolChains/Linux.cpp
  clang/lib/Driver/ToolChains/RISCVToolchain.cpp
  clang/lib/Sema/SemaChecking.cpp
  clang/lib/Sema/SemaDeclAttr.cpp
  lld/ELF/Arch/RISCV.cpp
  lld/ELF/InputFiles.cpp
  lldb/source/Utility/ArchSpec.cpp
  llvm/cmake/config-ix.cmake
  llvm/cmake/config.guess
  llvm/include/llvm/ADT/Triple.h
  llvm/include/llvm/Object/ELFObjectFile.h
  llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp
  llvm/lib/ExecutionEngine/JITLink/ELF.cpp
  llvm/lib/ExecutionEngine/JITLink/ELF_riscv.cpp
  llvm/lib/ExecutionEngine/Orc/EPCIndirectionUtils.cpp
  llvm/lib/ExecutionEngine/Orc/IndirectionUtils.cpp
  llvm/lib/ExecutionEngine/Orc/LazyReexports.cpp
  llvm/lib/Object/RelocationResolver.cpp
  llvm/lib/Support/Triple.cpp
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.h
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCAsmInfo.cpp
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp
  llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
  llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
  llvm/lib/Target/RISCV/TargetInfo/RISCVTargetInfo.cpp
  llvm/lib/Target/RISCV/TargetInfo/RISCVTargetInfo.h
  llvm/lib/Transforms/Instrumentation/AddressSanitizer.cpp
  llvm/tools/llvm-objcopy/ObjcopyOptions.cpp
  llvm/unittests/Object/ELFObjectFileTest.cpp

Index: llvm/unittests/Object/ELFObjectFileTest.cpp
===
--- llvm/unittests/Object/ELFObjectFileTest.cpp
+++ llvm/unittests/Object/ELFObjectFileTest.cpp
@@ -186,10 +186,10 @@
 }
 
 TEST(ELFObjectFileTest, MachineTestForRISCV) {
-  std::array Formats = {"elf32-littleriscv", "elf32-littleriscv",
-  "elf64-littleriscv", "elf64-littleriscv"};
-  std::array Archs = {Triple::riscv32, Triple::riscv32,
-   Triple::riscv64, Triple::riscv64};
+  std::array Formats = {"elf32-littleriscv", "elf32-bigriscv",
+  "elf64-littleriscv", "elf64-bigriscv"};
+  std::array Archs = {Triple::riscv32, Triple::riscv32be,
+   Triple::riscv64, Triple::riscv64be};
   size_t I = 0;
   for (const DataForTest &D : generateData(ELF::EM_RISCV)) {
 checkFormatAndArch(D, Formats[I], Archs[I]);
Index: llvm/tools/llvm-objcopy/ObjcopyOptions.cpp
===
--- llvm/tools/llvm-objcopy/ObjcopyOptions.cpp
+++ llvm/tools/llvm-objcopy/ObjcopyOptions.cpp
@@ -301,6 +301,8 @@
 // RISC-V
 {"elf32-littleriscv", {ELF::EM_RISCV, false, true}},
 {"elf64-littleriscv", {ELF::EM_RISCV, true, true}},
+{"elf32-bigriscv", {ELF::EM_RISCV, false, false}},
+{"elf64-bigriscv", {ELF::EM_RISCV, true, false}},
 // PowerPC
 {"elf32-powerpc", {ELF::EM_PPC, false, false}},
 {"elf32-powerpcle", {ELF::EM_PPC, false, true}},
Index: llvm/lib/Transforms/Instrumentation/AddressSanitizer.cpp
===
--- llvm/lib/Transforms/Instrumentation/AddressSanitizer.cpp
+++ llvm/lib/Transforms/Instrumentation/AddressSanitizer.cpp
@@ -479,7 +479,8 @@
   bool IsMIPS64 = TargetTriple.isMIPS64();
   bool IsArmOrThumb = TargetTriple.isARM() || TargetTriple.isThumb();
   bool IsAArch64 = TargetTriple.getArch() == Triple::aarch64;
-  bool IsRISCV64 = TargetTriple.getArch() == Triple::riscv64;
+  bool IsRISCV64 = TargetTriple.getArch() == Triple::riscv64 ||
+   TargetTriple.getArch() == Triple::riscv64be;
   bool IsWindows = TargetTriple.isOSWindows();
   bool IsFuchsia = TargetTriple.isOSFuchsia();
   bool IsEmscripten = TargetTriple.isOSEmscripten();
Index: llvm/lib/Target/RISCV/TargetInfo/RISCVTargetInfo.h
===
--- llvm/lib/Target/RISCV/TargetInfo/RISCVTargetInfo.h
+++ llvm/lib/Target/RISCV/TargetInfo/RISCVTargetInfo.h
@@ -15,6 +15,8 @@
 
 Target &getTheRISCV32Target();
 Target &getTheRISCV64Target();
+Target &getTheRISCV32beTarget

[PATCH] D128612: RISC-V big-endian support implementation

2022-06-27 Thread James Henderson via Phabricator via cfe-commits 
jhenderson added inline comments.



Comment at: llvm/include/llvm/ADT/Triple.h:864
 
   /// Tests whether the target is RISC-V (32- and 64-bit).
   bool isRISCV() const {

Perhaps worth updating to mention big and little endian here, like `isPPC64` 
above?



Comment at: llvm/tools/llvm-objcopy/ObjcopyOptions.cpp:304-305
 {"elf64-littleriscv", {ELF::EM_RISCV, true, true}},
+{"elf32-bigriscv", {ELF::EM_RISCV, false, false}},
+{"elf64-bigriscv", {ELF::EM_RISCV, true, false}},
 // PowerPC

We need llvm-objcopy testing for these new targets.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D128612/new/

https://reviews.llvm.org/D128612

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D128612: RISC-V big-endian support implementation

2022-06-26 Thread Craig Topper via Phabricator via cfe-commits 
craig.topper added inline comments.



Comment at: clang/lib/Basic/Targets/RISCV.h:111
 SizeType = UnsignedInt;
-resetDataLayout("e-m:e-p:32:32-i64:64-n32-S128");
   }

Instead of creating new classes, could we have a branch on the Arch or 
isLittleEndian portion of the triple to decide what to pass to resetDataLayout? 
That's what PPC32TargetInfo does for example.



Comment at: lld/ELF/Arch/RISCV.cpp:160
+  if (config->is64) {
+if (config->isLE)
+  write64le(buf, mainPart->dynamic->getVA());

Is it possible to use write64 instead of write64le/be? It looks like it checks 
the endianness internally.



Comment at: llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp:628
+  // For big endian cores, data fixup should be swapped.
+  bool swapValue = (Endian == support::big) && isDataFixup(Kind);
   for (unsigned i = 0; i != NumBytes; ++i) {

Capitalize `swapValue`



Comment at: llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.h:34
   const MCTargetOptions &Options)
-  : MCAsmBackend(support::little), STI(STI), OSABI(OSABI), 
Is64Bit(Is64Bit),
+  : MCAsmBackend(IsLittleEndian ? support::little : support::big), 
STI(STI), OSABI(OSABI), Is64Bit(Is64Bit),
 TargetOptions(Options) {

Is this longer than 80 columns?



Comment at: llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCAsmInfo.cpp:24
+  if (TT.getArch() == Triple::riscv32be || TT.getArch() == Triple::riscv64be)
+IsLittleEndian = false;
+

Could we do IsLittleEndian = TT.isLittleEndian()?



Comment at: llvm/lib/Target/RISCV/RISCVTargetMachine.cpp:64
+  return "e-m:e-p:64:64-i64:64-i128:128-n64-S128";
+else
+  return "E-m:e-p:64:64-i64:64-i128:128-n64-S128";

No else after return


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D128612/new/

https://reviews.llvm.org/D128612

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D128612: RISC-V big-endian support implementation

2022-06-26 Thread Guy Benyei via Phabricator via cfe-commits 
gbenyei created this revision.
gbenyei added a reviewer: asb.
gbenyei added projects: clang, LLVM, lld.
Herald added subscribers: Enna1, sunshaoce, VincentWu, luke957, StephenFan, 
vkmr, frasercrmck, luismarques, apazos, sameer.abuasal, s.egerton, Jim, ormris, 
jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, 
zzheng, jrtc27, shiva0217, kito-cheng, niosHD, sabuasal, simoncook, johnrusso, 
rbar, hiraditya, arichardson, mgorny, emaste.
Herald added a reviewer: alexander-shaposhnikov.
Herald added a reviewer: rupprecht.
Herald added a reviewer: jhenderson.
Herald added a reviewer: MaskRay.
Herald added a reviewer: aaron.ballman.
Herald added a project: All.
gbenyei requested review of this revision.
Herald added subscribers: lldb-commits, cfe-commits, pcwang-thead.
Herald added a project: LLDB.

Implement riscv32be and riscv64be targets.
The RISC-V big- and bi-endian targets are discussed in the RISC-V spec  Version 
20191213, but some aspects, like ABI are still unclear.
The instruction encoding is little endian in both big- and little-endian modes. 
ISA spec Volume 1 1.15: "Instructions are stored in memory as a sequence
of 16-bit little-endian parcels, regardless of memory system endianness".

RISC-V Big-endian cores are already supported by GCC. Where spec is unclear, we 
aim to be compatible with GCC.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D128612

Files:
  clang/include/clang/Basic/Attr.td
  clang/lib/Basic/Targets.cpp
  clang/lib/Basic/Targets/OSTargets.h
  clang/lib/Basic/Targets/RISCV.cpp
  clang/lib/Basic/Targets/RISCV.h
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/CodeGen/CodeGenModule.cpp
  clang/lib/CodeGen/TargetInfo.cpp
  clang/lib/Driver/Driver.cpp
  clang/lib/Driver/ToolChains/Arch/RISCV.cpp
  clang/lib/Driver/ToolChains/BareMetal.cpp
  clang/lib/Driver/ToolChains/Clang.cpp
  clang/lib/Driver/ToolChains/CommonArgs.cpp
  clang/lib/Driver/ToolChains/FreeBSD.cpp
  clang/lib/Driver/ToolChains/Gnu.cpp
  clang/lib/Driver/ToolChains/Linux.cpp
  clang/lib/Driver/ToolChains/RISCVToolchain.cpp
  clang/lib/Sema/SemaChecking.cpp
  clang/lib/Sema/SemaDeclAttr.cpp
  lld/ELF/Arch/RISCV.cpp
  lld/ELF/InputFiles.cpp
  lldb/source/Utility/ArchSpec.cpp
  llvm/cmake/config-ix.cmake
  llvm/cmake/config.guess
  llvm/include/llvm/ADT/Triple.h
  llvm/include/llvm/Object/ELFObjectFile.h
  llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp
  llvm/lib/ExecutionEngine/JITLink/ELF.cpp
  llvm/lib/ExecutionEngine/JITLink/ELF_riscv.cpp
  llvm/lib/ExecutionEngine/Orc/EPCIndirectionUtils.cpp
  llvm/lib/ExecutionEngine/Orc/IndirectionUtils.cpp
  llvm/lib/ExecutionEngine/Orc/LazyReexports.cpp
  llvm/lib/Object/RelocationResolver.cpp
  llvm/lib/Support/Triple.cpp
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.h
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCAsmInfo.cpp
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp
  llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
  llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
  llvm/lib/Target/RISCV/TargetInfo/RISCVTargetInfo.cpp
  llvm/lib/Target/RISCV/TargetInfo/RISCVTargetInfo.h
  llvm/lib/Transforms/Instrumentation/AddressSanitizer.cpp
  llvm/tools/llvm-objcopy/ObjcopyOptions.cpp
  llvm/unittests/Object/ELFObjectFileTest.cpp

Index: llvm/unittests/Object/ELFObjectFileTest.cpp
===
--- llvm/unittests/Object/ELFObjectFileTest.cpp
+++ llvm/unittests/Object/ELFObjectFileTest.cpp
@@ -186,10 +186,10 @@
 }
 
 TEST(ELFObjectFileTest, MachineTestForRISCV) {
-  std::array Formats = {"elf32-littleriscv", "elf32-littleriscv",
-  "elf64-littleriscv", "elf64-littleriscv"};
-  std::array Archs = {Triple::riscv32, Triple::riscv32,
-   Triple::riscv64, Triple::riscv64};
+  std::array Formats = {"elf32-littleriscv", "elf32-bigriscv",
+  "elf64-littleriscv", "elf64-bigriscv"};
+  std::array Archs = {Triple::riscv32, Triple::riscv32be,
+   Triple::riscv64, Triple::riscv64be};
   size_t I = 0;
   for (const DataForTest &D : generateData(ELF::EM_RISCV)) {
 checkFormatAndArch(D, Formats[I], Archs[I]);
Index: llvm/tools/llvm-objcopy/ObjcopyOptions.cpp
===
--- llvm/tools/llvm-objcopy/ObjcopyOptions.cpp
+++ llvm/tools/llvm-objcopy/ObjcopyOptions.cpp
@@ -301,6 +301,8 @@
 // RISC-V
 {"elf32-littleriscv", {ELF::EM_RISCV, false, true}},
 {"elf64-littleriscv", {ELF::EM_RISCV, true, true}},
+{"elf32-bigriscv", {ELF::EM_RISCV, false, false}},
+{"elf64-bigriscv", {ELF::EM_RISCV, true, false}},
 // PowerPC
 {"elf32-powerpc", {ELF::EM_PPC, false, false}},
 {"elf32-powerpcle", {ELF::EM_PPC, fa