[PATCH] D128714: [clang-format] Handle Verilog case statements

[sstwcw via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rGc88719483c69: [clang-format] Handle Verilog case statements 
(authored by sstwcw).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D128714/new/

https://reviews.llvm.org/D128714

Files:
  clang/lib/Format/ContinuationIndenter.cpp
  clang/lib/Format/Format.cpp
  clang/lib/Format/FormatToken.h
  clang/lib/Format/TokenAnnotator.cpp
  clang/lib/Format/UnwrappedLineParser.cpp
  clang/lib/Format/UnwrappedLineParser.h
  clang/unittests/Format/FormatTestVerilog.cpp
  clang/unittests/Format/TokenAnnotatorTest.cpp

Index: clang/unittests/Format/TokenAnnotatorTest.cpp
===
--- clang/unittests/Format/TokenAnnotatorTest.cpp
+++ clang/unittests/Format/TokenAnnotatorTest.cpp
@@ -838,6 +838,21 @@
   Tokens = Annotate("extern function [1 : 0] x;");
   ASSERT_EQ(Tokens.size(), 10u) << Tokens;
   EXPECT_TOKEN(Tokens[4], tok::colon, TT_BitFieldColon);
+  // Test case labels and ternary operators.
+  Tokens = Annotate("case (x)\n"
+"  x:\n"
+"x;\n"
+"endcase\n");
+  ASSERT_EQ(Tokens.size(), 10u) << Tokens;
+  EXPECT_TOKEN(Tokens[5], tok::colon, TT_GotoLabelColon);
+  Tokens = Annotate("case (x)\n"
+"  x ? x : x:\n"
+"x;\n"
+"endcase\n");
+  ASSERT_EQ(Tokens.size(), 14u) << Tokens;
+  EXPECT_TOKEN(Tokens[5], tok::question, TT_ConditionalExpr);
+  EXPECT_TOKEN(Tokens[7], tok::colon, TT_ConditionalExpr);
+  EXPECT_TOKEN(Tokens[9], tok::colon, TT_GotoLabelColon);
 }
 
 } // namespace
Index: clang/unittests/Format/FormatTestVerilog.cpp
===
--- clang/unittests/Format/FormatTestVerilog.cpp
+++ clang/unittests/Format/FormatTestVerilog.cpp
@@ -116,6 +116,90 @@
"x = x;");
 }
 
+TEST_F(FormatTestVerilog, Case) {
+  verifyFormat("case (data)\n"
+   "endcase");
+  verifyFormat("casex (data)\n"
+   "endcase");
+  verifyFormat("casez (data)\n"
+   "endcase");
+  verifyFormat("case (data) inside\n"
+   "endcase");
+  verifyFormat("case (data)\n"
+   "  16'd0:\n"
+   "result = 10'b01;\n"
+   "endcase");
+  verifyFormat("case (data)\n"
+   "  :\n"
+   "result = 10'b01;\n"
+   "endcase");
+  // Test labels with multiple options.
+  verifyFormat("case (data)\n"
+   "  16'd0, 16'd1:\n"
+   "result = 10'b01;\n"
+   "endcase");
+  verifyFormat("case (data)\n"
+   "  16'd0, //\n"
+   "  16'd1:\n"
+   "result = 10'b01;\n"
+   "endcase");
+  // Test that blocks following labels are indented.
+  verifyFormat("case (data)\n"
+   "  16'd1: fork\n"
+   "result = 10'b10;\n"
+   "  join\n"
+   "endcase\n");
+  verifyFormat("case (data)\n"
+   "  16'd1: fork : x\n"
+   "result = 10'b10;\n"
+   "  join : x\n"
+   "endcase\n");
+  // Test default.
+  verifyFormat("case (data)\n"
+   "  default\n"
+   "result = 10'b10;\n"
+   "endcase");
+  verifyFormat("case (data)\n"
+   "  default:\n"
+   "result = 10'b10;\n"
+   "endcase");
+  // Test that question marks and colons don't get mistaken as labels.
+  verifyFormat("case (data)\n"
+   "  8'b1???:\n"
+   "instruction1(ir);\n"
+   "endcase");
+  verifyFormat("case (data)\n"
+   "  x ? 8'b1??? : 1:\n"
+   "instruction3(ir);\n"
+   "endcase");
+  // Test indention options.
+  auto Style = getLLVMStyle(FormatStyle::LK_Verilog);
+  Style.IndentCaseLabels = false;
+  verifyFormat("case (data)\n"
+   "16'd0:\n"
+   "  result = 10'b01;\n"
+   "endcase",
+   Style);
+  verifyFormat("case (data)\n"
+   "16'd0: begin\n"
+   "  result = 10'b01;\n"
+   "end\n"
+   "endcase",
+   Style);
+  Style.IndentCaseLabels = true;
+  verifyFormat("case (data)\n"
+   "  16'd0:\n"
+   "result = 10'b01;\n"
+   "endcase",
+   Style);
+  verifyFormat("case (data)\n"
+   "  16'd0: begin\n"
+   "result = 10'b01;\n"
+   "  end\n"
+   "endcase",
+   Style);
+}
+
 TEST_F(FormatTestVerilog, Delay) {
   // Delay by the default unit.
   verifyFormat("#0;");
Index: clang/lib/Format/UnwrappedLineParser.h

[PATCH] D128714: [clang-format] Handle Verilog case statements

[sstwcw via Phabricator via cfe-commits]

sstwcw updated this revision to Diff 443608.

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D128714/new/

https://reviews.llvm.org/D128714

Files:
  clang/lib/Format/ContinuationIndenter.cpp
  clang/lib/Format/Format.cpp
  clang/lib/Format/FormatToken.h
  clang/lib/Format/TokenAnnotator.cpp
  clang/lib/Format/UnwrappedLineParser.cpp
  clang/lib/Format/UnwrappedLineParser.h
  clang/unittests/Format/FormatTestVerilog.cpp
  clang/unittests/Format/TokenAnnotatorTest.cpp

Index: clang/unittests/Format/TokenAnnotatorTest.cpp
===
--- clang/unittests/Format/TokenAnnotatorTest.cpp
+++ clang/unittests/Format/TokenAnnotatorTest.cpp
@@ -901,6 +901,21 @@
   Tokens = Annotate("extern function [1 : 0] x;");
   ASSERT_EQ(Tokens.size(), 10u) << Tokens;
   EXPECT_TOKEN(Tokens[4], tok::colon, TT_BitFieldColon);
+  // Test case labels and ternary operators.
+  Tokens = Annotate("case (x)\n"
+"  x:\n"
+"x;\n"
+"endcase\n");
+  ASSERT_EQ(Tokens.size(), 10u) << Tokens;
+  EXPECT_TOKEN(Tokens[5], tok::colon, TT_GotoLabelColon);
+  Tokens = Annotate("case (x)\n"
+"  x ? x : x:\n"
+"x;\n"
+"endcase\n");
+  ASSERT_EQ(Tokens.size(), 14u) << Tokens;
+  EXPECT_TOKEN(Tokens[5], tok::question, TT_ConditionalExpr);
+  EXPECT_TOKEN(Tokens[7], tok::colon, TT_ConditionalExpr);
+  EXPECT_TOKEN(Tokens[9], tok::colon, TT_GotoLabelColon);
 }
 
 } // namespace
Index: clang/unittests/Format/FormatTestVerilog.cpp
===
--- clang/unittests/Format/FormatTestVerilog.cpp
+++ clang/unittests/Format/FormatTestVerilog.cpp
@@ -116,6 +116,90 @@
"x = x;");
 }
 
+TEST_F(FormatTestVerilog, Case) {
+  verifyFormat("case (data)\n"
+   "endcase");
+  verifyFormat("casex (data)\n"
+   "endcase");
+  verifyFormat("casez (data)\n"
+   "endcase");
+  verifyFormat("case (data) inside\n"
+   "endcase");
+  verifyFormat("case (data)\n"
+   "  16'd0:\n"
+   "result = 10'b01;\n"
+   "endcase");
+  verifyFormat("case (data)\n"
+   "  :\n"
+   "result = 10'b01;\n"
+   "endcase");
+  // Test labels with multiple options.
+  verifyFormat("case (data)\n"
+   "  16'd0, 16'd1:\n"
+   "result = 10'b01;\n"
+   "endcase");
+  verifyFormat("case (data)\n"
+   "  16'd0, //\n"
+   "  16'd1:\n"
+   "result = 10'b01;\n"
+   "endcase");
+  // Test that blocks following labels are indented.
+  verifyFormat("case (data)\n"
+   "  16'd1: fork\n"
+   "result = 10'b10;\n"
+   "  join\n"
+   "endcase\n");
+  verifyFormat("case (data)\n"
+   "  16'd1: fork : x\n"
+   "result = 10'b10;\n"
+   "  join : x\n"
+   "endcase\n");
+  // Test default.
+  verifyFormat("case (data)\n"
+   "  default\n"
+   "result = 10'b10;\n"
+   "endcase");
+  verifyFormat("case (data)\n"
+   "  default:\n"
+   "result = 10'b10;\n"
+   "endcase");
+  // Test that question marks and colons don't get mistaken as labels.
+  verifyFormat("case (data)\n"
+   "  8'b1???:\n"
+   "instruction1(ir);\n"
+   "endcase");
+  verifyFormat("case (data)\n"
+   "  x ? 8'b1??? : 1:\n"
+   "instruction3(ir);\n"
+   "endcase");
+  // Test indention options.
+  auto Style = getLLVMStyle(FormatStyle::LK_Verilog);
+  Style.IndentCaseLabels = false;
+  verifyFormat("case (data)\n"
+   "16'd0:\n"
+   "  result = 10'b01;\n"
+   "endcase",
+   Style);
+  verifyFormat("case (data)\n"
+   "16'd0: begin\n"
+   "  result = 10'b01;\n"
+   "end\n"
+   "endcase",
+   Style);
+  Style.IndentCaseLabels = true;
+  verifyFormat("case (data)\n"
+   "  16'd0:\n"
+   "result = 10'b01;\n"
+   "endcase",
+   Style);
+  verifyFormat("case (data)\n"
+   "  16'd0: begin\n"
+   "result = 10'b01;\n"
+   "  end\n"
+   "endcase",
+   Style);
+}
+
 TEST_F(FormatTestVerilog, Delay) {
   // Delay by the default unit.
   verifyFormat("#0;");
Index: clang/lib/Format/UnwrappedLineParser.h
===
--- clang/lib/Format/UnwrappedLineParser.h
+++ clang/lib/Format/UnwrappedLineParser.h
@@ -183,6 

[PATCH] D128714: [clang-format] Handle Verilog case statements

[Björn Schäpers via Phabricator via cfe-commits]

HazardyKnusperkeks added inline comments.



Comment at: clang/lib/Format/Format.cpp:1265
   LLVMStyle.IndentAccessModifiers = false;
-  LLVMStyle.IndentCaseLabels = false;
+  LLVMStyle.IndentCaseLabels = LLVMStyle.isVerilog() ? true : false;
   LLVMStyle.IndentCaseBlocks = false;

You should put that below.



Comment at: clang/lib/Format/Format.cpp:1349
 
   // Defaults that differ when not C++.
   if (Language == FormatStyle::LK_TableGen)

Here.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D128714/new/

https://reviews.llvm.org/D128714

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[PATCH] D128714: [clang-format] Handle Verilog case statements

[sstwcw via Phabricator via cfe-commits]

sstwcw created this revision.
sstwcw added reviewers: HazardyKnusperkeks, MyDeveloperDay, curdeius, owenpan.
Herald added a project: All.
sstwcw requested review of this revision.
Herald added a project: clang.
Herald added a subscriber: cfe-commits.

These statements are like switch statements in C, but without the 'case'
keyword in labels.

How labels are parsed.  In UnwrappedLineParser, the program tries to
parse a statement every time it sees a colon.  In TokenAnnotator, a
colon that isn't part of an expression is annotated as a label.

The token type `TT_GotoLabelColon` is added.  We did not include Verilog
in the name because we thought we would eventually have to fix the
problem that case labels in C can't contain ternary conditional
expressions and we would use that token type.

The style is like below.  Labels are on separate lines and indented by
default.  The linked style guide also has examples where labels and the
corresponding statements are on the same lines.  They are not supported
for now.

https://github.com/lowRISC/style-guides/blob/master/VerilogCodingStyle.md

  case (state_q)
StIdle:
  state_d = StA;
StA: begin
  state_d = StB;
end
  endcase


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D128714

Files:
  clang/lib/Format/ContinuationIndenter.cpp
  clang/lib/Format/Format.cpp
  clang/lib/Format/FormatToken.h
  clang/lib/Format/TokenAnnotator.cpp
  clang/lib/Format/UnwrappedLineParser.cpp
  clang/lib/Format/UnwrappedLineParser.h
  clang/unittests/Format/FormatTestVerilog.cpp
  clang/unittests/Format/TokenAnnotatorTest.cpp

Index: clang/unittests/Format/TokenAnnotatorTest.cpp
===
--- clang/unittests/Format/TokenAnnotatorTest.cpp
+++ clang/unittests/Format/TokenAnnotatorTest.cpp
@@ -875,6 +875,21 @@
   Tokens = Annotate("extern function [1 : 0] x;");
   ASSERT_EQ(Tokens.size(), 10u) << Tokens;
   EXPECT_TOKEN(Tokens[4], tok::colon, TT_BitFieldColon);
+  // Test case labels and ternary operators.
+  Tokens = Annotate("case (x)\n"
+"  x:\n"
+"x;\n"
+"endcase\n");
+  ASSERT_EQ(Tokens.size(), 10u) << Tokens;
+  EXPECT_TOKEN(Tokens[5], tok::colon, TT_GotoLabelColon);
+  Tokens = Annotate("case (x)\n"
+"  x ? x : x:\n"
+"x;\n"
+"endcase\n");
+  ASSERT_EQ(Tokens.size(), 14u) << Tokens;
+  EXPECT_TOKEN(Tokens[5], tok::question, TT_ConditionalExpr);
+  EXPECT_TOKEN(Tokens[7], tok::colon, TT_ConditionalExpr);
+  EXPECT_TOKEN(Tokens[9], tok::colon, TT_GotoLabelColon);
 }
 
 } // namespace
Index: clang/unittests/Format/FormatTestVerilog.cpp
===
--- clang/unittests/Format/FormatTestVerilog.cpp
+++ clang/unittests/Format/FormatTestVerilog.cpp
@@ -116,6 +116,90 @@
"x = x;");
 }
 
+TEST_F(FormatTestVerilog, Case) {
+  verifyFormat("case (data)\n"
+   "endcase");
+  verifyFormat("casex (data)\n"
+   "endcase");
+  verifyFormat("casez (data)\n"
+   "endcase");
+  verifyFormat("case (data) inside\n"
+   "endcase");
+  verifyFormat("case (data)\n"
+   "  16'd0:\n"
+   "result = 10'b01;\n"
+   "endcase");
+  verifyFormat("case (data)\n"
+   "  :\n"
+   "result = 10'b01;\n"
+   "endcase");
+  // Test labels with multiple options.
+  verifyFormat("case (data)\n"
+   "  16'd0, 16'd1:\n"
+   "result = 10'b01;\n"
+   "endcase");
+  verifyFormat("case (data)\n"
+   "  16'd0, //\n"
+   "  16'd1:\n"
+   "result = 10'b01;\n"
+   "endcase");
+  // Test that blocks following labels are indented.
+  verifyFormat("case (data)\n"
+   "  16'd1: fork\n"
+   "result = 10'b10;\n"
+   "  join\n"
+   "endcase\n");
+  verifyFormat("case (data)\n"
+   "  16'd1: fork : x\n"
+   "result = 10'b10;\n"
+   "  join : x\n"
+   "endcase\n");
+  // Test default.
+  verifyFormat("case (data)\n"
+   "  default\n"
+   "result = 10'b10;\n"
+   "endcase");
+  verifyFormat("case (data)\n"
+   "  default:\n"
+   "result = 10'b10;\n"
+   "endcase");
+  // Test that question marks and colons don't get mistaken as labels.
+  verifyFormat("case (data)\n"
+   "  8'b1???:\n"
+   "instruction1(ir);\n"
+   "endcase");
+  verifyFormat("case (data)\n"
+   "  x ? 8'b1??? : 1:\n"
+   "instruction3(ir);\n"
+   "endcase");
+  // Test indention options.
+  auto Style =