[PATCH] D129043: [RISCV][Clang] Teach RISCVEmitter to generate BitCast for pointer operands.

2022-07-06 Thread Yeting Kuo via Phabricator via cfe-commits 
fakepaper56 added inline comments.



Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:111
+if (I.value()->isPointer()) {
+  assert(RVVI->getIntrinsicTypes().front() == -1 &&
+ "RVVI should be vector load intrinsic.");

khchen wrote:
> I feel this logic is not clear for reader, maybe you should add comment to 
> say why the return type -1 are load intrinsics?
You are right. Maybe I could rewrite the message of assertion to "RVVI should 
be vector load intrinsic, we don't support this feature for stores now."?


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[PATCH] D129043: [RISCV][Clang] Teach RISCVEmitter to generate BitCast for pointer operands.

2022-07-06 Thread Zakk Chen via Phabricator via cfe-commits 
khchen added inline comments.



Comment at: clang/utils/TableGen/RISCVVEmitter.cpp:111
+if (I.value()->isPointer()) {
+  assert(RVVI->getIntrinsicTypes().front() == -1 &&
+ "RVVI should be vector load intrinsic.");

I feel this logic is not clear for reader, maybe you should add comment to say 
why the return type -1 are load intrinsics?


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[PATCH] D129043: [RISCV][Clang] Teach RISCVEmitter to generate BitCast for pointer operands.

2022-07-04 Thread Yeting Kuo via Phabricator via cfe-commits 
This revision was automatically updated to reflect the committed changes.
Closed by commit rG939352b6ec31: [RISCV][Clang] Teach RISCVEmitter to generate 
BitCast for pointer operands. (authored by fakepaper56).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D129043/new/

https://reviews.llvm.org/D129043

Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/include/clang/Support/RISCVVIntrinsicUtils.h
  clang/utils/TableGen/RISCVVEmitter.cpp

Index: clang/utils/TableGen/RISCVVEmitter.cpp
===
--- clang/utils/TableGen/RISCVVEmitter.cpp
+++ clang/utils/TableGen/RISCVVEmitter.cpp
@@ -105,6 +105,16 @@
 return;
   }
 
+  // Cast pointer operand of vector load intrinsic.
+  for (const auto  : enumerate(RVVI->getInputTypes())) {
+if (I.value()->isPointer()) {
+  assert(RVVI->getIntrinsicTypes().front() == -1 &&
+ "RVVI should be vector load intrinsic.");
+  OS << "  Ops[" << I.index() << "] = Builder.CreateBitCast(Ops[";
+  OS << I.index() << "], ResultType->getPointerTo());\n";
+}
+  }
+
   if (RVVI->isMasked()) {
 if (RVVI->hasVL()) {
   OS << "  std::rotate(Ops.begin(), Ops.begin() + 1, Ops.end() - 1);\n";
Index: clang/include/clang/Support/RISCVVIntrinsicUtils.h
===
--- clang/include/clang/Support/RISCVVIntrinsicUtils.h
+++ clang/include/clang/Support/RISCVVIntrinsicUtils.h
@@ -225,6 +225,8 @@
 return isFloat() && ElementBitwidth == Width;
   }
 
+  bool isPointer() const { return IsPointer; }
+
 private:
   // Verify RVV vector type and set Valid.
   bool verifyType() const;
Index: clang/include/clang/Basic/riscv_vector.td
===
--- clang/include/clang/Basic/riscv_vector.td
+++ clang/include/clang/Basic/riscv_vector.td
@@ -582,18 +582,8 @@
 }
 
 let HasUnMaskedOverloaded = false,
-MaskedPolicy = NonePolicy,
-ManualCodegen = [{
-  IntrinsicTypes = {ResultType, Ops[1]->getType()};
-  Ops[0] = Builder.CreateBitCast(Ops[0], ResultType->getPointerTo());
-}],
-MaskedManualCodegen= [{
-  // Move mask to right before vl.
-  std::rotate(Ops.begin(), Ops.begin() + 1, Ops.end() - 1);
-  IntrinsicTypes = {ResultType, Ops[3]->getType()};
-  Ops[1] = Builder.CreateBitCast(Ops[1], ResultType->getPointerTo());
-}] in {
-  class RVVVLEMaskBuiltin : RVVBuiltin<"m", "mPCUe", "c"> {
+MaskedPolicy = NonePolicy in {
+  class RVVVLEMaskBuiltin : RVVOutBuiltin<"m", "mPCUe", "c"> {
 let Name = "vlm_v";
 let IRName = "vlm";
 let HasMasked = false;
@@ -601,26 +591,15 @@
 }
 
 let HasUnMaskedOverloaded = false,
-ManualCodegen = [{
-  IntrinsicTypes = {ResultType, Ops[1]->getType()};
-  Ops[0] = Builder.CreateBitCast(Ops[0], ResultType->getPointerTo());
-  Ops.insert(Ops.begin(), llvm::UndefValue::get(ResultType));
-}],
-MaskedManualCodegen= [{
-  // Move mask to right before vl.
-  std::rotate(Ops.begin(), Ops.begin() + 1, Ops.end() - 1);
-  Ops.push_back(ConstantInt::get(Ops.back()->getType(), TAIL_UNDISTURBED));
-  IntrinsicTypes = {ResultType, Ops[3]->getType()};
-  Ops[1] = Builder.CreateBitCast(Ops[1], ResultType->getPointerTo());
-}] in {
+UnMaskedPolicy = HasPassthruOperand in {
   multiclass RVVVLEBuiltin types> {
 let Name = NAME # "_v",
 IRName = "vle",
 MaskedIRName ="vle_mask" in {
   foreach type = types in {
-def : RVVBuiltin<"v", "vPCe", type>;
+def : RVVOutBuiltin<"v", "vPCe", type>;
 if !not(IsFloat.val) then {
-  def : RVVBuiltin<"Uv", "UvPCUe", type>;
+  def : RVVOutBuiltin<"Uv", "UvPCUe", type>;
 }
   }
 }
@@ -685,61 +664,39 @@
   IRName = "vlse",
   MaskedIRName ="vlse_mask",
   HasUnMaskedOverloaded = false,
-  ManualCodegen = [{
-IntrinsicTypes = {ResultType, Ops[2]->getType()};
-Ops[0] = Builder.CreateBitCast(Ops[0], ResultType->getPointerTo());
-Ops.insert(Ops.begin(), llvm::UndefValue::get(ResultType));
-  }],
-  MaskedManualCodegen= [{
-// Move mask to right before vl.
-std::rotate(Ops.begin(), Ops.begin() + 1, Ops.end() - 1);
-Ops.push_back(ConstantInt::get(Ops.back()->getType(), TAIL_UNDISTURBED));
-IntrinsicTypes = {ResultType, Ops[4]->getType()};
-Ops[1] = Builder.CreateBitCast(Ops[1], ResultType->getPointerTo());
-  }] in {
+  UnMaskedPolicy = HasPassthruOperand in {
 foreach type = types in {
-  def : RVVBuiltin<"v", "vPCet", type>;
+  def : RVVOutBuiltin<"v", "vPCet", type>;
   if !not(IsFloat.val) then {
-def : RVVBuiltin<"Uv", "UvPCUet", type>;
+def : RVVOutBuiltin<"Uv", "UvPCUet", type>;
   }
 }
   }
 }
 
 multiclass RVVIndexedLoad {
-  let ManualCodegen = [{
-IntrinsicTypes =

[PATCH] D129043: [RISCV][Clang] Teach RISCVEmitter to generate BitCast for pointer operands.

2022-07-04 Thread Kito Cheng via Phabricator via cfe-commits 
kito-cheng accepted this revision.
kito-cheng added a comment.
This revision is now accepted and ready to land.

LGTM, thanks for clean this up :)


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[PATCH] D129043: [RISCV][Clang] Teach RISCVEmitter to generate BitCast for pointer operands.

2022-07-03 Thread Yeting Kuo via Phabricator via cfe-commits 
fakepaper56 updated this revision to Diff 441943.
fakepaper56 added a comment.

Align output code in riscv_vector_builtin_cg.inc.


Repository:
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Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/include/clang/Support/RISCVVIntrinsicUtils.h
  clang/utils/TableGen/RISCVVEmitter.cpp

Index: clang/utils/TableGen/RISCVVEmitter.cpp
===
--- clang/utils/TableGen/RISCVVEmitter.cpp
+++ clang/utils/TableGen/RISCVVEmitter.cpp
@@ -105,6 +105,16 @@
 return;
   }
 
+  // Cast pointer operand of vector load intrinsic.
+  for (const auto  : enumerate(RVVI->getInputTypes())) {
+if (I.value()->isPointer()) {
+  assert(RVVI->getIntrinsicTypes().front() == -1 &&
+ "RVVI should be vector load intrinsic.");
+  OS << "  Ops[" << I.index() << "] = Builder.CreateBitCast(Ops[";
+  OS << I.index() << "], ResultType->getPointerTo());\n";
+}
+  }
+
   if (RVVI->isMasked()) {
 if (RVVI->hasVL()) {
   OS << "  std::rotate(Ops.begin(), Ops.begin() + 1, Ops.end() - 1);\n";
Index: clang/include/clang/Support/RISCVVIntrinsicUtils.h
===
--- clang/include/clang/Support/RISCVVIntrinsicUtils.h
+++ clang/include/clang/Support/RISCVVIntrinsicUtils.h
@@ -225,6 +225,8 @@
 return isFloat() && ElementBitwidth == Width;
   }
 
+  bool isPointer() const { return IsPointer; }
+
 private:
   // Verify RVV vector type and set Valid.
   bool verifyType() const;
Index: clang/include/clang/Basic/riscv_vector.td
===
--- clang/include/clang/Basic/riscv_vector.td
+++ clang/include/clang/Basic/riscv_vector.td
@@ -582,18 +582,8 @@
 }
 
 let HasUnMaskedOverloaded = false,
-MaskedPolicy = NonePolicy,
-ManualCodegen = [{
-  IntrinsicTypes = {ResultType, Ops[1]->getType()};
-  Ops[0] = Builder.CreateBitCast(Ops[0], ResultType->getPointerTo());
-}],
-MaskedManualCodegen= [{
-  // Move mask to right before vl.
-  std::rotate(Ops.begin(), Ops.begin() + 1, Ops.end() - 1);
-  IntrinsicTypes = {ResultType, Ops[3]->getType()};
-  Ops[1] = Builder.CreateBitCast(Ops[1], ResultType->getPointerTo());
-}] in {
-  class RVVVLEMaskBuiltin : RVVBuiltin<"m", "mPCUe", "c"> {
+MaskedPolicy = NonePolicy in {
+  class RVVVLEMaskBuiltin : RVVOutBuiltin<"m", "mPCUe", "c"> {
 let Name = "vlm_v";
 let IRName = "vlm";
 let HasMasked = false;
@@ -601,26 +591,15 @@
 }
 
 let HasUnMaskedOverloaded = false,
-ManualCodegen = [{
-  IntrinsicTypes = {ResultType, Ops[1]->getType()};
-  Ops[0] = Builder.CreateBitCast(Ops[0], ResultType->getPointerTo());
-  Ops.insert(Ops.begin(), llvm::UndefValue::get(ResultType));
-}],
-MaskedManualCodegen= [{
-  // Move mask to right before vl.
-  std::rotate(Ops.begin(), Ops.begin() + 1, Ops.end() - 1);
-  Ops.push_back(ConstantInt::get(Ops.back()->getType(), TAIL_UNDISTURBED));
-  IntrinsicTypes = {ResultType, Ops[3]->getType()};
-  Ops[1] = Builder.CreateBitCast(Ops[1], ResultType->getPointerTo());
-}] in {
+UnMaskedPolicy = HasPassthruOperand in {
   multiclass RVVVLEBuiltin types> {
 let Name = NAME # "_v",
 IRName = "vle",
 MaskedIRName ="vle_mask" in {
   foreach type = types in {
-def : RVVBuiltin<"v", "vPCe", type>;
+def : RVVOutBuiltin<"v", "vPCe", type>;
 if !not(IsFloat.val) then {
-  def : RVVBuiltin<"Uv", "UvPCUe", type>;
+  def : RVVOutBuiltin<"Uv", "UvPCUe", type>;
 }
   }
 }
@@ -685,61 +664,39 @@
   IRName = "vlse",
   MaskedIRName ="vlse_mask",
   HasUnMaskedOverloaded = false,
-  ManualCodegen = [{
-IntrinsicTypes = {ResultType, Ops[2]->getType()};
-Ops[0] = Builder.CreateBitCast(Ops[0], ResultType->getPointerTo());
-Ops.insert(Ops.begin(), llvm::UndefValue::get(ResultType));
-  }],
-  MaskedManualCodegen= [{
-// Move mask to right before vl.
-std::rotate(Ops.begin(), Ops.begin() + 1, Ops.end() - 1);
-Ops.push_back(ConstantInt::get(Ops.back()->getType(), TAIL_UNDISTURBED));
-IntrinsicTypes = {ResultType, Ops[4]->getType()};
-Ops[1] = Builder.CreateBitCast(Ops[1], ResultType->getPointerTo());
-  }] in {
+  UnMaskedPolicy = HasPassthruOperand in {
 foreach type = types in {
-  def : RVVBuiltin<"v", "vPCet", type>;
+  def : RVVOutBuiltin<"v", "vPCet", type>;
   if !not(IsFloat.val) then {
-def : RVVBuiltin<"Uv", "UvPCUet", type>;
+def : RVVOutBuiltin<"Uv", "UvPCUet", type>;
   }
 }
   }
 }
 
 multiclass RVVIndexedLoad {
-  let ManualCodegen = [{
-IntrinsicTypes = {ResultType, Ops[1]->getType(), Ops[2]->getType()};
-Ops[0] =

[PATCH] D129043: [RISCV][Clang] Teach RISCVEmitter to generate BitCast for pointer operands.

2022-07-03 Thread Yeting Kuo via Phabricator via cfe-commits 
fakepaper56 created this revision.
Herald added subscribers: sunshaoce, VincentWu, luke957, vkmr, frasercrmck, 
evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, 
jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, 
zzheng, jrtc27, shiva0217, kito-cheng, niosHD, sabuasal, simoncook, johnrusso, 
rbar, asb, arichardson.
Herald added a project: All.
fakepaper56 requested review of this revision.
Herald added subscribers: cfe-commits, pcwang-thead, eopXD, MaskRay.
Herald added a project: clang.

RVV C intrinsics use pointers to scalar for base address and their corresponding
IR intrinsics but use pointers to vector. It makes some vector load intrinsics
need specific ManualCodegen and MaskedManualCodegen to just add bitcast for
transforming to IR.

For simplifying riscv_vector.td, the patch make RISCVEmitter detect pointer
operands and bitcast them.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D129043

Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/include/clang/Support/RISCVVIntrinsicUtils.h
  clang/utils/TableGen/RISCVVEmitter.cpp

Index: clang/utils/TableGen/RISCVVEmitter.cpp
===
--- clang/utils/TableGen/RISCVVEmitter.cpp
+++ clang/utils/TableGen/RISCVVEmitter.cpp
@@ -105,6 +105,16 @@
 return;
   }
 
+  // Cast pointer operand of vector load intrinsic.
+  for (const auto  : enumerate(RVVI->getInputTypes())) {
+if (I.value()->isPointer()) {
+  assert(RVVI->getIntrinsicTypes().front() == -1 &&
+ "RVVI should be vector load intrinsic.");
+  OS << "Ops[" << I.index() << "] = Builder.CreateBitCast(Ops[";
+  OS << I.index() << "],ResultType->getPointerTo());\n";
+}
+  }
+
   if (RVVI->isMasked()) {
 if (RVVI->hasVL()) {
   OS << "  std::rotate(Ops.begin(), Ops.begin() + 1, Ops.end() - 1);\n";
Index: clang/include/clang/Support/RISCVVIntrinsicUtils.h
===
--- clang/include/clang/Support/RISCVVIntrinsicUtils.h
+++ clang/include/clang/Support/RISCVVIntrinsicUtils.h
@@ -225,6 +225,8 @@
 return isFloat() && ElementBitwidth == Width;
   }
 
+  bool isPointer() const { return IsPointer; }
+
 private:
   // Verify RVV vector type and set Valid.
   bool verifyType() const;
Index: clang/include/clang/Basic/riscv_vector.td
===
--- clang/include/clang/Basic/riscv_vector.td
+++ clang/include/clang/Basic/riscv_vector.td
@@ -582,18 +582,8 @@
 }
 
 let HasUnMaskedOverloaded = false,
-MaskedPolicy = NonePolicy,
-ManualCodegen = [{
-  IntrinsicTypes = {ResultType, Ops[1]->getType()};
-  Ops[0] = Builder.CreateBitCast(Ops[0], ResultType->getPointerTo());
-}],
-MaskedManualCodegen= [{
-  // Move mask to right before vl.
-  std::rotate(Ops.begin(), Ops.begin() + 1, Ops.end() - 1);
-  IntrinsicTypes = {ResultType, Ops[3]->getType()};
-  Ops[1] = Builder.CreateBitCast(Ops[1], ResultType->getPointerTo());
-}] in {
-  class RVVVLEMaskBuiltin : RVVBuiltin<"m", "mPCUe", "c"> {
+MaskedPolicy = NonePolicy in {
+  class RVVVLEMaskBuiltin : RVVOutBuiltin<"m", "mPCUe", "c"> {
 let Name = "vlm_v";
 let IRName = "vlm";
 let HasMasked = false;
@@ -601,26 +591,15 @@
 }
 
 let HasUnMaskedOverloaded = false,
-ManualCodegen = [{
-  IntrinsicTypes = {ResultType, Ops[1]->getType()};
-  Ops[0] = Builder.CreateBitCast(Ops[0], ResultType->getPointerTo());
-  Ops.insert(Ops.begin(), llvm::UndefValue::get(ResultType));
-}],
-MaskedManualCodegen= [{
-  // Move mask to right before vl.
-  std::rotate(Ops.begin(), Ops.begin() + 1, Ops.end() - 1);
-  Ops.push_back(ConstantInt::get(Ops.back()->getType(), TAIL_UNDISTURBED));
-  IntrinsicTypes = {ResultType, Ops[3]->getType()};
-  Ops[1] = Builder.CreateBitCast(Ops[1], ResultType->getPointerTo());
-}] in {
+UnMaskedPolicy = HasPassthruOperand in {
   multiclass RVVVLEBuiltin types> {
 let Name = NAME # "_v",
 IRName = "vle",
 MaskedIRName ="vle_mask" in {
   foreach type = types in {
-def : RVVBuiltin<"v", "vPCe", type>;
+def : RVVOutBuiltin<"v", "vPCe", type>;
 if !not(IsFloat.val) then {
-  def : RVVBuiltin<"Uv", "UvPCUe", type>;
+  def : RVVOutBuiltin<"Uv", "UvPCUe", type>;
 }
   }
 }
@@ -685,61 +664,39 @@
   IRName = "vlse",
   MaskedIRName ="vlse_mask",
   HasUnMaskedOverloaded = false,
-  ManualCodegen = [{
-IntrinsicTypes = {ResultType, Ops[2]->getType()};
-Ops[0] = Builder.CreateBitCast(Ops[0], ResultType->getPointerTo());
-Ops.insert(Ops.begin(), llvm::UndefValue::get(ResultType));
-  }],
-  MaskedManualCodegen= [{
-// Move mask to right before vl.
-std::rotate(Ops.begin(), Ops.begin() + 1, Ops.end() - 1);
-