[PATCH] D139387: [NFC][Clang] Add missing test cases for segment load

2022-12-11 Thread Brandon Wu via Phabricator via cfe-commits 
This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG4ca9c6a84f91: [NFC][Clang] Add missing test cases for 
segment load (authored by khchen, committed by 4vtomat).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D139387/new/

https://reviews.llvm.org/D139387

Files:
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlseg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vlseg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vlseg_mask.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vlsegff_mask.c

Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vlsegff_mask.c
===
--- clang/test/CodeGen/RISCV/rvv-intrinsics/vlsegff_mask.c
+++ clang/test/CodeGen/RISCV/rvv-intrinsics/vlsegff_mask.c
@@ -8204,3 +8204,107 @@
 void test_vlseg2e16ff_v_f16m4_m (vfloat16m4_t *v0, vfloat16m4_t *v1, vbool4_t mask, vfloat16m4_t maskedoff0, vfloat16m4_t maskedoff1, const _Float16 *base, size_t *new_vl, size_t vl) {
   return vlseg2e16ff_v_f16m4_m(v0, v1, mask, maskedoff0, maskedoff1, base, new_vl, vl);
 }
+
+// CHECK-RV32-LABEL: @test_vlseg2e32ff_v_u32mf2_tuma(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:[[TMP0:%.*]] = call { , , i32 } @llvm.riscv.vlseg2ff.mask.nxv1i32.i32( [[MERGE0:%.*]],  [[MERGE1:%.*]], ptr [[BASE:%.*]],  [[MASK:%.*]], i32 [[VL:%.*]], i32 2)
+// CHECK-RV32-NEXT:[[TMP1:%.*]] = extractvalue { , , i32 } [[TMP0]], 0
+// CHECK-RV32-NEXT:store  [[TMP1]], ptr [[V0:%.*]], align 4
+// CHECK-RV32-NEXT:[[TMP2:%.*]] = extractvalue { , , i32 } [[TMP0]], 1
+// CHECK-RV32-NEXT:store  [[TMP2]], ptr [[V1:%.*]], align 4
+// CHECK-RV32-NEXT:[[TMP3:%.*]] = extractvalue { , , i32 } [[TMP0]], 2
+// CHECK-RV32-NEXT:store i32 [[TMP3]], ptr [[NEW_VL:%.*]], align 4
+// CHECK-RV32-NEXT:ret void
+//
+// CHECK-RV64-LABEL: @test_vlseg2e32ff_v_u32mf2_tuma(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.mask.nxv1i32.i64( [[MERGE0:%.*]],  [[MERGE1:%.*]], ptr [[BASE:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
+// CHECK-RV64-NEXT:[[TMP1:%.*]] = extractvalue { , , i64 } [[TMP0]], 0
+// CHECK-RV64-NEXT:store  [[TMP1]], ptr [[V0:%.*]], align 4
+// CHECK-RV64-NEXT:[[TMP2:%.*]] = extractvalue { , , i64 } [[TMP0]], 1
+// CHECK-RV64-NEXT:store  [[TMP2]], ptr [[V1:%.*]], align 4
+// CHECK-RV64-NEXT:[[TMP3:%.*]] = extractvalue { , , i64 } [[TMP0]], 2
+// CHECK-RV64-NEXT:store i64 [[TMP3]], ptr [[NEW_VL:%.*]], align 4
+// CHECK-RV64-NEXT:ret void
+//
+void test_vlseg2e32ff_v_u32mf2_tuma(vuint32mf2_t *v0, vuint32mf2_t *v1, vbool64_t mask, vuint32mf2_t merge0, vuint32mf2_t merge1, const uint32_t *base, size_t *new_vl, size_t vl) {
+  return vlseg2e32ff_v_u32mf2_tuma(v0, v1, mask, merge0, merge1, base, new_vl, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg2e32ff_v_u32mf2_tumu(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:[[TMP0:%.*]] = call { , , i32 } @llvm.riscv.vlseg2ff.mask.nxv1i32.i32( [[MERGE0:%.*]],  [[MERGE1:%.*]], ptr [[BASE:%.*]],  [[MASK:%.*]], i32 [[VL:%.*]], i32 0)
+// CHECK-RV32-NEXT:[[TMP1:%.*]] = extractvalue { , , i32 } [[TMP0]], 0
+// CHECK-RV32-NEXT:store  [[TMP1]], ptr [[V0:%.*]], align 4
+// CHECK-RV32-NEXT:[[TMP2:%.*]] = extractvalue { , , i32 } [[TMP0]], 1
+// CHECK-RV32-NEXT:store  [[TMP2]], ptr [[V1:%.*]], align 4
+// CHECK-RV32-NEXT:[[TMP3:%.*]] = extractvalue { , , i32 } [[TMP0]], 2
+// CHECK-RV32-NEXT:store i32 [[TMP3]], ptr [[NEW_VL:%.*]], align 4
+// CHECK-RV32-NEXT:ret void
+//
+// CHECK-RV64-LABEL: @test_vlseg2e32ff_v_u32mf2_tumu(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.mask.nxv1i32.i64( [[MERGE0:%.*]],  [[MERGE1:%.*]], ptr [[BASE:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-RV64-NEXT:[[TMP1:%.*]] = extractvalue { , , i64 } [[TMP0]], 0
+// CHECK-RV64-NEXT:store  [[TMP1]], ptr [[V0:%.*]], align 4
+// CHECK-RV64-NEXT:[[TMP2:%.*]] = extractvalue { , , i64 } [[TMP0]], 1
+// CHECK-RV64-NEXT:store  [[TMP2]], ptr [[V1:%.*]], align 4
+// CHECK-RV64-NEXT:[[TMP3:%.*]] = extractvalue { , , i64 } [[TMP0]], 2
+// CHECK-RV64-NEXT:store i64 [[TMP3]], ptr [[NEW_VL:%.*]], align 4
+// CHECK-RV64-NEXT:ret void
+//
+void test_vlseg2e32ff_v_u32mf2_tumu(vuint32mf2_t *v0, vuint32mf2_t *v1, vbool64_t mask, vuint32mf2_t merge0, vuint32mf2_t merge1, const uint32_t *base, size_t *new_vl, size_t vl) {
+  return vlseg2e32ff_v_u32mf2_tumu(v0, v1, mask, merge0, merge1, base, new_vl, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg2e32ff_v_u32mf2_tama(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:[[TMP0:%.*]] = call { , , i32 } @llvm.riscv.vlseg2ff.mask.nxv1i32.i32( poison,  poison, ptr [[BASE:%.*]],  [[MASK:%.*]], i32 [[VL:%.*]], i32 3)
+// CHECK-RV32-NEXT:[[TMP1:%.*]] = extractvalue { , , i32 } [[TMP0]], 0

[PATCH] D139387: [NFC][Clang] Add missing test cases for segment load

2022-12-09 Thread Craig Topper via Phabricator via cfe-commits 
craig.topper accepted this revision.
craig.topper added a comment.

LGTM


Repository:
  rG LLVM Github Monorepo

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[PATCH] D139387: [NFC][Clang] Add missing test cases for segment load

2022-12-08 Thread Brandon Wu via Phabricator via cfe-commits 
4vtomat updated this revision to Diff 481521.
4vtomat added a comment.

Update failed test cases.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D139387/new/

https://reviews.llvm.org/D139387

Files:
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vlseg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vlseg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vlseg_mask.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vlsegff_mask.c

Index: clang/test/CodeGen/RISCV/rvv-intrinsics/vlsegff_mask.c
===
--- clang/test/CodeGen/RISCV/rvv-intrinsics/vlsegff_mask.c
+++ clang/test/CodeGen/RISCV/rvv-intrinsics/vlsegff_mask.c
@@ -8204,3 +8204,107 @@
 void test_vlseg2e16ff_v_f16m4_m (vfloat16m4_t *v0, vfloat16m4_t *v1, vbool4_t mask, vfloat16m4_t maskedoff0, vfloat16m4_t maskedoff1, const _Float16 *base, size_t *new_vl, size_t vl) {
   return vlseg2e16ff_v_f16m4_m(v0, v1, mask, maskedoff0, maskedoff1, base, new_vl, vl);
 }
+
+// CHECK-RV32-LABEL: @test_vlseg2e32ff_v_u32mf2_tuma(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:[[TMP0:%.*]] = call { , , i32 } @llvm.riscv.vlseg2ff.mask.nxv1i32.i32( [[MERGE0:%.*]],  [[MERGE1:%.*]], ptr [[BASE:%.*]],  [[MASK:%.*]], i32 [[VL:%.*]], i32 2)
+// CHECK-RV32-NEXT:[[TMP1:%.*]] = extractvalue { , , i32 } [[TMP0]], 0
+// CHECK-RV32-NEXT:store  [[TMP1]], ptr [[V0:%.*]], align 4
+// CHECK-RV32-NEXT:[[TMP2:%.*]] = extractvalue { , , i32 } [[TMP0]], 1
+// CHECK-RV32-NEXT:store  [[TMP2]], ptr [[V1:%.*]], align 4
+// CHECK-RV32-NEXT:[[TMP3:%.*]] = extractvalue { , , i32 } [[TMP0]], 2
+// CHECK-RV32-NEXT:store i32 [[TMP3]], ptr [[NEW_VL:%.*]], align 4
+// CHECK-RV32-NEXT:ret void
+//
+// CHECK-RV64-LABEL: @test_vlseg2e32ff_v_u32mf2_tuma(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.mask.nxv1i32.i64( [[MERGE0:%.*]],  [[MERGE1:%.*]], ptr [[BASE:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]], i64 2)
+// CHECK-RV64-NEXT:[[TMP1:%.*]] = extractvalue { , , i64 } [[TMP0]], 0
+// CHECK-RV64-NEXT:store  [[TMP1]], ptr [[V0:%.*]], align 4
+// CHECK-RV64-NEXT:[[TMP2:%.*]] = extractvalue { , , i64 } [[TMP0]], 1
+// CHECK-RV64-NEXT:store  [[TMP2]], ptr [[V1:%.*]], align 4
+// CHECK-RV64-NEXT:[[TMP3:%.*]] = extractvalue { , , i64 } [[TMP0]], 2
+// CHECK-RV64-NEXT:store i64 [[TMP3]], ptr [[NEW_VL:%.*]], align 4
+// CHECK-RV64-NEXT:ret void
+//
+void test_vlseg2e32ff_v_u32mf2_tuma(vuint32mf2_t *v0, vuint32mf2_t *v1, vbool64_t mask, vuint32mf2_t merge0, vuint32mf2_t merge1, const uint32_t *base, size_t *new_vl, size_t vl) {
+  return vlseg2e32ff_v_u32mf2_tuma(v0, v1, mask, merge0, merge1, base, new_vl, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg2e32ff_v_u32mf2_tumu(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:[[TMP0:%.*]] = call { , , i32 } @llvm.riscv.vlseg2ff.mask.nxv1i32.i32( [[MERGE0:%.*]],  [[MERGE1:%.*]], ptr [[BASE:%.*]],  [[MASK:%.*]], i32 [[VL:%.*]], i32 0)
+// CHECK-RV32-NEXT:[[TMP1:%.*]] = extractvalue { , , i32 } [[TMP0]], 0
+// CHECK-RV32-NEXT:store  [[TMP1]], ptr [[V0:%.*]], align 4
+// CHECK-RV32-NEXT:[[TMP2:%.*]] = extractvalue { , , i32 } [[TMP0]], 1
+// CHECK-RV32-NEXT:store  [[TMP2]], ptr [[V1:%.*]], align 4
+// CHECK-RV32-NEXT:[[TMP3:%.*]] = extractvalue { , , i32 } [[TMP0]], 2
+// CHECK-RV32-NEXT:store i32 [[TMP3]], ptr [[NEW_VL:%.*]], align 4
+// CHECK-RV32-NEXT:ret void
+//
+// CHECK-RV64-LABEL: @test_vlseg2e32ff_v_u32mf2_tumu(
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.mask.nxv1i32.i64( [[MERGE0:%.*]],  [[MERGE1:%.*]], ptr [[BASE:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]], i64 0)
+// CHECK-RV64-NEXT:[[TMP1:%.*]] = extractvalue { , , i64 } [[TMP0]], 0
+// CHECK-RV64-NEXT:store  [[TMP1]], ptr [[V0:%.*]], align 4
+// CHECK-RV64-NEXT:[[TMP2:%.*]] = extractvalue { , , i64 } [[TMP0]], 1
+// CHECK-RV64-NEXT:store  [[TMP2]], ptr [[V1:%.*]], align 4
+// CHECK-RV64-NEXT:[[TMP3:%.*]] = extractvalue { , , i64 } [[TMP0]], 2
+// CHECK-RV64-NEXT:store i64 [[TMP3]], ptr [[NEW_VL:%.*]], align 4
+// CHECK-RV64-NEXT:ret void
+//
+void test_vlseg2e32ff_v_u32mf2_tumu(vuint32mf2_t *v0, vuint32mf2_t *v1, vbool64_t mask, vuint32mf2_t merge0, vuint32mf2_t merge1, const uint32_t *base, size_t *new_vl, size_t vl) {
+  return vlseg2e32ff_v_u32mf2_tumu(v0, v1, mask, merge0, merge1, base, new_vl, vl);
+}
+
+// CHECK-RV32-LABEL: @test_vlseg2e32ff_v_u32mf2_tama(
+// CHECK-RV32-NEXT:  entry:
+// CHECK-RV32-NEXT:[[TMP0:%.*]] = call { , , i32 } @llvm.riscv.vlseg2ff.mask.nxv1i32.i32( poison,  poison, ptr [[BASE:%.*]],  [[MASK:%.*]], i32 [[VL:%.*]], i32 3)
+// CHECK-RV32-NEXT:[[TMP1:%.*]] = extractvalue { , , i32 } [[TMP0]], 0
+// CHECK-RV32-NEXT:store  [[TMP1]], ptr [[V0:%.*]], align 4
+// CHECK-RV32-NEXT:[[TMP2:%.*]] = extractvalue { , , i32 } [[TMP0]], 1
+// CHECK-RV32-NEXT: