[PATCH] D140942: [5/7][Clang][RISCV] Remove default tail-undisturbed for vcompress intrinsics

[Yueh-Ting (eop) Chen via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG380129657fe3: [5/7][Clang][RISCV] Remove default 
tail-undisturbed for vcompress intrinsics (authored by eopXD).
Herald added a subscriber: luke.

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D140942/new/

https://reviews.llvm.org/D140942

Files:
  clang/include/clang/Basic/riscv_vector.td
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcompress.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcompress.c

Index: clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcompress.c
===
--- clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcompress.c
+++ clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcompress.c
@@ -9,532 +9,532 @@
 
 // CHECK-RV64-LABEL: @test_vcompress_vm_f16mf4(
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vcompress.nxv1f16.i64( [[DEST:%.*]],  [[SRC:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vcompress.nxv1f16.i64( poison,  [[SRC:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
 // CHECK-RV64-NEXT:ret  [[TMP0]]
 //
-vfloat16mf4_t test_vcompress_vm_f16mf4(vfloat16mf4_t dest, vfloat16mf4_t src, vbool64_t mask, size_t vl) {
-  return vcompress(dest, src, mask, vl);
+vfloat16mf4_t test_vcompress_vm_f16mf4(vfloat16mf4_t src, vbool64_t mask, size_t vl) {
+  return vcompress(src, mask, vl);
 }
 
 // CHECK-RV64-LABEL: @test_vcompress_vm_f16mf2(
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vcompress.nxv2f16.i64( [[DEST:%.*]],  [[SRC:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vcompress.nxv2f16.i64( poison,  [[SRC:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
 // CHECK-RV64-NEXT:ret  [[TMP0]]
 //
-vfloat16mf2_t test_vcompress_vm_f16mf2(vfloat16mf2_t dest, vfloat16mf2_t src, vbool32_t mask, size_t vl) {
-  return vcompress(dest, src, mask, vl);
+vfloat16mf2_t test_vcompress_vm_f16mf2(vfloat16mf2_t src, vbool32_t mask, size_t vl) {
+  return vcompress(src, mask, vl);
 }
 
 // CHECK-RV64-LABEL: @test_vcompress_vm_f16m1(
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vcompress.nxv4f16.i64( [[DEST:%.*]],  [[SRC:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vcompress.nxv4f16.i64( poison,  [[SRC:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
 // CHECK-RV64-NEXT:ret  [[TMP0]]
 //
-vfloat16m1_t test_vcompress_vm_f16m1(vfloat16m1_t dest, vfloat16m1_t src, vbool16_t mask, size_t vl) {
-  return vcompress(dest, src, mask, vl);
+vfloat16m1_t test_vcompress_vm_f16m1(vfloat16m1_t src, vbool16_t mask, size_t vl) {
+  return vcompress(src, mask, vl);
 }
 
 // CHECK-RV64-LABEL: @test_vcompress_vm_f16m2(
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vcompress.nxv8f16.i64( [[DEST:%.*]],  [[SRC:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vcompress.nxv8f16.i64( poison,  [[SRC:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
 // CHECK-RV64-NEXT:ret  [[TMP0]]
 //
-vfloat16m2_t test_vcompress_vm_f16m2(vfloat16m2_t dest, vfloat16m2_t src, vbool8_t mask, size_t vl) {
-  return vcompress(dest, src, mask, vl);
+vfloat16m2_t test_vcompress_vm_f16m2(vfloat16m2_t src, vbool8_t mask, size_t vl) {
+  return vcompress(src, mask, vl);
 }
 
 // CHECK-RV64-LABEL: @test_vcompress_vm_f16m4(
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vcompress.nxv16f16.i64( [[DEST:%.*]],  [[SRC:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vcompress.nxv16f16.i64( poison,  [[SRC:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
 // CHECK-RV64-NEXT:ret  [[TMP0]]
 //
-vfloat16m4_t test_vcompress_vm_f16m4(vfloat16m4_t dest, vfloat16m4_t src, vbool4_t mask, size_t vl) {
-  return vcompress(dest, src, mask, vl);
+vfloat16m4_t test_vcompress_vm_f16m4(vfloat16m4_t src, vbool4_t mask, size_t vl) {
+  return vcompress(src, mask, vl);
 }
 
 // CHECK-RV64-LABEL: @test_vcompress_vm_f16m8(
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vcompress.nxv32f16.i64( [[DEST:%.*]],  [[SRC:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vcompress.nxv32f16.i64( poison,  [[SRC:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
 // CHECK-RV64-NEXT:ret  [[TMP0]]
 //
-vfloat16m8_t test_vcompress_vm_f16m8(vfloat16m8_t dest, vfloat16m8_t src, vbool2_t mask, size_t vl) {
-  return vcompress(dest, src, mask, vl);
+vfloat16m8_t test_vcompress_vm_f16m8(vfloat16m8_t src, vbool2_t mask, size_t vl) {
+  

[PATCH] D140942: [5/7][Clang][RISCV] Remove default tail-undisturbed for vcompress intrinsics

[Yueh-Ting (eop) Chen via Phabricator via cfe-commits]

eopXD updated this revision to Diff 489279.
eopXD added a comment.

Rebase upon latest main.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D140942/new/

https://reviews.llvm.org/D140942

Files:
  clang/include/clang/Basic/riscv_vector.td
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcompress.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcompress.c

Index: clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcompress.c
===
--- clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcompress.c
+++ clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcompress.c
@@ -9,532 +9,532 @@
 
 // CHECK-RV64-LABEL: @test_vcompress_vm_f16mf4(
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vcompress.nxv1f16.i64( [[DEST:%.*]],  [[SRC:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vcompress.nxv1f16.i64( poison,  [[SRC:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
 // CHECK-RV64-NEXT:ret  [[TMP0]]
 //
-vfloat16mf4_t test_vcompress_vm_f16mf4(vfloat16mf4_t dest, vfloat16mf4_t src, vbool64_t mask, size_t vl) {
-  return vcompress(dest, src, mask, vl);
+vfloat16mf4_t test_vcompress_vm_f16mf4(vfloat16mf4_t src, vbool64_t mask, size_t vl) {
+  return vcompress(src, mask, vl);
 }
 
 // CHECK-RV64-LABEL: @test_vcompress_vm_f16mf2(
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vcompress.nxv2f16.i64( [[DEST:%.*]],  [[SRC:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vcompress.nxv2f16.i64( poison,  [[SRC:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
 // CHECK-RV64-NEXT:ret  [[TMP0]]
 //
-vfloat16mf2_t test_vcompress_vm_f16mf2(vfloat16mf2_t dest, vfloat16mf2_t src, vbool32_t mask, size_t vl) {
-  return vcompress(dest, src, mask, vl);
+vfloat16mf2_t test_vcompress_vm_f16mf2(vfloat16mf2_t src, vbool32_t mask, size_t vl) {
+  return vcompress(src, mask, vl);
 }
 
 // CHECK-RV64-LABEL: @test_vcompress_vm_f16m1(
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vcompress.nxv4f16.i64( [[DEST:%.*]],  [[SRC:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vcompress.nxv4f16.i64( poison,  [[SRC:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
 // CHECK-RV64-NEXT:ret  [[TMP0]]
 //
-vfloat16m1_t test_vcompress_vm_f16m1(vfloat16m1_t dest, vfloat16m1_t src, vbool16_t mask, size_t vl) {
-  return vcompress(dest, src, mask, vl);
+vfloat16m1_t test_vcompress_vm_f16m1(vfloat16m1_t src, vbool16_t mask, size_t vl) {
+  return vcompress(src, mask, vl);
 }
 
 // CHECK-RV64-LABEL: @test_vcompress_vm_f16m2(
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vcompress.nxv8f16.i64( [[DEST:%.*]],  [[SRC:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vcompress.nxv8f16.i64( poison,  [[SRC:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
 // CHECK-RV64-NEXT:ret  [[TMP0]]
 //
-vfloat16m2_t test_vcompress_vm_f16m2(vfloat16m2_t dest, vfloat16m2_t src, vbool8_t mask, size_t vl) {
-  return vcompress(dest, src, mask, vl);
+vfloat16m2_t test_vcompress_vm_f16m2(vfloat16m2_t src, vbool8_t mask, size_t vl) {
+  return vcompress(src, mask, vl);
 }
 
 // CHECK-RV64-LABEL: @test_vcompress_vm_f16m4(
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vcompress.nxv16f16.i64( [[DEST:%.*]],  [[SRC:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vcompress.nxv16f16.i64( poison,  [[SRC:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
 // CHECK-RV64-NEXT:ret  [[TMP0]]
 //
-vfloat16m4_t test_vcompress_vm_f16m4(vfloat16m4_t dest, vfloat16m4_t src, vbool4_t mask, size_t vl) {
-  return vcompress(dest, src, mask, vl);
+vfloat16m4_t test_vcompress_vm_f16m4(vfloat16m4_t src, vbool4_t mask, size_t vl) {
+  return vcompress(src, mask, vl);
 }
 
 // CHECK-RV64-LABEL: @test_vcompress_vm_f16m8(
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vcompress.nxv32f16.i64( [[DEST:%.*]],  [[SRC:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vcompress.nxv32f16.i64( poison,  [[SRC:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
 // CHECK-RV64-NEXT:ret  [[TMP0]]
 //
-vfloat16m8_t test_vcompress_vm_f16m8(vfloat16m8_t dest, vfloat16m8_t src, vbool2_t mask, size_t vl) {
-  return vcompress(dest, src, mask, vl);
+vfloat16m8_t test_vcompress_vm_f16m8(vfloat16m8_t src, vbool2_t mask, size_t vl) {
+  return vcompress(src, mask, vl);
 }
 
 // CHECK-RV64-LABEL: @test_vcompress_vm_f32mf2(
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vcompress.nxv1f32.i64( 

[PATCH] D140942: [5/7][Clang][RISCV] Remove default tail-undisturbed for vcompress intrinsics

[Craig Topper via Phabricator via cfe-commits]

craig.topper accepted this revision.
craig.topper added a comment.
This revision is now accepted and ready to land.

LGTM


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D140942/new/

https://reviews.llvm.org/D140942

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[PATCH] D140942: [5/7][Clang][RISCV] Remove default tail-undisturbed for vcompress intrinsics

[Yueh-Ting (eop) Chen via Phabricator via cfe-commits]

eopXD updated this revision to Diff 488572.
eopXD added a comment.

Rebase upon update of [3/N]


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D140942/new/

https://reviews.llvm.org/D140942

Files:
  clang/include/clang/Basic/riscv_vector.td
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcompress.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcompress.c

Index: clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcompress.c
===
--- clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcompress.c
+++ clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcompress.c
@@ -9,532 +9,532 @@
 
 // CHECK-RV64-LABEL: @test_vcompress_vm_f16mf4(
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vcompress.nxv1f16.i64( [[DEST:%.*]],  [[SRC:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vcompress.nxv1f16.i64( poison,  [[SRC:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
 // CHECK-RV64-NEXT:ret  [[TMP0]]
 //
-vfloat16mf4_t test_vcompress_vm_f16mf4(vbool64_t mask, vfloat16mf4_t dest, vfloat16mf4_t src, size_t vl) {
-  return vcompress(mask, dest, src, vl);
+vfloat16mf4_t test_vcompress_vm_f16mf4(vbool64_t mask, vfloat16mf4_t src, size_t vl) {
+  return vcompress(mask, src, vl);
 }
 
 // CHECK-RV64-LABEL: @test_vcompress_vm_f16mf2(
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vcompress.nxv2f16.i64( [[DEST:%.*]],  [[SRC:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vcompress.nxv2f16.i64( poison,  [[SRC:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
 // CHECK-RV64-NEXT:ret  [[TMP0]]
 //
-vfloat16mf2_t test_vcompress_vm_f16mf2(vbool32_t mask, vfloat16mf2_t dest, vfloat16mf2_t src, size_t vl) {
-  return vcompress(mask, dest, src, vl);
+vfloat16mf2_t test_vcompress_vm_f16mf2(vbool32_t mask, vfloat16mf2_t src, size_t vl) {
+  return vcompress(mask, src, vl);
 }
 
 // CHECK-RV64-LABEL: @test_vcompress_vm_f16m1(
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vcompress.nxv4f16.i64( [[DEST:%.*]],  [[SRC:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vcompress.nxv4f16.i64( poison,  [[SRC:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
 // CHECK-RV64-NEXT:ret  [[TMP0]]
 //
-vfloat16m1_t test_vcompress_vm_f16m1(vbool16_t mask, vfloat16m1_t dest, vfloat16m1_t src, size_t vl) {
-  return vcompress(mask, dest, src, vl);
+vfloat16m1_t test_vcompress_vm_f16m1(vbool16_t mask, vfloat16m1_t src, size_t vl) {
+  return vcompress(mask, src, vl);
 }
 
 // CHECK-RV64-LABEL: @test_vcompress_vm_f16m2(
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vcompress.nxv8f16.i64( [[DEST:%.*]],  [[SRC:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vcompress.nxv8f16.i64( poison,  [[SRC:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
 // CHECK-RV64-NEXT:ret  [[TMP0]]
 //
-vfloat16m2_t test_vcompress_vm_f16m2(vbool8_t mask, vfloat16m2_t dest, vfloat16m2_t src, size_t vl) {
-  return vcompress(mask, dest, src, vl);
+vfloat16m2_t test_vcompress_vm_f16m2(vbool8_t mask, vfloat16m2_t src, size_t vl) {
+  return vcompress(mask, src, vl);
 }
 
 // CHECK-RV64-LABEL: @test_vcompress_vm_f16m4(
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vcompress.nxv16f16.i64( [[DEST:%.*]],  [[SRC:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vcompress.nxv16f16.i64( poison,  [[SRC:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
 // CHECK-RV64-NEXT:ret  [[TMP0]]
 //
-vfloat16m4_t test_vcompress_vm_f16m4(vbool4_t mask, vfloat16m4_t dest, vfloat16m4_t src, size_t vl) {
-  return vcompress(mask, dest, src, vl);
+vfloat16m4_t test_vcompress_vm_f16m4(vbool4_t mask, vfloat16m4_t src, size_t vl) {
+  return vcompress(mask, src, vl);
 }
 
 // CHECK-RV64-LABEL: @test_vcompress_vm_f16m8(
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vcompress.nxv32f16.i64( [[DEST:%.*]],  [[SRC:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vcompress.nxv32f16.i64( poison,  [[SRC:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
 // CHECK-RV64-NEXT:ret  [[TMP0]]
 //
-vfloat16m8_t test_vcompress_vm_f16m8(vbool2_t mask, vfloat16m8_t dest, vfloat16m8_t src, size_t vl) {
-  return vcompress(mask, dest, src, vl);
+vfloat16m8_t test_vcompress_vm_f16m8(vbool2_t mask, vfloat16m8_t src, size_t vl) {
+  return vcompress(mask, src, vl);
 }
 
 // CHECK-RV64-LABEL: @test_vcompress_vm_f32mf2(
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vcompress.nxv1f32.i64( 

[PATCH] D140942: [5/7][Clang][RISCV] Remove default tail-undisturbed for vcompress intrinsics

[Yueh-Ting (eop) Chen via Phabricator via cfe-commits]

eopXD updated this revision to Diff 488152.
eopXD added a comment.

Rebase on top of landing of D141198 .


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D140942/new/

https://reviews.llvm.org/D140942

Files:
  clang/include/clang/Basic/riscv_vector.td
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcompress.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcompress.c

Index: clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcompress.c
===
--- clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcompress.c
+++ clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcompress.c
@@ -9,532 +9,532 @@
 
 // CHECK-RV64-LABEL: @test_vcompress_vm_f16mf4(
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vcompress.nxv1f16.i64( [[DEST:%.*]],  [[SRC:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vcompress.nxv1f16.i64( poison,  [[SRC:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
 // CHECK-RV64-NEXT:ret  [[TMP0]]
 //
-vfloat16mf4_t test_vcompress_vm_f16mf4(vbool64_t mask, vfloat16mf4_t dest, vfloat16mf4_t src, size_t vl) {
-  return vcompress(mask, dest, src, vl);
+vfloat16mf4_t test_vcompress_vm_f16mf4(vbool64_t mask, vfloat16mf4_t src, size_t vl) {
+  return vcompress(mask, src, vl);
 }
 
 // CHECK-RV64-LABEL: @test_vcompress_vm_f16mf2(
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vcompress.nxv2f16.i64( [[DEST:%.*]],  [[SRC:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vcompress.nxv2f16.i64( poison,  [[SRC:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
 // CHECK-RV64-NEXT:ret  [[TMP0]]
 //
-vfloat16mf2_t test_vcompress_vm_f16mf2(vbool32_t mask, vfloat16mf2_t dest, vfloat16mf2_t src, size_t vl) {
-  return vcompress(mask, dest, src, vl);
+vfloat16mf2_t test_vcompress_vm_f16mf2(vbool32_t mask, vfloat16mf2_t src, size_t vl) {
+  return vcompress(mask, src, vl);
 }
 
 // CHECK-RV64-LABEL: @test_vcompress_vm_f16m1(
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vcompress.nxv4f16.i64( [[DEST:%.*]],  [[SRC:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vcompress.nxv4f16.i64( poison,  [[SRC:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
 // CHECK-RV64-NEXT:ret  [[TMP0]]
 //
-vfloat16m1_t test_vcompress_vm_f16m1(vbool16_t mask, vfloat16m1_t dest, vfloat16m1_t src, size_t vl) {
-  return vcompress(mask, dest, src, vl);
+vfloat16m1_t test_vcompress_vm_f16m1(vbool16_t mask, vfloat16m1_t src, size_t vl) {
+  return vcompress(mask, src, vl);
 }
 
 // CHECK-RV64-LABEL: @test_vcompress_vm_f16m2(
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vcompress.nxv8f16.i64( [[DEST:%.*]],  [[SRC:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vcompress.nxv8f16.i64( poison,  [[SRC:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
 // CHECK-RV64-NEXT:ret  [[TMP0]]
 //
-vfloat16m2_t test_vcompress_vm_f16m2(vbool8_t mask, vfloat16m2_t dest, vfloat16m2_t src, size_t vl) {
-  return vcompress(mask, dest, src, vl);
+vfloat16m2_t test_vcompress_vm_f16m2(vbool8_t mask, vfloat16m2_t src, size_t vl) {
+  return vcompress(mask, src, vl);
 }
 
 // CHECK-RV64-LABEL: @test_vcompress_vm_f16m4(
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vcompress.nxv16f16.i64( [[DEST:%.*]],  [[SRC:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vcompress.nxv16f16.i64( poison,  [[SRC:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
 // CHECK-RV64-NEXT:ret  [[TMP0]]
 //
-vfloat16m4_t test_vcompress_vm_f16m4(vbool4_t mask, vfloat16m4_t dest, vfloat16m4_t src, size_t vl) {
-  return vcompress(mask, dest, src, vl);
+vfloat16m4_t test_vcompress_vm_f16m4(vbool4_t mask, vfloat16m4_t src, size_t vl) {
+  return vcompress(mask, src, vl);
 }
 
 // CHECK-RV64-LABEL: @test_vcompress_vm_f16m8(
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vcompress.nxv32f16.i64( [[DEST:%.*]],  [[SRC:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call  @llvm.riscv.vcompress.nxv32f16.i64( poison,  [[SRC:%.*]],  [[MASK:%.*]], i64 [[VL:%.*]])
 // CHECK-RV64-NEXT:ret  [[TMP0]]
 //
-vfloat16m8_t test_vcompress_vm_f16m8(vbool2_t mask, vfloat16m8_t dest, vfloat16m8_t src, size_t vl) {
-  return vcompress(mask, dest, src, vl);
+vfloat16m8_t test_vcompress_vm_f16m8(vbool2_t mask, vfloat16m8_t src, size_t vl) {
+  return vcompress(mask, src, vl);
 }
 
 // CHECK-RV64-LABEL: @test_vcompress_vm_f32mf2(
 // CHECK-RV64-NEXT:  entry:
-// CHECK-RV64-NEXT:[[TMP0:%.*]] =