[PATCH] D142596: [RISCV] Bump Zca, Zcd, Zcf version to 1.0.
craig.topper updated this revision to Diff 492810.
craig.topper added a comment.
Add Zcb
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D142596/new/
https://reviews.llvm.org/D142596
Files:
clang/test/Driver/riscv-arch.c
clang/test/Preprocessor/riscv-target-features.c
llvm/docs/RISCVUsage.rst
llvm/lib/Support/RISCVISAInfo.cpp
llvm/lib/Target/RISCV/RISCVInstrInfoZc.td
llvm/test/CodeGen/RISCV/attributes.ll
llvm/test/MC/RISCV/attribute-arch.s
Index: llvm/test/MC/RISCV/attribute-arch.s
===
--- llvm/test/MC/RISCV/attribute-arch.s
+++ llvm/test/MC/RISCV/attribute-arch.s
@@ -176,11 +176,17 @@
.attribute arch, "rv32if_zkt1p0_zve32f1p0_zve32x1p0_zvl32b1p0"
# CHECK: attribute 5, "rv32i2p0_f2p0_zkt1p0_zve32f1p0_zve32x1p0_zvl32b1p0"
-.attribute arch, "rv32izca0p70"
-# CHECK: attribute 5, "rv32i2p0_zca0p70"
+.attribute arch, "rv32izca1p0"
+# CHECK: attribute 5, "rv32i2p0_zca1p0"
-.attribute arch, "rv32izcb0p70"
-# CHECK: attribute 5, "rv32i2p0_zca0p70_zcb0p70"
+.attribute arch, "rv32izcd1p0"
+# CHECK: attribute 5, "rv32i2p0_zcd1p0"
+
+.attribute arch, "rv32izcf1p0"
+# CHECK: attribute 5, "rv32i2p0_zcf1p0"
+
+.attribute arch, "rv32izcb1p0"
+# CHECK: attribute 5, "rv32i2p0_zca1p0_zcb1p0"
.attribute arch, "rv32izawrs1p0"
# CHECK: attribute 5, "rv32i2p0_zawrs1p0"
Index: llvm/test/CodeGen/RISCV/attributes.ll
===
--- llvm/test/CodeGen/RISCV/attributes.ll
+++ llvm/test/CodeGen/RISCV/attributes.ll
@@ -42,6 +42,8 @@
; RUN: llc -mtriple=riscv32 -mattr=+svinval %s -o - | FileCheck --check-prefix=RV32SVINVAL %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zca %s -o - | FileCheck --check-prefix=RV32ZCA %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zcb %s -o - | FileCheck --check-prefix=RV32ZCB %s
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-zcd %s -o - | FileCheck --check-prefix=RV32ZCD %s
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-zcf %s -o - | FileCheck --check-prefix=RV32ZCF %s
; RUN: llc -mtriple=riscv64 -mattr=+m %s -o - | FileCheck --check-prefix=RV64M %s
; RUN: llc -mtriple=riscv64 -mattr=+zmmul %s -o - | FileCheck --check-prefix=RV64ZMMUL %s
@@ -89,6 +91,7 @@
; RUN: llc -mtriple=riscv64 -mattr=+experimental-ztso %s -o - | FileCheck --check-prefix=RV64ZTSO %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zca %s -o - | FileCheck --check-prefix=RV64ZCA %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zcb %s -o - | FileCheck --check-prefix=RV64ZCB %s
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-zcd %s -o - | FileCheck --check-prefix=RV64ZCD %s
; RV32M: .attribute 5, "rv32i2p0_m2p0"
; RV32ZMMUL: .attribute 5, "rv32i2p0_zmmul1p0"
@@ -130,8 +133,10 @@
; RV32SVNAPOT: .attribute 5, "rv32i2p0_svnapot1p0"
; RV32SVPBMT: .attribute 5, "rv32i2p0_svpbmt1p0"
; RV32SVINVAL: .attribute 5, "rv32i2p0_svinval1p0"
-; RV32ZCA: .attribute 5, "rv32i2p0_zca0p70"
-; RV32ZCB: .attribute 5, "rv32i2p0_zca0p70_zcb0p70"
+; RV32ZCA: .attribute 5, "rv32i2p0_zca1p0"
+; RV32ZCB: .attribute 5, "rv32i2p0_zca1p0_zcb1p0"
+; RV32ZCD: .attribute 5, "rv32i2p0_zcd1p0"
+; RV32ZCF: .attribute 5, "rv32i2p0_zcf1p0"
; RV64M: .attribute 5, "rv64i2p0_m2p0"
; RV64ZMMUL: .attribute 5, "rv64i2p0_zmmul1p0"
@@ -177,8 +182,9 @@
; RV64XVENTANACONDOPS: .attribute 5, "rv64i2p0_xventanacondops1p0"
; RV64XTHEADVDOT: .attribute 5, "rv64i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xtheadvdot1p0"
; RV64ZTSO: .attribute 5, "rv64i2p0_ztso0p1"
-; RV64ZCA: .attribute 5, "rv64i2p0_zca0p70"
-; RV64ZCB: .attribute 5, "rv64i2p0_zca0p70_zcb0p70"
+; RV64ZCA: .attribute 5, "rv64i2p0_zca1p0"
+; RV64ZCB: .attribute 5, "rv64i2p0_zca1p0_zcb1p0"
+; RV64ZCD: .attribute 5, "rv64i2p0_zcd1p0"
define i32 @addi(i32 %a) {
%1 = add i32 %a, 1
Index: llvm/lib/Target/RISCV/RISCVInstrInfoZc.td
===
--- llvm/lib/Target/RISCV/RISCVInstrInfoZc.td
+++ llvm/lib/Target/RISCV/RISCVInstrInfoZc.td
@@ -7,7 +7,7 @@
//===--===//
///
/// This file describes the RISC-V instructions from the 'Zc*' compressed
-/// instruction extensions, version 0.70.4.
+/// instruction extensions, version 1.0.1.
/// This version is still experimental as the 'Zc*' extensions haven't been
/// ratified yet.
///
Index: llvm/lib/Support/RISCVISAInfo.cpp
===
--- llvm/lib/Support/RISCVISAInfo.cpp
+++ llvm/lib/Support/RISCVISAInfo.cpp
@@ -114,10 +114,10 @@
static const RISCVSupportedExtension SupportedExperimentalExtensions[] = {
{"zihintntl", RISCVExtensionVersion{0, 2}},
-{"zca", RISCVExtensionVersion{0, 70}},
-{"zcb", RISCVExtensionVersion{0, 70}},
-{"zcd",
[PATCH] D142596: [RISCV] Bump Zca, Zcd, Zcf version to 1.0.
craig.topper updated this revision to Diff 492337.
craig.topper added a comment.
Update tests
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D142596/new/
https://reviews.llvm.org/D142596
Files:
clang/test/Driver/riscv-arch.c
clang/test/Preprocessor/riscv-target-features.c
llvm/docs/RISCVUsage.rst
llvm/lib/Support/RISCVISAInfo.cpp
llvm/test/CodeGen/RISCV/attributes.ll
llvm/test/MC/RISCV/attribute-arch.s
Index: llvm/test/MC/RISCV/attribute-arch.s
===
--- llvm/test/MC/RISCV/attribute-arch.s
+++ llvm/test/MC/RISCV/attribute-arch.s
@@ -176,8 +176,14 @@
.attribute arch, "rv32if_zkt1p0_zve32f1p0_zve32x1p0_zvl32b1p0"
# CHECK: attribute 5, "rv32i2p0_f2p0_zkt1p0_zve32f1p0_zve32x1p0_zvl32b1p0"
-.attribute arch, "rv32izca0p70"
-# CHECK: attribute 5, "rv32i2p0_zca0p70"
+.attribute arch, "rv32izca1p0"
+# CHECK: attribute 5, "rv32i2p0_zca1p0"
+
+.attribute arch, "rv32izcd1p0"
+# CHECK: attribute 5, "rv32i2p0_zcd1p0"
+
+.attribute arch, "rv32izcf1p0"
+# CHECK: attribute 5, "rv32i2p0_zcf1p0"
.attribute arch, "rv32izawrs1p0"
# CHECK: attribute 5, "rv32i2p0_zawrs1p0"
Index: llvm/test/CodeGen/RISCV/attributes.ll
===
--- llvm/test/CodeGen/RISCV/attributes.ll
+++ llvm/test/CodeGen/RISCV/attributes.ll
@@ -41,6 +41,8 @@
; RUN: llc -mtriple=riscv32 -mattr=+svpbmt %s -o - | FileCheck --check-prefix=RV32SVPBMT %s
; RUN: llc -mtriple=riscv32 -mattr=+svinval %s -o - | FileCheck --check-prefix=RV32SVINVAL %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zca %s -o - | FileCheck --check-prefix=RV32ZCA %s
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-zcd %s -o - | FileCheck --check-prefix=RV32ZCD %s
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-zcf %s -o - | FileCheck --check-prefix=RV32ZCF %s
; RUN: llc -mtriple=riscv64 -mattr=+m %s -o - | FileCheck --check-prefix=RV64M %s
; RUN: llc -mtriple=riscv64 -mattr=+zmmul %s -o - | FileCheck --check-prefix=RV64ZMMUL %s
@@ -87,6 +89,7 @@
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zawrs %s -o - | FileCheck --check-prefix=RV64ZAWRS %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-ztso %s -o - | FileCheck --check-prefix=RV64ZTSO %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-zca %s -o - | FileCheck --check-prefix=RV64ZCA %s
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-zcd %s -o - | FileCheck --check-prefix=RV64ZCD %s
; RV32M: .attribute 5, "rv32i2p0_m2p0"
; RV32ZMMUL: .attribute 5, "rv32i2p0_zmmul1p0"
@@ -128,7 +131,9 @@
; RV32SVNAPOT: .attribute 5, "rv32i2p0_svnapot1p0"
; RV32SVPBMT: .attribute 5, "rv32i2p0_svpbmt1p0"
; RV32SVINVAL: .attribute 5, "rv32i2p0_svinval1p0"
-; RV32ZCA: .attribute 5, "rv32i2p0_zca0p70"
+; RV32ZCA: .attribute 5, "rv32i2p0_zca1p0"
+; RV32ZCD: .attribute 5, "rv32i2p0_zcd1p0"
+; RV32ZCF: .attribute 5, "rv32i2p0_zcf1p0"
; RV64M: .attribute 5, "rv64i2p0_m2p0"
; RV64ZMMUL: .attribute 5, "rv64i2p0_zmmul1p0"
@@ -174,7 +179,8 @@
; RV64XVENTANACONDOPS: .attribute 5, "rv64i2p0_xventanacondops1p0"
; RV64XTHEADVDOT: .attribute 5, "rv64i2p0_f2p0_d2p0_v1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_xtheadvdot1p0"
; RV64ZTSO: .attribute 5, "rv64i2p0_ztso0p1"
-; RV64ZCA: .attribute 5, "rv64i2p0_zca0p70"
+; RV64ZCA: .attribute 5, "rv64i2p0_zca1p0"
+; RV64ZCD: .attribute 5, "rv64i2p0_zcd1p0"
define i32 @addi(i32 %a) {
%1 = add i32 %a, 1
Index: llvm/lib/Support/RISCVISAInfo.cpp
===
--- llvm/lib/Support/RISCVISAInfo.cpp
+++ llvm/lib/Support/RISCVISAInfo.cpp
@@ -114,9 +114,9 @@
static const RISCVSupportedExtension SupportedExperimentalExtensions[] = {
{"zihintntl", RISCVExtensionVersion{0, 2}},
-{"zca", RISCVExtensionVersion{0, 70}},
-{"zcd", RISCVExtensionVersion{0, 70}},
-{"zcf", RISCVExtensionVersion{0, 70}},
+{"zca", RISCVExtensionVersion{1, 0}},
+{"zcd", RISCVExtensionVersion{1, 0}},
+{"zcf", RISCVExtensionVersion{1, 0}},
{"zvfh", RISCVExtensionVersion{0, 1}},
{"zawrs", RISCVExtensionVersion{1, 0}},
{"ztso", RISCVExtensionVersion{0, 1}},
Index: llvm/docs/RISCVUsage.rst
===
--- llvm/docs/RISCVUsage.rst
+++ llvm/docs/RISCVUsage.rst
@@ -136,13 +136,13 @@
LLVM implements the `1.0-rc3 draft specification `_. Note that have been backwards incompatible changes made between release candidates for the 1.0 draft.
``experimental-zca``
- LLVM implements the `0.70 draft specification `_.
+ LLVM implements the `1.0.1 draft specification `_.
``experimental-zcd``
- LLVM
