[PATCH] D143355: [RISCV] Default to -ffixed-x18 for Fuchsia

2023-02-05 Thread Roland McGrath via Phabricator via cfe-commits 
This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG03ff435da540: [RISCV] Default to -ffixed-x18 for Fuchsia 
(authored by mcgrathr).

Repository:
  rG LLVM Github Monorepo

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Files:
  clang/lib/Driver/SanitizerArgs.cpp
  clang/test/Driver/sanitizer-ld.c
  llvm/include/llvm/TargetParser/RISCVTargetParser.h
  llvm/lib/Target/RISCV/RISCVSubtarget.cpp
  llvm/lib/TargetParser/RISCVTargetParser.cpp
  llvm/test/CodeGen/RISCV/reserved-regs.ll

Index: llvm/test/CodeGen/RISCV/reserved-regs.ll
===
--- llvm/test/CodeGen/RISCV/reserved-regs.ll
+++ llvm/test/CodeGen/RISCV/reserved-regs.ll
@@ -57,6 +57,8 @@
 ; RUN: llc -mtriple=riscv32 -mattr=+reserve-x31 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X31
 ; RUN: llc -mtriple=riscv64 -mattr=+reserve-x31 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X31
 
+; RUN: llc -mtriple=riscv64-fuchsia -verify-machineinstrs < %s | FileCheck %s -check-prefix=X18
+
 ; This program is free to use all registers, but needs a stack pointer for
 ; spill values, so do not test for reserving the stack pointer.
 
Index: llvm/lib/TargetParser/RISCVTargetParser.cpp
===
--- llvm/lib/TargetParser/RISCVTargetParser.cpp
+++ llvm/lib/TargetParser/RISCVTargetParser.cpp
@@ -14,6 +14,7 @@
 #include "llvm/TargetParser/RISCVTargetParser.h"
 #include "llvm/ADT/SmallVector.h"
 #include "llvm/ADT/StringSwitch.h"
+#include "llvm/TargetParser/Triple.h"
 
 namespace llvm {
 namespace RISCV {
@@ -100,5 +101,10 @@
   return true;
 }
 
+bool isX18ReservedByDefault(const Triple ) {
+  // X18 is reserved for the ShadowCallStack ABI (even when not enabled).
+  return TT.isOSFuchsia();
+}
+
 } // namespace RISCV
 } // namespace llvm
Index: llvm/lib/Target/RISCV/RISCVSubtarget.cpp
===
--- llvm/lib/Target/RISCV/RISCVSubtarget.cpp
+++ llvm/lib/Target/RISCV/RISCVSubtarget.cpp
@@ -83,6 +83,9 @@
   FrameLowering(
   initializeSubtargetDependencies(TT, CPU, TuneCPU, FS, ABIName)),
   InstrInfo(*this), RegInfo(getHwMode()), TLInfo(TM, *this) {
+  if (RISCV::isX18ReservedByDefault(TT))
+UserReservedRegister.set(RISCV::X18);
+
   CallLoweringInfo.reset(new RISCVCallLowering(*getTargetLowering()));
   Legalizer.reset(new RISCVLegalizerInfo(*this));
 
Index: llvm/include/llvm/TargetParser/RISCVTargetParser.h
===
--- llvm/include/llvm/TargetParser/RISCVTargetParser.h
+++ llvm/include/llvm/TargetParser/RISCVTargetParser.h
@@ -18,6 +18,9 @@
 #include 
 
 namespace llvm {
+
+class Triple;
+
 namespace RISCV {
 
 // We use 64 bits as the known part in the scalable vector types.
@@ -38,6 +41,8 @@
 void fillValidTuneCPUArchList(SmallVectorImpl , bool IsRV64);
 bool getCPUFeaturesExceptStdExt(CPUKind Kind, std::vector );
 
+bool isX18ReservedByDefault(const Triple );
+
 } // namespace RISCV
 } // namespace llvm
 
Index: clang/test/Driver/sanitizer-ld.c
===
--- clang/test/Driver/sanitizer-ld.c
+++ clang/test/Driver/sanitizer-ld.c
@@ -731,6 +731,11 @@
 // RUN:   | FileCheck --check-prefix=CHECK-SHADOWCALLSTACK-LINUX-RISCV64 %s
 // CHECK-SHADOWCALLSTACK-LINUX-RISCV64: '-fsanitize=shadow-call-stack' only allowed with '-ffixed-x18'
 
+// RUN: %clang -fsanitize=shadow-call-stack -### %s 2>&1 \
+// RUN: --target=riscv64-unknown-fuchsia -fuse-ld=ld \
+// RUN:   | FileCheck --check-prefix=CHECK-SHADOWCALLSTACK-FUCHSIA-RISCV64 %s
+// CHECK-SHADOWCALLSTACK-FUCHSIA-RISCV64-NOT: error:
+
 // RUN: %clang -fsanitize=shadow-call-stack -### %s 2>&1 \
 // RUN: --target=aarch64-unknown-linux -fuse-ld=ld -ffixed-x18 \
 // RUN:   | FileCheck --check-prefix=CHECK-SHADOWCALLSTACK-LINUX-AARCH64-X18 %s
Index: clang/lib/Driver/SanitizerArgs.cpp
===
--- clang/lib/Driver/SanitizerArgs.cpp
+++ clang/lib/Driver/SanitizerArgs.cpp
@@ -19,6 +19,7 @@
 #include "llvm/Support/TargetParser.h"
 #include "llvm/Support/VirtualFileSystem.h"
 #include "llvm/TargetParser/AArch64TargetParser.h"
+#include "llvm/TargetParser/RISCVTargetParser.h"
 #include "llvm/Transforms/Instrumentation/AddressSanitizerOptions.h"
 #include 
 
@@ -545,7 +546,8 @@
   if ((Kinds & SanitizerKind::ShadowCallStack) &&
   ((TC.getTriple().isAArch64() &&
 !llvm::AArch64::isX18ReservedByDefault(TC.getTriple())) ||
-   TC.getTriple().isRISCV()) &&
+   (TC.getTriple().isRISCV() &&
+!llvm::RISCV::isX18ReservedByDefault(TC.getTriple( &&
   !Args.hasArg(options::OPT_ffixed_x18) && DiagnoseErrors) {
 D.Diag(diag::err_drv_argument_only_allowed_with)

[PATCH] D143355: [RISCV] Default to -ffixed-x18 for Fuchsia

2023-02-05 Thread Roland McGrath via Phabricator via cfe-commits 
mcgrathr updated this revision to Diff 494972.
mcgrathr added a comment.

rebased, added clang driver test vs -fsanitize=shadow-call-stack


Repository:
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Files:
  clang/lib/Driver/SanitizerArgs.cpp
  clang/test/Driver/sanitizer-ld.c
  llvm/include/llvm/TargetParser/RISCVTargetParser.h
  llvm/lib/Target/RISCV/RISCVSubtarget.cpp
  llvm/lib/TargetParser/RISCVTargetParser.cpp
  llvm/test/CodeGen/RISCV/reserved-regs.ll

Index: llvm/test/CodeGen/RISCV/reserved-regs.ll
===
--- llvm/test/CodeGen/RISCV/reserved-regs.ll
+++ llvm/test/CodeGen/RISCV/reserved-regs.ll
@@ -57,6 +57,8 @@
 ; RUN: llc -mtriple=riscv32 -mattr=+reserve-x31 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X31
 ; RUN: llc -mtriple=riscv64 -mattr=+reserve-x31 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X31
 
+; RUN: llc -mtriple=riscv64-fuchsia -verify-machineinstrs < %s | FileCheck %s -check-prefix=X18
+
 ; This program is free to use all registers, but needs a stack pointer for
 ; spill values, so do not test for reserving the stack pointer.
 
Index: llvm/lib/TargetParser/RISCVTargetParser.cpp
===
--- llvm/lib/TargetParser/RISCVTargetParser.cpp
+++ llvm/lib/TargetParser/RISCVTargetParser.cpp
@@ -14,6 +14,7 @@
 #include "llvm/TargetParser/RISCVTargetParser.h"
 #include "llvm/ADT/SmallVector.h"
 #include "llvm/ADT/StringSwitch.h"
+#include "llvm/TargetParser/Triple.h"
 
 namespace llvm {
 namespace RISCV {
@@ -100,5 +101,10 @@
   return true;
 }
 
+bool isX18ReservedByDefault(const Triple ) {
+  // X18 is reserved for the ShadowCallStack ABI (even when not enabled).
+  return TT.isOSFuchsia();
+}
+
 } // namespace RISCV
 } // namespace llvm
Index: llvm/lib/Target/RISCV/RISCVSubtarget.cpp
===
--- llvm/lib/Target/RISCV/RISCVSubtarget.cpp
+++ llvm/lib/Target/RISCV/RISCVSubtarget.cpp
@@ -83,6 +83,9 @@
   FrameLowering(
   initializeSubtargetDependencies(TT, CPU, TuneCPU, FS, ABIName)),
   InstrInfo(*this), RegInfo(getHwMode()), TLInfo(TM, *this) {
+  if (RISCV::isX18ReservedByDefault(TT))
+UserReservedRegister.set(RISCV::X18);
+
   CallLoweringInfo.reset(new RISCVCallLowering(*getTargetLowering()));
   Legalizer.reset(new RISCVLegalizerInfo(*this));
 
Index: llvm/include/llvm/TargetParser/RISCVTargetParser.h
===
--- llvm/include/llvm/TargetParser/RISCVTargetParser.h
+++ llvm/include/llvm/TargetParser/RISCVTargetParser.h
@@ -18,6 +18,9 @@
 #include 
 
 namespace llvm {
+
+class Triple;
+
 namespace RISCV {
 
 // We use 64 bits as the known part in the scalable vector types.
@@ -38,6 +41,8 @@
 void fillValidTuneCPUArchList(SmallVectorImpl , bool IsRV64);
 bool getCPUFeaturesExceptStdExt(CPUKind Kind, std::vector );
 
+bool isX18ReservedByDefault(const Triple );
+
 } // namespace RISCV
 } // namespace llvm
 
Index: clang/test/Driver/sanitizer-ld.c
===
--- clang/test/Driver/sanitizer-ld.c
+++ clang/test/Driver/sanitizer-ld.c
@@ -731,6 +731,11 @@
 // RUN:   | FileCheck --check-prefix=CHECK-SHADOWCALLSTACK-LINUX-RISCV64 %s
 // CHECK-SHADOWCALLSTACK-LINUX-RISCV64: '-fsanitize=shadow-call-stack' only allowed with '-ffixed-x18'
 
+// RUN: %clang -fsanitize=shadow-call-stack -### %s 2>&1 \
+// RUN: --target=riscv64-unknown-fuchsia -fuse-ld=ld \
+// RUN:   | FileCheck --check-prefix=CHECK-SHADOWCALLSTACK-FUCHSIA-RISCV64 %s
+// CHECK-SHADOWCALLSTACK-FUCHSIA-RISCV64-NOT: error:
+
 // RUN: %clang -fsanitize=shadow-call-stack -### %s 2>&1 \
 // RUN: --target=aarch64-unknown-linux -fuse-ld=ld -ffixed-x18 \
 // RUN:   | FileCheck --check-prefix=CHECK-SHADOWCALLSTACK-LINUX-AARCH64-X18 %s
Index: clang/lib/Driver/SanitizerArgs.cpp
===
--- clang/lib/Driver/SanitizerArgs.cpp
+++ clang/lib/Driver/SanitizerArgs.cpp
@@ -19,6 +19,7 @@
 #include "llvm/Support/TargetParser.h"
 #include "llvm/Support/VirtualFileSystem.h"
 #include "llvm/TargetParser/AArch64TargetParser.h"
+#include "llvm/TargetParser/RISCVTargetParser.h"
 #include "llvm/Transforms/Instrumentation/AddressSanitizerOptions.h"
 #include 
 
@@ -545,7 +546,8 @@
   if ((Kinds & SanitizerKind::ShadowCallStack) &&
   ((TC.getTriple().isAArch64() &&
 !llvm::AArch64::isX18ReservedByDefault(TC.getTriple())) ||
-   TC.getTriple().isRISCV()) &&
+   (TC.getTriple().isRISCV() &&
+!llvm::RISCV::isX18ReservedByDefault(TC.getTriple( &&
   !Args.hasArg(options::OPT_ffixed_x18) && DiagnoseErrors) {
 D.Diag(diag::err_drv_argument_only_allowed_with)
 << lastArgumentForMask(D, Args, Kinds & SanitizerKind::ShadowCallStack)

[PATCH] D143355: [RISCV] Default to -ffixed-x18 for Fuchsia

2023-02-05 Thread Fangrui Song via Phabricator via cfe-commits 
MaskRay added inline comments.



Comment at: llvm/lib/Target/RISCV/RISCVSubtarget.cpp:16
+#include "GISel/RISCVLegalizerInfo.h"
+#include "GISel/RISCVRegisterBankInfo.h"
 #include "RISCV.h"

mcgrathr wrote:
> jrtc27 wrote:
> > Unrelated change
> arcanist requested it via clang-format
> 
Rebase. I fixed it.


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[PATCH] D143355: [RISCV] Default to -ffixed-x18 for Fuchsia

2023-02-05 Thread Roland McGrath via Phabricator via cfe-commits 
mcgrathr updated this revision to Diff 494970.
mcgrathr added a comment.

rebased


Repository:
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Files:
  clang/lib/Driver/SanitizerArgs.cpp
  llvm/include/llvm/TargetParser/RISCVTargetParser.h
  llvm/lib/Target/RISCV/RISCVSubtarget.cpp
  llvm/lib/TargetParser/RISCVTargetParser.cpp
  llvm/test/CodeGen/RISCV/reserved-regs.ll

Index: llvm/test/CodeGen/RISCV/reserved-regs.ll
===
--- llvm/test/CodeGen/RISCV/reserved-regs.ll
+++ llvm/test/CodeGen/RISCV/reserved-regs.ll
@@ -57,6 +57,8 @@
 ; RUN: llc -mtriple=riscv32 -mattr=+reserve-x31 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X31
 ; RUN: llc -mtriple=riscv64 -mattr=+reserve-x31 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X31
 
+; RUN: llc -mtriple=riscv64-fuchsia -verify-machineinstrs < %s | FileCheck %s -check-prefix=X18
+
 ; This program is free to use all registers, but needs a stack pointer for
 ; spill values, so do not test for reserving the stack pointer.
 
Index: llvm/lib/TargetParser/RISCVTargetParser.cpp
===
--- llvm/lib/TargetParser/RISCVTargetParser.cpp
+++ llvm/lib/TargetParser/RISCVTargetParser.cpp
@@ -14,6 +14,7 @@
 #include "llvm/TargetParser/RISCVTargetParser.h"
 #include "llvm/ADT/SmallVector.h"
 #include "llvm/ADT/StringSwitch.h"
+#include "llvm/TargetParser/Triple.h"
 
 namespace llvm {
 namespace RISCV {
@@ -100,5 +101,10 @@
   return true;
 }
 
+bool isX18ReservedByDefault(const Triple ) {
+  // X18 is reserved for the ShadowCallStack ABI (even when not enabled).
+  return TT.isOSFuchsia();
+}
+
 } // namespace RISCV
 } // namespace llvm
Index: llvm/lib/Target/RISCV/RISCVSubtarget.cpp
===
--- llvm/lib/Target/RISCV/RISCVSubtarget.cpp
+++ llvm/lib/Target/RISCV/RISCVSubtarget.cpp
@@ -11,13 +11,13 @@
 //===--===//
 
 #include "RISCVSubtarget.h"
+#include "GISel/RISCVCallLowering.h"
+#include "GISel/RISCVLegalizerInfo.h"
+#include "GISel/RISCVRegisterBankInfo.h"
 #include "RISCV.h"
 #include "RISCVFrameLowering.h"
 #include "RISCVMacroFusion.h"
 #include "RISCVTargetMachine.h"
-#include "GISel/RISCVCallLowering.h"
-#include "GISel/RISCVLegalizerInfo.h"
-#include "GISel/RISCVRegisterBankInfo.h"
 #include "llvm/MC/TargetRegistry.h"
 #include "llvm/Support/ErrorHandling.h"
 
@@ -83,6 +83,9 @@
   FrameLowering(
   initializeSubtargetDependencies(TT, CPU, TuneCPU, FS, ABIName)),
   InstrInfo(*this), RegInfo(getHwMode()), TLInfo(TM, *this) {
+  if (RISCV::isX18ReservedByDefault(TT))
+UserReservedRegister.set(RISCV::X18);
+
   CallLoweringInfo.reset(new RISCVCallLowering(*getTargetLowering()));
   Legalizer.reset(new RISCVLegalizerInfo(*this));
 
Index: llvm/include/llvm/TargetParser/RISCVTargetParser.h
===
--- llvm/include/llvm/TargetParser/RISCVTargetParser.h
+++ llvm/include/llvm/TargetParser/RISCVTargetParser.h
@@ -18,6 +18,9 @@
 #include 
 
 namespace llvm {
+
+class Triple;
+
 namespace RISCV {
 
 // We use 64 bits as the known part in the scalable vector types.
@@ -38,6 +41,8 @@
 void fillValidTuneCPUArchList(SmallVectorImpl , bool IsRV64);
 bool getCPUFeaturesExceptStdExt(CPUKind Kind, std::vector );
 
+bool isX18ReservedByDefault(const Triple );
+
 } // namespace RISCV
 } // namespace llvm
 
Index: clang/lib/Driver/SanitizerArgs.cpp
===
--- clang/lib/Driver/SanitizerArgs.cpp
+++ clang/lib/Driver/SanitizerArgs.cpp
@@ -19,6 +19,7 @@
 #include "llvm/Support/TargetParser.h"
 #include "llvm/Support/VirtualFileSystem.h"
 #include "llvm/TargetParser/AArch64TargetParser.h"
+#include "llvm/TargetParser/RISCVTargetParser.h"
 #include "llvm/Transforms/Instrumentation/AddressSanitizerOptions.h"
 #include 
 
@@ -545,7 +546,8 @@
   if ((Kinds & SanitizerKind::ShadowCallStack) &&
   ((TC.getTriple().isAArch64() &&
 !llvm::AArch64::isX18ReservedByDefault(TC.getTriple())) ||
-   TC.getTriple().isRISCV()) &&
+   (TC.getTriple().isRISCV() &&
+!llvm::RISCV::isX18ReservedByDefault(TC.getTriple( &&
   !Args.hasArg(options::OPT_ffixed_x18) && DiagnoseErrors) {
 D.Diag(diag::err_drv_argument_only_allowed_with)
 << lastArgumentForMask(D, Args, Kinds & SanitizerKind::ShadowCallStack)
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[PATCH] D143355: [RISCV] Default to -ffixed-x18 for Fuchsia

2023-02-05 Thread Roland McGrath via Phabricator via cfe-commits 
mcgrathr added inline comments.



Comment at: llvm/lib/Target/RISCV/RISCVSubtarget.cpp:16
+#include "GISel/RISCVLegalizerInfo.h"
+#include "GISel/RISCVRegisterBankInfo.h"
 #include "RISCV.h"

jrtc27 wrote:
> Unrelated change
arcanist requested it via clang-format



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[PATCH] D143355: [RISCV] Default to -ffixed-x18 for Fuchsia

2023-02-05 Thread Jessica Clarke via Phabricator via cfe-commits 
jrtc27 added inline comments.



Comment at: llvm/lib/Target/RISCV/RISCVSubtarget.cpp:16
+#include "GISel/RISCVLegalizerInfo.h"
+#include "GISel/RISCVRegisterBankInfo.h"
 #include "RISCV.h"

Unrelated change


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[PATCH] D143355: [RISCV] Default to -ffixed-x18 for Fuchsia

2023-02-05 Thread Petr Hosek via Phabricator via cfe-commits 
phosek accepted this revision.
phosek added a comment.
This revision is now accepted and ready to land.

LGTM


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[PATCH] D143355: [RISCV] Default to -ffixed-x18 for Fuchsia

2023-02-05 Thread Roland McGrath via Phabricator via cfe-commits 
mcgrathr created this revision.
mcgrathr added reviewers: phosek, paulkirth, leonardchan.
Herald added subscribers: luke, VincentWu, abrachet, vkmr, frasercrmck, 
evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, 
jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, 
zzheng, jrtc27, shiva0217, kito-cheng, niosHD, sabuasal, simoncook, johnrusso, 
rbar, asb, hiraditya, arichardson.
Herald added a project: All.
mcgrathr requested review of this revision.
Herald added subscribers: llvm-commits, cfe-commits, pcwang-thead, eopXD, 
MaskRay.
Herald added projects: clang, LLVM.

Fuchsia's ABI always reserves the x18 (s2) register for the
ShadowCallStack ABI, even when -fsanitize=shadow-call-stack is
not enabled.


Repository:
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Files:
  clang/lib/Driver/SanitizerArgs.cpp
  llvm/include/llvm/TargetParser/RISCVTargetParser.h
  llvm/lib/Target/RISCV/RISCVSubtarget.cpp
  llvm/lib/TargetParser/RISCVTargetParser.cpp
  llvm/test/CodeGen/RISCV/reserved-regs.ll

Index: llvm/test/CodeGen/RISCV/reserved-regs.ll
===
--- llvm/test/CodeGen/RISCV/reserved-regs.ll
+++ llvm/test/CodeGen/RISCV/reserved-regs.ll
@@ -57,6 +57,8 @@
 ; RUN: llc -mtriple=riscv32 -mattr=+reserve-x31 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X31
 ; RUN: llc -mtriple=riscv64 -mattr=+reserve-x31 -verify-machineinstrs < %s | FileCheck %s -check-prefix=X31
 
+; RUN: llc -mtriple=riscv64-fuchsia -verify-machineinstrs < %s | FileCheck %s -check-prefix=X18
+
 ; This program is free to use all registers, but needs a stack pointer for
 ; spill values, so do not test for reserving the stack pointer.
 
Index: llvm/lib/TargetParser/RISCVTargetParser.cpp
===
--- llvm/lib/TargetParser/RISCVTargetParser.cpp
+++ llvm/lib/TargetParser/RISCVTargetParser.cpp
@@ -14,6 +14,7 @@
 #include "llvm/TargetParser/RISCVTargetParser.h"
 #include "llvm/ADT/SmallVector.h"
 #include "llvm/ADT/StringSwitch.h"
+#include "llvm/TargetParser/Triple.h"
 
 namespace llvm {
 namespace RISCV {
@@ -100,5 +101,10 @@
   return true;
 }
 
+bool isX18ReservedByDefault(const Triple ) {
+  // X18 is reserved for the ShadowCallStack ABI (even when not enabled).
+  return TT.isOSFuchsia();
+}
+
 } // namespace RISCV
 } // namespace llvm
Index: llvm/lib/Target/RISCV/RISCVSubtarget.cpp
===
--- llvm/lib/Target/RISCV/RISCVSubtarget.cpp
+++ llvm/lib/Target/RISCV/RISCVSubtarget.cpp
@@ -11,13 +11,13 @@
 //===--===//
 
 #include "RISCVSubtarget.h"
+#include "GISel/RISCVCallLowering.h"
+#include "GISel/RISCVLegalizerInfo.h"
+#include "GISel/RISCVRegisterBankInfo.h"
 #include "RISCV.h"
 #include "RISCVFrameLowering.h"
 #include "RISCVMacroFusion.h"
 #include "RISCVTargetMachine.h"
-#include "GISel/RISCVCallLowering.h"
-#include "GISel/RISCVLegalizerInfo.h"
-#include "GISel/RISCVRegisterBankInfo.h"
 #include "llvm/MC/TargetRegistry.h"
 #include "llvm/Support/ErrorHandling.h"
 
@@ -84,6 +84,9 @@
   initializeSubtargetDependencies(TT, CPU, TuneCPU, FS, ABIName)),
   InstrInfo(*this), RegInfo(getHwMode()), TLInfo(TM, *this),
   TargetTriple(TT) {
+  if (RISCV::isX18ReservedByDefault(TT))
+UserReservedRegister.set(RISCV::X18);
+
   CallLoweringInfo.reset(new RISCVCallLowering(*getTargetLowering()));
   Legalizer.reset(new RISCVLegalizerInfo(*this));
 
Index: llvm/include/llvm/TargetParser/RISCVTargetParser.h
===
--- llvm/include/llvm/TargetParser/RISCVTargetParser.h
+++ llvm/include/llvm/TargetParser/RISCVTargetParser.h
@@ -18,6 +18,9 @@
 #include 
 
 namespace llvm {
+
+class Triple;
+
 namespace RISCV {
 
 // We use 64 bits as the known part in the scalable vector types.
@@ -38,6 +41,8 @@
 void fillValidTuneCPUArchList(SmallVectorImpl , bool IsRV64);
 bool getCPUFeaturesExceptStdExt(CPUKind Kind, std::vector );
 
+bool isX18ReservedByDefault(const Triple );
+
 } // namespace RISCV
 } // namespace llvm
 
Index: clang/lib/Driver/SanitizerArgs.cpp
===
--- clang/lib/Driver/SanitizerArgs.cpp
+++ clang/lib/Driver/SanitizerArgs.cpp
@@ -19,6 +19,7 @@
 #include "llvm/Support/TargetParser.h"
 #include "llvm/Support/VirtualFileSystem.h"
 #include "llvm/TargetParser/AArch64TargetParser.h"
+#include "llvm/TargetParser/RISCVTargetParser.h"
 #include "llvm/Transforms/Instrumentation/AddressSanitizerOptions.h"
 #include 
 
@@ -545,7 +546,8 @@
   if ((Kinds & SanitizerKind::ShadowCallStack) &&
   ((TC.getTriple().isAArch64() &&
 !llvm::AArch64::isX18ReservedByDefault(TC.getTriple())) ||
-   TC.getTriple().isRISCV()) &&
+   (TC.getTriple().isRISCV() &&
+