subject:"\[PATCH\] D146946\: \[RISCV\]\[MC\] Add support for experimental zicond extension"

[PATCH] D146946: [RISCV][MC] Add support for experimental zicond extension

2023-03-29 Thread Alex Bradbury via Phabricator via cfe-commits

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGd3291c692c0a: [RISCV][MC] Add support for the experimental 
zicond extension (authored by asb).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D146946/new/

https://reviews.llvm.org/D146946

Files:
  clang/test/Preprocessor/riscv-target-features.c
  llvm/docs/RISCVUsage.rst
  llvm/docs/ReleaseNotes.rst
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/RISCVFeatures.td
  llvm/lib/Target/RISCV/RISCVInstrInfo.td
  llvm/lib/Target/RISCV/RISCVInstrInfoZicond.td
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/MC/RISCV/attribute-arch.s
  llvm/test/MC/RISCV/rv32zicond-invalid.s
  llvm/test/MC/RISCV/rv32zicond-valid.s

Index: llvm/test/MC/RISCV/rv32zicond-valid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rv32zicond-valid.s
@@ -0,0 +1,18 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zicond -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zicond -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zicond < %s \
+# RUN: | llvm-objdump --mattr=+experimental-zicond -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zicond < %s \
+# RUN: | llvm-objdump --mattr=+experimental-zicond -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+
+# CHECK-ASM-AND-OBJ: czero.eqz t0, a3, ra
+# CHECK-ASM: encoding: [0xb3,0xd2,0x16,0x0e]
+czero.eqz t0, a3, ra
+
+# CHECK-ASM-AND-OBJ: czero.nez a1, gp, t6
+# CHECK-ASM: encoding: [0xb3,0xf5,0xf1,0x0f]
+czero.nez a1, gp, t6
Index: llvm/test/MC/RISCV/rv32zicond-invalid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rv32zicond-invalid.s
@@ -0,0 +1,18 @@
+# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-zicond < %s 2>&1 | FileCheck %s
+# RUN: not llvm-mc -triple riscv64 -mattr=+experimental-zicond < %s 2>&1 | FileCheck %s
+
+# Use of operand modifier on register name
+czero.eqz t1, %lo(t2), t3 # CHECK: :[[@LINE]]:15: error: invalid operand for instruction
+
+# Invalid register name
+czero.nez a4, a3, foo # CHECK: :[[@LINE]]:19: error: invalid operand for instruction
+
+# Invalid operand type
+czero.eqz t1, 2, t3 # CHECK: :[[@LINE]]:15: error: invalid operand for instruction
+
+# Too many operands
+czero.eqz t1, t2, t3, t4 # CHECK: :[[@LINE]]:23: error: invalid operand for instruction
+czero.nez t1, t2, t3, 4 # CHECK: :[[@LINE]]:23: error: invalid operand for instruction
+
+# Too few operands
+czero.eqz t1, t2 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
Index: llvm/test/MC/RISCV/attribute-arch.s
===
--- llvm/test/MC/RISCV/attribute-arch.s
+++ llvm/test/MC/RISCV/attribute-arch.s
@@ -236,3 +236,6 @@
 
 .attribute arch, "rv32izfa0p1"
 # CHECK: attribute  5, "rv32i2p0_f2p0_zfa0p1"
+
+.attribute arch, "rv32izicond1p0"
+# CHECK: attribute  5, "rv32i2p0_zicond1p0"
Index: llvm/test/CodeGen/RISCV/attributes.ll
===
--- llvm/test/CodeGen/RISCV/attributes.ll
+++ llvm/test/CodeGen/RISCV/attributes.ll
@@ -64,6 +64,7 @@
 ; RUN: llc -mtriple=riscv32 -mattr=+zve32x -mattr=+experimental-zvks %s -o - | FileCheck --check-prefix=RV32ZVKS %s
 ; RUN: llc -mtriple=riscv32 -mattr=+zve32x -mattr=+experimental-zvksed %s -o - | FileCheck --check-prefix=RV32ZVKSED %s
 ; RUN: llc -mtriple=riscv32 -mattr=+zve32x -mattr=+experimental-zvksh %s -o - | FileCheck --check-prefix=RV32ZVKSH %s
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-zicond %s -o - | FileCheck --check-prefix=RV32ZICOND %s
 
 ; RUN: llc -mtriple=riscv64 %s -o - | FileCheck %s
 ; RUN: llc -mtriple=riscv64 -mattr=+m %s -o - | FileCheck --check-prefixes=CHECK,RV64M %s
@@ -135,6 +136,7 @@
 ; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+experimental-zvks %s -o - | FileCheck --check-prefix=RV64ZVKS %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+experimental-zvksed %s -o - | FileCheck --check-prefix=RV64ZVKSED %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+experimental-zvksh %s -o - | FileCheck --check-prefix=RV64ZVKSH %s
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-zicond %s -o - | FileCheck --check-prefix=RV64ZICOND %s
 
 ; CHECK: .attribute 4, 16
 
@@ -201,6 +203,7 @@
 ; RV32ZVKS: .attribute 5, "rv32i2p0_zve32x1p0_zvkb0p3_zvks0p3_zvksed0p3_zvksh0p3_zvl32b1p0"
 ; RV32ZVKSED: .attribute 5, "rv32i2p0_zve32x1p0_zvksed0p3_zvl32b1p0"
 ; RV32ZVKSH: .attribute 5, "rv32i2p0_zve32x1p0_zvksh0p3_zvl32b1p0"
+; RV32ZICOND: .attribute 5, "rv32i2p0_zicon

[PATCH] D146946: [RISCV][MC] Add support for experimental zicond extension

2023-03-27 Thread Craig Topper via Phabricator via cfe-commits

craig.topper accepted this revision.
craig.topper added a comment.
This revision is now accepted and ready to land.

LGTM


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D146946/new/

https://reviews.llvm.org/D146946

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[PATCH] D146946: [RISCV][MC] Add support for experimental zicond extension

2023-03-27 Thread Alex Bradbury via Phabricator via cfe-commits

asb created this revision.
asb added reviewers: reames, craig.topper.
Herald added subscribers: jobnoorman, luke, wingo, pmatos, VincentWu, vkmr, 
frasercrmck, jdoerfert, evandro, luismarques, apazos, sameer.abuasal, 
s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, 
rogfer01, edward-jones, zzheng, jrtc27, shiva0217, kito-cheng, niosHD, 
sabuasal, simoncook, johnrusso, rbar, hiraditya, arichardson.
Herald added a project: All.
asb requested review of this revision.
Herald added subscribers: cfe-commits, pcwang-thead, eopXD, MaskRay.
Herald added projects: clang, LLVM.

This patch adds the basic MC layer support for Zicond, based on 1.0-rc1 
. As with other 
extensions, if there are additional changes between release candidates without 
incrementing the version number we won't be able to reflect that in the version 
number. I believe we've previously decided this is not a problem for extensions 
still considered experimental (i.e. not yet ratified).


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D146946

Files:
  clang/test/Preprocessor/riscv-target-features.c
  llvm/docs/RISCVUsage.rst
  llvm/docs/ReleaseNotes.rst
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/RISCVFeatures.td
  llvm/lib/Target/RISCV/RISCVInstrInfo.td
  llvm/lib/Target/RISCV/RISCVInstrInfoZicond.td
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/MC/RISCV/attribute-arch.s
  llvm/test/MC/RISCV/rv32zicond-invalid.s
  llvm/test/MC/RISCV/rv32zicond-valid.s

Index: llvm/test/MC/RISCV/rv32zicond-valid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rv32zicond-valid.s
@@ -0,0 +1,18 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zicond -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zicond -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zicond < %s \
+# RUN: | llvm-objdump --mattr=+experimental-zicond -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zicond < %s \
+# RUN: | llvm-objdump --mattr=+experimental-zicond -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+
+# CHECK-ASM-AND-OBJ: czero.eqz t0, a3, ra
+# CHECK-ASM: encoding: [0xb3,0xd2,0x16,0x0e]
+czero.eqz t0, a3, ra
+
+# CHECK-ASM-AND-OBJ: czero.nez a1, gp, t6
+# CHECK-ASM: encoding: [0xb3,0xf5,0xf1,0x0f]
+czero.nez a1, gp, t6
Index: llvm/test/MC/RISCV/rv32zicond-invalid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rv32zicond-invalid.s
@@ -0,0 +1,18 @@
+# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-zicond < %s 2>&1 | FileCheck %s
+# RUN: not llvm-mc -triple riscv64 -mattr=+experimental-zicond < %s 2>&1 | FileCheck %s
+
+# Use of operand modifier on register name
+czero.eqz t1, %lo(t2), t3 # CHECK: :[[@LINE]]:15: error: invalid operand for instruction
+
+# Invalid register name
+czero.nez a4, a3, foo # CHECK: :[[@LINE]]:19: error: invalid operand for instruction
+
+# Invalid operand type
+czero.eqz t1, 2, t3 # CHECK: :[[@LINE]]:15: error: invalid operand for instruction
+
+# Too many operands
+czero.eqz t1, t2, t3, t4 # CHECK: :[[@LINE]]:23: error: invalid operand for instruction
+czero.nez t1, t2, t3, 4 # CHECK: :[[@LINE]]:23: error: invalid operand for instruction
+
+# Too few operands
+czero.eqz t1, t2 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
Index: llvm/test/MC/RISCV/attribute-arch.s
===
--- llvm/test/MC/RISCV/attribute-arch.s
+++ llvm/test/MC/RISCV/attribute-arch.s
@@ -236,3 +236,6 @@
 
 .attribute arch, "rv32izfa0p1"
 # CHECK: attribute  5, "rv32i2p0_f2p0_zfa0p1"
+
+.attribute arch, "rv32izicond1p0"
+# CHECK: attribute  5, "rv32i2p0_zicond1p0"
Index: llvm/test/CodeGen/RISCV/attributes.ll
===
--- llvm/test/CodeGen/RISCV/attributes.ll
+++ llvm/test/CodeGen/RISCV/attributes.ll
@@ -64,6 +64,7 @@
 ; RUN: llc -mtriple=riscv32 -mattr=+zve32x -mattr=+experimental-zvks %s -o - | FileCheck --check-prefix=RV32ZVKS %s
 ; RUN: llc -mtriple=riscv32 -mattr=+zve32x -mattr=+experimental-zvksed %s -o - | FileCheck --check-prefix=RV32ZVKSED %s
 ; RUN: llc -mtriple=riscv32 -mattr=+zve32x -mattr=+experimental-zvksh %s -o - | FileCheck --check-prefix=RV32ZVKSH %s
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-zicond %s -o - | FileCheck --check-prefix=RV32ZICOND %s
 
 ; RUN: llc -mtriple=riscv64 %s -o - | FileCheck %s
 ; RUN: llc -mtriple=riscv64 -mattr=+m %s -o - | FileCheck --check-prefixes=CHECK,RV64M %s
@@ -135,6 +136,7 @@
 ; RUN: llc -mtriple=riscv64 -mattr=+zve32x -

[PATCH] D146946: [RISCV][MC] Add support for experimental zicond extension

[PATCH] D146946: [RISCV][MC] Add support for experimental zicond extension

[PATCH] D146946: [RISCV][MC] Add support for experimental zicond extension

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