[PATCH] D147914: [8/11][POC][Clang][RISCV] Define tuple type variant of vloxseg2ei32 vluxseg2ei32

2023-05-22 Thread Yueh-Ting (eop) Chen via Phabricator via cfe-commits 
This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG827f43918836: [8/11][POC][Clang][RISCV] Define tuple type 
variant of vloxseg2ei32 vluxseg2ei32 (authored by eopXD).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D147914/new/

https://reviews.llvm.org/D147914

Files:
  clang/include/clang/Basic/riscv_vector.td
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei32_tuple.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei32_tuple.c

Index: clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei32_tuple.c
===
--- /dev/null
+++ clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei32_tuple.c
@@ -0,0 +1,28 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
+// REQUIRES: riscv-registered-target
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \
+// RUN:   -target-feature +experimental-zvfh -disable-O0-optnone  \
+// RUN:   -emit-llvm %s -o - | opt -S -passes=mem2reg | \
+// RUN:   FileCheck --check-prefix=CHECK-RV64 %s
+
+#include 
+
+// CHECK-RV64-LABEL: define dso_local { ,  } @test_vluxseg2ei32_v_tuple_i32m1
+// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]],  [[BINDEX:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call { ,  } @llvm.riscv.vluxseg2.nxv2i32.nxv2i32.i64( poison,  poison, ptr [[BASE]],  [[BINDEX]], i64 [[VL]])
+// CHECK-RV64-NEXT:ret { ,  } [[TMP0]]
+//
+vint32m1x2_t test_vluxseg2ei32_v_tuple_i32m1(const int32_t *base, vuint32m1_t bindex, size_t vl) {
+  return __riscv_vluxseg2ei32_v_tuple_i32m1(base, bindex, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local { ,  } @test_vluxseg2ei32_v_tuple_i32m1_m
+// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]],  [[BINDEX:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call { ,  } @llvm.riscv.vluxseg2.mask.nxv2i32.nxv2i32.i64( poison,  poison, ptr [[BASE]],  [[BINDEX]],  [[MASK]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT:ret { ,  } [[TMP0]]
+//
+vint32m1x2_t test_vluxseg2ei32_v_tuple_i32m1_m(vbool32_t mask, const int32_t *base, vuint32m1_t bindex, size_t vl) {
+  return __riscv_vluxseg2ei32_v_tuple_i32m1_m(mask, base, bindex, vl);
+}
Index: clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei32_tuple.c
===
--- /dev/null
+++ clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei32_tuple.c
@@ -0,0 +1,28 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
+// REQUIRES: riscv-registered-target
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \
+// RUN:   -target-feature +experimental-zvfh -disable-O0-optnone  \
+// RUN:   -emit-llvm %s -o - | opt -S -passes=mem2reg | \
+// RUN:   FileCheck --check-prefix=CHECK-RV64 %s
+
+#include 
+
+// CHECK-RV64-LABEL: define dso_local { ,  } @test_vloxseg2ei32_v_tuple_i32m1
+// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]],  [[BINDEX:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call { ,  } @llvm.riscv.vloxseg2.nxv2i32.nxv2i32.i64( poison,  poison, ptr [[BASE]],  [[BINDEX]], i64 [[VL]])
+// CHECK-RV64-NEXT:ret { ,  } [[TMP0]]
+//
+vint32m1x2_t test_vloxseg2ei32_v_tuple_i32m1(const int32_t *base, vuint32m1_t bindex, size_t vl) {
+  return __riscv_vloxseg2ei32_v_tuple_i32m1(base, bindex, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local { ,  } @test_vloxseg2ei32_v_tuple_i32m1_m
+// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]],  [[BINDEX:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call { ,  } @llvm.riscv.vloxseg2.mask.nxv2i32.nxv2i32.i64( poison,  poison, ptr [[BASE]],  [[BINDEX]],  [[MASK]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT:ret { ,  } [[TMP0]]
+//
+vint32m1x2_t test_vloxseg2ei32_v_tuple_i32m1_m(vbool32_t mask, const int32_t *base, vuint32m1_t bindex, size_t vl) {
+  return __riscv_vloxseg2ei32_v_tuple_i32m1_m(mask, base, bindex, vl);
+}
Index: clang/include/clang/Basic/riscv_vector.td
===
--- clang/include/clang/Basic/riscv_vector.td
+++ clang/include/clang/Basic/riscv_vector.td
@@ -1744,6 +1744,57 @@
   }
 }
 
+multiclass RVVIndexedSegLoadTuple {
+  foreach type = ["i"] in {
+foreach eew_info = [["32", "(Log2EEW:5)"]] in {
+  defvar eew = eew_info[0];
+  defvar eew_type = eew_info[1];
+  for

[PATCH] D147914: [8/11][POC][Clang][RISCV] Define tuple type variant of vloxseg2ei32 vluxseg2ei32

2023-05-19 Thread Yueh-Ting (eop) Chen via Phabricator via cfe-commits 
eopXD updated this revision to Diff 523852.
eopXD added a comment.

Rebase.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D147914/new/

https://reviews.llvm.org/D147914

Files:
  clang/include/clang/Basic/riscv_vector.td
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei32_tuple.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei32_tuple.c

Index: clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei32_tuple.c
===
--- /dev/null
+++ clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei32_tuple.c
@@ -0,0 +1,28 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
+// REQUIRES: riscv-registered-target
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \
+// RUN:   -target-feature +experimental-zvfh -disable-O0-optnone  \
+// RUN:   -emit-llvm %s -o - | opt -S -passes=mem2reg | \
+// RUN:   FileCheck --check-prefix=CHECK-RV64 %s
+
+#include 
+
+// CHECK-RV64-LABEL: define dso_local { ,  } @test_vluxseg2ei32_v_tuple_i32m1
+// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]],  [[BINDEX:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call { ,  } @llvm.riscv.vluxseg2.nxv2i32.nxv2i32.i64( poison,  poison, ptr [[BASE]],  [[BINDEX]], i64 [[VL]])
+// CHECK-RV64-NEXT:ret { ,  } [[TMP0]]
+//
+vint32m1x2_t test_vluxseg2ei32_v_tuple_i32m1(const int32_t *base, vuint32m1_t bindex, size_t vl) {
+  return __riscv_vluxseg2ei32_v_tuple_i32m1(base, bindex, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local { ,  } @test_vluxseg2ei32_v_tuple_i32m1_m
+// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]],  [[BINDEX:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call { ,  } @llvm.riscv.vluxseg2.mask.nxv2i32.nxv2i32.i64( poison,  poison, ptr [[BASE]],  [[BINDEX]],  [[MASK]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT:ret { ,  } [[TMP0]]
+//
+vint32m1x2_t test_vluxseg2ei32_v_tuple_i32m1_m(vbool32_t mask, const int32_t *base, vuint32m1_t bindex, size_t vl) {
+  return __riscv_vluxseg2ei32_v_tuple_i32m1_m(mask, base, bindex, vl);
+}
Index: clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei32_tuple.c
===
--- /dev/null
+++ clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei32_tuple.c
@@ -0,0 +1,28 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
+// REQUIRES: riscv-registered-target
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \
+// RUN:   -target-feature +experimental-zvfh -disable-O0-optnone  \
+// RUN:   -emit-llvm %s -o - | opt -S -passes=mem2reg | \
+// RUN:   FileCheck --check-prefix=CHECK-RV64 %s
+
+#include 
+
+// CHECK-RV64-LABEL: define dso_local { ,  } @test_vloxseg2ei32_v_tuple_i32m1
+// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]],  [[BINDEX:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call { ,  } @llvm.riscv.vloxseg2.nxv2i32.nxv2i32.i64( poison,  poison, ptr [[BASE]],  [[BINDEX]], i64 [[VL]])
+// CHECK-RV64-NEXT:ret { ,  } [[TMP0]]
+//
+vint32m1x2_t test_vloxseg2ei32_v_tuple_i32m1(const int32_t *base, vuint32m1_t bindex, size_t vl) {
+  return __riscv_vloxseg2ei32_v_tuple_i32m1(base, bindex, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local { ,  } @test_vloxseg2ei32_v_tuple_i32m1_m
+// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]],  [[BINDEX:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call { ,  } @llvm.riscv.vloxseg2.mask.nxv2i32.nxv2i32.i64( poison,  poison, ptr [[BASE]],  [[BINDEX]],  [[MASK]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT:ret { ,  } [[TMP0]]
+//
+vint32m1x2_t test_vloxseg2ei32_v_tuple_i32m1_m(vbool32_t mask, const int32_t *base, vuint32m1_t bindex, size_t vl) {
+  return __riscv_vloxseg2ei32_v_tuple_i32m1_m(mask, base, bindex, vl);
+}
Index: clang/include/clang/Basic/riscv_vector.td
===
--- clang/include/clang/Basic/riscv_vector.td
+++ clang/include/clang/Basic/riscv_vector.td
@@ -1744,6 +1744,57 @@
   }
 }
 
+multiclass RVVIndexedSegLoadTuple {
+  foreach type = ["i"] in {
+foreach eew_info = [["32", "(Log2EEW:5)"]] in {
+  defvar eew = eew_info[0];
+  defvar eew_type = eew_info[1];
+  foreach nf = [2] in {
+let Name = op # nf # "ei" # eew # "_v_tuple",
+OverloadedName = op # nf # "ei" # eew # "_tuple",
+IRName = op # nf,
+MaskedIR

[PATCH] D147914: [8/11][POC][Clang][RISCV] Define tuple type variant of vloxseg2ei32 vluxseg2ei32

2023-05-18 Thread Craig Topper via Phabricator via cfe-commits 
craig.topper accepted this revision.
craig.topper added a comment.
This revision is now accepted and ready to land.

LGTM


Repository:
  rG LLVM Github Monorepo

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[PATCH] D147914: [8/11][POC][Clang][RISCV] Define tuple type variant of vloxseg2ei32 vluxseg2ei32

2023-05-18 Thread Yueh-Ting (eop) Chen via Phabricator via cfe-commits 
eopXD updated this revision to Diff 523625.
eopXD added a comment.

Removed another variable that is too verbose.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D147914/new/

https://reviews.llvm.org/D147914

Files:
  clang/include/clang/Basic/riscv_vector.td
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei32_tuple.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei32_tuple.c

Index: clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei32_tuple.c
===
--- /dev/null
+++ clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei32_tuple.c
@@ -0,0 +1,28 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
+// REQUIRES: riscv-registered-target
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \
+// RUN:   -target-feature +experimental-zvfh -disable-O0-optnone  \
+// RUN:   -emit-llvm %s -o - | opt -S -passes=mem2reg | \
+// RUN:   FileCheck --check-prefix=CHECK-RV64 %s
+
+#include 
+
+// CHECK-RV64-LABEL: define dso_local { ,  } @test_vluxseg2ei32_v_tuple_i32m1
+// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]],  [[BINDEX:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call { ,  } @llvm.riscv.vluxseg2.nxv2i32.nxv2i32.i64( poison,  poison, ptr [[BASE]],  [[BINDEX]], i64 [[VL]])
+// CHECK-RV64-NEXT:ret { ,  } [[TMP0]]
+//
+vint32m1x2_t test_vluxseg2ei32_v_tuple_i32m1(const int32_t *base, vuint32m1_t bindex, size_t vl) {
+  return __riscv_vluxseg2ei32_v_tuple_i32m1(base, bindex, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local { ,  } @test_vluxseg2ei32_v_tuple_i32m1_m
+// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]],  [[BINDEX:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call { ,  } @llvm.riscv.vluxseg2.mask.nxv2i32.nxv2i32.i64( poison,  poison, ptr [[BASE]],  [[BINDEX]],  [[MASK]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT:ret { ,  } [[TMP0]]
+//
+vint32m1x2_t test_vluxseg2ei32_v_tuple_i32m1_m(vbool32_t mask, const int32_t *base, vuint32m1_t bindex, size_t vl) {
+  return __riscv_vluxseg2ei32_v_tuple_i32m1_m(mask, base, bindex, vl);
+}
Index: clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei32_tuple.c
===
--- /dev/null
+++ clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei32_tuple.c
@@ -0,0 +1,28 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
+// REQUIRES: riscv-registered-target
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \
+// RUN:   -target-feature +experimental-zvfh -disable-O0-optnone  \
+// RUN:   -emit-llvm %s -o - | opt -S -passes=mem2reg | \
+// RUN:   FileCheck --check-prefix=CHECK-RV64 %s
+
+#include 
+
+// CHECK-RV64-LABEL: define dso_local { ,  } @test_vloxseg2ei32_v_tuple_i32m1
+// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]],  [[BINDEX:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call { ,  } @llvm.riscv.vloxseg2.nxv2i32.nxv2i32.i64( poison,  poison, ptr [[BASE]],  [[BINDEX]], i64 [[VL]])
+// CHECK-RV64-NEXT:ret { ,  } [[TMP0]]
+//
+vint32m1x2_t test_vloxseg2ei32_v_tuple_i32m1(const int32_t *base, vuint32m1_t bindex, size_t vl) {
+  return __riscv_vloxseg2ei32_v_tuple_i32m1(base, bindex, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local { ,  } @test_vloxseg2ei32_v_tuple_i32m1_m
+// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]],  [[BINDEX:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call { ,  } @llvm.riscv.vloxseg2.mask.nxv2i32.nxv2i32.i64( poison,  poison, ptr [[BASE]],  [[BINDEX]],  [[MASK]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT:ret { ,  } [[TMP0]]
+//
+vint32m1x2_t test_vloxseg2ei32_v_tuple_i32m1_m(vbool32_t mask, const int32_t *base, vuint32m1_t bindex, size_t vl) {
+  return __riscv_vloxseg2ei32_v_tuple_i32m1_m(mask, base, bindex, vl);
+}
Index: clang/include/clang/Basic/riscv_vector.td
===
--- clang/include/clang/Basic/riscv_vector.td
+++ clang/include/clang/Basic/riscv_vector.td
@@ -1773,6 +1773,57 @@
   }
 }
 
+multiclass RVVIndexedSegLoadTuple {
+  foreach type = ["i"] in {
+foreach eew_info = [["32", "(Log2EEW:5)"]] in {
+  defvar eew = eew_info[0];
+  defvar eew_type = eew_info[1];
+  foreach nf = [2] in {
+let Name = op # nf # "ei" # eew # "_v_tuple",
+OverloadedName = op # nf # "ei" # eew # "_tuple",
+I

[PATCH] D147914: [8/11][POC][Clang][RISCV] Define tuple type variant of vloxseg2ei32 vluxseg2ei32

2023-05-18 Thread Yueh-Ting (eop) Chen via Phabricator via cfe-commits 
eopXD updated this revision to Diff 523503.
eopXD added a comment.

Reduce variables declared but only used once.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D147914/new/

https://reviews.llvm.org/D147914

Files:
  clang/include/clang/Basic/riscv_vector.td
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei32_tuple.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei32_tuple.c

Index: clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei32_tuple.c
===
--- /dev/null
+++ clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei32_tuple.c
@@ -0,0 +1,28 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
+// REQUIRES: riscv-registered-target
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \
+// RUN:   -target-feature +experimental-zvfh -disable-O0-optnone  \
+// RUN:   -emit-llvm %s -o - | opt -S -passes=mem2reg | \
+// RUN:   FileCheck --check-prefix=CHECK-RV64 %s
+
+#include 
+
+// CHECK-RV64-LABEL: define dso_local { ,  } @test_vluxseg2ei32_v_tuple_i32m1
+// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]],  [[BINDEX:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call { ,  } @llvm.riscv.vluxseg2.nxv2i32.nxv2i32.i64( poison,  poison, ptr [[BASE]],  [[BINDEX]], i64 [[VL]])
+// CHECK-RV64-NEXT:ret { ,  } [[TMP0]]
+//
+vint32m1x2_t test_vluxseg2ei32_v_tuple_i32m1(const int32_t *base, vuint32m1_t bindex, size_t vl) {
+  return __riscv_vluxseg2ei32_v_tuple_i32m1(base, bindex, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local { ,  } @test_vluxseg2ei32_v_tuple_i32m1_m
+// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]],  [[BINDEX:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call { ,  } @llvm.riscv.vluxseg2.mask.nxv2i32.nxv2i32.i64( poison,  poison, ptr [[BASE]],  [[BINDEX]],  [[MASK]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT:ret { ,  } [[TMP0]]
+//
+vint32m1x2_t test_vluxseg2ei32_v_tuple_i32m1_m(vbool32_t mask, const int32_t *base, vuint32m1_t bindex, size_t vl) {
+  return __riscv_vluxseg2ei32_v_tuple_i32m1_m(mask, base, bindex, vl);
+}
Index: clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei32_tuple.c
===
--- /dev/null
+++ clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei32_tuple.c
@@ -0,0 +1,28 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
+// REQUIRES: riscv-registered-target
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \
+// RUN:   -target-feature +experimental-zvfh -disable-O0-optnone  \
+// RUN:   -emit-llvm %s -o - | opt -S -passes=mem2reg | \
+// RUN:   FileCheck --check-prefix=CHECK-RV64 %s
+
+#include 
+
+// CHECK-RV64-LABEL: define dso_local { ,  } @test_vloxseg2ei32_v_tuple_i32m1
+// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]],  [[BINDEX:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call { ,  } @llvm.riscv.vloxseg2.nxv2i32.nxv2i32.i64( poison,  poison, ptr [[BASE]],  [[BINDEX]], i64 [[VL]])
+// CHECK-RV64-NEXT:ret { ,  } [[TMP0]]
+//
+vint32m1x2_t test_vloxseg2ei32_v_tuple_i32m1(const int32_t *base, vuint32m1_t bindex, size_t vl) {
+  return __riscv_vloxseg2ei32_v_tuple_i32m1(base, bindex, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local { ,  } @test_vloxseg2ei32_v_tuple_i32m1_m
+// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]],  [[BINDEX:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call { ,  } @llvm.riscv.vloxseg2.mask.nxv2i32.nxv2i32.i64( poison,  poison, ptr [[BASE]],  [[BINDEX]],  [[MASK]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT:ret { ,  } [[TMP0]]
+//
+vint32m1x2_t test_vloxseg2ei32_v_tuple_i32m1_m(vbool32_t mask, const int32_t *base, vuint32m1_t bindex, size_t vl) {
+  return __riscv_vloxseg2ei32_v_tuple_i32m1_m(mask, base, bindex, vl);
+}
Index: clang/include/clang/Basic/riscv_vector.td
===
--- clang/include/clang/Basic/riscv_vector.td
+++ clang/include/clang/Basic/riscv_vector.td
@@ -1773,6 +1773,59 @@
   }
 }
 
+multiclass RVVIndexedSegLoadTuple {
+  foreach type = ["i"] in {
+foreach eew_info = [["32", "(Log2EEW:5)"]] in {
+  defvar eew = eew_info[0];
+  defvar eew_type = eew_info[1];
+  foreach nf = [2] in {
+let Name = op # nf # "ei" # eew # "_v_tuple",
+OverloadedName = op # nf # "ei" # eew # "_tuple",
+I

[PATCH] D147914: [8/11][POC][Clang][RISCV] Define tuple type variant of vloxseg2ei32 vluxseg2ei32

2023-05-17 Thread Yueh-Ting (eop) Chen via Phabricator via cfe-commits 
eopXD updated this revision to Diff 522934.
eopXD added a comment.

Rebase.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D147914/new/

https://reviews.llvm.org/D147914

Files:
  clang/include/clang/Basic/riscv_vector.td
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei32_tuple.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei32_tuple.c

Index: clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei32_tuple.c
===
--- /dev/null
+++ clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei32_tuple.c
@@ -0,0 +1,28 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
+// REQUIRES: riscv-registered-target
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \
+// RUN:   -target-feature +experimental-zvfh -disable-O0-optnone  \
+// RUN:   -emit-llvm %s -o - | opt -S -passes=mem2reg | \
+// RUN:   FileCheck --check-prefix=CHECK-RV64 %s
+
+#include 
+
+// CHECK-RV64-LABEL: define dso_local { ,  } @test_vluxseg2ei32_v_tuple_i32m1
+// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]],  [[BINDEX:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call { ,  } @llvm.riscv.vluxseg2.nxv2i32.nxv2i32.i64( poison,  poison, ptr [[BASE]],  [[BINDEX]], i64 [[VL]])
+// CHECK-RV64-NEXT:ret { ,  } [[TMP0]]
+//
+vint32m1x2_t test_vluxseg2ei32_v_tuple_i32m1(const int32_t *base, vuint32m1_t bindex, size_t vl) {
+  return __riscv_vluxseg2ei32_v_tuple_i32m1(base, bindex, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local { ,  } @test_vluxseg2ei32_v_tuple_i32m1_m
+// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]],  [[BINDEX:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call { ,  } @llvm.riscv.vluxseg2.mask.nxv2i32.nxv2i32.i64( poison,  poison, ptr [[BASE]],  [[BINDEX]],  [[MASK]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT:ret { ,  } [[TMP0]]
+//
+vint32m1x2_t test_vluxseg2ei32_v_tuple_i32m1_m(vbool32_t mask, const int32_t *base, vuint32m1_t bindex, size_t vl) {
+  return __riscv_vluxseg2ei32_v_tuple_i32m1_m(mask, base, bindex, vl);
+}
Index: clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei32_tuple.c
===
--- /dev/null
+++ clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei32_tuple.c
@@ -0,0 +1,28 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
+// REQUIRES: riscv-registered-target
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \
+// RUN:   -target-feature +experimental-zvfh -disable-O0-optnone  \
+// RUN:   -emit-llvm %s -o - | opt -S -passes=mem2reg | \
+// RUN:   FileCheck --check-prefix=CHECK-RV64 %s
+
+#include 
+
+// CHECK-RV64-LABEL: define dso_local { ,  } @test_vloxseg2ei32_v_tuple_i32m1
+// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]],  [[BINDEX:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call { ,  } @llvm.riscv.vloxseg2.nxv2i32.nxv2i32.i64( poison,  poison, ptr [[BASE]],  [[BINDEX]], i64 [[VL]])
+// CHECK-RV64-NEXT:ret { ,  } [[TMP0]]
+//
+vint32m1x2_t test_vloxseg2ei32_v_tuple_i32m1(const int32_t *base, vuint32m1_t bindex, size_t vl) {
+  return __riscv_vloxseg2ei32_v_tuple_i32m1(base, bindex, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local { ,  } @test_vloxseg2ei32_v_tuple_i32m1_m
+// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]],  [[BINDEX:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call { ,  } @llvm.riscv.vloxseg2.mask.nxv2i32.nxv2i32.i64( poison,  poison, ptr [[BASE]],  [[BINDEX]],  [[MASK]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT:ret { ,  } [[TMP0]]
+//
+vint32m1x2_t test_vloxseg2ei32_v_tuple_i32m1_m(vbool32_t mask, const int32_t *base, vuint32m1_t bindex, size_t vl) {
+  return __riscv_vloxseg2ei32_v_tuple_i32m1_m(mask, base, bindex, vl);
+}
Index: clang/include/clang/Basic/riscv_vector.td
===
--- clang/include/clang/Basic/riscv_vector.td
+++ clang/include/clang/Basic/riscv_vector.td
@@ -1773,6 +1773,63 @@
   }
 }
 
+multiclass RVVIndexedSegLoadTuple {
+  foreach type = ["i"] in {
+foreach eew_info = [["32", "(Log2EEW:5)"]] in {
+  defvar eew = eew_info[0];
+  defvar eew_type = eew_info[1];
+  foreach nf = [2] in {
+let Name = op # nf # "ei" # eew # "_v_tuple",
+OverloadedName = op # nf # "ei" # eew # "_tuple",
+IRName = op # nf,
+MaskedIR

[PATCH] D147914: [8/11][POC][Clang][RISCV] Define tuple type variant of vloxseg2ei32 vluxseg2ei32

2023-04-24 Thread Yueh-Ting (eop) Chen via Phabricator via cfe-commits 
eopXD updated this revision to Diff 516306.
eopXD marked an inline comment as done.
eopXD added a comment.

Address comments from Craig.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D147914/new/

https://reviews.llvm.org/D147914

Files:
  clang/include/clang/Basic/riscv_vector.td
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei32_tuple.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei32_tuple.c

Index: clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei32_tuple.c
===
--- /dev/null
+++ clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vluxseg2ei32_tuple.c
@@ -0,0 +1,28 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
+// REQUIRES: riscv-registered-target
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \
+// RUN:   -target-feature +experimental-zvfh -disable-O0-optnone  \
+// RUN:   -emit-llvm %s -o - | opt -S -passes=mem2reg | \
+// RUN:   FileCheck --check-prefix=CHECK-RV64 %s
+
+#include 
+
+// CHECK-RV64-LABEL: define dso_local { ,  } @test_vluxseg2ei32_v_tuple_i32m1
+// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]],  [[BINDEX:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call { ,  } @llvm.riscv.vluxseg2.nxv2i32.nxv2i32.i64( poison,  poison, ptr [[BASE]],  [[BINDEX]], i64 [[VL]])
+// CHECK-RV64-NEXT:ret { ,  } [[TMP0]]
+//
+vint32m1x2_t test_vluxseg2ei32_v_tuple_i32m1(const int32_t *base, vuint32m1_t bindex, size_t vl) {
+  return __riscv_vluxseg2ei32_v_tuple_i32m1(base, bindex, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local { ,  } @test_vluxseg2ei32_v_tuple_i32m1_m
+// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]],  [[BINDEX:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call { ,  } @llvm.riscv.vluxseg2.mask.nxv2i32.nxv2i32.i64( poison,  poison, ptr [[BASE]],  [[BINDEX]],  [[MASK]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT:ret { ,  } [[TMP0]]
+//
+vint32m1x2_t test_vluxseg2ei32_v_tuple_i32m1_m(vbool32_t mask, const int32_t *base, vuint32m1_t bindex, size_t vl) {
+  return __riscv_vluxseg2ei32_v_tuple_i32m1_m(mask, base, bindex, vl);
+}
Index: clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei32_tuple.c
===
--- /dev/null
+++ clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vloxseg2ei32_tuple.c
@@ -0,0 +1,28 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
+// REQUIRES: riscv-registered-target
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \
+// RUN:   -target-feature +experimental-zvfh -disable-O0-optnone  \
+// RUN:   -emit-llvm %s -o - | opt -S -passes=mem2reg | \
+// RUN:   FileCheck --check-prefix=CHECK-RV64 %s
+
+#include 
+
+// CHECK-RV64-LABEL: define dso_local { ,  } @test_vloxseg2ei32_v_tuple_i32m1
+// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]],  [[BINDEX:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call { ,  } @llvm.riscv.vloxseg2.nxv2i32.nxv2i32.i64( poison,  poison, ptr [[BASE]],  [[BINDEX]], i64 [[VL]])
+// CHECK-RV64-NEXT:ret { ,  } [[TMP0]]
+//
+vint32m1x2_t test_vloxseg2ei32_v_tuple_i32m1(const int32_t *base, vuint32m1_t bindex, size_t vl) {
+  return __riscv_vloxseg2ei32_v_tuple_i32m1(base, bindex, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local { ,  } @test_vloxseg2ei32_v_tuple_i32m1_m
+// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]],  [[BINDEX:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = call { ,  } @llvm.riscv.vloxseg2.mask.nxv2i32.nxv2i32.i64( poison,  poison, ptr [[BASE]],  [[BINDEX]],  [[MASK]], i64 [[VL]], i64 3)
+// CHECK-RV64-NEXT:ret { ,  } [[TMP0]]
+//
+vint32m1x2_t test_vloxseg2ei32_v_tuple_i32m1_m(vbool32_t mask, const int32_t *base, vuint32m1_t bindex, size_t vl) {
+  return __riscv_vloxseg2ei32_v_tuple_i32m1_m(mask, base, bindex, vl);
+}
Index: clang/include/clang/Basic/riscv_vector.td
===
--- clang/include/clang/Basic/riscv_vector.td
+++ clang/include/clang/Basic/riscv_vector.td
@@ -1997,6 +1997,63 @@
   }
 }
 
+multiclass RVVIndexedSegLoadTuple {
+  foreach type = ["i"] in {
+foreach eew_info = [["32", "(Log2EEW:5)"]] in {
+  defvar eew = eew_info[0];
+  defvar eew_type = eew_info[1];
+  foreach nf = [2] in {
+let Name = op # nf # "ei" # eew # "_v_tuple",
+OverloadedName = op # nf # "ei" # eew # "

[PATCH] D147914: [8/11][POC][Clang][RISCV] Define tuple type variant of vloxseg2ei32 vluxseg2ei32

2023-04-18 Thread Craig Topper via Phabricator via cfe-commits 
craig.topper added inline comments.



Comment at: clang/include/clang/Basic/riscv_vector.td:2014
+
+  llvm::Value *MaskOperand = IsMasked ? Ops[0] : nullptr;
+  llvm::Value *PtrOperand = IsMasked ? Ops[1] : Ops[0];

Same comment as last review


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D147914/new/

https://reviews.llvm.org/D147914

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