[PATCH] D147915: [9/11][POC][Clang][RISCV] Define tuple type variant of vsoxseg2ei32 vsuxseg2ei32

2023-05-22 Thread Yueh-Ting (eop) Chen via Phabricator via cfe-commits 
This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG5eb1b1fc1f88: [9/11][POC][Clang][RISCV] Define tuple type 
variant of vsoxseg2ei32 vsuxseg2ei32 (authored by eopXD).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D147915/new/

https://reviews.llvm.org/D147915

Files:
  clang/include/clang/Basic/riscv_vector.td
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei32_tuple.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei32_tuple.c

Index: clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei32_tuple.c
===
--- /dev/null
+++ clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei32_tuple.c
@@ -0,0 +1,36 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
+// REQUIRES: riscv-registered-target
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \
+// RUN:   -target-feature +experimental-zvfh -disable-O0-optnone  \
+// RUN:   -emit-llvm %s -o - | opt -S -passes=mem2reg | \
+// RUN:   FileCheck --check-prefix=CHECK-RV64 %s
+
+#include 
+
+// CHECK-RV64-LABEL: define dso_local void @test_vsuxseg2ei32_v_tuple_i32m1
+// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]],  [[BINDEX:%.*]],  [[V_TUPLE_COERCE0:%.*]],  [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = insertvalue { ,  } poison,  [[V_TUPLE_COERCE0]], 0
+// CHECK-RV64-NEXT:[[TMP1:%.*]] = insertvalue { ,  } [[TMP0]],  [[V_TUPLE_COERCE1]], 1
+// CHECK-RV64-NEXT:[[TMP2:%.*]] = extractvalue { ,  } [[TMP1]], 0
+// CHECK-RV64-NEXT:[[TMP3:%.*]] = extractvalue { ,  } [[TMP1]], 1
+// CHECK-RV64-NEXT:call void @llvm.riscv.vsuxseg2.nxv2i32.nxv2i32.i64( [[TMP2]],  [[TMP3]], ptr [[BASE]],  [[BINDEX]], i64 [[VL]])
+// CHECK-RV64-NEXT:ret void
+//
+void test_vsuxseg2ei32_v_tuple_i32m1(int32_t *base, vuint32m1_t bindex, vint32m1x2_t v_tuple, size_t vl) {
+  return __riscv_vsuxseg2ei32_v_tuple_i32m1(base, bindex, v_tuple, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local void @test_vsuxseg2ei32_v_tuple_i32m1_m
+// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]],  [[BINDEX:%.*]],  [[V_TUPLE_COERCE0:%.*]],  [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = insertvalue { ,  } poison,  [[V_TUPLE_COERCE0]], 0
+// CHECK-RV64-NEXT:[[TMP1:%.*]] = insertvalue { ,  } [[TMP0]],  [[V_TUPLE_COERCE1]], 1
+// CHECK-RV64-NEXT:[[TMP2:%.*]] = extractvalue { ,  } [[TMP1]], 0
+// CHECK-RV64-NEXT:[[TMP3:%.*]] = extractvalue { ,  } [[TMP1]], 1
+// CHECK-RV64-NEXT:call void @llvm.riscv.vsuxseg2.mask.nxv2i32.nxv2i32.i64( [[TMP2]],  [[TMP3]], ptr [[BASE]],  [[BINDEX]],  [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT:ret void
+//
+void test_vsuxseg2ei32_v_tuple_i32m1_m(vbool32_t mask, int32_t *base, vuint32m1_t bindex, vint32m1x2_t v_tuple, size_t vl) {
+  return __riscv_vsuxseg2ei32_v_tuple_i32m1_m(mask, base, bindex, v_tuple, vl);
+}
Index: clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei32_tuple.c
===
--- /dev/null
+++ clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei32_tuple.c
@@ -0,0 +1,36 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
+// REQUIRES: riscv-registered-target
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \
+// RUN:   -target-feature +experimental-zvfh -disable-O0-optnone  \
+// RUN:   -emit-llvm %s -o - | opt -S -passes=mem2reg | \
+// RUN:   FileCheck --check-prefix=CHECK-RV64 %s
+
+#include 
+
+// CHECK-RV64-LABEL: define dso_local void @test_vsoxseg2ei32_v_tuple_i32m1
+// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]],  [[BINDEX:%.*]],  [[V_TUPLE_COERCE0:%.*]],  [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = insertvalue { ,  } poison,  [[V_TUPLE_COERCE0]], 0
+// CHECK-RV64-NEXT:[[TMP1:%.*]] = insertvalue { ,  } [[TMP0]],  [[V_TUPLE_COERCE1]], 1
+// CHECK-RV64-NEXT:[[TMP2:%.*]] = extractvalue { ,  } [[TMP1]], 0
+// CHECK-RV64-NEXT:[[TMP3:%.*]] = extractvalue { ,  } [[TMP1]], 1
+// CHECK-RV64-NEXT:call void @llvm.riscv.vsoxseg2.nxv2i32.nxv2i32.i64( [[TMP2]],  [[TMP3]], ptr [[BASE]],  [[BINDEX]], i64 [[VL]])
+// CHECK-RV64-NEXT:ret void
+//
+void test_vsoxseg2ei32_v_tuple_i32m1(int32_t *base, vuint32m1_t bindex, vint32m1x2_t v_tuple, size_t vl) {
+  return __riscv_vsoxseg2ei32_v_tuple_i32m1(base, bindex, v_tuple

[PATCH] D147915: [9/11][POC][Clang][RISCV] Define tuple type variant of vsoxseg2ei32 vsuxseg2ei32

2023-05-19 Thread Yueh-Ting (eop) Chen via Phabricator via cfe-commits 
eopXD updated this revision to Diff 523853.
eopXD added a comment.

Rebase.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D147915/new/

https://reviews.llvm.org/D147915

Files:
  clang/include/clang/Basic/riscv_vector.td
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei32_tuple.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei32_tuple.c

Index: clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei32_tuple.c
===
--- /dev/null
+++ clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei32_tuple.c
@@ -0,0 +1,36 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
+// REQUIRES: riscv-registered-target
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \
+// RUN:   -target-feature +experimental-zvfh -disable-O0-optnone  \
+// RUN:   -emit-llvm %s -o - | opt -S -passes=mem2reg | \
+// RUN:   FileCheck --check-prefix=CHECK-RV64 %s
+
+#include 
+
+// CHECK-RV64-LABEL: define dso_local void @test_vsuxseg2ei32_v_tuple_i32m1
+// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]],  [[BINDEX:%.*]],  [[V_TUPLE_COERCE0:%.*]],  [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = insertvalue { ,  } poison,  [[V_TUPLE_COERCE0]], 0
+// CHECK-RV64-NEXT:[[TMP1:%.*]] = insertvalue { ,  } [[TMP0]],  [[V_TUPLE_COERCE1]], 1
+// CHECK-RV64-NEXT:[[TMP2:%.*]] = extractvalue { ,  } [[TMP1]], 0
+// CHECK-RV64-NEXT:[[TMP3:%.*]] = extractvalue { ,  } [[TMP1]], 1
+// CHECK-RV64-NEXT:call void @llvm.riscv.vsuxseg2.nxv2i32.nxv2i32.i64( [[TMP2]],  [[TMP3]], ptr [[BASE]],  [[BINDEX]], i64 [[VL]])
+// CHECK-RV64-NEXT:ret void
+//
+void test_vsuxseg2ei32_v_tuple_i32m1(int32_t *base, vuint32m1_t bindex, vint32m1x2_t v_tuple, size_t vl) {
+  return __riscv_vsuxseg2ei32_v_tuple_i32m1(base, bindex, v_tuple, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local void @test_vsuxseg2ei32_v_tuple_i32m1_m
+// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]],  [[BINDEX:%.*]],  [[V_TUPLE_COERCE0:%.*]],  [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = insertvalue { ,  } poison,  [[V_TUPLE_COERCE0]], 0
+// CHECK-RV64-NEXT:[[TMP1:%.*]] = insertvalue { ,  } [[TMP0]],  [[V_TUPLE_COERCE1]], 1
+// CHECK-RV64-NEXT:[[TMP2:%.*]] = extractvalue { ,  } [[TMP1]], 0
+// CHECK-RV64-NEXT:[[TMP3:%.*]] = extractvalue { ,  } [[TMP1]], 1
+// CHECK-RV64-NEXT:call void @llvm.riscv.vsuxseg2.mask.nxv2i32.nxv2i32.i64( [[TMP2]],  [[TMP3]], ptr [[BASE]],  [[BINDEX]],  [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT:ret void
+//
+void test_vsuxseg2ei32_v_tuple_i32m1_m(vbool32_t mask, int32_t *base, vuint32m1_t bindex, vint32m1x2_t v_tuple, size_t vl) {
+  return __riscv_vsuxseg2ei32_v_tuple_i32m1_m(mask, base, bindex, v_tuple, vl);
+}
Index: clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei32_tuple.c
===
--- /dev/null
+++ clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei32_tuple.c
@@ -0,0 +1,36 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
+// REQUIRES: riscv-registered-target
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \
+// RUN:   -target-feature +experimental-zvfh -disable-O0-optnone  \
+// RUN:   -emit-llvm %s -o - | opt -S -passes=mem2reg | \
+// RUN:   FileCheck --check-prefix=CHECK-RV64 %s
+
+#include 
+
+// CHECK-RV64-LABEL: define dso_local void @test_vsoxseg2ei32_v_tuple_i32m1
+// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]],  [[BINDEX:%.*]],  [[V_TUPLE_COERCE0:%.*]],  [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = insertvalue { ,  } poison,  [[V_TUPLE_COERCE0]], 0
+// CHECK-RV64-NEXT:[[TMP1:%.*]] = insertvalue { ,  } [[TMP0]],  [[V_TUPLE_COERCE1]], 1
+// CHECK-RV64-NEXT:[[TMP2:%.*]] = extractvalue { ,  } [[TMP1]], 0
+// CHECK-RV64-NEXT:[[TMP3:%.*]] = extractvalue { ,  } [[TMP1]], 1
+// CHECK-RV64-NEXT:call void @llvm.riscv.vsoxseg2.nxv2i32.nxv2i32.i64( [[TMP2]],  [[TMP3]], ptr [[BASE]],  [[BINDEX]], i64 [[VL]])
+// CHECK-RV64-NEXT:ret void
+//
+void test_vsoxseg2ei32_v_tuple_i32m1(int32_t *base, vuint32m1_t bindex, vint32m1x2_t v_tuple, size_t vl) {
+  return __riscv_vsoxseg2ei32_v_tuple_i32m1(base, bindex, v_tuple, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local void @test_vsoxseg2ei32_v_tuple_i32m1_m
+// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]],  [[BINDEX:%.*]],  [[V_TUPLE_COERCE0

[PATCH] D147915: [9/11][POC][Clang][RISCV] Define tuple type variant of vsoxseg2ei32 vsuxseg2ei32

2023-05-18 Thread Craig Topper via Phabricator via cfe-commits 
craig.topper accepted this revision.
craig.topper added a comment.
This revision is now accepted and ready to land.

LGTM


Repository:
  rG LLVM Github Monorepo

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[PATCH] D147915: [9/11][POC][Clang][RISCV] Define tuple type variant of vsoxseg2ei32 vsuxseg2ei32

2023-05-18 Thread Yueh-Ting (eop) Chen via Phabricator via cfe-commits 
eopXD updated this revision to Diff 523626.
eopXD added a comment.

Removed another variable that is too verbose.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D147915/new/

https://reviews.llvm.org/D147915

Files:
  clang/include/clang/Basic/riscv_vector.td
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei32_tuple.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei32_tuple.c

Index: clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei32_tuple.c
===
--- /dev/null
+++ clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei32_tuple.c
@@ -0,0 +1,36 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
+// REQUIRES: riscv-registered-target
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \
+// RUN:   -target-feature +experimental-zvfh -disable-O0-optnone  \
+// RUN:   -emit-llvm %s -o - | opt -S -passes=mem2reg | \
+// RUN:   FileCheck --check-prefix=CHECK-RV64 %s
+
+#include 
+
+// CHECK-RV64-LABEL: define dso_local void @test_vsuxseg2ei32_v_tuple_i32m1
+// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]],  [[BINDEX:%.*]],  [[V_TUPLE_COERCE0:%.*]],  [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = insertvalue { ,  } poison,  [[V_TUPLE_COERCE0]], 0
+// CHECK-RV64-NEXT:[[TMP1:%.*]] = insertvalue { ,  } [[TMP0]],  [[V_TUPLE_COERCE1]], 1
+// CHECK-RV64-NEXT:[[TMP2:%.*]] = extractvalue { ,  } [[TMP1]], 0
+// CHECK-RV64-NEXT:[[TMP3:%.*]] = extractvalue { ,  } [[TMP1]], 1
+// CHECK-RV64-NEXT:call void @llvm.riscv.vsuxseg2.nxv2i32.nxv2i32.i64( [[TMP2]],  [[TMP3]], ptr [[BASE]],  [[BINDEX]], i64 [[VL]])
+// CHECK-RV64-NEXT:ret void
+//
+void test_vsuxseg2ei32_v_tuple_i32m1(int32_t *base, vuint32m1_t bindex, vint32m1x2_t v_tuple, size_t vl) {
+  return __riscv_vsuxseg2ei32_v_tuple_i32m1(base, bindex, v_tuple, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local void @test_vsuxseg2ei32_v_tuple_i32m1_m
+// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]],  [[BINDEX:%.*]],  [[V_TUPLE_COERCE0:%.*]],  [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = insertvalue { ,  } poison,  [[V_TUPLE_COERCE0]], 0
+// CHECK-RV64-NEXT:[[TMP1:%.*]] = insertvalue { ,  } [[TMP0]],  [[V_TUPLE_COERCE1]], 1
+// CHECK-RV64-NEXT:[[TMP2:%.*]] = extractvalue { ,  } [[TMP1]], 0
+// CHECK-RV64-NEXT:[[TMP3:%.*]] = extractvalue { ,  } [[TMP1]], 1
+// CHECK-RV64-NEXT:call void @llvm.riscv.vsuxseg2.mask.nxv2i32.nxv2i32.i64( [[TMP2]],  [[TMP3]], ptr [[BASE]],  [[BINDEX]],  [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT:ret void
+//
+void test_vsuxseg2ei32_v_tuple_i32m1_m(vbool32_t mask, int32_t *base, vuint32m1_t bindex, vint32m1x2_t v_tuple, size_t vl) {
+  return __riscv_vsuxseg2ei32_v_tuple_i32m1_m(mask, base, bindex, v_tuple, vl);
+}
Index: clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei32_tuple.c
===
--- /dev/null
+++ clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei32_tuple.c
@@ -0,0 +1,36 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
+// REQUIRES: riscv-registered-target
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \
+// RUN:   -target-feature +experimental-zvfh -disable-O0-optnone  \
+// RUN:   -emit-llvm %s -o - | opt -S -passes=mem2reg | \
+// RUN:   FileCheck --check-prefix=CHECK-RV64 %s
+
+#include 
+
+// CHECK-RV64-LABEL: define dso_local void @test_vsoxseg2ei32_v_tuple_i32m1
+// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]],  [[BINDEX:%.*]],  [[V_TUPLE_COERCE0:%.*]],  [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = insertvalue { ,  } poison,  [[V_TUPLE_COERCE0]], 0
+// CHECK-RV64-NEXT:[[TMP1:%.*]] = insertvalue { ,  } [[TMP0]],  [[V_TUPLE_COERCE1]], 1
+// CHECK-RV64-NEXT:[[TMP2:%.*]] = extractvalue { ,  } [[TMP1]], 0
+// CHECK-RV64-NEXT:[[TMP3:%.*]] = extractvalue { ,  } [[TMP1]], 1
+// CHECK-RV64-NEXT:call void @llvm.riscv.vsoxseg2.nxv2i32.nxv2i32.i64( [[TMP2]],  [[TMP3]], ptr [[BASE]],  [[BINDEX]], i64 [[VL]])
+// CHECK-RV64-NEXT:ret void
+//
+void test_vsoxseg2ei32_v_tuple_i32m1(int32_t *base, vuint32m1_t bindex, vint32m1x2_t v_tuple, size_t vl) {
+  return __riscv_vsoxseg2ei32_v_tuple_i32m1(base, bindex, v_tuple, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local void @test_vsoxseg2ei32_v_tuple_i32m1_m
+// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]

[PATCH] D147915: [9/11][POC][Clang][RISCV] Define tuple type variant of vsoxseg2ei32 vsuxseg2ei32

2023-05-18 Thread Yueh-Ting (eop) Chen via Phabricator via cfe-commits 
eopXD updated this revision to Diff 523506.
eopXD added a comment.

Reduce variables declared but only used once.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D147915/new/

https://reviews.llvm.org/D147915

Files:
  clang/include/clang/Basic/riscv_vector.td
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei32_tuple.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei32_tuple.c

Index: clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei32_tuple.c
===
--- /dev/null
+++ clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei32_tuple.c
@@ -0,0 +1,36 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
+// REQUIRES: riscv-registered-target
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \
+// RUN:   -target-feature +experimental-zvfh -disable-O0-optnone  \
+// RUN:   -emit-llvm %s -o - | opt -S -passes=mem2reg | \
+// RUN:   FileCheck --check-prefix=CHECK-RV64 %s
+
+#include 
+
+// CHECK-RV64-LABEL: define dso_local void @test_vsuxseg2ei32_v_tuple_i32m1
+// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]],  [[BINDEX:%.*]],  [[V_TUPLE_COERCE0:%.*]],  [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = insertvalue { ,  } poison,  [[V_TUPLE_COERCE0]], 0
+// CHECK-RV64-NEXT:[[TMP1:%.*]] = insertvalue { ,  } [[TMP0]],  [[V_TUPLE_COERCE1]], 1
+// CHECK-RV64-NEXT:[[TMP2:%.*]] = extractvalue { ,  } [[TMP1]], 0
+// CHECK-RV64-NEXT:[[TMP3:%.*]] = extractvalue { ,  } [[TMP1]], 1
+// CHECK-RV64-NEXT:call void @llvm.riscv.vsuxseg2.nxv2i32.nxv2i32.i64( [[TMP2]],  [[TMP3]], ptr [[BASE]],  [[BINDEX]], i64 [[VL]])
+// CHECK-RV64-NEXT:ret void
+//
+void test_vsuxseg2ei32_v_tuple_i32m1(int32_t *base, vuint32m1_t bindex, vint32m1x2_t v_tuple, size_t vl) {
+  return __riscv_vsuxseg2ei32_v_tuple_i32m1(base, bindex, v_tuple, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local void @test_vsuxseg2ei32_v_tuple_i32m1_m
+// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]],  [[BINDEX:%.*]],  [[V_TUPLE_COERCE0:%.*]],  [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = insertvalue { ,  } poison,  [[V_TUPLE_COERCE0]], 0
+// CHECK-RV64-NEXT:[[TMP1:%.*]] = insertvalue { ,  } [[TMP0]],  [[V_TUPLE_COERCE1]], 1
+// CHECK-RV64-NEXT:[[TMP2:%.*]] = extractvalue { ,  } [[TMP1]], 0
+// CHECK-RV64-NEXT:[[TMP3:%.*]] = extractvalue { ,  } [[TMP1]], 1
+// CHECK-RV64-NEXT:call void @llvm.riscv.vsuxseg2.mask.nxv2i32.nxv2i32.i64( [[TMP2]],  [[TMP3]], ptr [[BASE]],  [[BINDEX]],  [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT:ret void
+//
+void test_vsuxseg2ei32_v_tuple_i32m1_m(vbool32_t mask, int32_t *base, vuint32m1_t bindex, vint32m1x2_t v_tuple, size_t vl) {
+  return __riscv_vsuxseg2ei32_v_tuple_i32m1_m(mask, base, bindex, v_tuple, vl);
+}
Index: clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei32_tuple.c
===
--- /dev/null
+++ clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei32_tuple.c
@@ -0,0 +1,36 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
+// REQUIRES: riscv-registered-target
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \
+// RUN:   -target-feature +experimental-zvfh -disable-O0-optnone  \
+// RUN:   -emit-llvm %s -o - | opt -S -passes=mem2reg | \
+// RUN:   FileCheck --check-prefix=CHECK-RV64 %s
+
+#include 
+
+// CHECK-RV64-LABEL: define dso_local void @test_vsoxseg2ei32_v_tuple_i32m1
+// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]],  [[BINDEX:%.*]],  [[V_TUPLE_COERCE0:%.*]],  [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = insertvalue { ,  } poison,  [[V_TUPLE_COERCE0]], 0
+// CHECK-RV64-NEXT:[[TMP1:%.*]] = insertvalue { ,  } [[TMP0]],  [[V_TUPLE_COERCE1]], 1
+// CHECK-RV64-NEXT:[[TMP2:%.*]] = extractvalue { ,  } [[TMP1]], 0
+// CHECK-RV64-NEXT:[[TMP3:%.*]] = extractvalue { ,  } [[TMP1]], 1
+// CHECK-RV64-NEXT:call void @llvm.riscv.vsoxseg2.nxv2i32.nxv2i32.i64( [[TMP2]],  [[TMP3]], ptr [[BASE]],  [[BINDEX]], i64 [[VL]])
+// CHECK-RV64-NEXT:ret void
+//
+void test_vsoxseg2ei32_v_tuple_i32m1(int32_t *base, vuint32m1_t bindex, vint32m1x2_t v_tuple, size_t vl) {
+  return __riscv_vsoxseg2ei32_v_tuple_i32m1(base, bindex, v_tuple, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local void @test_vsoxseg2ei32_v_tuple_i32m1_m
+// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]

[PATCH] D147915: [9/11][POC][Clang][RISCV] Define tuple type variant of vsoxseg2ei32 vsuxseg2ei32

2023-05-17 Thread Yueh-Ting (eop) Chen via Phabricator via cfe-commits 
eopXD updated this revision to Diff 522937.
eopXD added a comment.

Rebase.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D147915/new/

https://reviews.llvm.org/D147915

Files:
  clang/include/clang/Basic/riscv_vector.td
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei32_tuple.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei32_tuple.c

Index: clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei32_tuple.c
===
--- /dev/null
+++ clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei32_tuple.c
@@ -0,0 +1,36 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
+// REQUIRES: riscv-registered-target
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \
+// RUN:   -target-feature +experimental-zvfh -disable-O0-optnone  \
+// RUN:   -emit-llvm %s -o - | opt -S -passes=mem2reg | \
+// RUN:   FileCheck --check-prefix=CHECK-RV64 %s
+
+#include 
+
+// CHECK-RV64-LABEL: define dso_local void @test_vsuxseg2ei32_v_tuple_i32m1
+// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]],  [[BINDEX:%.*]],  [[V_TUPLE_COERCE0:%.*]],  [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = insertvalue { ,  } poison,  [[V_TUPLE_COERCE0]], 0
+// CHECK-RV64-NEXT:[[TMP1:%.*]] = insertvalue { ,  } [[TMP0]],  [[V_TUPLE_COERCE1]], 1
+// CHECK-RV64-NEXT:[[TMP2:%.*]] = extractvalue { ,  } [[TMP1]], 0
+// CHECK-RV64-NEXT:[[TMP3:%.*]] = extractvalue { ,  } [[TMP1]], 1
+// CHECK-RV64-NEXT:call void @llvm.riscv.vsuxseg2.nxv2i32.nxv2i32.i64( [[TMP2]],  [[TMP3]], ptr [[BASE]],  [[BINDEX]], i64 [[VL]])
+// CHECK-RV64-NEXT:ret void
+//
+void test_vsuxseg2ei32_v_tuple_i32m1(int32_t *base, vuint32m1_t bindex, vint32m1x2_t v_tuple, size_t vl) {
+  return __riscv_vsuxseg2ei32_v_tuple_i32m1(base, bindex, v_tuple, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local void @test_vsuxseg2ei32_v_tuple_i32m1_m
+// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]],  [[BINDEX:%.*]],  [[V_TUPLE_COERCE0:%.*]],  [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = insertvalue { ,  } poison,  [[V_TUPLE_COERCE0]], 0
+// CHECK-RV64-NEXT:[[TMP1:%.*]] = insertvalue { ,  } [[TMP0]],  [[V_TUPLE_COERCE1]], 1
+// CHECK-RV64-NEXT:[[TMP2:%.*]] = extractvalue { ,  } [[TMP1]], 0
+// CHECK-RV64-NEXT:[[TMP3:%.*]] = extractvalue { ,  } [[TMP1]], 1
+// CHECK-RV64-NEXT:call void @llvm.riscv.vsuxseg2.mask.nxv2i32.nxv2i32.i64( [[TMP2]],  [[TMP3]], ptr [[BASE]],  [[BINDEX]],  [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT:ret void
+//
+void test_vsuxseg2ei32_v_tuple_i32m1_m(vbool32_t mask, int32_t *base, vuint32m1_t bindex, vint32m1x2_t v_tuple, size_t vl) {
+  return __riscv_vsuxseg2ei32_v_tuple_i32m1_m(mask, base, bindex, v_tuple, vl);
+}
Index: clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei32_tuple.c
===
--- /dev/null
+++ clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei32_tuple.c
@@ -0,0 +1,36 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
+// REQUIRES: riscv-registered-target
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \
+// RUN:   -target-feature +experimental-zvfh -disable-O0-optnone  \
+// RUN:   -emit-llvm %s -o - | opt -S -passes=mem2reg | \
+// RUN:   FileCheck --check-prefix=CHECK-RV64 %s
+
+#include 
+
+// CHECK-RV64-LABEL: define dso_local void @test_vsoxseg2ei32_v_tuple_i32m1
+// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]],  [[BINDEX:%.*]],  [[V_TUPLE_COERCE0:%.*]],  [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = insertvalue { ,  } poison,  [[V_TUPLE_COERCE0]], 0
+// CHECK-RV64-NEXT:[[TMP1:%.*]] = insertvalue { ,  } [[TMP0]],  [[V_TUPLE_COERCE1]], 1
+// CHECK-RV64-NEXT:[[TMP2:%.*]] = extractvalue { ,  } [[TMP1]], 0
+// CHECK-RV64-NEXT:[[TMP3:%.*]] = extractvalue { ,  } [[TMP1]], 1
+// CHECK-RV64-NEXT:call void @llvm.riscv.vsoxseg2.nxv2i32.nxv2i32.i64( [[TMP2]],  [[TMP3]], ptr [[BASE]],  [[BINDEX]], i64 [[VL]])
+// CHECK-RV64-NEXT:ret void
+//
+void test_vsoxseg2ei32_v_tuple_i32m1(int32_t *base, vuint32m1_t bindex, vint32m1x2_t v_tuple, size_t vl) {
+  return __riscv_vsoxseg2ei32_v_tuple_i32m1(base, bindex, v_tuple, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local void @test_vsoxseg2ei32_v_tuple_i32m1_m
+// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]],  [[BINDEX:%.*]],  [[V_TUPLE_COERCE0

[PATCH] D147915: [9/11][POC][Clang][RISCV] Define tuple type variant of vsoxseg2ei32 vsuxseg2ei32

2023-04-24 Thread Yueh-Ting (eop) Chen via Phabricator via cfe-commits 
eopXD updated this revision to Diff 516313.
eopXD added a comment.

Address comment from Craig.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D147915/new/

https://reviews.llvm.org/D147915

Files:
  clang/include/clang/Basic/riscv_vector.td
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei32_tuple.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei32_tuple.c

Index: clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei32_tuple.c
===
--- /dev/null
+++ clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei32_tuple.c
@@ -0,0 +1,36 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
+// REQUIRES: riscv-registered-target
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \
+// RUN:   -target-feature +experimental-zvfh -disable-O0-optnone  \
+// RUN:   -emit-llvm %s -o - | opt -S -passes=mem2reg | \
+// RUN:   FileCheck --check-prefix=CHECK-RV64 %s
+
+#include 
+
+// CHECK-RV64-LABEL: define dso_local void @test_vsuxseg2ei32_v_tuple_i32m1
+// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]],  [[BINDEX:%.*]],  [[V_TUPLE_COERCE0:%.*]],  [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = insertvalue { ,  } undef,  [[V_TUPLE_COERCE0]], 0
+// CHECK-RV64-NEXT:[[TMP1:%.*]] = insertvalue { ,  } [[TMP0]],  [[V_TUPLE_COERCE1]], 1
+// CHECK-RV64-NEXT:[[TMP2:%.*]] = extractvalue { ,  } [[TMP1]], 0
+// CHECK-RV64-NEXT:[[TMP3:%.*]] = extractvalue { ,  } [[TMP1]], 1
+// CHECK-RV64-NEXT:call void @llvm.riscv.vsuxseg2.nxv2i32.nxv2i32.i64( [[TMP2]],  [[TMP3]], ptr [[BASE]],  [[BINDEX]], i64 [[VL]])
+// CHECK-RV64-NEXT:ret void
+//
+void test_vsuxseg2ei32_v_tuple_i32m1(int32_t *base, vuint32m1_t bindex, vint32m1x2_t v_tuple, size_t vl) {
+  return __riscv_vsuxseg2ei32_v_tuple_i32m1(base, bindex, v_tuple, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local void @test_vsuxseg2ei32_v_tuple_i32m1_m
+// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]],  [[BINDEX:%.*]],  [[V_TUPLE_COERCE0:%.*]],  [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = insertvalue { ,  } undef,  [[V_TUPLE_COERCE0]], 0
+// CHECK-RV64-NEXT:[[TMP1:%.*]] = insertvalue { ,  } [[TMP0]],  [[V_TUPLE_COERCE1]], 1
+// CHECK-RV64-NEXT:[[TMP2:%.*]] = extractvalue { ,  } [[TMP1]], 0
+// CHECK-RV64-NEXT:[[TMP3:%.*]] = extractvalue { ,  } [[TMP1]], 1
+// CHECK-RV64-NEXT:call void @llvm.riscv.vsuxseg2.mask.nxv2i32.nxv2i32.i64( [[TMP2]],  [[TMP3]], ptr [[BASE]],  [[BINDEX]],  [[MASK]], i64 [[VL]])
+// CHECK-RV64-NEXT:ret void
+//
+void test_vsuxseg2ei32_v_tuple_i32m1_m(vbool32_t mask, int32_t *base, vuint32m1_t bindex, vint32m1x2_t v_tuple, size_t vl) {
+  return __riscv_vsuxseg2ei32_v_tuple_i32m1_m(mask, base, bindex, v_tuple, vl);
+}
Index: clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei32_tuple.c
===
--- /dev/null
+++ clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei32_tuple.c
@@ -0,0 +1,36 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
+// REQUIRES: riscv-registered-target
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \
+// RUN:   -target-feature +experimental-zvfh -disable-O0-optnone  \
+// RUN:   -emit-llvm %s -o - | opt -S -passes=mem2reg | \
+// RUN:   FileCheck --check-prefix=CHECK-RV64 %s
+
+#include 
+
+// CHECK-RV64-LABEL: define dso_local void @test_vsoxseg2ei32_v_tuple_i32m1
+// CHECK-RV64-SAME: (ptr noundef [[BASE:%.*]],  [[BINDEX:%.*]],  [[V_TUPLE_COERCE0:%.*]],  [[V_TUPLE_COERCE1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
+// CHECK-RV64-NEXT:  entry:
+// CHECK-RV64-NEXT:[[TMP0:%.*]] = insertvalue { ,  } undef,  [[V_TUPLE_COERCE0]], 0
+// CHECK-RV64-NEXT:[[TMP1:%.*]] = insertvalue { ,  } [[TMP0]],  [[V_TUPLE_COERCE1]], 1
+// CHECK-RV64-NEXT:[[TMP2:%.*]] = extractvalue { ,  } [[TMP1]], 0
+// CHECK-RV64-NEXT:[[TMP3:%.*]] = extractvalue { ,  } [[TMP1]], 1
+// CHECK-RV64-NEXT:call void @llvm.riscv.vsoxseg2.nxv2i32.nxv2i32.i64( [[TMP2]],  [[TMP3]], ptr [[BASE]],  [[BINDEX]], i64 [[VL]])
+// CHECK-RV64-NEXT:ret void
+//
+void test_vsoxseg2ei32_v_tuple_i32m1(int32_t *base, vuint32m1_t bindex, vint32m1x2_t v_tuple, size_t vl) {
+  return __riscv_vsoxseg2ei32_v_tuple_i32m1(base, bindex, v_tuple, vl);
+}
+
+// CHECK-RV64-LABEL: define dso_local void @test_vsoxseg2ei32_v_tuple_i32m1_m
+// CHECK-RV64-SAME: ( [[MASK:%.*]], ptr noundef [[BASE:%.*]],  [[BINDEX:%.*]],