[PATCH] D148308: [RISCV] Split out SiFive VCIX C intrinsics from riscv_vector.td

[Kito Cheng via Phabricator via cfe-commits]

kito-cheng accepted this revision.
kito-cheng added a comment.
This revision is now accepted and ready to land.

LGTM, thanks!


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D148308/new/

https://reviews.llvm.org/D148308

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[PATCH] D148308: [RISCV] Split out SiFive VCIX C intrinsics from riscv_vector.td

[Brandon Wu via Phabricator via cfe-commits]

4vtomat updated this revision to Diff 514817.
4vtomat added a comment.

Resolved Kito's comments.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D148308/new/

https://reviews.llvm.org/D148308

Files:
  clang/include/clang/Basic/BuiltinsRISCVVector.def
  clang/include/clang/Basic/CMakeLists.txt
  clang/include/clang/Basic/riscv_sifive_vector.td
  clang/include/clang/Basic/riscv_vector.td
  clang/include/clang/Sema/RISCVIntrinsicManager.h
  clang/include/clang/Sema/Sema.h
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/Headers/CMakeLists.txt
  clang/lib/Headers/sifive_vector.h
  clang/lib/Parse/ParsePragma.cpp
  clang/lib/Sema/SemaLookup.cpp
  clang/lib/Sema/SemaRISCVVectorLookup.cpp
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/xsfvcp-x-rv64.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/xsfvcp-x.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/xsfvcp-xv-rv64.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/xsfvcp-xv.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/xsfvcp-xvv-rv64.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/xsfvcp-xvv.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/xsfvcp-xvw.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/xsfvcp-index-out-of-range.c
  clang/test/Sema/riscv-bad-intrinsic-pragma.c
  clang/utils/TableGen/TableGen.cpp
  llvm/docs/CommandGuide/tblgen.rst

Index: llvm/docs/CommandGuide/tblgen.rst
===
--- llvm/docs/CommandGuide/tblgen.rst
+++ llvm/docs/CommandGuide/tblgen.rst
@@ -348,6 +348,14 @@
 
   Generate ``riscv_vector_builtin_cg.inc`` for Clang.
 
+.. option:: -gen-riscv-sifive-vector-builtins
+
+  Generate ``riscv_sifive_vector_builtins.inc`` for Clang.
+
+.. option:: -gen-riscv-sifive-vector-builtin-codegen
+
+  Generate ``riscv_sifive_vector_builtin_cg.inc`` for Clang.
+
 .. option:: -gen-attr-docs
 
   Generate attribute documentation.
Index: clang/utils/TableGen/TableGen.cpp
===
--- clang/utils/TableGen/TableGen.cpp
+++ clang/utils/TableGen/TableGen.cpp
@@ -91,6 +91,9 @@
   GenRISCVVectorBuiltins,
   GenRISCVVectorBuiltinCG,
   GenRISCVVectorBuiltinSema,
+  GenRISCVSiFiveVectorBuiltins,
+  GenRISCVSiFiveVectorBuiltinCG,
+  GenRISCVSiFiveVectorBuiltinSema,
   GenAttrDocs,
   GenDiagDocs,
   GenOptDocs,
@@ -251,6 +254,12 @@
"Generate riscv_vector_builtin_cg.inc for clang"),
 clEnumValN(GenRISCVVectorBuiltinSema, "gen-riscv-vector-builtin-sema",
"Generate riscv_vector_builtin_sema.inc for clang"),
+clEnumValN(GenRISCVSiFiveVectorBuiltins, "gen-riscv-sifive-vector-builtins",
+   "Generate riscv_sifive_vector_builtins.inc for clang"),
+clEnumValN(GenRISCVSiFiveVectorBuiltinCG, "gen-riscv-sifive-vector-builtin-codegen",
+   "Generate riscv_sifive_vector_builtin_cg.inc for clang"),
+clEnumValN(GenRISCVSiFiveVectorBuiltinSema, "gen-riscv-sifive-vector-builtin-sema",
+   "Generate riscv_sifive_vector_builtin_sema.inc for clang"),
 clEnumValN(GenAttrDocs, "gen-attr-docs",
"Generate attribute documentation"),
 clEnumValN(GenDiagDocs, "gen-diag-docs",
@@ -472,6 +481,15 @@
   case GenRISCVVectorBuiltinSema:
 EmitRVVBuiltinSema(Records, OS);
 break;
+  case GenRISCVSiFiveVectorBuiltins:
+EmitRVVBuiltins(Records, OS);
+break;
+  case GenRISCVSiFiveVectorBuiltinCG:
+EmitRVVBuiltinCG(Records, OS);
+break;
+  case GenRISCVSiFiveVectorBuiltinSema:
+EmitRVVBuiltinSema(Records, OS);
+break;
   case GenAttrDocs:
 EmitClangAttrDocs(Records, OS);
 break;
Index: clang/test/Sema/riscv-bad-intrinsic-pragma.c
===
--- clang/test/Sema/riscv-bad-intrinsic-pragma.c
+++ clang/test/Sema/riscv-bad-intrinsic-pragma.c
@@ -2,7 +2,7 @@
 // RUN:2>&1 | FileCheck %s
 
 #pragma clang riscv intrinsic 
-// CHECK:  warning: unexpected argument '' to '#pragma riscv'; expected 'vector' [-Wignored-pragmas]
+// CHECK:  warning: unexpected argument '' to '#pragma riscv'; expected 'vector' or 'sifive_vector' [-Wignored-pragmas]
 
 #pragma clang riscv what + 3241
 // CHECK:  warning: unexpected argument 'what' to '#pragma riscv'; expected 'intrinsic' [-Wignored-pragmas]
Index: clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/xsfvcp-index-out-of-range.c
===
--- clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/xsfvcp-index-out-of-range.c
+++ clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/xsfvcp-index-out-of-range.c
@@ -5,7 

[PATCH] D148308: [RISCV] Split out SiFive VCIX C intrinsics from riscv_vector.td

[Kito Cheng via Phabricator via cfe-commits]

kito-cheng added inline comments.



Comment at: clang/include/clang/Basic/riscv_vector.td:15
 
-//===--===//
-// Instruction definitions
-//===--===//
-// Each record of the class RVVBuiltin defines a collection of builtins (i.e.
-// "def vadd : RVVBuiltin" will be used to define things like "vadd_vv_i32m1",
-// "vadd_vv_i32m2", etc).
-//
-// The elements of this collection are defined by an instantiation process the
-// range of which is specified by the cross product of the LMUL attribute and
-// every element in the attribute TypeRange. By default builtins have LMUL = 
[1,
-// 2, 4, 8, 1/2, 1/4, 1/8] so the process is repeated 7 times. In tablegen we
-// use the Log2LMUL [0, 1, 2, 3, -1, -2, -3] to represent the LMUL.
-//
-// LMUL represents the fact that the types of values used by that builtin are
-// values generated by instructions that are executed under that LMUL. However,
-// this does not mean the builtin is necessarily lowered into an instruction
-// that executes under the specified LMUL. An example where this happens are
-// loads and stores of masks. A mask like `vbool8_t` can be generated, for
-// instance, by comparing two `__rvv_int8m1_t` (this is LMUL=1) or comparing 
two
-// `__rvv_int16m2_t` (this is LMUL=2). The actual load or store, however, will
-// be performed under LMUL=1 because mask registers are not grouped.
-//
-// TypeRange is a non-empty sequence of basic types:
-//
-//   c: int8_t (i8)
-//   s: int16_t (i16)
-//   i: int32_t (i32)
-//   l: int64_t (i64)
-//   x: float16_t (half)
-//   f: float32_t (float)
-//   d: float64_t (double)
-//
-// This way, given an LMUL, a record with a TypeRange "sil" will cause the
-// definition of 3 builtins. Each type "t" in the TypeRange (in this example
-// they are int16_t, int32_t, int64_t) is used as a parameter that drives the
-// definition of that particular builtin (for the given LMUL).
-//
-// During the instantiation, types can be transformed or modified using type
-// transformers. Given a type "t" the following primitive type transformers can
-// be applied to it to yield another type.
-//
-//   e: type of "t" as is (identity)
-//   v: computes a vector type whose element type is "t" for the current LMUL
-//   w: computes a vector type identical to what 'v' computes except for the
-//  element type which is twice as wide as the element type of 'v'
-//   q: computes a vector type identical to what 'v' computes except for the
-//  element type which is four times as wide as the element type of 'v'
-//   o: computes a vector type identical to what 'v' computes except for the
-//  element type which is eight times as wide as the element type of 'v'
-//   m: computes a vector type identical to what 'v' computes except for the
-//  element type which is bool
-//   0: void type, ignores "t"
-//   z: size_t, ignores "t"
-//   t: ptrdiff_t, ignores "t"
-//   u: unsigned long, ignores "t"
-//   l: long, ignores "t"
-//
-// So for instance if t is "i", i.e. int, then "e" will yield int again. "v"
-// will yield an RVV vector type (assume LMUL=1), so __rvv_int32m1_t.
-// Accordingly "w" would yield __rvv_int64m2_t.
-//
-// A type transformer can be prefixed by other non-primitive type transformers.
-//
-//   P: constructs a pointer to the current type
-//   C: adds const to the type
-//   K: requires the integer type to be a constant expression
-//   U: given an integer type or vector type, computes its unsigned variant
-//   I: given a vector type, compute the vector type with integer type
-//  elements of the same width
-//   F: given a vector type, compute the vector type with floating-point type
-//  elements of the same width
-//   S: given a vector type, computes its equivalent one for LMUL=1. This is a
-//  no-op if the vector was already LMUL=1
-//   (Log2EEW:Value): Log2EEW value could be 3/4/5/6 (8/16/32/64), given a
-//  vector type (SEW and LMUL) and EEW (8/16/32/64), computes its
-//  equivalent integer vector type with EEW and corresponding ELMUL (elmul 
=
-//  (eew/sew) * lmul). For example, vector type is __rvv_float16m4
-//  (SEW=16, LMUL=4) and Log2EEW is 3 (EEW=8), and then equivalent vector
-//  type is __rvv_uint8m2_t (elmul=(8/16)*4 = 2). Ignore to define a new
-//  builtins if its equivalent type has illegal lmul.
-//   (FixedSEW:Value): Given a vector type (SEW and LMUL), and computes another
-//  vector type which only changed SEW as given value. Ignore to define a 
new
-//  builtin if its equivalent type has illegal lmul or the SEW does not 
changed.
-//   (SFixedLog2LMUL:Value): Smaller Fixed Log2LMUL. Given a vector type (SEW
-//  and LMUL), and computes another vector type which only changed LMUL as
-//  given value. The new LMUL should be smaller than the old one. Ignore to
-//  define a 

[PATCH] D148308: [RISCV] Split out SiFive VCIX C intrinsics from riscv_vector.td

[Brandon Wu via Phabricator via cfe-commits]

4vtomat created this revision.
Herald added subscribers: jobnoorman, luke, VincentWu, vkmr, frasercrmck, 
evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, 
jocewei, PkmX, arphaman, the_o, brucehoult, MartinMosbeck, rogfer01, 
edward-jones, zzheng, jrtc27, shiva0217, kito-cheng, niosHD, sabuasal, 
simoncook, johnrusso, rbar, asb, arichardson.
Herald added a project: All.
4vtomat requested review of this revision.
Herald added subscribers: llvm-commits, cfe-commits, pcwang-thead, eopXD, 
MaskRay.
Herald added projects: clang, LLVM.

Since we don't always need the vendor extension to be in riscv_vector.td,
so it's better to make it be in separated header.

Depends on D148223 


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D148308

Files:
  clang/include/clang/Basic/BuiltinsRISCVVector.def
  clang/include/clang/Basic/CMakeLists.txt
  clang/include/clang/Basic/riscv_sifive_vcix.td
  clang/include/clang/Basic/riscv_vector.td
  clang/include/clang/Basic/riscv_vector_common.td
  clang/include/clang/Sema/RISCVIntrinsicManager.h
  clang/include/clang/Sema/Sema.h
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/Headers/CMakeLists.txt
  clang/lib/Headers/sifive_vector.h
  clang/lib/Parse/ParsePragma.cpp
  clang/lib/Sema/SemaLookup.cpp
  clang/lib/Sema/SemaRISCVVectorLookup.cpp
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/xsfvcp-x-rv64.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/xsfvcp-x.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/xsfvcp-xv-rv64.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/xsfvcp-xv.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/xsfvcp-xvv-rv64.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/xsfvcp-xvv.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/xsfvcp-xvw.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/xsfvcp-index-out-of-range.c
  clang/test/Sema/riscv-bad-intrinsic-pragma.c
  clang/utils/TableGen/TableGen.cpp
  llvm/docs/CommandGuide/tblgen.rst

Index: llvm/docs/CommandGuide/tblgen.rst
===
--- llvm/docs/CommandGuide/tblgen.rst
+++ llvm/docs/CommandGuide/tblgen.rst
@@ -348,6 +348,14 @@
 
   Generate ``riscv_vector_builtin_cg.inc`` for Clang.
 
+.. option:: -gen-riscv-sifive-vcix-builtins
+
+  Generate ``riscv_sifive_vcix_builtins.inc`` for Clang.
+
+.. option:: -gen-riscv-sifive-vcix-builtin-codegen
+
+  Generate ``riscv_sifive_vcix_builtin_cg.inc`` for Clang.
+
 .. option:: -gen-attr-docs
 
   Generate attribute documentation.
Index: clang/utils/TableGen/TableGen.cpp
===
--- clang/utils/TableGen/TableGen.cpp
+++ clang/utils/TableGen/TableGen.cpp
@@ -91,6 +91,9 @@
   GenRISCVVectorBuiltins,
   GenRISCVVectorBuiltinCG,
   GenRISCVVectorBuiltinSema,
+  GenRISCVSiFiveVCIXBuiltins,
+  GenRISCVSiFiveVCIXBuiltinCG,
+  GenRISCVSiFiveVCIXBuiltinSema,
   GenAttrDocs,
   GenDiagDocs,
   GenOptDocs,
@@ -251,6 +254,12 @@
"Generate riscv_vector_builtin_cg.inc for clang"),
 clEnumValN(GenRISCVVectorBuiltinSema, "gen-riscv-vector-builtin-sema",
"Generate riscv_vector_builtin_sema.inc for clang"),
+clEnumValN(GenRISCVSiFiveVCIXBuiltins, "gen-riscv-sifive-vcix-builtins",
+   "Generate riscv_sifive_vcix_builtins.inc for clang"),
+clEnumValN(GenRISCVSiFiveVCIXBuiltinCG, "gen-riscv-sifive-vcix-builtin-codegen",
+   "Generate riscv_sifive_vcix_builtin_cg.inc for clang"),
+clEnumValN(GenRISCVSiFiveVCIXBuiltinSema, "gen-riscv-sifive-vcix-builtin-sema",
+   "Generate riscv_sifive_vcix_builtin_sema.inc for clang"),
 clEnumValN(GenAttrDocs, "gen-attr-docs",
"Generate attribute documentation"),
 clEnumValN(GenDiagDocs, "gen-diag-docs",
@@ -472,6 +481,15 @@
   case GenRISCVVectorBuiltinSema:
 EmitRVVBuiltinSema(Records, OS);
 break;
+  case GenRISCVSiFiveVCIXBuiltins:
+EmitRVVBuiltins(Records, OS);
+break;
+  case GenRISCVSiFiveVCIXBuiltinCG:
+EmitRVVBuiltinCG(Records, OS);
+break;
+  case GenRISCVSiFiveVCIXBuiltinSema:
+EmitRVVBuiltinSema(Records, OS);
+break;
   case GenAttrDocs:
 EmitClangAttrDocs(Records, OS);
 break;
Index: clang/test/Sema/riscv-bad-intrinsic-pragma.c
===
--- clang/test/Sema/riscv-bad-intrinsic-pragma.c
+++ clang/test/Sema/riscv-bad-intrinsic-pragma.c
@@ -2,7 +2,7 @@
 // RUN:2>&1 | FileCheck %s
 
 #pragma clang riscv intrinsic 
-// CHECK:  warning: unexpected argument '' to '#pragma riscv'; expected 'vector' [-Wignored-pragmas]
+// CHECK: