[PATCH] D150996: LLVM_FALLTHROUGH => [[fallthrough]]. NFC

2023-05-24 Thread Craig Topper via Phabricator via cfe-commits 
This revision was automatically updated to reflect the committed changes.
Closed by commit rG6006d43e2d7d: LLVM_FALLTHROUGH = [[fallthrough]]. NFC 
(authored by craig.topper).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D150996/new/

https://reviews.llvm.org/D150996

Files:
  clang/lib/AST/TemplateBase.cpp
  clang/lib/Basic/SourceManager.cpp
  clang/lib/Sema/SemaChecking.cpp
  lldb/source/Plugins/ExpressionParser/Clang/ClangExpressionParser.cpp
  llvm/lib/Analysis/MemoryLocation.cpp
  llvm/lib/Analysis/ScalarEvolution.cpp
  llvm/lib/DebugInfo/LogicalView/Readers/LVBinaryReader.cpp
  llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
  llvm/lib/ProfileData/InstrProf.cpp
  llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
  llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
  llvm/lib/Target/PowerPC/PPCISelLowering.cpp
  llvm/lib/Target/PowerPC/PPCRegisterInfo.h
  llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp
  llvm/lib/Transforms/Vectorize/LoopVectorize.cpp

Index: llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
===
--- llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+++ llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
@@ -8487,7 +8487,7 @@
   Ops[1] = SafeRHS;
   return new VPWidenRecipe(*I, make_range(Ops.begin(), Ops.end()));
 }
-LLVM_FALLTHROUGH;
+[[fallthrough]];
   }
   case Instruction::Add:
   case Instruction::And:
Index: llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp
===
--- llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp
+++ llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp
@@ -55,7 +55,7 @@
   switch (Intrinsic) {
   case Intrinsic::spv_load:
 AlignIdx = 2;
-LLVM_FALLTHROUGH;
+[[fallthrough]];
   case Intrinsic::spv_store: {
 if (I.getNumOperands() >= AlignIdx + 1) {
   auto *AlignOp = cast(I.getOperand(AlignIdx));
Index: llvm/lib/Target/PowerPC/PPCRegisterInfo.h
===
--- llvm/lib/Target/PowerPC/PPCRegisterInfo.h
+++ llvm/lib/Target/PowerPC/PPCRegisterInfo.h
@@ -183,7 +183,7 @@
   case 'f':
 if (RegName[1] == 'p')
   return RegName + 2;
-LLVM_FALLTHROUGH;
+[[fallthrough]];
   case 'r':
   case 'v':
 if (RegName[1] == 's') {
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
===
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -10686,7 +10686,7 @@
   RetOps.push_back(Extract);
   return DAG.getMergeValues(RetOps, dl);
 }
-LLVM_FALLTHROUGH;
+[[fallthrough]];
   }
   case Intrinsic::ppc_vsx_disassemble_pair: {
 int NumVecs = 2;
Index: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
===
--- llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
+++ llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
@@ -3994,7 +3994,7 @@
   if (SRLConst && SRLConst->getSExtValue() == 16)
 return false;
 }
-LLVM_FALLTHROUGH;
+[[fallthrough]];
   case ISD::ROTL:
   case ISD::SHL:
   case ISD::AND:
Index: llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
===
--- llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
+++ llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
@@ -2529,7 +2529,7 @@
   return 2 * LT.first;
 if (!Ty->getScalarType()->isFP128Ty())
   return LT.first;
-LLVM_FALLTHROUGH;
+[[fallthrough]];
   case ISD::FMUL:
   case ISD::FDIV:
 // These nodes are marked as 'custom' just to lower them to SVE.
Index: llvm/lib/ProfileData/InstrProf.cpp
===
--- llvm/lib/ProfileData/InstrProf.cpp
+++ llvm/lib/ProfileData/InstrProf.cpp
@@ -1385,7 +1385,7 @@
   case 10ull:
 H.TemporalProfTracesOffset =
 read(Buffer, offsetOf(::TemporalProfTracesOffset));
-LLVM_FALLTHROUGH;
+[[fallthrough]];
   case 9ull:
 H.BinaryIdOffset = read(Buffer, offsetOf(::BinaryIdOffset));
 [[fallthrough]];
Index: llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
===
--- llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
+++ llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
@@ -2420,7 +2420,7 @@
   case OMPScheduleType::BaseRuntimeSimd:
 assert(!ChunkSize &&
"schedule type does not support user-defined chunk sizes");
-LLVM_FALLTHROUGH;
+[[fallthrough]];
   case OMPScheduleType::BaseDynamicChunked:
   case OMPScheduleType::BaseGuidedChunked:
   case OMPScheduleType::BaseGuidedIterativeChunked:
Index: llvm/lib/DebugInfo/LogicalView/Readers/LVBinaryReader.cpp
===
--- llvm/lib/DebugInfo/LogicalView/Readers/LVBinaryReader.cpp
+++

[PATCH] D150996: LLVM_FALLTHROUGH => [[fallthrough]]. NFC

2023-05-24 Thread Fangrui Song via Phabricator via cfe-commits 
MaskRay accepted this revision.
MaskRay added a comment.
This revision is now accepted and ready to land.

Thanks!


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D150996/new/

https://reviews.llvm.org/D150996

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[PATCH] D150996: LLVM_FALLTHROUGH => [[fallthrough]]. NFC

2023-05-19 Thread Craig Topper via Phabricator via cfe-commits 
craig.topper created this revision.
craig.topper added a reviewer: MaskRay.
Herald added subscribers: ThomasRaoux, kbarton, hiraditya, nemanjai.
Herald added a project: All.
craig.topper requested review of this revision.
Herald added a reviewer: zuban32.
Herald added subscribers: lldb-commits, cfe-commits, pcwang-thead.
Herald added a reviewer: mpaszkowski.
Herald added projects: clang, LLDB, LLVM.

Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D150996

Files:
  clang/lib/AST/TemplateBase.cpp
  clang/lib/Basic/SourceManager.cpp
  clang/lib/Sema/SemaChecking.cpp
  lldb/source/Plugins/ExpressionParser/Clang/ClangExpressionParser.cpp
  llvm/lib/Analysis/MemoryLocation.cpp
  llvm/lib/Analysis/ScalarEvolution.cpp
  llvm/lib/DebugInfo/LogicalView/Readers/LVBinaryReader.cpp
  llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
  llvm/lib/ProfileData/InstrProf.cpp
  llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
  llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
  llvm/lib/Target/PowerPC/PPCISelLowering.cpp
  llvm/lib/Target/PowerPC/PPCRegisterInfo.h
  llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp
  llvm/lib/Transforms/Vectorize/LoopVectorize.cpp

Index: llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
===
--- llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+++ llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
@@ -8487,7 +8487,7 @@
   Ops[1] = SafeRHS;
   return new VPWidenRecipe(*I, make_range(Ops.begin(), Ops.end()));
 }
-LLVM_FALLTHROUGH;
+[[fallthrough]];
   }
   case Instruction::Add:
   case Instruction::And:
Index: llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp
===
--- llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp
+++ llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp
@@ -55,7 +55,7 @@
   switch (Intrinsic) {
   case Intrinsic::spv_load:
 AlignIdx = 2;
-LLVM_FALLTHROUGH;
+[[fallthrough]];
   case Intrinsic::spv_store: {
 if (I.getNumOperands() >= AlignIdx + 1) {
   auto *AlignOp = cast(I.getOperand(AlignIdx));
Index: llvm/lib/Target/PowerPC/PPCRegisterInfo.h
===
--- llvm/lib/Target/PowerPC/PPCRegisterInfo.h
+++ llvm/lib/Target/PowerPC/PPCRegisterInfo.h
@@ -183,7 +183,7 @@
   case 'f':
 if (RegName[1] == 'p')
   return RegName + 2;
-LLVM_FALLTHROUGH;
+[[fallthrough]];
   case 'r':
   case 'v':
 if (RegName[1] == 's') {
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
===
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -10686,7 +10686,7 @@
   RetOps.push_back(Extract);
   return DAG.getMergeValues(RetOps, dl);
 }
-LLVM_FALLTHROUGH;
+[[fallthrough]];
   }
   case Intrinsic::ppc_vsx_disassemble_pair: {
 int NumVecs = 2;
Index: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
===
--- llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
+++ llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
@@ -3994,7 +3994,7 @@
   if (SRLConst && SRLConst->getSExtValue() == 16)
 return false;
 }
-LLVM_FALLTHROUGH;
+[[fallthrough]];
   case ISD::ROTL:
   case ISD::SHL:
   case ISD::AND:
Index: llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
===
--- llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
+++ llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
@@ -2523,7 +2523,7 @@
   return 2 * LT.first;
 if (!Ty->getScalarType()->isFP128Ty())
   return LT.first;
-LLVM_FALLTHROUGH;
+[[fallthrough]];
   case ISD::FMUL:
   case ISD::FDIV:
 // These nodes are marked as 'custom' just to lower them to SVE.
Index: llvm/lib/ProfileData/InstrProf.cpp
===
--- llvm/lib/ProfileData/InstrProf.cpp
+++ llvm/lib/ProfileData/InstrProf.cpp
@@ -1385,7 +1385,7 @@
   case 10ull:
 H.TemporalProfTracesOffset =
 read(Buffer, offsetOf(::TemporalProfTracesOffset));
-LLVM_FALLTHROUGH;
+[[fallthrough]];
   case 9ull:
 H.BinaryIdOffset = read(Buffer, offsetOf(::BinaryIdOffset));
 [[fallthrough]];
Index: llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
===
--- llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
+++ llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
@@ -2420,7 +2420,7 @@
   case OMPScheduleType::BaseRuntimeSimd:
 assert(!ChunkSize &&
"schedule type does not support user-defined chunk sizes");
-LLVM_FALLTHROUGH;
+[[fallthrough]];
   case OMPScheduleType::BaseDynamicChunked:
   case OMPScheduleType::BaseGuidedChunked:
   case OMPScheduleType::BaseGuidedIterativeChunked:
Index: