[PATCH] D156214: [LLVM][RISCV] Check more extension dependencies
imkiva added a comment. Looks like I am reading a very old version of the spec haha. Anyway, thank you all for giving me the newest information and useful links! Thanks!! Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D156214/new/ https://reviews.llvm.org/D156214 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D156214: [LLVM][RISCV] Check more extension dependencies
craig.topper added a comment. I have deleted the two TODOs in r02c11c5aed59624046125cf512c12f70d2fa358d Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D156214/new/ https://reviews.llvm.org/D156214 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D156214: [LLVM][RISCV] Check more extension dependencies
craig.topper added inline comments. Comment at: llvm/lib/Support/RISCVISAInfo.cpp:948 - // TODO: The 'q' extension requires rv64. - // TODO: It is illegal to specify 'e' extensions with 'f' and 'd'. craig.topper wrote: > asb wrote: > > imkiva wrote: > > > wangpc wrote: > > > > I think the comment is outdated here. `E` can be combined with all > > > > other extensions according to spec: > > > > > Unless otherwise stated, standard extensions compatible with RV32I > > > > > and RV64I are also compatible with RV32E and RV64E, respectively. > > > > And, please see also D70401 for more context. > > > I downloaded the specification from > > > [here](https://github.com/riscv/riscv-isa-manual/releases/download/Ratified-IMAFDQC/riscv-spec-20191213.pdf), > > > and in page 34 the footnote says: > > > > > > > RV32E can be combined with all current standard extensions. Defining > > > > the F, D, and Q extensions as having a 16-entry floating point register > > > > file when combined with RV32E was considered but **decided against**. > > > > To support systems with reduced floating-point register state, we > > > > intend to define a “Zfinx” extension... > > > > > > It seems in the spec version 20191213, they rejected the combination of > > > `E` with standard floating-point extensions, instead, a separate > > > extension `Zfinx` is chosen for the original purpose. > > > I am not sure if there's any newer specification that decides to allow > > > this combination. > > > > > > > > There's a link to the ratified version on > > https://wiki.riscv.org/display/HOME/Recently+Ratified+Extensions - see > > https://drive.google.com/file/d/1GjHmphVKvJlOBJydAt36g0Oc8yCOPtKw/view > > > > As @wangpc says, the restriction was removed and so the comment is out of > > date. > > RV32E can be combined with all current standard extensions. Defining the F, > > D, and Q extensions as having a 16-entry floating point register file when > > combined with RV32E was considered but decided against. To support systems > > with reduced floating-point register state, we intend to define a “Zfinx” > > extension... > > That really only says that the register file for F and D is still 32 entries > with RV32E. It doesn't say they are incompatible. Maybe there was some even > older text? There was older text removed here https://github.com/riscv/riscv-isa-manual/commit/4845f5d61f96a827ec4d21d2c5a80b6bf7881e56 Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D156214/new/ https://reviews.llvm.org/D156214 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D156214: [LLVM][RISCV] Check more extension dependencies
craig.topper added inline comments. Comment at: llvm/lib/Support/RISCVISAInfo.cpp:948 - // TODO: The 'q' extension requires rv64. - // TODO: It is illegal to specify 'e' extensions with 'f' and 'd'. asb wrote: > imkiva wrote: > > wangpc wrote: > > > I think the comment is outdated here. `E` can be combined with all other > > > extensions according to spec: > > > > Unless otherwise stated, standard extensions compatible with RV32I and > > > > RV64I are also compatible with RV32E and RV64E, respectively. > > > And, please see also D70401 for more context. > > I downloaded the specification from > > [here](https://github.com/riscv/riscv-isa-manual/releases/download/Ratified-IMAFDQC/riscv-spec-20191213.pdf), > > and in page 34 the footnote says: > > > > > RV32E can be combined with all current standard extensions. Defining the > > > F, D, and Q extensions as having a 16-entry floating point register file > > > when combined with RV32E was considered but **decided against**. To > > > support systems with reduced floating-point register state, we intend to > > > define a “Zfinx” extension... > > > > It seems in the spec version 20191213, they rejected the combination of `E` > > with standard floating-point extensions, instead, a separate extension > > `Zfinx` is chosen for the original purpose. > > I am not sure if there's any newer specification that decides to allow this > > combination. > > > > > There's a link to the ratified version on > https://wiki.riscv.org/display/HOME/Recently+Ratified+Extensions - see > https://drive.google.com/file/d/1GjHmphVKvJlOBJydAt36g0Oc8yCOPtKw/view > > As @wangpc says, the restriction was removed and so the comment is out of > date. > RV32E can be combined with all current standard extensions. Defining the F, > D, and Q extensions as having a 16-entry floating point register file when > combined with RV32E was considered but decided against. To support systems > with reduced floating-point register state, we intend to define a “Zfinx” > extension... That really only says that the register file for F and D is still 32 entries with RV32E. It doesn't say they are incompatible. Maybe there was some even older text? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D156214/new/ https://reviews.llvm.org/D156214 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D156214: [LLVM][RISCV] Check more extension dependencies
craig.topper added inline comments.
Comment at: llvm/lib/Support/RISCVISAInfo.cpp:948
// Additional dependency checks.
- // TODO: The 'q' extension requires rv64.
- // TODO: It is illegal to specify 'e' extensions with 'f' and 'd'.
+ // The 'q' extension requires rv64.
+ if (XLen != 64 && Exts.count("q"))
craig.topper wrote:
> I'm not sure this is true.
The restriction was removed 4 years ago
https://github.com/riscv/riscv-isa-manual/commit/013ba6dc8a504ee4ad7bee42554fecaef7ba797f
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[PATCH] D156214: [LLVM][RISCV] Check more extension dependencies
craig.topper added inline comments.
Comment at: llvm/lib/Support/RISCVISAInfo.cpp:948
// Additional dependency checks.
- // TODO: The 'q' extension requires rv64.
- // TODO: It is illegal to specify 'e' extensions with 'f' and 'd'.
+ // The 'q' extension requires rv64.
+ if (XLen != 64 && Exts.count("q"))
I'm not sure this is true.
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[PATCH] D156214: [LLVM][RISCV] Check more extension dependencies
asb added inline comments. Comment at: llvm/lib/Support/RISCVISAInfo.cpp:948 - // TODO: The 'q' extension requires rv64. - // TODO: It is illegal to specify 'e' extensions with 'f' and 'd'. imkiva wrote: > wangpc wrote: > > I think the comment is outdated here. `E` can be combined with all other > > extensions according to spec: > > > Unless otherwise stated, standard extensions compatible with RV32I and > > > RV64I are also compatible with RV32E and RV64E, respectively. > > And, please see also D70401 for more context. > I downloaded the specification from > [here](https://github.com/riscv/riscv-isa-manual/releases/download/Ratified-IMAFDQC/riscv-spec-20191213.pdf), > and in page 34 the footnote says: > > > RV32E can be combined with all current standard extensions. Defining the F, > > D, and Q extensions as having a 16-entry floating point register file when > > combined with RV32E was considered but **decided against**. To support > > systems with reduced floating-point register state, we intend to define a > > “Zfinx” extension... > > It seems in the spec version 20191213, they rejected the combination of `E` > with standard floating-point extensions, instead, a separate extension > `Zfinx` is chosen for the original purpose. > I am not sure if there's any newer specification that decides to allow this > combination. > > There's a link to the ratified version on https://wiki.riscv.org/display/HOME/Recently+Ratified+Extensions - see https://drive.google.com/file/d/1GjHmphVKvJlOBJydAt36g0Oc8yCOPtKw/view As @wangpc says, the restriction was removed and so the comment is out of date. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D156214/new/ https://reviews.llvm.org/D156214 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D156214: [LLVM][RISCV] Check more extension dependencies
imkiva added a comment. address review comments Comment at: llvm/lib/Support/RISCVISAInfo.cpp:948 - // TODO: The 'q' extension requires rv64. - // TODO: It is illegal to specify 'e' extensions with 'f' and 'd'. wangpc wrote: > I think the comment is outdated here. `E` can be combined with all other > extensions according to spec: > > Unless otherwise stated, standard extensions compatible with RV32I and > > RV64I are also compatible with RV32E and RV64E, respectively. > And, please see also D70401 for more context. I downloaded the specification from [here](https://github.com/riscv/riscv-isa-manual/releases/download/Ratified-IMAFDQC/riscv-spec-20191213.pdf), and in page 34 the footnote says: > RV32E can be combined with all current standard extensions. Defining the F, > D, and Q extensions as having a 16-entry floating point register file when > combined with RV32E was considered but **decided against**. To support > systems with reduced floating-point register state, we intend to define a > “Zfinx” extension... It seems in the spec version 20191213, they rejected the combination of `E` with standard floating-point extensions, instead, a separate extension `Zfinx` is chosen for the original purpose. I am not sure if there's any newer specification that decides to allow this combination. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D156214/new/ https://reviews.llvm.org/D156214 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D156214: [LLVM][RISCV] Check more extension dependencies
wangpc added inline comments. Comment at: llvm/lib/Support/RISCVISAInfo.cpp:948 - // TODO: The 'q' extension requires rv64. - // TODO: It is illegal to specify 'e' extensions with 'f' and 'd'. I think the comment is outdated here. `E` can be combined with all other extensions according to spec: > Unless otherwise stated, standard extensions compatible with RV32I and RV64I > are also compatible with RV32E and RV64E, respectively. And, please see also D70401 for more context. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D156214/new/ https://reviews.llvm.org/D156214 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D156214: [LLVM][RISCV] Check more extension dependencies
imkiva updated this revision to Diff 543890.
imkiva added a comment.
Removed some tests that used `e` together with `f` or `d`
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
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https://reviews.llvm.org/D156214
Files:
clang/test/Driver/riscv-arch.c
llvm/lib/Support/RISCVISAInfo.cpp
llvm/test/MC/RISCV/target-abi-invalid.s
llvm/unittests/Support/RISCVISAInfoTest.cpp
Index: llvm/unittests/Support/RISCVISAInfoTest.cpp
===
--- llvm/unittests/Support/RISCVISAInfoTest.cpp
+++ llvm/unittests/Support/RISCVISAInfoTest.cpp
@@ -474,6 +474,17 @@
EXPECT_EQ(toString(RISCVISAInfo::parseArchString(Input, true).takeError()),
"'zcf' is only supported for 'rv32'");
}
+
+ for (StringRef Input : {"rv64efd", "rv32efd", "rv64ed", "rv32ed"}) {
+EXPECT_EQ(toString(RISCVISAInfo::parseArchString(Input, true).takeError()),
+ "'e' extension is incompatible with 'f' extension"
+ " and 'd' extension");
+ }
+
+ for (StringRef Input : {"rv64ef", "rv32ef"}) {
+EXPECT_EQ(toString(RISCVISAInfo::parseArchString(Input, true).takeError()),
+ "'e' extension is incompatible with 'f' extension");
+ }
}
TEST(ToFeatureVector, IIsDroppedAndExperimentalExtensionsArePrefixed) {
Index: llvm/test/MC/RISCV/target-abi-invalid.s
===
--- llvm/test/MC/RISCV/target-abi-invalid.s
+++ llvm/test/MC/RISCV/target-abi-invalid.s
@@ -28,10 +28,6 @@
# RUN: | FileCheck -check-prefix=RV32IFD-LP64D %s
# RUN: llvm-mc -triple=riscv32 -mattr=+e -target-abi lp64 < %s 2>&1 \
# RUN: | FileCheck -check-prefix=RV32E-LP64 %s
-# RUN: llvm-mc -triple=riscv32 -mattr=+e,+f -target-abi lp64f < %s 2>&1 \
-# RUN: | FileCheck -check-prefix=RV32EF-LP64F %s
-# RUN: llvm-mc -triple=riscv32 -mattr=+e,+d -target-abi lp64f < %s 2>&1 \
-# RUN: | FileCheck -check-prefix=RV32EFD-LP64D %s
# RUN: llvm-mc -triple=riscv32 -mattr=+e -target-abi lp64e %s 2>&1 \
# RUN: | FileCheck -check-prefix=RV32E-LP64E %s
@@ -39,8 +35,6 @@
# RV32IF-LP64F: 64-bit ABIs are not supported for 32-bit targets (ignoring target-abi)
# RV32IFD-LP64D: 64-bit ABIs are not supported for 32-bit targets (ignoring target-abi)
# RV32E-LP64: 64-bit ABIs are not supported for 32-bit targets (ignoring target-abi)
-# RV32EF-LP64F: 64-bit ABIs are not supported for 32-bit targets (ignoring target-abi)
-# RV32EFD-LP64D: 64-bit ABIs are not supported for 32-bit targets (ignoring target-abi)
# RV32E-LP64E: 64-bit ABIs are not supported for 32-bit targets (ignoring target-abi)
# RUN: llvm-mc -triple=riscv32 -target-abi ilp32f < %s 2>&1 \
@@ -66,31 +60,13 @@
# RV64IF-LP64D: Hard-float 'd' ABI can't be used for a target that doesn't support the D instruction set extension (ignoring target-abi)
# RUN: llvm-mc -triple=riscv32 -mattr=+e -target-abi ilp32 < %s 2>&1 \
-# RUN: | FileCheck -check-prefix=RV32EF-ILP32F %s
-# RUN: llvm-mc -triple=riscv32 -mattr=+e,+f -target-abi ilp32f < %s 2>&1 \
-# RUN: | FileCheck -check-prefix=RV32EF-ILP32F %s
-# RUN: llvm-mc -triple=riscv32 -mattr=+e,+d -target-abi ilp32f < %s 2>&1 \
-# RUN: | FileCheck -check-prefix=RV32EFD-ILP32F %s
-# RUN: llvm-mc -triple=riscv32 -mattr=+e,+d -target-abi ilp32d < %s 2>&1 \
-# RUN: | FileCheck -check-prefix=RV32EFD-ILP32D %s
+# RUN: | FileCheck -check-prefix=RV32E-ILP32 %s
# RV32E-ILP32: Only the ilp32e ABI is supported for RV32E (ignoring target-abi)
-# RV32EF-ILP32F: Only the ilp32e ABI is supported for RV32E (ignoring target-abi)
-# RV32EFD-ILP32F: Only the ilp32e ABI is supported for RV32E (ignoring target-abi)
-# RV32EFD-ILP32D: Only the ilp32e ABI is supported for RV32E (ignoring target-abi)
# RUN: llvm-mc -triple=riscv64 -mattr=+e -target-abi lp64 < %s 2>&1 \
-# RUN: | FileCheck -check-prefix=RV64EF-LP64F %s
-# RUN: llvm-mc -triple=riscv64 -mattr=+e,+f -target-abi lp64f < %s 2>&1 \
-# RUN: | FileCheck -check-prefix=RV64EF-LP64F %s
-# RUN: llvm-mc -triple=riscv64 -mattr=+e,+d -target-abi lp64f < %s 2>&1 \
-# RUN: | FileCheck -check-prefix=RV64EFD-LP64F %s
-# RUN: llvm-mc -triple=riscv64 -mattr=+e,+d -target-abi lp64d < %s 2>&1 \
-# RUN: | FileCheck -check-prefix=RV64EFD-LP64D %s
+# RUN: | FileCheck -check-prefix=RV64E-LP64 %s
# RV64E-LP64: Only the lp64e ABI is supported for RV64E (ignoring target-abi)
-# RV64EF-LP64F: Only the lp64e ABI is supported for RV64E (ignoring target-abi)
-# RV64EFD-LP64F: Only the lp64e ABI is supported for RV64E (ignoring target-abi)
-# RV64EFD-LP64D: Only the lp64e ABI is supported for RV64E (ignoring target-abi)
nop
Index: llvm/lib/Support/RISCVISAInfo.cpp
===
--- llvm/lib/Support/RISCVISAInfo.cpp
+++ llvm/lib/Support/RISCVISAInfo.cpp
@@ -895,6 +895,7 @@
Error RISCVISAInfo::checkDependency() {
bool HasC = Exts.count("c") != 0;
bool HasF =
[PATCH] D156214: [LLVM][RISCV] Check more extension dependencies
imkiva created this revision.
imkiva added a reviewer: craig.topper.
imkiva added a project: LLVM.
Herald added subscribers: jobnoorman, luke, VincentWu, vkmr, frasercrmck,
luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei,
PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27,
shiva0217, kito-cheng, niosHD, sabuasal, simoncook, johnrusso, rbar, asb,
hiraditya, arichardson.
Herald added a project: All.
imkiva requested review of this revision.
Herald added subscribers: llvm-commits, cfe-commits, wangpc, eopXD, MaskRay.
Herald added a project: clang.
This patch addresses two TODOs in `RISCVISAInfo::checkDependency`:
- Report error when both `e` and `f` (or `d`) extensions are specified in
`-march`
- Report error when `q` extension is specified when `rv64` is unavailable
- Corresponding unit tests are also updated
Currently, I cannot add a test about the `q` extension case because there's no
`q` extension registered in either supported extensions or experimental
extensions,
but the code added here should work fine if we have a proper `q` implementation
in the future.
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D156214
Files:
clang/test/Driver/riscv-arch.c
llvm/lib/Support/RISCVISAInfo.cpp
llvm/unittests/Support/RISCVISAInfoTest.cpp
Index: llvm/unittests/Support/RISCVISAInfoTest.cpp
===
--- llvm/unittests/Support/RISCVISAInfoTest.cpp
+++ llvm/unittests/Support/RISCVISAInfoTest.cpp
@@ -474,6 +474,17 @@
EXPECT_EQ(toString(RISCVISAInfo::parseArchString(Input, true).takeError()),
"'zcf' is only supported for 'rv32'");
}
+
+ for (StringRef Input : {"rv64efd", "rv32efd", "rv64ed", "rv32ed"}) {
+EXPECT_EQ(toString(RISCVISAInfo::parseArchString(Input, true).takeError()),
+ "'e' extension is incompatible with 'f' extension"
+ " and 'd' extension");
+ }
+
+ for (StringRef Input : {"rv64ef", "rv32ef"}) {
+EXPECT_EQ(toString(RISCVISAInfo::parseArchString(Input, true).takeError()),
+ "'e' extension is incompatible with 'f' extension");
+ }
}
TEST(ToFeatureVector, IIsDroppedAndExperimentalExtensionsArePrefixed) {
Index: llvm/lib/Support/RISCVISAInfo.cpp
===
--- llvm/lib/Support/RISCVISAInfo.cpp
+++ llvm/lib/Support/RISCVISAInfo.cpp
@@ -895,6 +895,7 @@
Error RISCVISAInfo::checkDependency() {
bool HasC = Exts.count("c") != 0;
bool HasF = Exts.count("f") != 0;
+ bool HasD = Exts.count("d") != 0;
bool HasZfinx = Exts.count("zfinx") != 0;
bool HasVector = Exts.count("zve32x") != 0;
bool HasZvl = MinVLen != 0;
@@ -931,7 +932,7 @@
errc::invalid_argument,
"'zvknhb' requires 'v' or 'zve64*' extension to also be specified");
- if ((HasZcmt || Exts.count("zcmp")) && Exts.count("d") &&
+ if ((HasZcmt || Exts.count("zcmp")) && HasD &&
(HasC || Exts.count("zcd")))
return createStringError(
errc::invalid_argument,
@@ -944,8 +945,17 @@
"'zcf' is only supported for 'rv32'");
// Additional dependency checks.
- // TODO: The 'q' extension requires rv64.
- // TODO: It is illegal to specify 'e' extensions with 'f' and 'd'.
+ // The 'q' extension requires rv64.
+ if (XLen != 64 && Exts.count("q"))
+return createStringError(errc::invalid_argument,
+ "'q' extension is only supported for 'rv64'");
+
+ // It is illegal to specify 'e' extensions with 'f' and 'd'.
+ if (Exts.count("e") && (HasF || HasD))
+return createStringError(
+errc::invalid_argument,
+Twine("'e' extension is incompatible with ") +
+(HasD ? "'f' extension and 'd' extension" : "'f' extension"));
return Error::success();
}
Index: clang/test/Driver/riscv-arch.c
===
--- clang/test/Driver/riscv-arch.c
+++ clang/test/Driver/riscv-arch.c
@@ -541,3 +541,14 @@
// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-D-ZDINX-ER %s
// RV32-D-ZDINX-ER: error: invalid arch name 'rv32idzdinx',
// RV32-D-ZFINX-ER: 'f' and 'zfinx' extensions are incompatible
+
+// RUN: %clang --target=riscv32-unknown-elf -march=rv32ef -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-EF-BADVARS %s
+// RV32-EF-BADVARS: error: invalid arch name 'rv32ef',
+// RV32-EF-BADVARS: 'e' extension is incompatible with 'f' extension
+
+// RUN: %clang --target=riscv32-unknown-elf -march=rv32ed -### %s \
+// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-ED-BADVARS %s
+// RV32-ED-BADVARS: error: invalid arch name 'rv32ed',
+// RV32-ED-BADVARS: 'e' extension is incompatible with 'f' extension and 'd'
extension
+
Index: llvm/unittests/Support/RISCVISAInfoTest.cpp
===
---
