[PATCH] D158259: [clang][RISCV] Support operators for RVV sizeless vector types

2023-10-31 Thread Craig Topper via Phabricator via cfe-commits 
craig.topper added a comment.

Need to update the table here 
https://clang.llvm.org/docs/LanguageExtensions.html#vector-operations to 
include RVV


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[PATCH] D158259: [clang][RISCV] Support operators for RVV sizeless vector types

2023-09-06 Thread Jianjian Guan via Phabricator via cfe-commits 
jacquesguan marked an inline comment as done.
jacquesguan added a comment.

ping.


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[PATCH] D158259: [clang][RISCV] Support operators for RVV sizeless vector types

2023-08-22 Thread Jianjian Guan via Phabricator via cfe-commits 
jacquesguan marked an inline comment as done.
jacquesguan added inline comments.



Comment at: clang/test/CodeGen/riscv-rvv-vla-arith-ops.c:90
+//
+vfloat32m1_t add_f32(vfloat32m1_t a, vfloat32m1_t b) {
+  return a + b;

Jim wrote:
> Do we support operation for vfloat16 here?
Thanks to point it. I added fp16 vector cases.


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[PATCH] D158259: [clang][RISCV] Support operators for RVV sizeless vector types

2023-08-21 Thread Jim Lin via Phabricator via cfe-commits 
Jim added inline comments.



Comment at: clang/test/CodeGen/riscv-rvv-vla-arith-ops.c:3
+// RUN: %clang_cc1 -triple riscv64-none-linux-gnu -target-feature +zve64d \
+// RUN: -target-feature +f -target-feature +d -disable-O0-optnone \
+// RUN: -mvscale-min=4 -mvscale-max=4 -emit-llvm -o - %s | \

Jim wrote:
> zve64d has implied f and d.
I misunderstand it. Please ignore the comment.


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[PATCH] D158259: [clang][RISCV] Support operators for RVV sizeless vector types

2023-08-21 Thread Jim Lin via Phabricator via cfe-commits 
Jim added inline comments.



Comment at: clang/test/CodeGen/riscv-rvv-vla-arith-ops.c:3
+// RUN: %clang_cc1 -triple riscv64-none-linux-gnu -target-feature +zve64d \
+// RUN: -target-feature +f -target-feature +d -disable-O0-optnone \
+// RUN: -mvscale-min=4 -mvscale-max=4 -emit-llvm -o - %s | \

zve64d has implied f and d.



Comment at: clang/test/CodeGen/riscv-rvv-vla-arith-ops.c:90
+//
+vfloat32m1_t add_f32(vfloat32m1_t a, vfloat32m1_t b) {
+  return a + b;

Do we support operation for vfloat16 here?


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[PATCH] D158259: [clang][RISCV] Support operators for RVV sizeless vector types

2023-08-20 Thread Jianjian Guan via Phabricator via cfe-commits 
jacquesguan marked an inline comment as done.
jacquesguan added inline comments.



Comment at: clang/lib/Sema/SemaChecking.cpp:14906
+// specified
+if (S.Context.areCompatibleRVVTypes(QualType(OriginalTarget, 0),
+QualType(Source, 0)) ||

craig.topper wrote:
> Why do we need this, but SVE doesn't?
Merged with the former sve function.



Comment at: clang/lib/Sema/SemaExpr.cpp:12294
 
+  if ((LHSBuiltinTy && LHSBuiltinTy->isSVEBool()) ||
+  (RHSBuiltinTy && RHSBuiltinTy->isSVEBool())) {

craig.topper wrote:
> This code looks identical to the code above it.
Removed.



Comment at: clang/lib/Sema/SemaExpr.cpp:16322
   break;
-else if (resultType->isSveVLSBuiltinType()) // SVE vectors allow + and -
+else if (resultType->isVLSBuiltinType()) // SVE vectors allow + and -
   break;

craig.topper wrote:
> Update "SVE" to mention "RVV" too?
Done.


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[PATCH] D158259: [clang][RISCV] Support operators for RVV sizeless vector types

2023-08-18 Thread Craig Topper via Phabricator via cfe-commits 
craig.topper added inline comments.



Comment at: clang/lib/Sema/SemaChecking.cpp:14906
+// specified
+if (S.Context.areCompatibleRVVTypes(QualType(OriginalTarget, 0),
+QualType(Source, 0)) ||

Why do we need this, but SVE doesn't?



Comment at: clang/lib/Sema/SemaExpr.cpp:12294
 
+  if ((LHSBuiltinTy && LHSBuiltinTy->isSVEBool()) ||
+  (RHSBuiltinTy && RHSBuiltinTy->isSVEBool())) {

This code looks identical to the code above it.



Comment at: clang/lib/Sema/SemaExpr.cpp:16322
   break;
-else if (resultType->isSveVLSBuiltinType()) // SVE vectors allow + and -
+else if (resultType->isVLSBuiltinType()) // SVE vectors allow + and -
   break;

Update "SVE" to mention "RVV" too?


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