[PATCH] D158824: [RISCV][MC] MC layer support for xcvmem and xcvelw extensions
This revision was automatically updated to reflect the committed changes. Closed by commit rG71a7108ee91a: [RISCV][MC] MC layer support for xcvmem and xcvelw extensions (authored by liaolucy). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D158824/new/ https://reviews.llvm.org/D158824 Files: clang/test/Preprocessor/riscv-target-features.c llvm/docs/RISCVUsage.rst llvm/lib/Support/RISCVISAInfo.cpp llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.h llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp llvm/lib/Target/RISCV/RISCVFeatures.td llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td llvm/test/CodeGen/RISCV/attributes.ll llvm/test/MC/RISCV/attribute-arch.s llvm/test/MC/RISCV/corev/XCVelw-invalid.s llvm/test/MC/RISCV/corev/XCVelw-valid.s llvm/test/MC/RISCV/corev/XCVmem-invalid.s llvm/test/MC/RISCV/corev/XCVmem-valid.s llvm/unittests/Support/RISCVISAInfoTest.cpp Index: llvm/unittests/Support/RISCVISAInfoTest.cpp === --- llvm/unittests/Support/RISCVISAInfoTest.cpp +++ llvm/unittests/Support/RISCVISAInfoTest.cpp @@ -712,7 +712,9 @@ xcvalu 1.0 xcvbi 1.0 xcvbitmanip 1.0 +xcvelw 1.0 xcvmac 1.0 +xcvmem 1.0 xcvsimd 1.0 xsfcie 1.0 xsfvcp 1.0 Index: llvm/test/MC/RISCV/corev/XCVmem-valid.s === --- /dev/null +++ llvm/test/MC/RISCV/corev/XCVmem-valid.s @@ -0,0 +1,247 @@ +# RUN: llvm-mc -triple=riscv32 --mattr=+xcvmem -show-encoding %s \ +# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INSTR +# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+xcvmem < %s \ +# RUN: | llvm-objdump --mattr=+xcvmem -M no-aliases -d -r - \ +# RUN: | FileCheck --check-prefix=CHECK-INSTR %s +# RUN: not llvm-mc -triple riscv32 %s 2>&1 \ +# RUN: | FileCheck -check-prefix=CHECK-NO-EXT %s + +cv.lb t0, (t1), 0 +# CHECK-INSTR: cv.lb t0, (t1), 0 +# CHECK-ENCODING: [0x8b,0x02,0x03,0x00] +# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}} + +cv.lb a0, (a1), 2047 +# CHECK-INSTR: cv.lb a0, (a1), 2047 +# CHECK-ENCODING: [0x0b,0x85,0xf5,0x7f] +# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}} + +cv.lb t0, (t1), t2 +# CHECK-INSTR: cv.lb t0, (t1), t2 +# CHECK-ENCODING: [0xab,0x32,0x73,0x00] +# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}} + +cv.lb a0, (a1), a2 +# CHECK-INSTR: cv.lb a0, (a1), a2 +# CHECK-ENCODING: [0x2b,0xb5,0xc5,0x00] +# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}} + +cv.lb t0, t2(t1) +# CHECK-INSTR: cv.lb t0, t2(t1) +# CHECK-ENCODING: [0xab,0x32,0x73,0x08] +# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}} + +cv.lb a0, a2(a1) +# CHECK-INSTR: cv.lb a0, a2(a1) +# CHECK-ENCODING: [0x2b,0xb5,0xc5,0x08] +# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}} + +cv.lbu t0, (t1), 0 +# CHECK-INSTR: cv.lbu t0, (t1), 0 +# CHECK-ENCODING: [0x8b,0x42,0x03,0x00] +# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}} + +cv.lbu a0, (a1), 2047 +# CHECK-INSTR: cv.lbu a0, (a1), 2047 +# CHECK-ENCODING: [0x0b,0xc5,0xf5,0x7f] +# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}} + +cv.lbu t0, (t1), t2 +# CHECK-INSTR: cv.lbu t0, (t1), t2 +# CHECK-ENCODING: [0xab,0x32,0x73,0x10] +# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}} + +cv.lbu a0, (a1), a2 +# CHECK-INSTR: cv.lbu a0, (a1), a2 +# CHECK-ENCODING: [0x2b,0xb5,0xc5,0x10] +# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}} + +cv.lbu t0, t2(t1) +# CHECK-INSTR: cv.lbu t0, t2(t1) +# CHECK-ENCODING: [0xab,0x32,0x73,0x18] +# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}} + +cv.lbu a0, a2(a1) +# CHECK-INSTR: cv.lbu a0, a2(a1) +# CHECK-ENCODING: [0x2b,0xb5,0xc5,0x18] +# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}} + +cv.lh t0, (t1), 0 +# CHECK-INSTR: cv.lh t0, (t1), 0 +# CHECK-ENCODING: [0x8b,0x12,0x03,0x00] +# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}} + +cv.lh a0, (a1), 2047 +# CHECK-INSTR: cv.lh a0, (a1), 2047 +# CHECK-ENCODING: [0x0b,0x95,0xf5,0
[PATCH] D158824: [RISCV][MC] MC layer support for xcvmem and xcvelw extensions
craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D158824/new/ https://reviews.llvm.org/D158824 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D158824: [RISCV][MC] MC layer support for xcvmem and xcvelw extensions
liaolucy updated this revision to Diff 558107. liaolucy added a comment. 1. use a custom parser to parse Register-Register load/store 2. Rebase Thanks Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D158824/new/ https://reviews.llvm.org/D158824 Files: clang/test/Preprocessor/riscv-target-features.c llvm/docs/RISCVUsage.rst llvm/lib/Support/RISCVISAInfo.cpp llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.h llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp llvm/lib/Target/RISCV/RISCVFeatures.td llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td llvm/test/CodeGen/RISCV/attributes.ll llvm/test/MC/RISCV/attribute-arch.s llvm/test/MC/RISCV/corev/XCVelw-invalid.s llvm/test/MC/RISCV/corev/XCVelw-valid.s llvm/test/MC/RISCV/corev/XCVmem-invalid.s llvm/test/MC/RISCV/corev/XCVmem-valid.s llvm/unittests/Support/RISCVISAInfoTest.cpp Index: llvm/unittests/Support/RISCVISAInfoTest.cpp === --- llvm/unittests/Support/RISCVISAInfoTest.cpp +++ llvm/unittests/Support/RISCVISAInfoTest.cpp @@ -712,7 +712,9 @@ xcvalu 1.0 xcvbi 1.0 xcvbitmanip 1.0 +xcvelw 1.0 xcvmac 1.0 +xcvmem 1.0 xcvsimd 1.0 xsfcie 1.0 xsfvcp 1.0 Index: llvm/test/MC/RISCV/corev/XCVmem-valid.s === --- /dev/null +++ llvm/test/MC/RISCV/corev/XCVmem-valid.s @@ -0,0 +1,247 @@ +# RUN: llvm-mc -triple=riscv32 --mattr=+xcvmem -show-encoding %s \ +# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INSTR +# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+xcvmem < %s \ +# RUN: | llvm-objdump --mattr=+xcvmem -M no-aliases -d -r - \ +# RUN: | FileCheck --check-prefix=CHECK-INSTR %s +# RUN: not llvm-mc -triple riscv32 %s 2>&1 \ +# RUN: | FileCheck -check-prefix=CHECK-NO-EXT %s + +cv.lb t0, (t1), 0 +# CHECK-INSTR: cv.lb t0, (t1), 0 +# CHECK-ENCODING: [0x8b,0x02,0x03,0x00] +# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}} + +cv.lb a0, (a1), 2047 +# CHECK-INSTR: cv.lb a0, (a1), 2047 +# CHECK-ENCODING: [0x0b,0x85,0xf5,0x7f] +# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}} + +cv.lb t0, (t1), t2 +# CHECK-INSTR: cv.lb t0, (t1), t2 +# CHECK-ENCODING: [0xab,0x32,0x73,0x00] +# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}} + +cv.lb a0, (a1), a2 +# CHECK-INSTR: cv.lb a0, (a1), a2 +# CHECK-ENCODING: [0x2b,0xb5,0xc5,0x00] +# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}} + +cv.lb t0, t2(t1) +# CHECK-INSTR: cv.lb t0, t2(t1) +# CHECK-ENCODING: [0xab,0x32,0x73,0x08] +# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}} + +cv.lb a0, a2(a1) +# CHECK-INSTR: cv.lb a0, a2(a1) +# CHECK-ENCODING: [0x2b,0xb5,0xc5,0x08] +# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}} + +cv.lbu t0, (t1), 0 +# CHECK-INSTR: cv.lbu t0, (t1), 0 +# CHECK-ENCODING: [0x8b,0x42,0x03,0x00] +# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}} + +cv.lbu a0, (a1), 2047 +# CHECK-INSTR: cv.lbu a0, (a1), 2047 +# CHECK-ENCODING: [0x0b,0xc5,0xf5,0x7f] +# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}} + +cv.lbu t0, (t1), t2 +# CHECK-INSTR: cv.lbu t0, (t1), t2 +# CHECK-ENCODING: [0xab,0x32,0x73,0x10] +# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}} + +cv.lbu a0, (a1), a2 +# CHECK-INSTR: cv.lbu a0, (a1), a2 +# CHECK-ENCODING: [0x2b,0xb5,0xc5,0x10] +# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}} + +cv.lbu t0, t2(t1) +# CHECK-INSTR: cv.lbu t0, t2(t1) +# CHECK-ENCODING: [0xab,0x32,0x73,0x18] +# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}} + +cv.lbu a0, a2(a1) +# CHECK-INSTR: cv.lbu a0, a2(a1) +# CHECK-ENCODING: [0x2b,0xb5,0xc5,0x18] +# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}} + +cv.lh t0, (t1), 0 +# CHECK-INSTR: cv.lh t0, (t1), 0 +# CHECK-ENCODING: [0x8b,0x12,0x03,0x00] +# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}} + +cv.lh a0, (a1), 2047 +# CHECK-INSTR: cv.lh a0, (a1), 2047 +# CHECK-ENCODING: [0x0b,0x95,0xf5,0x7f] +# CHECK-NO-EXT: instruction requir
[PATCH] D158824: [RISCV][MC] MC layer support for xcvmem and xcvelw extensions
craig.topper added inline comments. Comment at: llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp:2509 // Attempt to parse token as a register. - if (parseRegister(Operands, true).isSuccess()) + if (parseRegister(Operands, true).isSuccess()) { +// Parse memory base register if present (CORE-V only) Is it possible to use a custom parser instead of adding a special case to the generic parser? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D158824/new/ https://reviews.llvm.org/D158824 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D158824: [RISCV][MC] MC layer support for xcvmem and xcvelw extensions
liaolucy added a comment. ping Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D158824/new/ https://reviews.llvm.org/D158824 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D158824: [RISCV][MC] MC layer support for xcvmem and xcvelw extensions
liaolucy updated this revision to Diff 556222. liaolucy added a comment. 1. Rebase. 2. Update RISCVISAInfoTest.cpp Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D158824/new/ https://reviews.llvm.org/D158824 Files: clang/test/Preprocessor/riscv-target-features.c llvm/docs/RISCVUsage.rst llvm/lib/Support/RISCVISAInfo.cpp llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp llvm/lib/Target/RISCV/RISCVFeatures.td llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td llvm/test/CodeGen/RISCV/attributes.ll llvm/test/MC/RISCV/attribute-arch.s llvm/test/MC/RISCV/corev/XCVelw-invalid.s llvm/test/MC/RISCV/corev/XCVelw-valid.s llvm/test/MC/RISCV/corev/XCVmem-invalid.s llvm/test/MC/RISCV/corev/XCVmem-valid.s llvm/unittests/Support/RISCVISAInfoTest.cpp Index: llvm/unittests/Support/RISCVISAInfoTest.cpp === --- llvm/unittests/Support/RISCVISAInfoTest.cpp +++ llvm/unittests/Support/RISCVISAInfoTest.cpp @@ -707,7 +707,9 @@ xcvalu 1.0 xcvbi 1.0 xcvbitmanip 1.0 + xcvelw 1.0 xcvmac 1.0 + xcvmem 1.0 xcvsimd 1.0 xsfcie 1.0 xsfvcp 1.0 Index: llvm/test/MC/RISCV/corev/XCVmem-valid.s === --- /dev/null +++ llvm/test/MC/RISCV/corev/XCVmem-valid.s @@ -0,0 +1,247 @@ +# RUN: llvm-mc -triple=riscv32 --mattr=+xcvmem -show-encoding %s \ +# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INSTR +# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+xcvmem < %s \ +# RUN: | llvm-objdump --mattr=+xcvmem -M no-aliases -d -r - \ +# RUN: | FileCheck --check-prefix=CHECK-INSTR %s +# RUN: not llvm-mc -triple riscv32 %s 2>&1 \ +# RUN: | FileCheck -check-prefix=CHECK-NO-EXT %s + +cv.lb t0, (t1), 0 +# CHECK-INSTR: cv.lb t0, (t1), 0 +# CHECK-ENCODING: [0x8b,0x02,0x03,0x00] +# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}} + +cv.lb a0, (a1), 2047 +# CHECK-INSTR: cv.lb a0, (a1), 2047 +# CHECK-ENCODING: [0x0b,0x85,0xf5,0x7f] +# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}} + +cv.lb t0, (t1), t2 +# CHECK-INSTR: cv.lb t0, (t1), t2 +# CHECK-ENCODING: [0xab,0x32,0x73,0x00] +# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}} + +cv.lb a0, (a1), a2 +# CHECK-INSTR: cv.lb a0, (a1), a2 +# CHECK-ENCODING: [0x2b,0xb5,0xc5,0x00] +# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}} + +cv.lb t0, t2(t1) +# CHECK-INSTR: cv.lb t0, t2(t1) +# CHECK-ENCODING: [0xab,0x32,0x73,0x08] +# CHECK-NO-EXT: unexpected token + +cv.lb a0, a2(a1) +# CHECK-INSTR: cv.lb a0, a2(a1) +# CHECK-ENCODING: [0x2b,0xb5,0xc5,0x08] +# CHECK-NO-EXT: unexpected token + +cv.lbu t0, (t1), 0 +# CHECK-INSTR: cv.lbu t0, (t1), 0 +# CHECK-ENCODING: [0x8b,0x42,0x03,0x00] +# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}} + +cv.lbu a0, (a1), 2047 +# CHECK-INSTR: cv.lbu a0, (a1), 2047 +# CHECK-ENCODING: [0x0b,0xc5,0xf5,0x7f] +# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}} + +cv.lbu t0, (t1), t2 +# CHECK-INSTR: cv.lbu t0, (t1), t2 +# CHECK-ENCODING: [0xab,0x32,0x73,0x10] +# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}} + +cv.lbu a0, (a1), a2 +# CHECK-INSTR: cv.lbu a0, (a1), a2 +# CHECK-ENCODING: [0x2b,0xb5,0xc5,0x10] +# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}} + +cv.lbu t0, t2(t1) +# CHECK-INSTR: cv.lbu t0, t2(t1) +# CHECK-ENCODING: [0xab,0x32,0x73,0x18] +# CHECK-NO-EXT: unexpected token + +cv.lbu a0, a2(a1) +# CHECK-INSTR: cv.lbu a0, a2(a1) +# CHECK-ENCODING: [0x2b,0xb5,0xc5,0x18] +# CHECK-NO-EXT: unexpected token + +cv.lh t0, (t1), 0 +# CHECK-INSTR: cv.lh t0, (t1), 0 +# CHECK-ENCODING: [0x8b,0x12,0x03,0x00] +# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}} + +cv.lh a0, (a1), 2047 +# CHECK-INSTR: cv.lh a0, (a1), 2047 +# CHECK-ENCODING: [0x0b,0x95,0xf5,0x7f] +# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}} + +cv.lh t0, (t1), t2 +# CHECK-INSTR: cv.lh t0, (t1), t2 +# CHECK-ENCODING: [0xab,0x32,0x73,0x02] +# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}} + +cv.lh a0, (a1), a2 +# CHECK-INSTR: cv.lh a0, (a1), a2 +# CHECK-ENCODING: [0x2b,0xb5,0xc5,0x02] +# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}} + +cv.lh t0, t2(t1) +# CHECK-INSTR: cv.lh t0, t2
[PATCH] D158824: [RISCV][MC] MC layer support for xcvmem and xcvelw extensions
liaolucy updated this revision to Diff 553911. liaolucy added a comment. Herald added a project: clang. Herald added a subscriber: cfe-commits. Address comments from Jim, thanks. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D158824/new/ https://reviews.llvm.org/D158824 Files: clang/test/Preprocessor/riscv-target-features.c llvm/docs/RISCVUsage.rst llvm/lib/Support/RISCVISAInfo.cpp llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp llvm/lib/Target/RISCV/RISCVFeatures.td llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td llvm/test/CodeGen/RISCV/attributes.ll llvm/test/MC/RISCV/attribute-arch.s llvm/test/MC/RISCV/corev/XCVelw-invalid.s llvm/test/MC/RISCV/corev/XCVelw-valid.s llvm/test/MC/RISCV/corev/XCVmem-invalid.s llvm/test/MC/RISCV/corev/XCVmem-valid.s Index: llvm/test/MC/RISCV/corev/XCVmem-valid.s === --- /dev/null +++ llvm/test/MC/RISCV/corev/XCVmem-valid.s @@ -0,0 +1,247 @@ +# RUN: llvm-mc -triple=riscv32 --mattr=+xcvmem -show-encoding %s \ +# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INSTR +# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+xcvmem < %s \ +# RUN: | llvm-objdump --mattr=+xcvmem -M no-aliases -d -r - \ +# RUN: | FileCheck --check-prefix=CHECK-INSTR %s +# RUN: not llvm-mc -triple riscv32 %s 2>&1 \ +# RUN: | FileCheck -check-prefix=CHECK-NO-EXT %s + +cv.lb t0, (t1), 0 +# CHECK-INSTR: cv.lb t0, (t1), 0 +# CHECK-ENCODING: [0x8b,0x02,0x03,0x00] +# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}} + +cv.lb a0, (a1), 2047 +# CHECK-INSTR: cv.lb a0, (a1), 2047 +# CHECK-ENCODING: [0x0b,0x85,0xf5,0x7f] +# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}} + +cv.lb t0, (t1), t2 +# CHECK-INSTR: cv.lb t0, (t1), t2 +# CHECK-ENCODING: [0xab,0x32,0x73,0x00] +# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}} + +cv.lb a0, (a1), a2 +# CHECK-INSTR: cv.lb a0, (a1), a2 +# CHECK-ENCODING: [0x2b,0xb5,0xc5,0x00] +# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}} + +cv.lb t0, t2(t1) +# CHECK-INSTR: cv.lb t0, t2(t1) +# CHECK-ENCODING: [0xab,0x32,0x73,0x08] +# CHECK-NO-EXT: unexpected token + +cv.lb a0, a2(a1) +# CHECK-INSTR: cv.lb a0, a2(a1) +# CHECK-ENCODING: [0x2b,0xb5,0xc5,0x08] +# CHECK-NO-EXT: unexpected token + +cv.lbu t0, (t1), 0 +# CHECK-INSTR: cv.lbu t0, (t1), 0 +# CHECK-ENCODING: [0x8b,0x42,0x03,0x00] +# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}} + +cv.lbu a0, (a1), 2047 +# CHECK-INSTR: cv.lbu a0, (a1), 2047 +# CHECK-ENCODING: [0x0b,0xc5,0xf5,0x7f] +# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}} + +cv.lbu t0, (t1), t2 +# CHECK-INSTR: cv.lbu t0, (t1), t2 +# CHECK-ENCODING: [0xab,0x32,0x73,0x10] +# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}} + +cv.lbu a0, (a1), a2 +# CHECK-INSTR: cv.lbu a0, (a1), a2 +# CHECK-ENCODING: [0x2b,0xb5,0xc5,0x10] +# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}} + +cv.lbu t0, t2(t1) +# CHECK-INSTR: cv.lbu t0, t2(t1) +# CHECK-ENCODING: [0xab,0x32,0x73,0x18] +# CHECK-NO-EXT: unexpected token + +cv.lbu a0, a2(a1) +# CHECK-INSTR: cv.lbu a0, a2(a1) +# CHECK-ENCODING: [0x2b,0xb5,0xc5,0x18] +# CHECK-NO-EXT: unexpected token + +cv.lh t0, (t1), 0 +# CHECK-INSTR: cv.lh t0, (t1), 0 +# CHECK-ENCODING: [0x8b,0x12,0x03,0x00] +# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}} + +cv.lh a0, (a1), 2047 +# CHECK-INSTR: cv.lh a0, (a1), 2047 +# CHECK-ENCODING: [0x0b,0x95,0xf5,0x7f] +# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}} + +cv.lh t0, (t1), t2 +# CHECK-INSTR: cv.lh t0, (t1), t2 +# CHECK-ENCODING: [0xab,0x32,0x73,0x02] +# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}} + +cv.lh a0, (a1), a2 +# CHECK-INSTR: cv.lh a0, (a1), a2 +# CHECK-ENCODING: [0x2b,0xb5,0xc5,0x02] +# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}} + +cv.lh t0, t2(t1) +# CHECK-INSTR: cv.lh t0, t2(t1) +# CHECK-ENCODING: [0xab,0x32,0x73,0x0a] +# CHECK-NO-EXT: unexpected token + +cv.lh a0, a2(a1) +# CHECK-INSTR: cv.lh a0, a2(a1) +# CHECK-ENCODING: [0x2b,0xb5,0xc5,0x0a] +# CHECK-NO-EXT: unexpected token + +cv.lhu t0, (t1), 0 +# CHECK-INSTR: cv.lhu t0, (t1), 0 +# CHECK-ENCODING: [0x8b,0x52,0x03,0x00] +# CHECK-NO-EXT: instruction requires the following: 'XCVmem' (CORE-V Post-incrementing Load & Store){{$}} + +cv.lhu a0, (a1), 2047 +# CHECK-INST