[PATCH] D45668: [NEON] Define vget_high_f16() and vget_low_f16() intrinsics in AArch64 mode only
kosarev added a comment. Thanks Sjoerd and James. Just added a comment referring to this revision in https://reviews.llvm.org/rL330420. Repository: rL LLVM https://reviews.llvm.org/D45668 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D45668: [NEON] Define vget_high_f16() and vget_low_f16() intrinsics in AArch64 mode only
SjoerdMeijer added a comment. Thanks James! Repository: rL LLVM https://reviews.llvm.org/D45668 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D45668: [NEON] Define vget_high_f16() and vget_low_f16() intrinsics in AArch64 mode only
jgreenhalgh added a comment. In https://reviews.llvm.org/D45668#1070878, @SjoerdMeijer wrote: > Thanks, and I am going to try to get some clarity on this doc issue. But > looks like it should be "ARMv7, ARMv8", as it used to be. Make sense to > comment on this in the commit message, if that's what you mean. These should be available whenever the float16x4_t and float16x8_t types are available. So v7/A32/A64. I have pushed this change to the docs locally; but I don't know when this will make it to public documentation, so you will just have to take my word for it when I say this is a documentation bug and it will be fixed in a future release. Repository: rL LLVM https://reviews.llvm.org/D45668 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D45668: [NEON] Define vget_high_f16() and vget_low_f16() intrinsics in AArch64 mode only
SjoerdMeijer added a comment. Thanks, and I am going to try to get some clarity on this doc issue. But looks like it should be "ARMv7, ARMv8", as it used to be. Make sense to comment on this in the commit message, if that's what you mean. Repository: rL LLVM https://reviews.llvm.org/D45668 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D45668: [NEON] Define vget_high_f16() and vget_low_f16() intrinsics in AArch64 mode only
kosarev added a comment. Sure, will do. Should we treat these intrinsics as ARMv8 or ARMv7/v8? Also, would you mind if I commit a comment under this differential revision explaining the situation? Repository: rL LLVM https://reviews.llvm.org/D45668 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D45668: [NEON] Define vget_high_f16() and vget_low_f16() intrinsics in AArch64 mode only
SjoerdMeijer added a comment. Sorry, I have second thoughts on this. This seems more like a doc issue than anything else. There is no reason why this could not be supported in A32. GCC is also supporting this, and removing it is a bit user unfriendly. Would you mind reverting this? Repository: rL LLVM https://reviews.llvm.org/D45668 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D45668: [NEON] Define vget_high_f16() and vget_low_f16() intrinsics in AArch64 mode only
This revision was automatically updated to reflect the committed changes.
Closed by commit rL330195: [NEON] Define vget_high_f16() and vget_low_f16()
intrinsics in AArch64 mode only (authored by kosarev, committed by ).
Herald added a subscriber: llvm-commits.
Changed prior to commit:
https://reviews.llvm.org/D45668?vs=142558=142789#toc
Repository:
rL LLVM
https://reviews.llvm.org/D45668
Files:
cfe/trunk/include/clang/Basic/arm_neon.td
cfe/trunk/test/CodeGen/arm_neon_intrinsics.c
Index: cfe/trunk/include/clang/Basic/arm_neon.td
===
--- cfe/trunk/include/clang/Basic/arm_neon.td
+++ cfe/trunk/include/clang/Basic/arm_neon.td
@@ -398,8 +398,14 @@
// E.3.21 Splitting vectors
let InstName = "vmov" in {
-def VGET_HIGH : NoTestOpInst<"vget_high", "dk", "csilhfUcUsUiUlPcPs", OP_HI>;
-def VGET_LOW : NoTestOpInst<"vget_low", "dk", "csilhfUcUsUiUlPcPs", OP_LO>;
+def VGET_HIGH : NoTestOpInst<"vget_high", "dk", "csilfUcUsUiUlPcPs", OP_HI>;
+def VGET_LOW : NoTestOpInst<"vget_low", "dk", "csilfUcUsUiUlPcPs", OP_LO>;
+}
+let ArchGuard = "__ARM_ARCH >= 8 && defined(__aarch64__)" in {
+ let InstName = "vmov" in {
+ def VGET_HIGH_F16 : NoTestOpInst<"vget_high", "dk", "h", OP_HI>;
+ def VGET_LOW_F16 : NoTestOpInst<"vget_low", "dk", "h", OP_LO>;
+ }
}
Index: cfe/trunk/test/CodeGen/arm_neon_intrinsics.c
===
--- cfe/trunk/test/CodeGen/arm_neon_intrinsics.c
+++ cfe/trunk/test/CodeGen/arm_neon_intrinsics.c
@@ -3254,13 +3254,6 @@
return vget_high_s64(a);
}
-// CHECK-LABEL: @test_vget_high_f16(
-// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <8 x half> %a, <8 x half> %a, <4
x i32>
-// CHECK: ret <4 x half> [[SHUFFLE_I]]
-float16x4_t test_vget_high_f16(float16x8_t a) {
- return vget_high_f16(a);
-}
-
// CHECK-LABEL: @test_vget_high_f32(
// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <4 x float> %a, <4 x float> %a,
<2 x i32>
// CHECK: ret <2 x float> [[SHUFFLE_I]]
@@ -3560,13 +3553,6 @@
return vget_low_s64(a);
}
-// CHECK-LABEL: @test_vget_low_f16(
-// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <8 x half> %a, <8 x half> %a, <4
x i32>
-// CHECK: ret <4 x half> [[SHUFFLE_I]]
-float16x4_t test_vget_low_f16(float16x8_t a) {
- return vget_low_f16(a);
-}
-
// CHECK-LABEL: @test_vget_low_f32(
// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <4 x float> %a, <4 x float> %a,
<2 x i32>
// CHECK: ret <2 x float> [[SHUFFLE_I]]
Index: cfe/trunk/include/clang/Basic/arm_neon.td
===
--- cfe/trunk/include/clang/Basic/arm_neon.td
+++ cfe/trunk/include/clang/Basic/arm_neon.td
@@ -398,8 +398,14 @@
// E.3.21 Splitting vectors
let InstName = "vmov" in {
-def VGET_HIGH : NoTestOpInst<"vget_high", "dk", "csilhfUcUsUiUlPcPs", OP_HI>;
-def VGET_LOW : NoTestOpInst<"vget_low", "dk", "csilhfUcUsUiUlPcPs", OP_LO>;
+def VGET_HIGH : NoTestOpInst<"vget_high", "dk", "csilfUcUsUiUlPcPs", OP_HI>;
+def VGET_LOW : NoTestOpInst<"vget_low", "dk", "csilfUcUsUiUlPcPs", OP_LO>;
+}
+let ArchGuard = "__ARM_ARCH >= 8 && defined(__aarch64__)" in {
+ let InstName = "vmov" in {
+ def VGET_HIGH_F16 : NoTestOpInst<"vget_high", "dk", "h", OP_HI>;
+ def VGET_LOW_F16 : NoTestOpInst<"vget_low", "dk", "h", OP_LO>;
+ }
}
Index: cfe/trunk/test/CodeGen/arm_neon_intrinsics.c
===
--- cfe/trunk/test/CodeGen/arm_neon_intrinsics.c
+++ cfe/trunk/test/CodeGen/arm_neon_intrinsics.c
@@ -3254,13 +3254,6 @@
return vget_high_s64(a);
}
-// CHECK-LABEL: @test_vget_high_f16(
-// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <8 x half> %a, <8 x half> %a, <4 x i32>
-// CHECK: ret <4 x half> [[SHUFFLE_I]]
-float16x4_t test_vget_high_f16(float16x8_t a) {
- return vget_high_f16(a);
-}
-
// CHECK-LABEL: @test_vget_high_f32(
// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <4 x float> %a, <4 x float> %a, <2 x i32>
// CHECK: ret <2 x float> [[SHUFFLE_I]]
@@ -3560,13 +3553,6 @@
return vget_low_s64(a);
}
-// CHECK-LABEL: @test_vget_low_f16(
-// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <8 x half> %a, <8 x half> %a, <4 x i32>
-// CHECK: ret <4 x half> [[SHUFFLE_I]]
-float16x4_t test_vget_low_f16(float16x8_t a) {
- return vget_low_f16(a);
-}
-
// CHECK-LABEL: @test_vget_low_f32(
// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <4 x float> %a, <4 x float> %a, <2 x i32>
// CHECK: ret <2 x float> [[SHUFFLE_I]]
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[PATCH] D45668: [NEON] Define vget_high_f16() and vget_low_f16() intrinsics in AArch64 mode only
SjoerdMeijer accepted this revision. SjoerdMeijer added a comment. This revision is now accepted and ready to land. Yep, agreed, also on the new shiny https://developer.arm.com/technologies/neon/intrinsics it is listed as A64 only. https://reviews.llvm.org/D45668 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D45668: [NEON] Define vget_high_f16() and vget_low_f16() intrinsics in AArch64 mode only
kosarev added a comment. The NEON Intrinsics Reference (http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ihi0073a/index.html) reads like they are AArch64-only. https://reviews.llvm.org/D45668 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D45668: [NEON] Define vget_high_f16() and vget_low_f16() intrinsics in AArch64 mode only
SjoerdMeijer added a comment. Not really familiar with these 2 intrinsics, I had a quick look at the ACLE: > T vget_high_ST(T 2 a); > T vget_low_ST(T 2 a); > > Gets the high, or low, half of a 128-bit vector. There are 24 intrinsics. > ARMv8 > adds 4 more intrinsics for 128-bit vectors with float64_t and poly64_t lane > type. I don't read here that they are unavailable in AArch32. Have I missed something? https://reviews.llvm.org/D45668 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D45668: [NEON] Define vget_high_f16() and vget_low_f16() intrinsics in AArch64 mode only
kosarev created this revision.
kosarev added reviewers: t.p.northover, rengolin, SjoerdMeijer.
kosarev added a project: clang.
Herald added subscribers: kristof.beyls, javed.absar.
These are AArch64-specific intrinsics. The patch removes AArch32-mode test
cases and maintains AArch64 ones in
tools/clang/test/CodeGen/aarch64-neon-vget-hilo.c.
https://reviews.llvm.org/D45668
Files:
include/clang/Basic/arm_neon.td
test/CodeGen/arm_neon_intrinsics.c
Index: test/CodeGen/arm_neon_intrinsics.c
===
--- test/CodeGen/arm_neon_intrinsics.c
+++ test/CodeGen/arm_neon_intrinsics.c
@@ -3254,13 +3254,6 @@
return vget_high_s64(a);
}
-// CHECK-LABEL: @test_vget_high_f16(
-// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <8 x half> %a, <8 x half> %a, <4
x i32>
-// CHECK: ret <4 x half> [[SHUFFLE_I]]
-float16x4_t test_vget_high_f16(float16x8_t a) {
- return vget_high_f16(a);
-}
-
// CHECK-LABEL: @test_vget_high_f32(
// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <4 x float> %a, <4 x float> %a,
<2 x i32>
// CHECK: ret <2 x float> [[SHUFFLE_I]]
@@ -3560,13 +3553,6 @@
return vget_low_s64(a);
}
-// CHECK-LABEL: @test_vget_low_f16(
-// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <8 x half> %a, <8 x half> %a, <4
x i32>
-// CHECK: ret <4 x half> [[SHUFFLE_I]]
-float16x4_t test_vget_low_f16(float16x8_t a) {
- return vget_low_f16(a);
-}
-
// CHECK-LABEL: @test_vget_low_f32(
// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <4 x float> %a, <4 x float> %a,
<2 x i32>
// CHECK: ret <2 x float> [[SHUFFLE_I]]
Index: include/clang/Basic/arm_neon.td
===
--- include/clang/Basic/arm_neon.td
+++ include/clang/Basic/arm_neon.td
@@ -398,8 +398,14 @@
// E.3.21 Splitting vectors
let InstName = "vmov" in {
-def VGET_HIGH : NoTestOpInst<"vget_high", "dk", "csilhfUcUsUiUlPcPs", OP_HI>;
-def VGET_LOW : NoTestOpInst<"vget_low", "dk", "csilhfUcUsUiUlPcPs", OP_LO>;
+def VGET_HIGH : NoTestOpInst<"vget_high", "dk", "csilfUcUsUiUlPcPs", OP_HI>;
+def VGET_LOW : NoTestOpInst<"vget_low", "dk", "csilfUcUsUiUlPcPs", OP_LO>;
+}
+let ArchGuard = "__ARM_ARCH >= 8 && defined(__aarch64__)" in {
+ let InstName = "vmov" in {
+ def VGET_HIGH_F16 : NoTestOpInst<"vget_high", "dk", "h", OP_HI>;
+ def VGET_LOW_F16 : NoTestOpInst<"vget_low", "dk", "h", OP_LO>;
+ }
}
Index: test/CodeGen/arm_neon_intrinsics.c
===
--- test/CodeGen/arm_neon_intrinsics.c
+++ test/CodeGen/arm_neon_intrinsics.c
@@ -3254,13 +3254,6 @@
return vget_high_s64(a);
}
-// CHECK-LABEL: @test_vget_high_f16(
-// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <8 x half> %a, <8 x half> %a, <4 x i32>
-// CHECK: ret <4 x half> [[SHUFFLE_I]]
-float16x4_t test_vget_high_f16(float16x8_t a) {
- return vget_high_f16(a);
-}
-
// CHECK-LABEL: @test_vget_high_f32(
// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <4 x float> %a, <4 x float> %a, <2 x i32>
// CHECK: ret <2 x float> [[SHUFFLE_I]]
@@ -3560,13 +3553,6 @@
return vget_low_s64(a);
}
-// CHECK-LABEL: @test_vget_low_f16(
-// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <8 x half> %a, <8 x half> %a, <4 x i32>
-// CHECK: ret <4 x half> [[SHUFFLE_I]]
-float16x4_t test_vget_low_f16(float16x8_t a) {
- return vget_low_f16(a);
-}
-
// CHECK-LABEL: @test_vget_low_f32(
// CHECK: [[SHUFFLE_I:%.*]] = shufflevector <4 x float> %a, <4 x float> %a, <2 x i32>
// CHECK: ret <2 x float> [[SHUFFLE_I]]
Index: include/clang/Basic/arm_neon.td
===
--- include/clang/Basic/arm_neon.td
+++ include/clang/Basic/arm_neon.td
@@ -398,8 +398,14 @@
// E.3.21 Splitting vectors
let InstName = "vmov" in {
-def VGET_HIGH : NoTestOpInst<"vget_high", "dk", "csilhfUcUsUiUlPcPs", OP_HI>;
-def VGET_LOW : NoTestOpInst<"vget_low", "dk", "csilhfUcUsUiUlPcPs", OP_LO>;
+def VGET_HIGH : NoTestOpInst<"vget_high", "dk", "csilfUcUsUiUlPcPs", OP_HI>;
+def VGET_LOW : NoTestOpInst<"vget_low", "dk", "csilfUcUsUiUlPcPs", OP_LO>;
+}
+let ArchGuard = "__ARM_ARCH >= 8 && defined(__aarch64__)" in {
+ let InstName = "vmov" in {
+ def VGET_HIGH_F16 : NoTestOpInst<"vget_high", "dk", "h", OP_HI>;
+ def VGET_LOW_F16 : NoTestOpInst<"vget_low", "dk", "h", OP_LO>;
+ }
}
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