[PATCH] D49075: [NEON] Define fp16 vld and vst intrinsics conditionally

2018-08-19 Thread Ivan Kosarev via Phabricator via cfe-commits 
This revision was automatically updated to reflect the committed changes.
Closed by commit rC340140: [NEON] Define fp16 vld and vst intrinsics 
conditionally (authored by kosarev, committed by ).

Repository:
  rC Clang

https://reviews.llvm.org/D49075

Files:
  include/clang/Basic/arm_neon.td
  test/CodeGen/arm-neon-vld.c
  test/CodeGen/arm-neon-vst.c
  test/Sema/arm-no-fp16.c

Index: include/clang/Basic/arm_neon.td
===
--- include/clang/Basic/arm_neon.td
+++ include/clang/Basic/arm_neon.td
@@ -337,48 +337,78 @@
 
 // E.3.14 Loads and stores of a single vector
 def VLD1  : WInst<"vld1", "dc",
-  "QUcQUsQUiQUlQcQsQiQlQhQfQPcQPsUcUsUiUlcsilhfPcPs">;
+  "QUcQUsQUiQUlQcQsQiQlQfQPcQPsUcUsUiUlcsilfPcPs">;
 def VLD1_X2   : WInst<"vld1_x2", "2c",
-  "cfhilsUcUiUlUsQcQfQhQiQlQsQUcQUiQUlQUsPcPsQPcQPs">;
+  "cfilsUcUiUlUsQcQfQiQlQsQUcQUiQUlQUsPcPsQPcQPs">;
 def VLD1_X3   : WInst<"vld1_x3", "3c",
-  "cfhilsUcUiUlUsQcQfQhQiQlQsQUcQUiQUlQUsPcPsQPcQPs">;
+  "cfilsUcUiUlUsQcQfQiQlQsQUcQUiQUlQUsPcPsQPcQPs">;
 def VLD1_X4   : WInst<"vld1_x4", "4c",
-  "cfhilsUcUiUlUsQcQfQhQiQlQsQUcQUiQUlQUsPcPsQPcQPs">;
+  "cfilsUcUiUlUsQcQfQiQlQsQUcQUiQUlQUsPcPsQPcQPs">;
 def VLD1_LANE : WInst<"vld1_lane", "dcdi",
-  "QUcQUsQUiQUlQcQsQiQlQhQfQPcQPsUcUsUiUlcsilhfPcPs">;
+  "QUcQUsQUiQUlQcQsQiQlQfQPcQPsUcUsUiUlcsilfPcPs">;
 def VLD1_DUP  : WInst<"vld1_dup", "dc",
-  "QUcQUsQUiQUlQcQsQiQlQhQfQPcQPsUcUsUiUlcsilhfPcPs">;
+  "QUcQUsQUiQUlQcQsQiQlQfQPcQPsUcUsUiUlcsilfPcPs">;
 def VST1  : WInst<"vst1", "vpd",
-  "QUcQUsQUiQUlQcQsQiQlQhQfQPcQPsUcUsUiUlcsilhfPcPs">;
+  "QUcQUsQUiQUlQcQsQiQlQfQPcQPsUcUsUiUlcsilfPcPs">;
 def VST1_X2   : WInst<"vst1_x2", "vp2",
-  "cfhilsUcUiUlUsQcQfQhQiQlQsQUcQUiQUlQUsPcPsQPcQPs">;
+  "cfilsUcUiUlUsQcQfQiQlQsQUcQUiQUlQUsPcPsQPcQPs">;
 def VST1_X3   : WInst<"vst1_x3", "vp3",
-  "cfhilsUcUiUlUsQcQfQhQiQlQsQUcQUiQUlQUsPcPsQPcQPs">;
+  "cfilsUcUiUlUsQcQfQiQlQsQUcQUiQUlQUsPcPsQPcQPs">;
 def VST1_X4   : WInst<"vst1_x4", "vp4",
-  "cfhilsUcUiUlUsQcQfQhQiQlQsQUcQUiQUlQUsPcPsQPcQPs">;
+  "cfilsUcUiUlUsQcQfQiQlQsQUcQUiQUlQUsPcPsQPcQPs">;
 def VST1_LANE : WInst<"vst1_lane", "vpdi",
-  "QUcQUsQUiQUlQcQsQiQlQhQfQPcQPsUcUsUiUlcsilhfPcPs">;
+  "QUcQUsQUiQUlQcQsQiQlQfQPcQPsUcUsUiUlcsilfPcPs">;
+let ArchGuard = "(__ARM_FP & 2)" in {
+def VLD1_F16  : WInst<"vld1", "dc", "hQh">;
+def VLD1_X2_F16   : WInst<"vld1_x2", "2c", "hQh">;
+def VLD1_X3_F16   : WInst<"vld1_x3", "3c", "hQh">;
+def VLD1_X4_F16   : WInst<"vld1_x4", "4c", "hQh">;
+def VLD1_LANE_F16 : WInst<"vld1_lane", "dcdi", "hQh">;
+def VLD1_DUP_F16  : WInst<"vld1_dup", "dc", "hQh">;
+def VST1_F16  : WInst<"vst1", "vpd", "hQh">;
+def VST1_X2_F16   : WInst<"vst1_x2", "vp2", "hQh">;
+def VST1_X3_F16   : WInst<"vst1_x3", "vp3", "hQh">;
+def VST1_X4_F16   : WInst<"vst1_x4", "vp4", "hQh">;
+def VST1_LANE_F16 : WInst<"vst1_lane", "vpdi", "hQh">;
+}
 
 
 // E.3.15 Loads and stores of an N-element structure
-def VLD2 : WInst<"vld2", "2c", "QUcQUsQUiQcQsQiQhQfQPcQPsUcUsUiUlcsilhfPcPs">;
-def VLD3 : WInst<"vld3", "3c", "QUcQUsQUiQcQsQiQhQfQPcQPsUcUsUiUlcsilhfPcPs">;
-def VLD4 : WInst<"vld4", "4c", "QUcQUsQUiQcQsQiQhQfQPcQPsUcUsUiUlcsilhfPcPs">;
+def VLD2 : WInst<"vld2", "2c", "QUcQUsQUiQcQsQiQfQPcQPsUcUsUiUlcsilfPcPs">;
+def VLD3 : WInst<"vld3", "3c", "QUcQUsQUiQcQsQiQfQPcQPsUcUsUiUlcsilfPcPs">;
+def VLD4 : WInst<"vld4", "4c", "QUcQUsQUiQcQsQiQfQPcQPsUcUsUiUlcsilfPcPs">;
 def VLD2_DUP  : WInst<"vld2_dup", "2c",
-  "UcUsUiUlcsilhfPcPsQcQfQhQiQlQsQPcQPsQUcQUiQUlQUs">;
+  "UcUsUiUlcsilfPcPsQcQfQiQlQsQPcQPsQUcQUiQUlQUs">;
 def VLD3_DUP  : WInst<"vld3_dup", "3c",
-  "UcUsUiUlcsilhfPcPsQcQfQhQiQlQsQPcQPsQUcQUiQUlQUs">;
+  "UcUsUiUlcsilfPcPsQcQfQiQlQsQPcQPsQUcQUiQUlQUs">;
 def VLD4_DUP  : WInst<"vld4_dup", "4c",
-  "UcUsUiUlcsilhfPcPsQcQfQhQiQlQsQPcQPsQUcQUiQUlQUs">;
-def VLD2_LANE : WInst<"vld2_lane", "2c2i", "QUsQUiQsQiQhQfQPsUcUsUicsihfPcPs">;
-def VLD3_LANE : WInst<"vld3_lane", "3c3i", "QUsQUiQsQiQhQfQPsUcUsUicsihfPcPs">;
-def VLD4_LANE : WInst<"vld4_lane", "4c4i", "QUsQUiQsQiQhQfQPsUcUsUicsihfPcPs">;
-def VST2 : WInst<"vst2", "vp2", "QUcQUsQUiQcQsQiQhQfQPcQPsUcUsUiUlcsilhfPcPs">;
-def VST3 : WInst<"vst3", "vp3", "QUcQUsQUiQcQsQiQhQfQPcQPsUcUsUiUlcsilhfPcPs">;
-def VST4 : WInst<"vst4", "vp4", "QUcQUsQUiQcQsQiQhQfQPcQPsUcUsUiUlcs

[PATCH] D49075: [NEON] Define fp16 vld and vst intrinsics conditionally

2018-08-19 Thread Ivan Kosarev via Phabricator via cfe-commits 
This revision was automatically updated to reflect the committed changes.
Closed by commit rL340140: [NEON] Define fp16 vld and vst intrinsics 
conditionally (authored by kosarev, committed by ).
Herald added a subscriber: llvm-commits.

Changed prior to commit:
  https://reviews.llvm.org/D49075?vs=157960&id=161400#toc

Repository:
  rC Clang

https://reviews.llvm.org/D49075

Files:
  cfe/trunk/include/clang/Basic/arm_neon.td
  cfe/trunk/test/CodeGen/arm-neon-vld.c
  cfe/trunk/test/CodeGen/arm-neon-vst.c
  cfe/trunk/test/Sema/arm-no-fp16.c

Index: cfe/trunk/test/CodeGen/arm-neon-vst.c
===
--- cfe/trunk/test/CodeGen/arm-neon-vst.c
+++ cfe/trunk/test/CodeGen/arm-neon-vst.c
@@ -2,8 +2,8 @@
 // RUN: -S -disable-O0-optnone -emit-llvm -o - %s | opt -S -mem2reg | \
 // RUN: FileCheck -check-prefixes=CHECK,CHECK-A64 %s
 // RUN: %clang_cc1 -triple armv8-none-linux-gnueabi -target-feature +neon \
-// RUN: -S -disable-O0-optnone -emit-llvm -o - %s | opt -S -mem2reg | \
-// RUN: FileCheck -check-prefixes=CHECK,CHECK-A32 %s
+// RUN: -target-feature +fp16 -S -disable-O0-optnone -emit-llvm -o - %s | \
+// RUN: opt -S -mem2reg | FileCheck -check-prefixes=CHECK,CHECK-A32 %s
 
 #include 
 
Index: cfe/trunk/test/CodeGen/arm-neon-vld.c
===
--- cfe/trunk/test/CodeGen/arm-neon-vld.c
+++ cfe/trunk/test/CodeGen/arm-neon-vld.c
@@ -2,8 +2,8 @@
 // RUN: -S -disable-O0-optnone -emit-llvm -o - %s | opt -S -mem2reg | \
 // RUN: FileCheck -check-prefixes=CHECK,CHECK-A64 %s
 // RUN: %clang_cc1 -triple armv8-none-linux-gnueabi -target-feature +neon \
-// RUN: -S -disable-O0-optnone -emit-llvm -o - %s | opt -S -mem2reg | \
-// RUN: FileCheck -check-prefixes=CHECK,CHECK-A32 %s
+// RUN: -target-feature +fp16 -S -disable-O0-optnone -emit-llvm -o - %s | \
+// RUN: opt -S -mem2reg | FileCheck -check-prefixes=CHECK,CHECK-A32 %s
 
 #include 
 
Index: cfe/trunk/test/Sema/arm-no-fp16.c
===
--- cfe/trunk/test/Sema/arm-no-fp16.c
+++ cfe/trunk/test/Sema/arm-no-fp16.c
@@ -83,3 +83,213 @@
 float16x8_t test_vminnmq_f16(float16x8_t a, float16x8_t b) {
   return vminnmq_f16(a, b); // expected-warning{{implicit declaration of function 'vminnmq_f16'}} expected-error{{returning 'int' from a function with incompatible result type 'float16x8_t'}}
 }
+
+float16x4_t test_vld1_f16(const float16_t *a) {
+  return vld1_f16(a); // expected-warning{{implicit declaration of function 'vld1_f16'}} expected-error{{returning 'int' from a function with incompatible result type 'float16x4_t'}}
+}
+
+float16x8_t test_vld1q_f16(const float16_t *a) {
+  return vld1q_f16(a); // expected-warning{{implicit declaration of function 'vld1q_f16'}} expected-error{{returning 'int' from a function with incompatible result type 'float16x8_t'}}
+}
+
+float16x4_t test_vld1_dup_f16(const float16_t *a) {
+  return vld1_dup_f16(a); // expected-warning{{implicit declaration of function 'vld1_dup_f16'}} expected-error{{returning 'int' from a function with incompatible result type 'float16x4_t'}}
+}
+
+float16x8_t test_vld1q_dup_f16(const float16_t *a) {
+  return vld1q_dup_f16(a); // expected-warning{{implicit declaration of function 'vld1q_dup_f16'}} expected-error{{returning 'int' from a function with incompatible result type 'float16x8_t'}}
+}
+
+float16x4_t test_vld1_lane_f16(const float16_t *a, float16x4_t b) {
+  return vld1_lane_f16(a, b, 3); // expected-warning{{implicit declaration of function 'vld1_lane_f16'}} expected-error{{returning 'int' from a function with incompatible result type 'float16x4_t'}}
+}
+
+float16x8_t test_vld1q_lane_f16(const float16_t *a, float16x8_t b) {
+  return vld1q_lane_f16(a, b, 7); // expected-warning{{implicit declaration of function 'vld1q_lane_f16'}} expected-error{{returning 'int' from a function with incompatible result type 'float16x8_t'}}
+}
+
+float16x4x2_t test_vld1_f16_x2(const float16_t *a) {
+  return vld1_f16_x2(a); // expected-warning{{implicit declaration of function 'vld1_f16_x2'}} expected-error{{returning 'int' from a function with incompatible result type 'float16x4x2_t'}}
+}
+
+float16x8x2_t test_vld1q_f16_x2(const float16_t *a) {
+  return vld1q_f16_x2(a); // expected-warning{{implicit declaration of function 'vld1q_f16_x2'}} expected-error{{returning 'int' from a function with incompatible result type 'float16x8x2_t'}}
+}
+
+float16x4x3_t test_vld1_f16_x3(const float16_t *a) {
+  return vld1_f16_x3(a); // expected-warning{{implicit declaration of function 'vld1_f16_x3'}} expected-error{{returning 'int' from a function with incompatible result type 'float16x4x3_t'}}
+}
+
+float16x8x3_t test_vld1q_f16_x3(const float16_t *a) {
+  return vld1q_f16_x3(a); // expected-warning{{implicit declaration of function 'vld1q_f16_x3'}} expected-error{{returning 'int' from a function with incompatible result type 'fl

[PATCH] D49075: [NEON] Define fp16 vld and vst intrinsics conditionally

2018-08-06 Thread Sjoerd Meijer via Phabricator via cfe-commits 
SjoerdMeijer accepted this revision.
SjoerdMeijer added a comment.
This revision is now accepted and ready to land.

Thanks, LGTM.


https://reviews.llvm.org/D49075



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[PATCH] D49075: [NEON] Define fp16 vld and vst intrinsics conditionally

2018-08-06 Thread Ivan Kosarev via Phabricator via cfe-commits 
kosarev added a comment.

Ping.


https://reviews.llvm.org/D49075



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[PATCH] D49075: [NEON] Define fp16 vld and vst intrinsics conditionally

2018-07-30 Thread Ivan Kosarev via Phabricator via cfe-commits 
kosarev updated this revision to Diff 157960.
kosarev added a comment.

Test that the affected intrinsics are not defined in no-fp16 mode.


https://reviews.llvm.org/D49075

Files:
  include/clang/Basic/arm_neon.td
  test/CodeGen/arm-neon-vld.c
  test/CodeGen/arm-neon-vst.c
  test/Sema/arm-no-fp16.c

Index: test/Sema/arm-no-fp16.c
===
--- test/Sema/arm-no-fp16.c
+++ test/Sema/arm-no-fp16.c
@@ -83,3 +83,213 @@
 float16x8_t test_vminnmq_f16(float16x8_t a, float16x8_t b) {
   return vminnmq_f16(a, b); // expected-warning{{implicit declaration of function 'vminnmq_f16'}} expected-error{{returning 'int' from a function with incompatible result type 'float16x8_t'}}
 }
+
+float16x4_t test_vld1_f16(const float16_t *a) {
+  return vld1_f16(a); // expected-warning{{implicit declaration of function 'vld1_f16'}} expected-error{{returning 'int' from a function with incompatible result type 'float16x4_t'}}
+}
+
+float16x8_t test_vld1q_f16(const float16_t *a) {
+  return vld1q_f16(a); // expected-warning{{implicit declaration of function 'vld1q_f16'}} expected-error{{returning 'int' from a function with incompatible result type 'float16x8_t'}}
+}
+
+float16x4_t test_vld1_dup_f16(const float16_t *a) {
+  return vld1_dup_f16(a); // expected-warning{{implicit declaration of function 'vld1_dup_f16'}} expected-error{{returning 'int' from a function with incompatible result type 'float16x4_t'}}
+}
+
+float16x8_t test_vld1q_dup_f16(const float16_t *a) {
+  return vld1q_dup_f16(a); // expected-warning{{implicit declaration of function 'vld1q_dup_f16'}} expected-error{{returning 'int' from a function with incompatible result type 'float16x8_t'}}
+}
+
+float16x4_t test_vld1_lane_f16(const float16_t *a, float16x4_t b) {
+  return vld1_lane_f16(a, b, 3); // expected-warning{{implicit declaration of function 'vld1_lane_f16'}} expected-error{{returning 'int' from a function with incompatible result type 'float16x4_t'}}
+}
+
+float16x8_t test_vld1q_lane_f16(const float16_t *a, float16x8_t b) {
+  return vld1q_lane_f16(a, b, 7); // expected-warning{{implicit declaration of function 'vld1q_lane_f16'}} expected-error{{returning 'int' from a function with incompatible result type 'float16x8_t'}}
+}
+
+float16x4x2_t test_vld1_f16_x2(const float16_t *a) {
+  return vld1_f16_x2(a); // expected-warning{{implicit declaration of function 'vld1_f16_x2'}} expected-error{{returning 'int' from a function with incompatible result type 'float16x4x2_t'}}
+}
+
+float16x8x2_t test_vld1q_f16_x2(const float16_t *a) {
+  return vld1q_f16_x2(a); // expected-warning{{implicit declaration of function 'vld1q_f16_x2'}} expected-error{{returning 'int' from a function with incompatible result type 'float16x8x2_t'}}
+}
+
+float16x4x3_t test_vld1_f16_x3(const float16_t *a) {
+  return vld1_f16_x3(a); // expected-warning{{implicit declaration of function 'vld1_f16_x3'}} expected-error{{returning 'int' from a function with incompatible result type 'float16x4x3_t'}}
+}
+
+float16x8x3_t test_vld1q_f16_x3(const float16_t *a) {
+  return vld1q_f16_x3(a); // expected-warning{{implicit declaration of function 'vld1q_f16_x3'}} expected-error{{returning 'int' from a function with incompatible result type 'float16x8x3_t'}}
+}
+
+float16x4x4_t test_vld1_f16_x4(const float16_t *a) {
+  return vld1_f16_x4(a); // expected-warning{{implicit declaration of function 'vld1_f16_x4'}} expected-error{{returning 'int' from a function with incompatible result type 'float16x4x4_t'}}
+}
+
+float16x8x4_t test_vld1q_f16_x4(const float16_t *a) {
+  return vld1q_f16_x4(a); // expected-warning{{implicit declaration of function 'vld1q_f16_x4'}} expected-error{{returning 'int' from a function with incompatible result type 'float16x8x4_t'}}
+}
+
+float16x4x2_t test_vld2_f16(const float16_t *a) {
+  return vld2_f16(a); // expected-warning{{implicit declaration of function 'vld2_f16'}} expected-error{{returning 'int' from a function with incompatible result type 'float16x4x2_t'}}
+}
+
+float16x8x2_t test_vld2q_f16(const float16_t *a) {
+  return vld2q_f16(a); // expected-warning{{implicit declaration of function 'vld2q_f16'}} expected-error{{returning 'int' from a function with incompatible result type 'float16x8x2_t'}}
+}
+
+float16x4x2_t test_vld2_lane_f16(const float16_t *a, float16x4x2_t b) {
+  return vld2_lane_f16(a, b, 3); // expected-warning{{implicit declaration of function 'vld2_lane_f16'}} expected-error{{returning 'int' from a function with incompatible result type 'float16x4x2_t'}}
+}
+
+float16x8x2_t test_vld2q_lane_f16(const float16_t *a, float16x8x2_t b) {
+  return vld2q_lane_f16(a, b, 7); // expected-warning{{implicit declaration of function 'vld2q_lane_f16'}} expected-error{{returning 'int' from a function with incompatible result type 'float16x8x2_t'}}
+}
+
+float16x4x2_t test_vld2_dup_f16(const float16_t *src) {
+  return vld2_dup_f16(src); // expected-warning{{implicit declaration of function 'vld2_dup_f16'}} expecte

[PATCH] D49075: [NEON] Define fp16 vld and vst intrinsics conditionally

2018-07-23 Thread Sjoerd Meijer via Phabricator via cfe-commits 
SjoerdMeijer added a comment.

Now that they are conditionally defined, do we need negative tests (in 
test/Sema/arm-no-fp16.c?) to check that they are not available when fp16 is not 
enabled?


https://reviews.llvm.org/D49075



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[PATCH] D49075: [NEON] Define fp16 vld and vst intrinsics conditionally

2018-07-23 Thread Ivan Kosarev via Phabricator via cfe-commits 
kosarev added a comment.

Ping.


https://reviews.llvm.org/D49075



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[PATCH] D49075: [NEON] Define fp16 vld and vst intrinsics conditionally

2018-07-18 Thread Ivan Kosarev via Phabricator via cfe-commits 
kosarev added a comment.

Ping.


https://reviews.llvm.org/D49075



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[PATCH] D49075: [NEON] Define fp16 vld and vst intrinsics conditionally

2018-07-09 Thread Ivan Kosarev via Phabricator via cfe-commits 
kosarev created this revision.
kosarev added reviewers: SjoerdMeijer, jgreenhalgh, rengolin.
kosarev added a project: clang.
Herald added a reviewer: javed.absar.

This patch fixes definitions of vld and vst NEON intrinsics so that we only 
define them if half-precision arithmetic is supported on the target platform, 
as prescribed in ACLE 2.0.


https://reviews.llvm.org/D49075

Files:
  include/clang/Basic/arm_neon.td
  test/CodeGen/arm-neon-vld.c
  test/CodeGen/arm-neon-vst.c

Index: test/CodeGen/arm-neon-vst.c
===
--- test/CodeGen/arm-neon-vst.c
+++ test/CodeGen/arm-neon-vst.c
@@ -2,8 +2,8 @@
 // RUN: -S -disable-O0-optnone -emit-llvm -o - %s | opt -S -mem2reg | \
 // RUN: FileCheck -check-prefixes=CHECK,CHECK-A64 %s
 // RUN: %clang_cc1 -triple armv8-none-linux-gnueabi -target-feature +neon \
-// RUN: -S -disable-O0-optnone -emit-llvm -o - %s | opt -S -mem2reg | \
-// RUN: FileCheck -check-prefixes=CHECK,CHECK-A32 %s
+// RUN: -target-feature +fp16 -S -disable-O0-optnone -emit-llvm -o - %s | \
+// RUN: opt -S -mem2reg | FileCheck -check-prefixes=CHECK,CHECK-A32 %s
 
 #include 
 
Index: test/CodeGen/arm-neon-vld.c
===
--- test/CodeGen/arm-neon-vld.c
+++ test/CodeGen/arm-neon-vld.c
@@ -2,8 +2,8 @@
 // RUN: -S -disable-O0-optnone -emit-llvm -o - %s | opt -S -mem2reg | \
 // RUN: FileCheck -check-prefixes=CHECK,CHECK-A64 %s
 // RUN: %clang_cc1 -triple armv8-none-linux-gnueabi -target-feature +neon \
-// RUN: -S -disable-O0-optnone -emit-llvm -o - %s | opt -S -mem2reg | \
-// RUN: FileCheck -check-prefixes=CHECK,CHECK-A32 %s
+// RUN: -target-feature +fp16 -S -disable-O0-optnone -emit-llvm -o - %s | \
+// RUN: opt -S -mem2reg | FileCheck -check-prefixes=CHECK,CHECK-A32 %s
 
 #include 
 
Index: include/clang/Basic/arm_neon.td
===
--- include/clang/Basic/arm_neon.td
+++ include/clang/Basic/arm_neon.td
@@ -337,48 +337,78 @@
 
 // E.3.14 Loads and stores of a single vector
 def VLD1  : WInst<"vld1", "dc",
-  "QUcQUsQUiQUlQcQsQiQlQhQfQPcQPsUcUsUiUlcsilhfPcPs">;
+  "QUcQUsQUiQUlQcQsQiQlQfQPcQPsUcUsUiUlcsilfPcPs">;
 def VLD1_X2   : WInst<"vld1_x2", "2c",
-  "cfhilsUcUiUlUsQcQfQhQiQlQsQUcQUiQUlQUsPcPsQPcQPs">;
+  "cfilsUcUiUlUsQcQfQiQlQsQUcQUiQUlQUsPcPsQPcQPs">;
 def VLD1_X3   : WInst<"vld1_x3", "3c",
-  "cfhilsUcUiUlUsQcQfQhQiQlQsQUcQUiQUlQUsPcPsQPcQPs">;
+  "cfilsUcUiUlUsQcQfQiQlQsQUcQUiQUlQUsPcPsQPcQPs">;
 def VLD1_X4   : WInst<"vld1_x4", "4c",
-  "cfhilsUcUiUlUsQcQfQhQiQlQsQUcQUiQUlQUsPcPsQPcQPs">;
+  "cfilsUcUiUlUsQcQfQiQlQsQUcQUiQUlQUsPcPsQPcQPs">;
 def VLD1_LANE : WInst<"vld1_lane", "dcdi",
-  "QUcQUsQUiQUlQcQsQiQlQhQfQPcQPsUcUsUiUlcsilhfPcPs">;
+  "QUcQUsQUiQUlQcQsQiQlQfQPcQPsUcUsUiUlcsilfPcPs">;
 def VLD1_DUP  : WInst<"vld1_dup", "dc",
-  "QUcQUsQUiQUlQcQsQiQlQhQfQPcQPsUcUsUiUlcsilhfPcPs">;
+  "QUcQUsQUiQUlQcQsQiQlQfQPcQPsUcUsUiUlcsilfPcPs">;
 def VST1  : WInst<"vst1", "vpd",
-  "QUcQUsQUiQUlQcQsQiQlQhQfQPcQPsUcUsUiUlcsilhfPcPs">;
+  "QUcQUsQUiQUlQcQsQiQlQfQPcQPsUcUsUiUlcsilfPcPs">;
 def VST1_X2   : WInst<"vst1_x2", "vp2",
-  "cfhilsUcUiUlUsQcQfQhQiQlQsQUcQUiQUlQUsPcPsQPcQPs">;
+  "cfilsUcUiUlUsQcQfQiQlQsQUcQUiQUlQUsPcPsQPcQPs">;
 def VST1_X3   : WInst<"vst1_x3", "vp3",
-  "cfhilsUcUiUlUsQcQfQhQiQlQsQUcQUiQUlQUsPcPsQPcQPs">;
+  "cfilsUcUiUlUsQcQfQiQlQsQUcQUiQUlQUsPcPsQPcQPs">;
 def VST1_X4   : WInst<"vst1_x4", "vp4",
-  "cfhilsUcUiUlUsQcQfQhQiQlQsQUcQUiQUlQUsPcPsQPcQPs">;
+  "cfilsUcUiUlUsQcQfQiQlQsQUcQUiQUlQUsPcPsQPcQPs">;
 def VST1_LANE : WInst<"vst1_lane", "vpdi",
-  "QUcQUsQUiQUlQcQsQiQlQhQfQPcQPsUcUsUiUlcsilhfPcPs">;
+  "QUcQUsQUiQUlQcQsQiQlQfQPcQPsUcUsUiUlcsilfPcPs">;
+let ArchGuard = "(__ARM_FP & 2)" in {
+def VLD1_F16  : WInst<"vld1", "dc", "hQh">;
+def VLD1_X2_F16   : WInst<"vld1_x2", "2c", "hQh">;
+def VLD1_X3_F16   : WInst<"vld1_x3", "3c", "hQh">;
+def VLD1_X4_F16   : WInst<"vld1_x4", "4c", "hQh">;
+def VLD1_LANE_F16 : WInst<"vld1_lane", "dcdi", "hQh">;
+def VLD1_DUP_F16  : WInst<"vld1_dup", "dc", "hQh">;
+def VST1_F16  : WInst<"vst1", "vpd", "hQh">;
+def VST1_X2_F16   : WInst<"vst1_x2", "vp2", "hQh">;
+def VST1_X3_F16   : WInst<"vst1_x3", "vp3", "hQh">;
+def VST1_X4_F16   : WInst<"vst1_x4", "vp4", "hQh">;
+def VST1_LANE_F16 : WInst<"vst1_lane", "vpdi", "hQh">;
+}
 
 ///