[PATCH] D60552: [X86] Enable intrinsics of AVX512_BF16, which are supported for BFLOAT16 in Cooper Lake
This revision was automatically updated to reflect the committed changes.
Closed by commit rL360018: Enable intrinsics of AVX512_BF16, which are
supported for BFLOAT16 in Cooper… (authored by LuoYuanke, committed by ).
Herald added a project: LLVM.
Herald added a subscriber: llvm-commits.
Changed prior to commit:
https://reviews.llvm.org/D60552?vs=198168=198233#toc
Repository:
rL LLVM
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D60552/new/
https://reviews.llvm.org/D60552
Files:
cfe/trunk/docs/ClangCommandLineReference.rst
cfe/trunk/include/clang/Basic/BuiltinsX86.def
cfe/trunk/include/clang/Driver/Options.td
cfe/trunk/lib/Basic/Targets/X86.cpp
cfe/trunk/lib/Basic/Targets/X86.h
cfe/trunk/lib/CodeGen/CGBuiltin.cpp
cfe/trunk/lib/Headers/CMakeLists.txt
cfe/trunk/lib/Headers/cpuid.h
cfe/trunk/lib/Headers/immintrin.h
cfe/trunk/test/CodeGen/attr-target-x86.c
cfe/trunk/test/Driver/x86-target-features.c
cfe/trunk/test/Preprocessor/x86_target_features.c
monorepo-root/trunk/lib/Headers/avx512bf16intrin.h
monorepo-root/trunk/lib/Headers/avx512vlbf16intrin.h
monorepo-root/trunk/test/CodeGen/avx512bf16-builtins.c
monorepo-root/trunk/test/CodeGen/avx512vlbf16-builtins.c
Index: cfe/trunk/docs/ClangCommandLineReference.rst
===
--- cfe/trunk/docs/ClangCommandLineReference.rst
+++ cfe/trunk/docs/ClangCommandLineReference.rst
@@ -2610,6 +2610,8 @@
.. option:: -mavx512bitalg, -mno-avx512bitalg
+.. option:: -mavx512bf16, -mno-avx512bf16
+
.. option:: -mavx512bw, -mno-avx512bw
.. option:: -mavx512cd, -mno-avx512cd
Index: cfe/trunk/include/clang/Driver/Options.td
===
--- cfe/trunk/include/clang/Driver/Options.td
+++ cfe/trunk/include/clang/Driver/Options.td
@@ -2854,6 +2854,8 @@
def mno_avx2 : Flag<["-"], "mno-avx2">, Group;
def mavx512f : Flag<["-"], "mavx512f">, Group;
def mno_avx512f : Flag<["-"], "mno-avx512f">, Group;
+def mavx512bf16 : Flag<["-"], "mavx512bf16">, Group;
+def mno_avx512bf16 : Flag<["-"], "mno-avx512bf16">, Group;
def mavx512bitalg : Flag<["-"], "mavx512bitalg">, Group;
def mno_avx512bitalg : Flag<["-"], "mno-avx512bitalg">, Group;
def mavx512bw : Flag<["-"], "mavx512bw">, Group;
Index: cfe/trunk/include/clang/Basic/BuiltinsX86.def
===
--- cfe/trunk/include/clang/Basic/BuiltinsX86.def
+++ cfe/trunk/include/clang/Basic/BuiltinsX86.def
@@ -1831,6 +1831,24 @@
TARGET_BUILTIN(__builtin_ia32_vpmultishiftqb512, "V64cV64cV64c", "ncV:512:", "avx512vbmi")
TARGET_BUILTIN(__builtin_ia32_vpmultishiftqb128, "V16cV16cV16c", "ncV:128:", "avx512vbmi,avx512vl")
TARGET_BUILTIN(__builtin_ia32_vpmultishiftqb256, "V32cV32cV32c", "ncV:256:", "avx512vbmi,avx512vl")
+TARGET_BUILTIN(__builtin_ia32_cvtne2ps2bf16_128, "V8sV4fV4f", "ncV:128:",
+ "avx512bf16,avx512vl")
+TARGET_BUILTIN(__builtin_ia32_cvtne2ps2bf16_256, "V16sV8fV8f", "ncV:256:",
+ "avx512bf16,avx512vl")
+TARGET_BUILTIN(__builtin_ia32_cvtne2ps2bf16_512, "V32sV16fV16f", "ncV:512:",
+ "avx512bf16")
+TARGET_BUILTIN(__builtin_ia32_cvtneps2bf16_128_mask, "V8sV4fV8sUc", "ncV:128:",
+"avx512bf16,avx512vl")
+TARGET_BUILTIN(__builtin_ia32_cvtneps2bf16_256, "V8sV8f", "ncV:256:",
+"avx512bf16,avx512vl")
+TARGET_BUILTIN(__builtin_ia32_cvtneps2bf16_512, "V16sV16f", "ncV:512:",
+"avx512bf16")
+TARGET_BUILTIN(__builtin_ia32_dpbf16ps_128, "V4fV4fV4iV4i", "ncV:128:",
+"avx512bf16,avx512vl")
+TARGET_BUILTIN(__builtin_ia32_dpbf16ps_256, "V8fV8fV8iV8i", "ncV:256:",
+"avx512bf16,avx512vl")
+TARGET_BUILTIN(__builtin_ia32_dpbf16ps_512, "V16fV16fV16iV16i", "ncV:512:",
+"avx512bf16")
// generic select intrinsics
TARGET_BUILTIN(__builtin_ia32_selectb_128, "V16cUsV16cV16c", "ncV:128:", "avx512bw,avx512vl")
Index: cfe/trunk/test/CodeGen/attr-target-x86.c
===
--- cfe/trunk/test/CodeGen/attr-target-x86.c
+++ cfe/trunk/test/CodeGen/attr-target-x86.c
@@ -50,9 +50,9 @@
// CHECK: use_before_def{{.*}} #7
// CHECK: #0 = {{.*}}"target-cpu"="i686" "target-features"="+cx8,+x87"
// CHECK: #1 = {{.*}}"target-cpu"="ivybridge" "target-features"="+avx,+cx16,+cx8,+f16c,+fsgsbase,+fxsr,+mmx,+pclmul,+popcnt,+rdrnd,+sahf,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87,+xsave,+xsaveopt"
-// CHECK: #2 = {{.*}}"target-cpu"="i686"
[PATCH] D60552: [X86] Enable intrinsics of AVX512_BF16, which are supported for BFLOAT16 in Cooper Lake
craig.topper accepted this revision. craig.topper added a comment. This revision is now accepted and ready to land. LGTM CHANGES SINCE LAST ACTION https://reviews.llvm.org/D60552/new/ https://reviews.llvm.org/D60552 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D60552: [X86] Enable intrinsics of AVX512_BF16, which are supported for BFLOAT16 in Cooper Lake
liutianle updated this revision to Diff 198168.
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D60552/new/
https://reviews.llvm.org/D60552
Files:
docs/ClangCommandLineReference.rst
include/clang/Basic/BuiltinsX86.def
include/clang/Driver/Options.td
lib/Basic/Targets/X86.cpp
lib/Basic/Targets/X86.h
lib/CodeGen/CGBuiltin.cpp
lib/Headers/CMakeLists.txt
lib/Headers/avx512bf16intrin.h
lib/Headers/avx512vlbf16intrin.h
lib/Headers/cpuid.h
lib/Headers/immintrin.h
test/CodeGen/attr-target-x86.c
test/CodeGen/avx512bf16-builtins.c
test/CodeGen/avx512vlbf16-builtins.c
test/Driver/x86-target-features.c
test/Preprocessor/x86_target_features.c
Index: test/Preprocessor/x86_target_features.c
===
--- test/Preprocessor/x86_target_features.c
+++ test/Preprocessor/x86_target_features.c
@@ -443,3 +443,18 @@
// RUN: %clang -target i386-unknown-unknown -march=atom -mrdpid -x c -E -dM -o - %s | FileCheck -match-full-lines --check-prefix=RDPID %s
// RDPID: #define __RDPID__ 1
+
+// RUN: %clang -target i386-unknown-unknown -march=atom -mavx512bf16 -x c -E -dM -o - %s | FileCheck -match-full-lines --check-prefix=AVX512BF16 %s
+
+// AVX512BF16: #define __AVX512BF16__ 1
+// AVX512BF16: #define __AVX512BW__ 1
+// AVX512BF16: #define __AVX512VL__ 1
+
+// RUN: %clang -target i386-unknown-unknown -march=atom -mavx512bf16 -mno-avx512bw -x c -E -dM -o - %s | FileCheck -match-full-lines --check-prefix=AVX512BF16_NOAVX512BW %s
+
+// AVX512BF16_NOAVX512BW-NOT: #define __AVX512BF16__ 1
+
+// RUN: %clang -target i386-unknown-unknown -march=atom -mavx512bf16 -mno-avx512vl -x c -E -dM -o - %s | FileCheck -match-full-lines --check-prefix=AVX512BF16_NOAVX512VL %s
+
+// AVX512BF16_NOAVX512VL-NOT: #define __AVX512BF16__ 1
+
Index: test/Driver/x86-target-features.c
===
--- test/Driver/x86-target-features.c
+++ test/Driver/x86-target-features.c
@@ -178,3 +178,8 @@
// RUN: %clang -target i386-unknown-linux-gnu -march=i386 -mno-invpcid %s -### -o %t.o 2>&1 | FileCheck -check-prefix=NO-INVPCID %s
// INVPCID: "-target-feature" "+invpcid"
// NO-INVPCID: "-target-feature" "-invpcid"
+
+// RUN: %clang -target i386-unknown-linux-gnu -march=i386 -mavx512bf16 %s -### -o %t.o 2>&1 | FileCheck -check-prefix=AVX512BF16 %s
+// RUN: %clang -target i386-unknown-linux-gnu -march=i386 -mno-avx512bf16 %s -### -o %t.o 2>&1 | FileCheck -check-prefix=NO-AVX512BF16 %s
+// AVX512BF16: "-target-feature" "+avx512bf16"
+// NO-AVX512BF16: "-target-feature" "-avx512bf16"
Index: test/CodeGen/avx512vlbf16-builtins.c
===
--- /dev/null
+++ test/CodeGen/avx512vlbf16-builtins.c
@@ -0,0 +1,163 @@
+// RUN: %clang_cc1 -ffreestanding %s -triple=x86_64-apple-darwin \
+// RUN:-target-feature +avx512bf16 -target-feature \
+// RUN:+avx512vl -emit-llvm -o - -Wall -Werror | FileCheck %s
+
+#include
+
+__m128bh test_mm_cvtne2ps2bf16(__m128 A, __m128 B) {
+ // CHECK-LABEL: @test_mm_cvtne2ps2bf16
+ // CHECK: @llvm.x86.avx512bf16.cvtne2ps2bf16.128
+ // CHECK: ret <8 x i16> %{{.*}}
+ return _mm_cvtne2ps_pbh(A, B);
+}
+
+__m128bh test_mm_maskz_cvtne2ps2bf16(__m128 A, __m128 B, __mmask8 U) {
+ // CHECK-LABEL: @test_mm_maskz_cvtne2ps2bf16
+ // CHECK: @llvm.x86.avx512bf16.cvtne2ps2bf16.128
+ // CHECK: select <8 x i1> %{{.*}}, <8 x i16> %{{.*}}, <8 x i16> %{{.*}}
+ // CHECK: ret <8 x i16> %{{.*}}
+ return _mm_maskz_cvtne2ps_pbh(U, A, B);
+}
+
+__m128bh test_mm_mask_cvtne2ps2bf16(__m128bh C, __mmask8 U, __m128 A, __m128 B) {
+ // CHECK-LABEL: @test_mm_mask_cvtne2ps2bf16
+ // CHECK: @llvm.x86.avx512bf16.cvtne2ps2bf16.128
+ // CHECK: select <8 x i1> %{{.*}}, <8 x i16> %{{.*}}, <8 x i16> %{{.*}}
+ // CHECK: ret <8 x i16> %{{.*}}
+ return _mm_mask_cvtne2ps_pbh(C, U, A, B);
+}
+
+__m256bh test_mm256_cvtne2ps2bf16(__m256 A, __m256 B) {
+ // CHECK-LABEL: @test_mm256_cvtne2ps2bf16
+ // CHECK: @llvm.x86.avx512bf16.cvtne2ps2bf16.256
+ // CHECK: ret <16 x i16> %{{.*}}
+ return _mm256_cvtne2ps_pbh(A, B);
+}
+
+__m256bh test_mm256_maskz_cvtne2ps2bf16(__m256 A, __m256 B, __mmask16 U) {
+ // CHECK-LABEL: @test_mm256_maskz_cvtne2ps2bf16
+ // CHECK: @llvm.x86.avx512bf16.cvtne2ps2bf16.256
+ // CHECK: select <16 x i1> %{{.*}}, <16 x i16> %{{.*}}, <16 x i16> %{{.*}}
+ // CHECK: ret <16 x i16> %{{.*}}
+ return _mm256_maskz_cvtne2ps_pbh(U, A, B);
+}
+
+__m256bh test_mm256_mask_cvtne2ps2bf16(__m256bh C, __mmask16 U, __m256 A, __m256 B) {
+ // CHECK-LABEL: @test_mm256_mask_cvtne2ps2bf16
+ // CHECK: @llvm.x86.avx512bf16.cvtne2ps2bf16.256
+ // CHECK: select <16 x i1> %{{.*}}, <16 x i16> %{{.*}}, <16 x i16> %{{.*}}
+ // CHECK: ret <16 x i16> %{{.*}}
+ return _mm256_mask_cvtne2ps_pbh(C, U, A, B);
+}
+
+__m512bh test_mm512_cvtne2ps2bf16(__m512 A, __m512 B) {
+ // CHECK-LABEL: @test_mm512_cvtne2ps2bf16
+ // CHECK:
[PATCH] D60552: [X86] Enable intrinsics of AVX512_BF16, which are supported for BFLOAT16 in Cooper Lake
craig.topper added inline comments. Comment at: lib/Basic/Targets/X86.cpp:667 if (Name == "avx512bw" && !Enabled) Features["avx512vbmi"] = Features["avx512vbmi2"] = Features["avx512bitalg"] = false; craig.topper wrote: > Need to also disable avx512fp16 when we disable "avx512vbmi" and > "avx512vbmi2". > > Need a new if to disable "avx512fp16" when "if (Name == "avx512vl" && > !Enabled)" That should have said avx512bf16. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D60552/new/ https://reviews.llvm.org/D60552 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D60552: [X86] Enable intrinsics of AVX512_BF16, which are supported for BFLOAT16 in Cooper Lake
craig.topper added a comment. We seem to be missing test cases in test/Driver/x86-target-feature.c to test the command line options work. And test/Preprocessor/x86_target_features.c to make sure -mavx512bf16 enables avx512vl and avx512bw. Also need tests to make sure "-mavx512bf16 -mno-avx512bw" will leave bf16 disabled. Same for "-mavx512bf16 -mno-avx512vl" Comment at: lib/Basic/Targets/X86.cpp:667 if (Name == "avx512bw" && !Enabled) Features["avx512vbmi"] = Features["avx512vbmi2"] = Features["avx512bitalg"] = false; Need to also disable avx512fp16 when we disable "avx512vbmi" and "avx512vbmi2". Need a new if to disable "avx512fp16" when "if (Name == "avx512vl" && !Enabled)" CHANGES SINCE LAST ACTION https://reviews.llvm.org/D60552/new/ https://reviews.llvm.org/D60552 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D60552: [X86] Enable intrinsics of AVX512_BF16, which are supported for BFLOAT16 in Cooper Lake
liutianle added a comment. @RKSimon @craig.topper , could you please review again? CHANGES SINCE LAST ACTION https://reviews.llvm.org/D60552/new/ https://reviews.llvm.org/D60552 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D60552: [X86] Enable intrinsics of AVX512_BF16, which are supported for BFLOAT16 in Cooper Lake
liutianle added a comment. @RKSimon I add doxygen based descriptions in header files and return type check in test files. Please review again. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D60552/new/ https://reviews.llvm.org/D60552 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D60552: [X86] Enable intrinsics of AVX512_BF16, which are supported for BFLOAT16 in Cooper Lake
liutianle updated this revision to Diff 196195.
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D60552/new/
https://reviews.llvm.org/D60552
Files:
docs/ClangCommandLineReference.rst
include/clang/Basic/BuiltinsX86.def
include/clang/Driver/Options.td
lib/Basic/Targets/X86.cpp
lib/Basic/Targets/X86.h
lib/CodeGen/CGBuiltin.cpp
lib/Headers/CMakeLists.txt
lib/Headers/avx512bf16intrin.h
lib/Headers/avx512vlbf16intrin.h
lib/Headers/cpuid.h
lib/Headers/immintrin.h
test/CodeGen/attr-target-x86.c
test/CodeGen/avx512bf16-builtins.c
test/CodeGen/avx512vlbf16-builtins.c
Index: test/CodeGen/avx512vlbf16-builtins.c
===
--- /dev/null
+++ test/CodeGen/avx512vlbf16-builtins.c
@@ -0,0 +1,163 @@
+// RUN: %clang_cc1 -ffreestanding %s -triple=x86_64-apple-darwin \
+// RUN:-target-feature +avx512bf16 -target-feature \
+// RUN:+avx512vl -emit-llvm -o - -Wall -Werror | FileCheck %s
+
+#include
+
+__m128bh test_mm_cvtne2ps2bf16(__m128 A, __m128 B) {
+ // CHECK-LABEL: @test_mm_cvtne2ps2bf16
+ // CHECK: @llvm.x86.avx512bf16.cvtne2ps2bf16.128
+ // CHECK: ret <8 x i16> %{{.*}}
+ return _mm_cvtne2ps_pbh(A, B);
+}
+
+__m128bh test_mm_maskz_cvtne2ps2bf16(__m128 A, __m128 B, __mmask8 U) {
+ // CHECK-LABEL: @test_mm_maskz_cvtne2ps2bf16
+ // CHECK: @llvm.x86.avx512bf16.cvtne2ps2bf16.128
+ // CHECK: select <8 x i1> %{{.*}}, <8 x i16> %{{.*}}, <8 x i16> %{{.*}}
+ // CHECK: ret <8 x i16> %{{.*}}
+ return _mm_maskz_cvtne2ps_pbh(U, A, B);
+}
+
+__m128bh test_mm_mask_cvtne2ps2bf16(__m128bh C, __mmask8 U, __m128 A, __m128 B) {
+ // CHECK-LABEL: @test_mm_mask_cvtne2ps2bf16
+ // CHECK: @llvm.x86.avx512bf16.cvtne2ps2bf16.128
+ // CHECK: select <8 x i1> %{{.*}}, <8 x i16> %{{.*}}, <8 x i16> %{{.*}}
+ // CHECK: ret <8 x i16> %{{.*}}
+ return _mm_mask_cvtne2ps_pbh(C, U, A, B);
+}
+
+__m256bh test_mm256_cvtne2ps2bf16(__m256 A, __m256 B) {
+ // CHECK-LABEL: @test_mm256_cvtne2ps2bf16
+ // CHECK: @llvm.x86.avx512bf16.cvtne2ps2bf16.256
+ // CHECK: ret <16 x i16> %{{.*}}
+ return _mm256_cvtne2ps_pbh(A, B);
+}
+
+__m256bh test_mm256_maskz_cvtne2ps2bf16(__m256 A, __m256 B, __mmask16 U) {
+ // CHECK-LABEL: @test_mm256_maskz_cvtne2ps2bf16
+ // CHECK: @llvm.x86.avx512bf16.cvtne2ps2bf16.256
+ // CHECK: select <16 x i1> %{{.*}}, <16 x i16> %{{.*}}, <16 x i16> %{{.*}}
+ // CHECK: ret <16 x i16> %{{.*}}
+ return _mm256_maskz_cvtne2ps_pbh(U, A, B);
+}
+
+__m256bh test_mm256_mask_cvtne2ps2bf16(__m256bh C, __mmask16 U, __m256 A, __m256 B) {
+ // CHECK-LABEL: @test_mm256_mask_cvtne2ps2bf16
+ // CHECK: @llvm.x86.avx512bf16.cvtne2ps2bf16.256
+ // CHECK: select <16 x i1> %{{.*}}, <16 x i16> %{{.*}}, <16 x i16> %{{.*}}
+ // CHECK: ret <16 x i16> %{{.*}}
+ return _mm256_mask_cvtne2ps_pbh(C, U, A, B);
+}
+
+__m512bh test_mm512_cvtne2ps2bf16(__m512 A, __m512 B) {
+ // CHECK-LABEL: @test_mm512_cvtne2ps2bf16
+ // CHECK: @llvm.x86.avx512bf16.cvtne2ps2bf16.512
+ // CHECK: ret <32 x i16> %{{.*}}
+ return _mm512_cvtne2ps_pbh(A, B);
+}
+
+__m512bh test_mm512_maskz_cvtne2ps2bf16(__m512 A, __m512 B, __mmask32 U) {
+ // CHECK-LABEL: @test_mm512_maskz_cvtne2ps2bf16
+ // CHECK: @llvm.x86.avx512bf16.cvtne2ps2bf16.512
+ // CHECK: select <32 x i1> %{{.*}}, <32 x i16> %{{.*}}, <32 x i16> %{{.*}}
+ // CHECK: ret <32 x i16> %{{.*}}
+ return _mm512_maskz_cvtne2ps_pbh(U, A, B);
+}
+
+__m512bh test_mm512_mask_cvtne2ps2bf16(__m512bh C, __mmask32 U, __m512 A, __m512 B) {
+ // CHECK-LABEL: @test_mm512_mask_cvtne2ps2bf16
+ // CHECK: @llvm.x86.avx512bf16.cvtne2ps2bf16.512
+ // CHECK: select <32 x i1> %{{.*}}, <32 x i16> %{{.*}}, <32 x i16> %{{.*}}
+ // CHECK: ret <32 x i16> %{{.*}}
+ return _mm512_mask_cvtne2ps_pbh(C, U, A, B);
+}
+
+__m128bh test_mm_cvtneps2bf16(__m128 A) {
+ // CHECK-LABEL: @test_mm_cvtneps2bf16
+ // CHECK: @llvm.x86.avx512bf16.mask.cvtneps2bf16.128
+ // CHECK: ret <8 x i16> %{{.*}}
+ return _mm_cvtneps_pbh(A);
+}
+
+__m128bh test_mm_mask_cvtneps2bf16(__m128bh C, __mmask8 U, __m128 A) {
+ // CHECK-LABEL: @test_mm_mask_cvtneps2bf16
+ // CHECK: @llvm.x86.avx512bf16.mask.cvtneps2bf16.
+ // CHECK: ret <8 x i16> %{{.*}}
+ return _mm_mask_cvtneps_pbh(C, U, A);
+}
+
+__m128bh test_mm_maskz_cvtneps2bf16(__m128 A, __mmask8 U) {
+ // CHECK-LABEL: @test_mm_maskz_cvtneps2bf16
+ // CHECK: @llvm.x86.avx512bf16.mask.cvtneps2bf16.128
+ // CHECK: ret <8 x i16> %{{.*}}
+ return _mm_maskz_cvtneps_pbh(U, A);
+}
+
+__m128bh test_mm256_cvtneps2bf16(__m256 A) {
+ // CHECK-LABEL: @test_mm256_cvtneps2bf16
+ // CHECK: @llvm.x86.avx512bf16.cvtneps2bf16.256
+ // CHECK: ret <8 x i16> %{{.*}}
+ return _mm256_cvtneps_pbh(A);
+}
+
+__m128bh test_mm256_mask_cvtneps2bf16(__m128bh C, __mmask8 U, __m256 A) {
+ // CHECK-LABEL: @test_mm256_mask_cvtneps2bf16
+ // CHECK: @llvm.x86.avx512bf16.cvtneps2bf16.256
+ // CHECK: select <8 x i1> %{{.*}}, <8 x i16> %{{.*}}, <8 x i16> %{{.*}}
+ // CHECK: ret <8 x i16> %{{.*}}
+ return
[PATCH] D60552: [X86] Enable intrinsics of AVX512_BF16, which are supported for BFLOAT16 in Cooper Lake
RKSimon added inline comments.
Comment at: lib/Headers/avx512bf16intrin.h:23
+
+static __inline__ __m512bh __DEFAULT_FN_ATTRS512
+_mm512_cvtne2ps_pbh(__m512 __A, __m512 __B) {
All of these need proper doxygen based descriptions - see xmmintrin.h etc. for
examples.
Comment at: test/CodeGen/avx512bf16-builtins.c:9
+ // CHECK-LABEL: @test_mm512_cvtne2ps2bf16
+ // CHECK: @llvm.x86.avx512bf16.cvtne2ps2bf16.512
+ return _mm512_cvtne2ps_pbh(A, B);
add ret/arg types?
Repository:
rC Clang
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D60552/new/
https://reviews.llvm.org/D60552
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