[PATCH] D73184: [CodeGen] Emit IR for compound assignment with fixed-point operands.

[Bevin Hansson via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG313461f6d8f9: [CodeGen] Emit IR for compound assignment with 
fixed-point operands. (authored by ebevhan).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D73184/new/

https://reviews.llvm.org/D73184

Files:
  clang/lib/CodeGen/CGExprScalar.cpp
  clang/lib/Sema/SemaExpr.cpp
  clang/test/Frontend/fixed_point_compound.c

Index: clang/test/Frontend/fixed_point_compound.c
===
--- /dev/null
+++ clang/test/Frontend/fixed_point_compound.c
@@ -0,0 +1,374 @@
+// RUN: %clang_cc1 -ffixed-point -S -emit-llvm %s -o - | FileCheck %s --check-prefixes=CHECK,SIGNED
+// RUN: %clang_cc1 -ffixed-point -fpadding-on-unsigned-fixed-point -S -emit-llvm %s -o - | FileCheck %s --check-prefixes=CHECK,UNSIGNED
+
+short _Fract shf;
+_Accum a;
+unsigned _Fract uf;
+unsigned long _Accum ula;
+
+_Sat short _Fract sshf;
+_Sat _Accum sa;
+_Sat unsigned _Fract suf;
+_Sat unsigned long _Accum sula;
+
+int i;
+unsigned int u;
+signed char c;
+
+
+// CHECK-LABEL: @Addition(
+void Addition() {
+// CHECK: [[TMP0:%.*]] = load i32, i32* @a, align 4
+// CHECK-NEXT:[[TMP1:%.*]] = load i8, i8* @shf, align 1
+// CHECK-NEXT:[[RESIZE:%.*]] = sext i8 [[TMP1]] to i32
+// CHECK-NEXT:[[UPSCALE:%.*]] = shl i32 [[RESIZE]], 8
+// CHECK-NEXT:[[TMP2:%.*]] = add i32 [[UPSCALE]], [[TMP0]]
+// CHECK-NEXT:[[DOWNSCALE:%.*]] = ashr i32 [[TMP2]], 8
+// CHECK-NEXT:[[RESIZE1:%.*]] = trunc i32 [[DOWNSCALE]] to i8
+// CHECK-NEXT:store i8 [[RESIZE1]], i8* @shf, align 1
+  shf += a;
+
+// CHECK: [[TMP3:%.*]] = load i16, i16* @uf, align 2
+// CHECK-NEXT:[[TMP4:%.*]] = load i32, i32* @a, align 4
+// SIGNED-NEXT:   [[RESIZE2:%.*]] = sext i32 [[TMP4]] to i33
+// SIGNED-NEXT:   [[UPSCALE3:%.*]] = shl i33 [[RESIZE2]], 1
+// SIGNED-NEXT:   [[RESIZE4:%.*]] = zext i16 [[TMP3]] to i33
+// SIGNED-NEXT:   [[TMP5:%.*]] = add i33 [[UPSCALE3]], [[RESIZE4]]
+// SIGNED-NEXT:   [[DOWNSCALE5:%.*]] = ashr i33 [[TMP5]], 1
+// SIGNED-NEXT:   [[RESIZE6:%.*]] = trunc i33 [[DOWNSCALE5]] to i32
+// SIGNED-NEXT:   store i32 [[RESIZE6]], i32* @a, align 4
+// UNSIGNED-NEXT: [[RESIZE2:%.*]] = zext i16 [[TMP3]] to i32
+// UNSIGNED-NEXT: [[TMP5:%.*]] = add i32 [[TMP4]], [[RESIZE2]]
+// UNSIGNED-NEXT: store i32 [[TMP5]], i32* @a, align 4
+  a += uf;
+
+// CHECK: [[TMP6:%.*]] = load i64, i64* @ula, align 8
+// CHECK-NEXT:[[TMP7:%.*]] = load i16, i16* @uf, align 2
+// CHECK-NEXT:[[RESIZE7:%.*]] = zext i16 [[TMP7]] to i64
+// CHECK-NEXT:[[UPSCALE8:%.*]] = shl i64 [[RESIZE7]], 16
+// CHECK-NEXT:[[TMP8:%.*]] = add i64 [[UPSCALE8]], [[TMP6]]
+// CHECK-NEXT:[[DOWNSCALE9:%.*]] = lshr i64 [[TMP8]], 16
+// CHECK-NEXT:[[RESIZE10:%.*]] = trunc i64 [[DOWNSCALE9]] to i16
+// CHECK-NEXT:store i16 [[RESIZE10]], i16* @uf, align 2
+  uf += ula;
+
+// CHECK: [[TMP9:%.*]] = load i8, i8* @shf, align 1
+// CHECK-NEXT:[[TMP10:%.*]] = load i64, i64* @ula, align 8
+// SIGNED-NEXT:   [[RESIZE11:%.*]] = zext i64 [[TMP10]] to i65
+// SIGNED-NEXT:   [[RESIZE12:%.*]] = sext i8 [[TMP9]] to i65
+// SIGNED-NEXT:   [[UPSCALE13:%.*]] = shl i65 [[RESIZE12]], 25
+// SIGNED-NEXT:   [[TMP11:%.*]] = add i65 [[RESIZE11]], [[UPSCALE13]]
+// SIGNED-NEXT:   [[DOWNSCALE14:%.*]] = ashr i65 [[TMP11]], 1
+// SIGNED-NEXT:   [[RESIZE15:%.*]] = trunc i65 [[DOWNSCALE14]] to i64
+// SIGNED-NEXT:   [[UPSCALE16:%.*]] = shl i64 [[RESIZE15]], 1
+// SIGNED-NEXT:   store i64 [[UPSCALE16]], i64* @ula, align 8
+// UNSIGNED-NEXT: [[RESIZE7:%.*]] = sext i8 [[TMP9]] to i64
+// UNSIGNED-NEXT: [[UPSCALE8:%.*]] = shl i64 [[RESIZE7]], 24
+// UNSIGNED-NEXT: [[TMP11:%.*]] = add i64 [[TMP10]], [[UPSCALE8]]
+// UNSIGNED-NEXT: store i64 [[TMP11]], i64* @ula, align 8
+  ula += shf;
+
+// CHECK: [[TMP12:%.*]] = load i8, i8* @shf, align 1
+// CHECK-NEXT:[[TMP13:%.*]] = load i16, i16* @uf, align 2
+// SIGNED-NEXT:   [[RESIZE17:%.*]] = zext i16 [[TMP13]] to i17
+// SIGNED-NEXT:   [[RESIZE18:%.*]] = sext i8 [[TMP12]] to i17
+// SIGNED-NEXT:   [[UPSCALE19:%.*]] = shl i17 [[RESIZE18]], 9
+// SIGNED-NEXT:   [[TMP14:%.*]] = add i17 [[RESIZE17]], [[UPSCALE19]]
+// SIGNED-NEXT:   [[DOWNSCALE20:%.*]] = ashr i17 [[TMP14]], 1
+// SIGNED-NEXT:   [[RESIZE21:%.*]] = trunc i17 [[DOWNSCALE20]] to i16
+// SIGNED-NEXT:   [[UPSCALE22:%.*]] = shl i16 [[RESIZE21]], 1
+// SIGNED-NEXT:   store i16 [[UPSCALE22]], i16* @uf, align 2
+// UNSIGNED-NEXT: [[RESIZE9:%.*]] = sext i8 [[TMP12]] to i16
+// UNSIGNED-NEXT: [[UPSCALE10:%.*]] = shl i16 [[RESIZE9]], 8
+// UNSIGNED-NEXT: [[TMP14:%.*]] = add i16 [[TMP13]], [[UPSCALE10]]
+// UNSIGNED-NEXT: store i16 [[TMP14]], i16* @uf, align 2
+  uf += shf;
+
+// CHECK: [[TMP15:%.*]] = load i8, i8* @shf, align 1
+// CHECK-NEXT:[[TMP16:%.*]] = load i32, i32* @a, align 4
+// CHECK-NEXT:[[RESIZE23:%.*]] = sext i8 [[TMP15]] to i32
+// CHECK-NEXT:

[PATCH] D73184: [CodeGen] Emit IR for compound assignment with fixed-point operands.

[Bevin Hansson via Phabricator via cfe-commits]

ebevhan updated this revision to Diff 255972.
ebevhan added a comment.

Rebased.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D73184/new/

https://reviews.llvm.org/D73184

Files:
  clang/lib/CodeGen/CGExprScalar.cpp
  clang/lib/Sema/SemaExpr.cpp
  clang/test/Frontend/fixed_point_compound.c

Index: clang/test/Frontend/fixed_point_compound.c
===
--- /dev/null
+++ clang/test/Frontend/fixed_point_compound.c
@@ -0,0 +1,374 @@
+// RUN: %clang_cc1 -ffixed-point -S -emit-llvm %s -o - | FileCheck %s --check-prefixes=CHECK,SIGNED
+// RUN: %clang_cc1 -ffixed-point -fpadding-on-unsigned-fixed-point -S -emit-llvm %s -o - | FileCheck %s --check-prefixes=CHECK,UNSIGNED
+
+short _Fract shf;
+_Accum a;
+unsigned _Fract uf;
+unsigned long _Accum ula;
+
+_Sat short _Fract sshf;
+_Sat _Accum sa;
+_Sat unsigned _Fract suf;
+_Sat unsigned long _Accum sula;
+
+int i;
+unsigned int u;
+signed char c;
+
+
+// CHECK-LABEL: @Addition(
+void Addition() {
+// CHECK: [[TMP0:%.*]] = load i32, i32* @a, align 4
+// CHECK-NEXT:[[TMP1:%.*]] = load i8, i8* @shf, align 1
+// CHECK-NEXT:[[RESIZE:%.*]] = sext i8 [[TMP1]] to i32
+// CHECK-NEXT:[[UPSCALE:%.*]] = shl i32 [[RESIZE]], 8
+// CHECK-NEXT:[[TMP2:%.*]] = add i32 [[UPSCALE]], [[TMP0]]
+// CHECK-NEXT:[[DOWNSCALE:%.*]] = ashr i32 [[TMP2]], 8
+// CHECK-NEXT:[[RESIZE1:%.*]] = trunc i32 [[DOWNSCALE]] to i8
+// CHECK-NEXT:store i8 [[RESIZE1]], i8* @shf, align 1
+  shf += a;
+
+// CHECK: [[TMP3:%.*]] = load i16, i16* @uf, align 2
+// CHECK-NEXT:[[TMP4:%.*]] = load i32, i32* @a, align 4
+// SIGNED-NEXT:   [[RESIZE2:%.*]] = sext i32 [[TMP4]] to i33
+// SIGNED-NEXT:   [[UPSCALE3:%.*]] = shl i33 [[RESIZE2]], 1
+// SIGNED-NEXT:   [[RESIZE4:%.*]] = zext i16 [[TMP3]] to i33
+// SIGNED-NEXT:   [[TMP5:%.*]] = add i33 [[UPSCALE3]], [[RESIZE4]]
+// SIGNED-NEXT:   [[DOWNSCALE5:%.*]] = ashr i33 [[TMP5]], 1
+// SIGNED-NEXT:   [[RESIZE6:%.*]] = trunc i33 [[DOWNSCALE5]] to i32
+// SIGNED-NEXT:   store i32 [[RESIZE6]], i32* @a, align 4
+// UNSIGNED-NEXT: [[RESIZE2:%.*]] = zext i16 [[TMP3]] to i32
+// UNSIGNED-NEXT: [[TMP5:%.*]] = add i32 [[TMP4]], [[RESIZE2]]
+// UNSIGNED-NEXT: store i32 [[TMP5]], i32* @a, align 4
+  a += uf;
+
+// CHECK: [[TMP6:%.*]] = load i64, i64* @ula, align 8
+// CHECK-NEXT:[[TMP7:%.*]] = load i16, i16* @uf, align 2
+// CHECK-NEXT:[[RESIZE7:%.*]] = zext i16 [[TMP7]] to i64
+// CHECK-NEXT:[[UPSCALE8:%.*]] = shl i64 [[RESIZE7]], 16
+// CHECK-NEXT:[[TMP8:%.*]] = add i64 [[UPSCALE8]], [[TMP6]]
+// CHECK-NEXT:[[DOWNSCALE9:%.*]] = lshr i64 [[TMP8]], 16
+// CHECK-NEXT:[[RESIZE10:%.*]] = trunc i64 [[DOWNSCALE9]] to i16
+// CHECK-NEXT:store i16 [[RESIZE10]], i16* @uf, align 2
+  uf += ula;
+
+// CHECK: [[TMP9:%.*]] = load i8, i8* @shf, align 1
+// CHECK-NEXT:[[TMP10:%.*]] = load i64, i64* @ula, align 8
+// SIGNED-NEXT:   [[RESIZE11:%.*]] = zext i64 [[TMP10]] to i65
+// SIGNED-NEXT:   [[RESIZE12:%.*]] = sext i8 [[TMP9]] to i65
+// SIGNED-NEXT:   [[UPSCALE13:%.*]] = shl i65 [[RESIZE12]], 25
+// SIGNED-NEXT:   [[TMP11:%.*]] = add i65 [[RESIZE11]], [[UPSCALE13]]
+// SIGNED-NEXT:   [[DOWNSCALE14:%.*]] = ashr i65 [[TMP11]], 1
+// SIGNED-NEXT:   [[RESIZE15:%.*]] = trunc i65 [[DOWNSCALE14]] to i64
+// SIGNED-NEXT:   [[UPSCALE16:%.*]] = shl i64 [[RESIZE15]], 1
+// SIGNED-NEXT:   store i64 [[UPSCALE16]], i64* @ula, align 8
+// UNSIGNED-NEXT: [[RESIZE7:%.*]] = sext i8 [[TMP9]] to i64
+// UNSIGNED-NEXT: [[UPSCALE8:%.*]] = shl i64 [[RESIZE7]], 24
+// UNSIGNED-NEXT: [[TMP11:%.*]] = add i64 [[TMP10]], [[UPSCALE8]]
+// UNSIGNED-NEXT: store i64 [[TMP11]], i64* @ula, align 8
+  ula += shf;
+
+// CHECK: [[TMP12:%.*]] = load i8, i8* @shf, align 1
+// CHECK-NEXT:[[TMP13:%.*]] = load i16, i16* @uf, align 2
+// SIGNED-NEXT:   [[RESIZE17:%.*]] = zext i16 [[TMP13]] to i17
+// SIGNED-NEXT:   [[RESIZE18:%.*]] = sext i8 [[TMP12]] to i17
+// SIGNED-NEXT:   [[UPSCALE19:%.*]] = shl i17 [[RESIZE18]], 9
+// SIGNED-NEXT:   [[TMP14:%.*]] = add i17 [[RESIZE17]], [[UPSCALE19]]
+// SIGNED-NEXT:   [[DOWNSCALE20:%.*]] = ashr i17 [[TMP14]], 1
+// SIGNED-NEXT:   [[RESIZE21:%.*]] = trunc i17 [[DOWNSCALE20]] to i16
+// SIGNED-NEXT:   [[UPSCALE22:%.*]] = shl i16 [[RESIZE21]], 1
+// SIGNED-NEXT:   store i16 [[UPSCALE22]], i16* @uf, align 2
+// UNSIGNED-NEXT: [[RESIZE9:%.*]] = sext i8 [[TMP12]] to i16
+// UNSIGNED-NEXT: [[UPSCALE10:%.*]] = shl i16 [[RESIZE9]], 8
+// UNSIGNED-NEXT: [[TMP14:%.*]] = add i16 [[TMP13]], [[UPSCALE10]]
+// UNSIGNED-NEXT: store i16 [[TMP14]], i16* @uf, align 2
+  uf += shf;
+
+// CHECK: [[TMP15:%.*]] = load i8, i8* @shf, align 1
+// CHECK-NEXT:[[TMP16:%.*]] = load i32, i32* @a, align 4
+// CHECK-NEXT:[[RESIZE23:%.*]] = sext i8 [[TMP15]] to i32
+// CHECK-NEXT:[[UPSCALE24:%.*]] = shl i32 [[RESIZE23]], 8
+// CHECK-NEXT:[[TMP17:%.*]] = add i32 [[TMP16]], [[UPSCALE24]]
+// 

[PATCH] D73184: [CodeGen] Emit IR for compound assignment with fixed-point operands.

[John McCall via Phabricator via cfe-commits]

rjmccall added a comment.

Please test the cases where the result is used; this should be handled for you 
automatically, but still.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D73184/new/

https://reviews.llvm.org/D73184



___
cfe-commits mailing list
cfe-commits@lists.llvm.org
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[PATCH] D73184: [CodeGen] Emit IR for compound assignment with fixed-point operands.

[Bevin Hansson via Phabricator via cfe-commits]

ebevhan updated this revision to Diff 239795.
ebevhan added a comment.

Rebased.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D73184/new/

https://reviews.llvm.org/D73184

Files:
  clang/lib/CodeGen/CGExprScalar.cpp
  clang/lib/Sema/SemaExpr.cpp
  clang/test/Frontend/fixed_point_compound.c

Index: clang/test/Frontend/fixed_point_compound.c
===
--- /dev/null
+++ clang/test/Frontend/fixed_point_compound.c
@@ -0,0 +1,374 @@
+// RUN: %clang_cc1 -ffixed-point -S -emit-llvm %s -o - | FileCheck %s --check-prefixes=CHECK,SIGNED
+// RUN: %clang_cc1 -ffixed-point -fpadding-on-unsigned-fixed-point -S -emit-llvm %s -o - | FileCheck %s --check-prefixes=CHECK,UNSIGNED
+
+short _Fract shf;
+_Accum a;
+unsigned _Fract uf;
+unsigned long _Accum ula;
+
+_Sat short _Fract sshf;
+_Sat _Accum sa;
+_Sat unsigned _Fract suf;
+_Sat unsigned long _Accum sula;
+
+int i;
+unsigned int u;
+signed char c;
+
+
+// CHECK-LABEL: @Addition(
+void Addition() {
+// CHECK: [[TMP0:%.*]] = load i32, i32* @a, align 4
+// CHECK-NEXT:[[TMP1:%.*]] = load i8, i8* @shf, align 1
+// CHECK-NEXT:[[RESIZE:%.*]] = sext i8 [[TMP1]] to i32
+// CHECK-NEXT:[[UPSCALE:%.*]] = shl i32 [[RESIZE]], 8
+// CHECK-NEXT:[[TMP2:%.*]] = add i32 [[UPSCALE]], [[TMP0]]
+// CHECK-NEXT:[[DOWNSCALE:%.*]] = ashr i32 [[TMP2]], 8
+// CHECK-NEXT:[[RESIZE1:%.*]] = trunc i32 [[DOWNSCALE]] to i8
+// CHECK-NEXT:store i8 [[RESIZE1]], i8* @shf, align 1
+  shf += a;
+
+// CHECK: [[TMP3:%.*]] = load i16, i16* @uf, align 2
+// CHECK-NEXT:[[TMP4:%.*]] = load i32, i32* @a, align 4
+// SIGNED-NEXT:   [[RESIZE2:%.*]] = sext i32 [[TMP4]] to i33
+// SIGNED-NEXT:   [[UPSCALE3:%.*]] = shl i33 [[RESIZE2]], 1
+// SIGNED-NEXT:   [[RESIZE4:%.*]] = zext i16 [[TMP3]] to i33
+// SIGNED-NEXT:   [[TMP5:%.*]] = add i33 [[UPSCALE3]], [[RESIZE4]]
+// SIGNED-NEXT:   [[DOWNSCALE5:%.*]] = ashr i33 [[TMP5]], 1
+// SIGNED-NEXT:   [[RESIZE6:%.*]] = trunc i33 [[DOWNSCALE5]] to i32
+// SIGNED-NEXT:   store i32 [[RESIZE6]], i32* @a, align 4
+// UNSIGNED-NEXT: [[RESIZE2:%.*]] = zext i16 [[TMP3]] to i32
+// UNSIGNED-NEXT: [[TMP5:%.*]] = add i32 [[TMP4]], [[RESIZE2]]
+// UNSIGNED-NEXT: store i32 [[TMP5]], i32* @a, align 4
+  a += uf;
+
+// CHECK: [[TMP6:%.*]] = load i64, i64* @ula, align 8
+// CHECK-NEXT:[[TMP7:%.*]] = load i16, i16* @uf, align 2
+// CHECK-NEXT:[[RESIZE7:%.*]] = zext i16 [[TMP7]] to i64
+// CHECK-NEXT:[[UPSCALE8:%.*]] = shl i64 [[RESIZE7]], 16
+// CHECK-NEXT:[[TMP8:%.*]] = add i64 [[UPSCALE8]], [[TMP6]]
+// CHECK-NEXT:[[DOWNSCALE9:%.*]] = lshr i64 [[TMP8]], 16
+// CHECK-NEXT:[[RESIZE10:%.*]] = trunc i64 [[DOWNSCALE9]] to i16
+// CHECK-NEXT:store i16 [[RESIZE10]], i16* @uf, align 2
+  uf += ula;
+
+// CHECK: [[TMP9:%.*]] = load i8, i8* @shf, align 1
+// CHECK-NEXT:[[TMP10:%.*]] = load i64, i64* @ula, align 8
+// SIGNED-NEXT:   [[RESIZE11:%.*]] = zext i64 [[TMP10]] to i65
+// SIGNED-NEXT:   [[RESIZE12:%.*]] = sext i8 [[TMP9]] to i65
+// SIGNED-NEXT:   [[UPSCALE13:%.*]] = shl i65 [[RESIZE12]], 25
+// SIGNED-NEXT:   [[TMP11:%.*]] = add i65 [[RESIZE11]], [[UPSCALE13]]
+// SIGNED-NEXT:   [[DOWNSCALE14:%.*]] = ashr i65 [[TMP11]], 1
+// SIGNED-NEXT:   [[RESIZE15:%.*]] = trunc i65 [[DOWNSCALE14]] to i64
+// SIGNED-NEXT:   [[UPSCALE16:%.*]] = shl i64 [[RESIZE15]], 1
+// SIGNED-NEXT:   store i64 [[UPSCALE16]], i64* @ula, align 8
+// UNSIGNED-NEXT: [[RESIZE7:%.*]] = sext i8 [[TMP9]] to i64
+// UNSIGNED-NEXT: [[UPSCALE8:%.*]] = shl i64 [[RESIZE7]], 24
+// UNSIGNED-NEXT: [[TMP11:%.*]] = add i64 [[TMP10]], [[UPSCALE8]]
+// UNSIGNED-NEXT: store i64 [[TMP11]], i64* @ula, align 8
+  ula += shf;
+
+// CHECK: [[TMP12:%.*]] = load i8, i8* @shf, align 1
+// CHECK-NEXT:[[TMP13:%.*]] = load i16, i16* @uf, align 2
+// SIGNED-NEXT:   [[RESIZE17:%.*]] = zext i16 [[TMP13]] to i17
+// SIGNED-NEXT:   [[RESIZE18:%.*]] = sext i8 [[TMP12]] to i17
+// SIGNED-NEXT:   [[UPSCALE19:%.*]] = shl i17 [[RESIZE18]], 9
+// SIGNED-NEXT:   [[TMP14:%.*]] = add i17 [[RESIZE17]], [[UPSCALE19]]
+// SIGNED-NEXT:   [[DOWNSCALE20:%.*]] = ashr i17 [[TMP14]], 1
+// SIGNED-NEXT:   [[RESIZE21:%.*]] = trunc i17 [[DOWNSCALE20]] to i16
+// SIGNED-NEXT:   [[UPSCALE22:%.*]] = shl i16 [[RESIZE21]], 1
+// SIGNED-NEXT:   store i16 [[UPSCALE22]], i16* @uf, align 2
+// UNSIGNED-NEXT: [[RESIZE9:%.*]] = sext i8 [[TMP12]] to i16
+// UNSIGNED-NEXT: [[UPSCALE10:%.*]] = shl i16 [[RESIZE9]], 8
+// UNSIGNED-NEXT: [[TMP14:%.*]] = add i16 [[TMP13]], [[UPSCALE10]]
+// UNSIGNED-NEXT: store i16 [[TMP14]], i16* @uf, align 2
+  uf += shf;
+
+// CHECK: [[TMP15:%.*]] = load i8, i8* @shf, align 1
+// CHECK-NEXT:[[TMP16:%.*]] = load i32, i32* @a, align 4
+// CHECK-NEXT:[[RESIZE23:%.*]] = sext i8 [[TMP15]] to i32
+// CHECK-NEXT:[[UPSCALE24:%.*]] = shl i32 [[RESIZE23]], 8
+// CHECK-NEXT:[[TMP17:%.*]] = add i32 [[TMP16]], [[UPSCALE24]]
+// 

[PATCH] D73184: [CodeGen] Emit IR for compound assignment with fixed-point operands.

[Bevin Hansson via Phabricator via cfe-commits]

ebevhan created this revision.
ebevhan added reviewers: rjmccall, leonardchan.
Herald added a project: clang.
Herald added a subscriber: cfe-commits.

Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D73184

Files:
  clang/lib/CodeGen/CGExprScalar.cpp
  clang/lib/Sema/SemaExpr.cpp
  clang/test/Frontend/fixed_point_compound.c

Index: clang/test/Frontend/fixed_point_compound.c
===
--- /dev/null
+++ clang/test/Frontend/fixed_point_compound.c
@@ -0,0 +1,374 @@
+// RUN: %clang_cc1 -ffixed-point -S -emit-llvm %s -o - | FileCheck %s --check-prefixes=CHECK,SIGNED
+// RUN: %clang_cc1 -ffixed-point -fpadding-on-unsigned-fixed-point -S -emit-llvm %s -o - | FileCheck %s --check-prefixes=CHECK,UNSIGNED
+
+short _Fract shf;
+_Accum a;
+unsigned _Fract uf;
+unsigned long _Accum ula;
+
+_Sat short _Fract sshf;
+_Sat _Accum sa;
+_Sat unsigned _Fract suf;
+_Sat unsigned long _Accum sula;
+
+int i;
+unsigned int u;
+signed char c;
+
+
+// CHECK-LABEL: @Addition(
+void Addition() {
+// CHECK: [[TMP0:%.*]] = load i32, i32* @a, align 4
+// CHECK-NEXT:[[TMP1:%.*]] = load i8, i8* @shf, align 1
+// CHECK-NEXT:[[RESIZE:%.*]] = sext i8 [[TMP1]] to i32
+// CHECK-NEXT:[[UPSCALE:%.*]] = shl i32 [[RESIZE]], 8
+// CHECK-NEXT:[[TMP2:%.*]] = add i32 [[UPSCALE]], [[TMP0]]
+// CHECK-NEXT:[[DOWNSCALE:%.*]] = ashr i32 [[TMP2]], 8
+// CHECK-NEXT:[[RESIZE1:%.*]] = trunc i32 [[DOWNSCALE]] to i8
+// CHECK-NEXT:store i8 [[RESIZE1]], i8* @shf, align 1
+  shf += a;
+
+// CHECK: [[TMP3:%.*]] = load i16, i16* @uf, align 2
+// CHECK-NEXT:[[TMP4:%.*]] = load i32, i32* @a, align 4
+// SIGNED-NEXT:   [[RESIZE2:%.*]] = sext i32 [[TMP4]] to i33
+// SIGNED-NEXT:   [[UPSCALE3:%.*]] = shl i33 [[RESIZE2]], 1
+// SIGNED-NEXT:   [[RESIZE4:%.*]] = zext i16 [[TMP3]] to i33
+// SIGNED-NEXT:   [[TMP5:%.*]] = add i33 [[UPSCALE3]], [[RESIZE4]]
+// SIGNED-NEXT:   [[DOWNSCALE5:%.*]] = ashr i33 [[TMP5]], 1
+// SIGNED-NEXT:   [[RESIZE6:%.*]] = trunc i33 [[DOWNSCALE5]] to i32
+// SIGNED-NEXT:   store i32 [[RESIZE6]], i32* @a, align 4
+// UNSIGNED-NEXT: [[RESIZE2:%.*]] = zext i16 [[TMP3]] to i32
+// UNSIGNED-NEXT: [[TMP5:%.*]] = add i32 [[TMP4]], [[RESIZE2]]
+// UNSIGNED-NEXT: store i32 [[TMP5]], i32* @a, align 4
+  a += uf;
+
+// CHECK: [[TMP6:%.*]] = load i64, i64* @ula, align 8
+// CHECK-NEXT:[[TMP7:%.*]] = load i16, i16* @uf, align 2
+// CHECK-NEXT:[[RESIZE7:%.*]] = zext i16 [[TMP7]] to i64
+// CHECK-NEXT:[[UPSCALE8:%.*]] = shl i64 [[RESIZE7]], 16
+// CHECK-NEXT:[[TMP8:%.*]] = add i64 [[UPSCALE8]], [[TMP6]]
+// CHECK-NEXT:[[DOWNSCALE9:%.*]] = lshr i64 [[TMP8]], 16
+// CHECK-NEXT:[[RESIZE10:%.*]] = trunc i64 [[DOWNSCALE9]] to i16
+// CHECK-NEXT:store i16 [[RESIZE10]], i16* @uf, align 2
+  uf += ula;
+
+// CHECK: [[TMP9:%.*]] = load i8, i8* @shf, align 1
+// CHECK-NEXT:[[TMP10:%.*]] = load i64, i64* @ula, align 8
+// SIGNED-NEXT:   [[RESIZE11:%.*]] = zext i64 [[TMP10]] to i65
+// SIGNED-NEXT:   [[RESIZE12:%.*]] = sext i8 [[TMP9]] to i65
+// SIGNED-NEXT:   [[UPSCALE13:%.*]] = shl i65 [[RESIZE12]], 25
+// SIGNED-NEXT:   [[TMP11:%.*]] = add i65 [[RESIZE11]], [[UPSCALE13]]
+// SIGNED-NEXT:   [[DOWNSCALE14:%.*]] = ashr i65 [[TMP11]], 1
+// SIGNED-NEXT:   [[RESIZE15:%.*]] = trunc i65 [[DOWNSCALE14]] to i64
+// SIGNED-NEXT:   [[UPSCALE16:%.*]] = shl i64 [[RESIZE15]], 1
+// SIGNED-NEXT:   store i64 [[UPSCALE16]], i64* @ula, align 8
+// UNSIGNED-NEXT: [[RESIZE7:%.*]] = sext i8 [[TMP9]] to i64
+// UNSIGNED-NEXT: [[UPSCALE8:%.*]] = shl i64 [[RESIZE7]], 24
+// UNSIGNED-NEXT: [[TMP11:%.*]] = add i64 [[TMP10]], [[UPSCALE8]]
+// UNSIGNED-NEXT: store i64 [[TMP11]], i64* @ula, align 8
+  ula += shf;
+
+// CHECK: [[TMP12:%.*]] = load i8, i8* @shf, align 1
+// CHECK-NEXT:[[TMP13:%.*]] = load i16, i16* @uf, align 2
+// SIGNED-NEXT:   [[RESIZE17:%.*]] = zext i16 [[TMP13]] to i17
+// SIGNED-NEXT:   [[RESIZE18:%.*]] = sext i8 [[TMP12]] to i17
+// SIGNED-NEXT:   [[UPSCALE19:%.*]] = shl i17 [[RESIZE18]], 9
+// SIGNED-NEXT:   [[TMP14:%.*]] = add i17 [[RESIZE17]], [[UPSCALE19]]
+// SIGNED-NEXT:   [[DOWNSCALE20:%.*]] = ashr i17 [[TMP14]], 1
+// SIGNED-NEXT:   [[RESIZE21:%.*]] = trunc i17 [[DOWNSCALE20]] to i16
+// SIGNED-NEXT:   [[UPSCALE22:%.*]] = shl i16 [[RESIZE21]], 1
+// SIGNED-NEXT:   store i16 [[UPSCALE22]], i16* @uf, align 2
+// UNSIGNED-NEXT: [[RESIZE9:%.*]] = sext i8 [[TMP12]] to i16
+// UNSIGNED-NEXT: [[UPSCALE10:%.*]] = shl i16 [[RESIZE9]], 8
+// UNSIGNED-NEXT: [[TMP14:%.*]] = add i16 [[TMP13]], [[UPSCALE10]]
+// UNSIGNED-NEXT: store i16 [[TMP14]], i16* @uf, align 2
+  uf += shf;
+
+// CHECK: [[TMP15:%.*]] = load i8, i8* @shf, align 1
+// CHECK-NEXT:[[TMP16:%.*]] = load i32, i32* @a, align 4
+// CHECK-NEXT:[[RESIZE23:%.*]] = sext i8 [[TMP15]] to i32
+// CHECK-NEXT:[[UPSCALE24:%.*]] = shl i32 [[RESIZE23]], 8
+// CHECK-NEXT:[[TMP17:%.*]] = add i32 [[TMP16]], [[UPSCALE24]]
+//