[PATCH] D74222: [AArch64][SVE] Add mul/mla/mls lane & dup intrinsics

2020-02-13 Thread Kerry McLaughlin via Phabricator via cfe-commits 
This revision was automatically updated to reflect the committed changes.
Closed by commit rG671cbc1fbba0: [AArch64][SVE] Add mul/mla/mls lane & dup 
intrinsics (authored by kmclaughlin).

Changed prior to commit:
  https://reviews.llvm.org/D74222?vs=243164&id=244372#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D74222/new/

https://reviews.llvm.org/D74222

Files:
  llvm/include/llvm/IR/IntrinsicsAArch64.td
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/lib/Target/AArch64/AArch64ISelLowering.h
  llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
  llvm/lib/Target/AArch64/SVEInstrFormats.td
  llvm/test/CodeGen/AArch64/sve-intrinsics-scalar-to-vec.ll
  llvm/test/CodeGen/AArch64/sve2-intrinsics-int-mul-lane.ll

Index: llvm/test/CodeGen/AArch64/sve2-intrinsics-int-mul-lane.ll
===
--- /dev/null
+++ llvm/test/CodeGen/AArch64/sve2-intrinsics-int-mul-lane.ll
@@ -0,0 +1,119 @@
+; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2 < %s | FileCheck %s
+
+;
+; MUL
+;
+
+define  @mul_lane_d( %a,  %b) {
+; CHECK-LABEL: mul_lane_d:
+; CHECK: mul z0.d, z0.d, z1.d[1]
+; CHECK-NEXT: ret
+  %out = call  @llvm.aarch64.sve.mul.lane.nxv2i64( %a,
+ %b,
+i32 1)
+  ret  %out
+}
+
+define  @mul_lane_s( %a,  %b) {
+; CHECK-LABEL: mul_lane_s:
+; CHECK: mul z0.s, z0.s, z1.s[1]
+; CHECK-NEXT: ret
+  %out = call  @llvm.aarch64.sve.mul.lane.nxv4i32( %a,
+ %b,
+i32 1)
+  ret  %out
+}
+
+define  @mul_lane_h( %a,  %b) {
+; CHECK-LABEL: mul_lane_h:
+; CHECK: mul z0.h, z0.h, z1.h[1]
+; CHECK-NEXT: ret
+  %out = call  @llvm.aarch64.sve.mul.lane.nxv8i16( %a,
+ %b,
+i32 1)
+  ret  %out
+}
+
+;
+; MLA
+;
+
+define  @mla_lane_d( %a,  %b,  %c) {
+; CHECK-LABEL: mla_lane_d:
+; CHECK: mla z0.d, z1.d, z2.d[1]
+; CHECK-NEXT: ret
+  %out = call  @llvm.aarch64.sve.mla.lane.nxv2i64( %a,
+ %b,
+ %c,
+i32 1)
+  ret  %out
+}
+
+define  @mla_lane_s( %a,  %b,  %c) {
+; CHECK-LABEL: mla_lane_s:
+; CHECK: mla z0.s, z1.s, z2.s[1]
+; CHECK-NEXT: ret
+  %out = call  @llvm.aarch64.sve.mla.lane.nxv4i32( %a,
+ %b,
+ %c,
+i32 1)
+  ret  %out
+}
+
+define  @mla_lane_h( %a,  %b,  %c) {
+; CHECK-LABEL: mla_lane_h:
+; CHECK: mla z0.h, z1.h, z2.h[1]
+; CHECK-NEXT: ret
+  %out = call  @llvm.aarch64.sve.mla.lane.nxv8i16( %a,
+ %b,
+ %c,
+i32 1)
+  ret  %out
+}
+
+;
+; MLS
+;
+
+define  @mls_lane_d( %a,  %b,  %c) {
+; CHECK-LABEL: mls_lane_d:
+; CHECK: mls z0.d, z1.d, z2.d[1]
+; CHECK-NEXT: ret
+  %out = call  @llvm.aarch64.sve.mls.lane.nxv2i64( %a,
+ %b,
+ %c,
+i32 1)
+  ret  %out
+}
+
+define  @mls_lane_s( %a,  %b,  %c) {
+; CHECK-LABEL: mls_lane_s:
+; CHECK: mls z0.s, z1.s, z2.s[1]
+; CHECK-NEXT: ret
+  %out = call  @llvm.aarch64.sve.mls.lane.nxv4i32( %a,
+ %b,
+ %c,
+i32 1)
+  ret  %out
+}
+
+define  @mls_lane_h( %a,  %b,  %c) {
+; CHECK-LABEL: mls_lane_h:
+; CHECK: mls z0.h, z1.h, z2.h[1]
+; CHECK-NEXT: ret
+  %out = call  @llvm.aarch64.sve.mls.lane.nxv8i16( %a,
+ %b,
+ %c,
+i32 1)
+  ret  %out
+}
+
+declare  @llvm.aarch64.sve.mul.lane.nxv8i16(, , i32)
+declare  @llvm.aarch64.sve.mul.lane.nxv4i32(, , i32)
+declare  @llvm.aarch64.sve.mul.lane.nxv2i64(, , i32)
+declare  @llvm.aarch64.sve.mla.lane.nxv8i16(, , , i32)
+declare  @llvm.aarch64.sve.mla.lane.nxv4i32(, , , i32)
+declare  @llvm.aarch64.sve.mla.lane.nxv2i64(, , , i32)
+declare  @llvm.aarch64.sve.mls.

[PATCH] D74222: [AArch64][SVE] Add mul/mla/mls lane & dup intrinsics

2020-02-12 Thread Sander de Smalen via Phabricator via cfe-commits 
sdesmalen accepted this revision.
sdesmalen added a comment.
This revision is now accepted and ready to land.

LGTM!


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D74222/new/

https://reviews.llvm.org/D74222



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[PATCH] D74222: [AArch64][SVE] Add mul/mla/mls lane & dup intrinsics

2020-02-07 Thread Kerry McLaughlin via Phabricator via cfe-commits 
kmclaughlin created this revision.
kmclaughlin added reviewers: c-rhodes, sdesmalen, dancgr, efriedma.
Herald added subscribers: psnobl, rkruppe, hiraditya, kristof.beyls, tschuett.
Herald added a reviewer: rengolin.
Herald added a project: LLVM.

Implements the following intrinsics:

- @llvm.aarch64.sve.dup
- @llvm.aarch64.sve.mul.lane
- @llvm.aarch64.sve.mla.lane
- @llvm.aarch64.sve.mls.lane


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D74222

Files:
  llvm/include/llvm/IR/IntrinsicsAArch64.td
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/lib/Target/AArch64/AArch64ISelLowering.h
  llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
  llvm/lib/Target/AArch64/SVEInstrFormats.td
  llvm/test/CodeGen/AArch64/sve-intrinsics-scalar-to-vec.ll
  llvm/test/CodeGen/AArch64/sve2-intrinsics-int-mul-lane.ll

Index: llvm/test/CodeGen/AArch64/sve2-intrinsics-int-mul-lane.ll
===
--- /dev/null
+++ llvm/test/CodeGen/AArch64/sve2-intrinsics-int-mul-lane.ll
@@ -0,0 +1,119 @@
+; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2 < %s | FileCheck %s
+
+;
+; MUL
+;
+
+define  @mul_lane_d( %a,  %b) {
+; CHECK-LABEL: mul_lane_d:
+; CHECK: mul z0.d, z0.d, z1.d[1]
+; CHECK-NEXT: ret
+  %out = call  @llvm.aarch64.sve.mul.lane.nxv2i64( %a,
+ %b,
+i32 1)
+  ret  %out
+}
+
+define  @mul_lane_s( %a,  %b) {
+; CHECK-LABEL: mul_lane_s:
+; CHECK: mul z0.s, z0.s, z1.s[1]
+; CHECK-NEXT: ret
+  %out = call  @llvm.aarch64.sve.mul.lane.nxv4i32( %a,
+ %b,
+i32 1)
+  ret  %out
+}
+
+define  @mul_lane_h( %a,  %b) {
+; CHECK-LABEL: mul_lane_h:
+; CHECK: mul z0.h, z0.h, z1.h[1]
+; CHECK-NEXT: ret
+  %out = call  @llvm.aarch64.sve.mul.lane.nxv8i16( %a,
+ %b,
+i32 1)
+  ret  %out
+}
+
+;
+; MLA
+;
+
+define  @mla_lane_d( %a,  %b,  %c) {
+; CHECK-LABEL: mla_lane_d:
+; CHECK: mla z0.d, z1.d, z2.d[1]
+; CHECK-NEXT: ret
+  %out = call  @llvm.aarch64.sve.mla.lane.nxv2i64( %a,
+ %b,
+ %c,
+i32 1)
+  ret  %out
+}
+
+define  @mla_lane_s( %a,  %b,  %c) {
+; CHECK-LABEL: mla_lane_s:
+; CHECK: mla z0.s, z1.s, z2.s[1]
+; CHECK-NEXT: ret
+  %out = call  @llvm.aarch64.sve.mla.lane.nxv4i32( %a,
+ %b,
+ %c,
+i32 1)
+  ret  %out
+}
+
+define  @mla_lane_h( %a,  %b,  %c) {
+; CHECK-LABEL: mla_lane_h:
+; CHECK: mla z0.h, z1.h, z2.h[1]
+; CHECK-NEXT: ret
+  %out = call  @llvm.aarch64.sve.mla.lane.nxv8i16( %a,
+ %b,
+ %c,
+i32 1)
+  ret  %out
+}
+
+;
+; MLS
+;
+
+define  @mls_lane_d( %a,  %b,  %c) {
+; CHECK-LABEL: mls_lane_d:
+; CHECK: mls z0.d, z1.d, z2.d[1]
+; CHECK-NEXT: ret
+  %out = call  @llvm.aarch64.sve.mls.lane.nxv2i64( %a,
+ %b,
+ %c,
+i32 1)
+  ret  %out
+}
+
+define  @mls_lane_s( %a,  %b,  %c) {
+; CHECK-LABEL: mls_lane_s:
+; CHECK: mls z0.s, z1.s, z2.s[1]
+; CHECK-NEXT: ret
+  %out = call  @llvm.aarch64.sve.mls.lane.nxv4i32( %a,
+ %b,
+ %c,
+i32 1)
+  ret  %out
+}
+
+define  @mls_lane_h( %a,  %b,  %c) {
+; CHECK-LABEL: mls_lane_h:
+; CHECK: mls z0.h, z1.h, z2.h[1]
+; CHECK-NEXT: ret
+  %out = call  @llvm.aarch64.sve.mls.lane.nxv8i16( %a,
+ %b,
+ %c,
+i32 1)
+  ret  %out
+}
+
+declare  @llvm.aarch64.sve.mul.lane.nxv8i16(, , i32)
+declare  @llvm.aarch64.sve.mul.lane.nxv4i32(, , i32)
+declare  @llvm.aarch64.sve.mul.lane.nxv2i64(, , i32)
+declare  @llvm.aarch64.sve.mla.lane.nxv8i16(, , , i32)
+declare  @llvm.aarch64.sve.mla.lane.nxv4i32(, , , i32)
+declare  @llvm.aarch64.sve.