[PATCH] D74483: [AArch64] Add Cortex-A34 Support for clang and llvm

2020-02-18 Thread Luke Geeson via Phabricator via cfe-commits 
LukeGeeson closed this revision.
LukeGeeson marked an inline comment as not done.
LukeGeeson added inline comments.



Comment at: llvm/unittests/Support/TargetParserTest.cpp:784
   EXPECT_TRUE(testAArch64CPU(
+  "cortex-a34", "armv8-a", "crypto-neon-fp-armv8",
+  AArch64::AEK_CRC | AArch64::AEK_SIMD |

SjoerdMeijer wrote:
> nit: this looks the same as the a35. Would be better to keep the same order 
> of arch extension and also the formatting (to make it easier to eyeball 
> differences).
Good spot thanks, fixed.


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[PATCH] D74483: [AArch64] Add Cortex-A34 Support for clang and llvm

2020-02-13 Thread Sjoerd Meijer via Phabricator via cfe-commits 
SjoerdMeijer added a comment.

Cheers, LGTM


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[PATCH] D74483: [AArch64] Add Cortex-A34 Support for clang and llvm

2020-02-13 Thread Luke Geeson via Phabricator via cfe-commits 
LukeGeeson updated this revision to Diff 244377.
LukeGeeson marked an inline comment as done.
LukeGeeson added a comment.

- Added MIDR to Host.cpp
- Fixed a clang test I missed (copy/paste error)


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Files:
  clang/test/Driver/aarch64-cpus.c
  clang/test/Preprocessor/aarch64-target-features.c
  llvm/include/llvm/Support/AArch64TargetParser.def
  llvm/lib/Support/Host.cpp
  llvm/lib/Target/AArch64/AArch64.td
  llvm/test/CodeGen/AArch64/cpus.ll
  llvm/test/CodeGen/AArch64/remat.ll
  llvm/unittests/Support/TargetParserTest.cpp

Index: llvm/unittests/Support/TargetParserTest.cpp
===
--- llvm/unittests/Support/TargetParserTest.cpp
+++ llvm/unittests/Support/TargetParserTest.cpp
@@ -781,6 +781,10 @@
   AArch64::AEK_NONE, ""));
 
   EXPECT_TRUE(testAArch64CPU(
+  "cortex-a34", "armv8-a", "crypto-neon-fp-armv8",
+  AArch64::AEK_CRC | AArch64::AEK_CRYPTO | AArch64::AEK_FP |
+  AArch64::AEK_SIMD, "8-A"));
+  EXPECT_TRUE(testAArch64CPU(
   "cortex-a35", "armv8-a", "crypto-neon-fp-armv8",
   AArch64::AEK_CRC | AArch64::AEK_CRYPTO | AArch64::AEK_FP |
   AArch64::AEK_SIMD, "8-A"));
@@ -957,7 +961,7 @@
   "8.2-A"));
 }
 
-static constexpr unsigned NumAArch64CPUArchs = 35;
+static constexpr unsigned NumAArch64CPUArchs = 36;
 
 TEST(TargetParserTest, testAArch64CPUArchList) {
   SmallVector List;
@@ -1002,6 +1006,8 @@
 }
 
 TEST(TargetParserTest, testAArch64Extension) {
+  EXPECT_FALSE(testAArch64Extension("cortex-a34",
+AArch64::ArchKind::INVALID, "ras"));
   EXPECT_FALSE(testAArch64Extension("cortex-a35",
 AArch64::ArchKind::INVALID, "ras"));
   EXPECT_FALSE(testAArch64Extension("cortex-a53",
Index: llvm/test/CodeGen/AArch64/remat.ll
===
--- llvm/test/CodeGen/AArch64/remat.ll
+++ llvm/test/CodeGen/AArch64/remat.ll
@@ -1,3 +1,4 @@
+; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=cortex-a34 -o - %s | FileCheck %s
 ; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=cortex-a35 -o - %s | FileCheck %s
 ; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=cortex-a53 -o - %s | FileCheck %s
 ; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=cortex-a55 -o - %s | FileCheck %s
Index: llvm/test/CodeGen/AArch64/cpus.ll
===
--- llvm/test/CodeGen/AArch64/cpus.ll
+++ llvm/test/CodeGen/AArch64/cpus.ll
@@ -3,6 +3,7 @@
 
 ; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=generic 2>&1 | FileCheck %s
 ; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=cortex-a35 2>&1 | FileCheck %s
+; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=cortex-a34 2>&1 | FileCheck %s
 ; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=cortex-a53 2>&1 | FileCheck %s
 ; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=cortex-a55 2>&1 | FileCheck %s
 ; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=cortex-a57 2>&1 | FileCheck %s
Index: llvm/lib/Target/AArch64/AArch64.td
===
--- llvm/lib/Target/AArch64/AArch64.td
+++ llvm/lib/Target/AArch64/AArch64.td
@@ -853,6 +853,7 @@
  ]>;
 
 def : ProcessorModel<"cortex-a35", CortexA53Model, [ProcA35]>;
+def : ProcessorModel<"cortex-a34", CortexA53Model, [ProcA35]>;
 def : ProcessorModel<"cortex-a53", CortexA53Model, [ProcA53]>;
 def : ProcessorModel<"cortex-a55", CortexA53Model, [ProcA55]>;
 def : ProcessorModel<"cortex-a57", CortexA57Model, [ProcA57]>;
Index: llvm/lib/Support/Host.cpp
===
--- llvm/lib/Support/Host.cpp
+++ llvm/lib/Support/Host.cpp
@@ -178,6 +178,8 @@
 // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The
 // values correspond to the "Part number" in the CP15/c0 register. The
 // contents are specified in the various processor manuals.
+// This corresponds to the Main ID Register in Technical Reference Manuals.
+// and is used in programs like sys-utils
 return StringSwitch(Lines[I].substr(8).ltrim("\t :"))
 .Case("0x926", "arm926ej-s")
 .Case("0xb02", "mpcore")
@@ -190,6 +192,7 @@
 .Case("0xc20", "cortex-m0")
 .Case("0xc23", "cortex-m3")
 .Case("0xc24", "cortex-m4")
+.Case("0xd02", "cortex-a34")
 .Case("0xd04", "cortex-a35")
 .Case("0xd03", "cortex-a53")
 .Case("0xd07", "cortex-a57")
Index: llvm/include/llvm/Support/AArch64TargetParser.def
===
--- llvm/include/llvm/Support/AArch64TargetParser.def
+++ llvm/include/llvm/Support/AArch64TargetParser.def
@@ -85,6 +85,8 @@
 #ifndef AARCH64_CPU_NAME
 #define AARCH64_CPU_NAME(NAME, ID, DEFAULT_FPU,

[PATCH] D74483: [AArch64] Add Cortex-A34 Support for clang and llvm

2020-02-12 Thread Sjoerd Meijer via Phabricator via cfe-commits 
SjoerdMeijer added a comment.

Ah, sorry, looks like this is all there is to it, both clang and llvm. It's 
just that a quick grep locally (for a similar core) showed some more results.

Can you (double) check if it needs adding to e.g. a switch in 
`llvm/lib/Support/Host.cpp`?


Repository:
  rG LLVM Github Monorepo

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[PATCH] D74483: [AArch64] Add Cortex-A34 Support for clang and llvm

2020-02-12 Thread Sjoerd Meijer via Phabricator via cfe-commits 
SjoerdMeijer accepted this revision.
SjoerdMeijer added a comment.
This revision is now accepted and ready to land.

Looks like the usual business of adding a cpu to me, with one nit inlined that 
can be fixed before committing.

Looks like you're doing the LLVM part separately. Now with the monorepo you 
could have conveniently done it in one patch, but nothing wrong with doing it 
separately.  You could have linked to the llvm part here if that is ready, 
which would be nice to get an overview.




Comment at: llvm/unittests/Support/TargetParserTest.cpp:784
   EXPECT_TRUE(testAArch64CPU(
+  "cortex-a34", "armv8-a", "crypto-neon-fp-armv8",
+  AArch64::AEK_CRC | AArch64::AEK_SIMD |

nit: this looks the same as the a35. Would be better to keep the same order of 
arch extension and also the formatting (to make it easier to eyeball 
differences).


Repository:
  rG LLVM Github Monorepo

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[PATCH] D74483: [AArch64] Add Cortex-A34 Support for clang and llvm

2020-02-12 Thread Luke Geeson via Phabricator via cfe-commits 
LukeGeeson created this revision.
Herald added subscribers: llvm-commits, cfe-commits, hiraditya, kristof.beyls.
Herald added projects: clang, LLVM.

This patch upstreams support for the AArch64 Armv8-A cpu Cortex-A34.


   

In detail adding support for:

- mcpu option in clang
- AArch64 Target Features in clang
- llvm AArch64 TargetParser definitions

  details of the cpu can be found here: 
https://developer.arm.com/ip-products/processors/cortex-a/cortex-a34


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D74483

Files:
  clang/test/Driver/aarch64-cpus.c
  clang/test/Preprocessor/aarch64-target-features.c
  llvm/include/llvm/Support/AArch64TargetParser.def
  llvm/lib/Target/AArch64/AArch64.td
  llvm/test/CodeGen/AArch64/cpus.ll
  llvm/test/CodeGen/AArch64/remat.ll
  llvm/unittests/Support/TargetParserTest.cpp

Index: llvm/unittests/Support/TargetParserTest.cpp
===
--- llvm/unittests/Support/TargetParserTest.cpp
+++ llvm/unittests/Support/TargetParserTest.cpp
@@ -781,6 +781,11 @@
   AArch64::AEK_NONE, ""));
 
   EXPECT_TRUE(testAArch64CPU(
+  "cortex-a34", "armv8-a", "crypto-neon-fp-armv8",
+  AArch64::AEK_CRC | AArch64::AEK_SIMD |
+  AArch64::AEK_FP | AArch64::AEK_CRYPTO,
+  "8-A"));
+  EXPECT_TRUE(testAArch64CPU(
   "cortex-a35", "armv8-a", "crypto-neon-fp-armv8",
   AArch64::AEK_CRC | AArch64::AEK_CRYPTO | AArch64::AEK_FP |
   AArch64::AEK_SIMD, "8-A"));
@@ -957,7 +962,7 @@
   "8.2-A"));
 }
 
-static constexpr unsigned NumAArch64CPUArchs = 35;
+static constexpr unsigned NumAArch64CPUArchs = 36;
 
 TEST(TargetParserTest, testAArch64CPUArchList) {
   SmallVector List;
@@ -1002,6 +1007,8 @@
 }
 
 TEST(TargetParserTest, testAArch64Extension) {
+  EXPECT_FALSE(testAArch64Extension("cortex-a34",
+AArch64::ArchKind::INVALID, "ras"));
   EXPECT_FALSE(testAArch64Extension("cortex-a35",
 AArch64::ArchKind::INVALID, "ras"));
   EXPECT_FALSE(testAArch64Extension("cortex-a53",
Index: llvm/test/CodeGen/AArch64/remat.ll
===
--- llvm/test/CodeGen/AArch64/remat.ll
+++ llvm/test/CodeGen/AArch64/remat.ll
@@ -1,3 +1,4 @@
+; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=cortex-a34 -o - %s | FileCheck %s
 ; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=cortex-a35 -o - %s | FileCheck %s
 ; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=cortex-a53 -o - %s | FileCheck %s
 ; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=cortex-a55 -o - %s | FileCheck %s
Index: llvm/test/CodeGen/AArch64/cpus.ll
===
--- llvm/test/CodeGen/AArch64/cpus.ll
+++ llvm/test/CodeGen/AArch64/cpus.ll
@@ -3,6 +3,7 @@
 
 ; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=generic 2>&1 | FileCheck %s
 ; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=cortex-a35 2>&1 | FileCheck %s
+; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=cortex-a34 2>&1 | FileCheck %s
 ; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=cortex-a53 2>&1 | FileCheck %s
 ; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=cortex-a55 2>&1 | FileCheck %s
 ; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=cortex-a57 2>&1 | FileCheck %s
Index: llvm/lib/Target/AArch64/AArch64.td
===
--- llvm/lib/Target/AArch64/AArch64.td
+++ llvm/lib/Target/AArch64/AArch64.td
@@ -853,6 +853,7 @@
  ]>;
 
 def : ProcessorModel<"cortex-a35", CortexA53Model, [ProcA35]>;
+def : ProcessorModel<"cortex-a34", CortexA53Model, [ProcA35]>;
 def : ProcessorModel<"cortex-a53", CortexA53Model, [ProcA53]>;
 def : ProcessorModel<"cortex-a55", CortexA53Model, [ProcA55]>;
 def : ProcessorModel<"cortex-a57", CortexA57Model, [ProcA57]>;
Index: llvm/include/llvm/Support/AArch64TargetParser.def
===
--- llvm/include/llvm/Support/AArch64TargetParser.def
+++ llvm/include/llvm/Support/AArch64TargetParser.def
@@ -85,6 +85,8 @@
 #ifndef AARCH64_CPU_NAME
 #define AARCH64_CPU_NAME(NAME, ID, DEFAULT_FPU, IS_DEFAULT, DEFAULT_EXT)
 #endif
+AARCH64_CPU_NAME("cortex-a34", ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false,
+ (AArch64::AEK_CRC))
 AARCH64_CPU_NAME("cortex-a35", ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false,
  (AArch64::AEK_CRC))
 AARCH64_CPU_NAME("cortex-a53", ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, true,
Index: clang/test/Preprocessor/aarch64-target-features.c
===
--- clang/test/Preprocessor/aarch64-target-features.c
+++ clang/test/Preprocessor/aarch64-target-features.c
@@ -152,6 +152,7 @@
 // RUN: %clang -target aarch64 -mcpu=apple-s4 -### -c %s 2>&1 | FileCheck