subject:"\[PATCH\] D76397\: \[WebAssembly\] SIMD bitmask intrinsics and builtin functions"

[PATCH] D76397: [WebAssembly] SIMD bitmask intrinsics and builtin functions

2020-03-19 Thread Thomas Lively via Phabricator via cfe-commits

This revision was automatically updated to reflect the committed changes.
Closed by commit rGa3f974f3c332: [WebAssembly] SIMD bitmask intrinsics and 
builtin functions (authored by tlively).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D76397/new/

https://reviews.llvm.org/D76397

Files:
  clang/include/clang/Basic/BuiltinsWebAssembly.def
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/builtins-wasm.c
  llvm/include/llvm/IR/IntrinsicsWebAssembly.td
  llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
  llvm/test/CodeGen/WebAssembly/simd-intrinsics.ll
  llvm/test/MC/WebAssembly/simd-encodings.s

Index: llvm/test/MC/WebAssembly/simd-encodings.s
===
--- llvm/test/MC/WebAssembly/simd-encodings.s
+++ llvm/test/MC/WebAssembly/simd-encodings.s
@@ -580,4 +580,13 @@
 # CHECK: i32x4.dot_i16x8_s # encoding: [0xfd,0xdb,0x01]
 i32x4.dot_i16x8_s
 
+# CHECK: i8x16.bitmask # encoding: [0xfd,0xe4,0x01]
+i8x16.bitmask
+
+# CHECK: i16x8.bitmask # encoding: [0xfd,0xe5,0x01]
+i16x8.bitmask
+
+# CHECK: i32x4.bitmask # encoding: [0xfd,0xe6,0x01]
+i32x4.bitmask
+
 end_function
Index: llvm/test/CodeGen/WebAssembly/simd-intrinsics.ll
===
--- llvm/test/CodeGen/WebAssembly/simd-intrinsics.ll
+++ llvm/test/CodeGen/WebAssembly/simd-intrinsics.ll
@@ -95,6 +95,16 @@
   ret i32 %a
 }
 
+; CHECK-LABEL: bitmask_v16i8:
+; SIMD128-NEXT: .functype bitmask_v16i8 (v128) -> (i32){{$}}
+; SIMD128-NEXT: i8x16.bitmask $push[[R:[0-9]+]]=, $0{{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+declare i32 @llvm.wasm.bitmask.v16i8(<16 x i8>)
+define i32 @bitmask_v16i8(<16 x i8> %x) {
+  %a = call i32 @llvm.wasm.bitmask.v16i8(<16 x i8> %x)
+  ret i32 %a
+}
+
 ; CHECK-LABEL: bitselect_v16i8:
 ; SIMD128-NEXT: .functype bitselect_v16i8 (v128, v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $0, $1, $2{{$}}
@@ -208,6 +218,16 @@
   ret i32 %a
 }
 
+; CHECK-LABEL: bitmask_v8i16:
+; SIMD128-NEXT: .functype bitmask_v8i16 (v128) -> (i32){{$}}
+; SIMD128-NEXT: i16x8.bitmask $push[[R:[0-9]+]]=, $0{{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+declare i32 @llvm.wasm.bitmask.v8i16(<8 x i16>)
+define i32 @bitmask_v8i16(<8 x i16> %x) {
+  %a = call i32 @llvm.wasm.bitmask.v8i16(<8 x i16> %x)
+  ret i32 %a
+}
+
 ; CHECK-LABEL: bitselect_v8i16:
 ; SIMD128-NEXT: .functype bitselect_v8i16 (v128, v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $0, $1, $2{{$}}
@@ -317,6 +337,16 @@
   ret i32 %a
 }
 
+; CHECK-LABEL: bitmask_v4i32:
+; SIMD128-NEXT: .functype bitmask_v4i32 (v128) -> (i32){{$}}
+; SIMD128-NEXT: i32x4.bitmask $push[[R:[0-9]+]]=, $0{{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+declare i32 @llvm.wasm.bitmask.v4i32(<4 x i32>)
+define i32 @bitmask_v4i32(<4 x i32> %x) {
+  %a = call i32 @llvm.wasm.bitmask.v4i32(<4 x i32> %x)
+  ret i32 %a
+}
+
 ; CHECK-LABEL: bitselect_v4i32:
 ; SIMD128-NEXT: .functype bitselect_v4i32 (v128, v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $0, $1, $2{{$}}
Index: llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
===
--- llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
+++ llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
@@ -606,6 +606,18 @@
   (i32 (!cast(reduction[1]#"_"#ty) (ty V128:$x)))>;
 }
 
+multiclass SIMDBitmask simdop> {
+  defm _#vec_t : SIMD_I<(outs I32:$dst), (ins V128:$vec), (outs), (ins),
+ [(set I32:$dst,
+   (i32 (int_wasm_bitmask (vec_t V128:$vec)))
+ )],
+ vec#".bitmask\t$dst, $vec", vec#".bitmask", simdop>;
+}
+
+defm BITMASK : SIMDBitmask;
+defm BITMASK : SIMDBitmask;
+defm BITMASK : SIMDBitmask;
+
 //===--===//
 // Bit shifts
 //===--===//
Index: llvm/include/llvm/IR/IntrinsicsWebAssembly.td
===
--- llvm/include/llvm/IR/IntrinsicsWebAssembly.td
+++ llvm/include/llvm/IR/IntrinsicsWebAssembly.td
@@ -129,6 +129,10 @@
   Intrinsic<[llvm_i32_ty],
 [llvm_anyvector_ty],
 [IntrNoMem, IntrSpeculatable]>;
+def int_wasm_bitmask :
+  Intrinsic<[llvm_i32_ty],
+[llvm_anyvector_ty],
+[IntrNoMem, IntrSpeculatable]>;
 def int_wasm_qfma :
   Intrinsic<[llvm_anyvector_ty],
 [LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>],
Index: clang/test/CodeGen/builtins-wasm.c
===
--- clang/test/CodeGen/builtins-wasm.c
+++ clang/test/CodeGen/builtins-wasm.c
@@ -511,6 +511,24 @@
   // WEBASSEMBLY: ret
 }
 
+int bitmask_i8x16(i8x16 x) {
+  return

[PATCH] D76397: [WebAssembly] SIMD bitmask intrinsics and builtin functions

2020-03-18 Thread Thomas Lively via Phabricator via cfe-commits

tlively created this revision.
tlively added a reviewer: aheejin.
Herald added subscribers: cfe-commits, sunfish, hiraditya, jgravelle-google, 
sbc100, dschuff.
Herald added a project: clang.

These experimental new instructions are proposed in
https://github.com/WebAssembly/simd/pull/201.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D76397

Files:
  clang/include/clang/Basic/BuiltinsWebAssembly.def
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/builtins-wasm.c
  llvm/include/llvm/IR/IntrinsicsWebAssembly.td
  llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
  llvm/test/CodeGen/WebAssembly/simd-intrinsics.ll
  llvm/test/MC/WebAssembly/simd-encodings.s

Index: llvm/test/MC/WebAssembly/simd-encodings.s
===
--- llvm/test/MC/WebAssembly/simd-encodings.s
+++ llvm/test/MC/WebAssembly/simd-encodings.s
@@ -580,4 +580,13 @@
 # CHECK: i32x4.dot_i16x8_s # encoding: [0xfd,0xdb,0x01]
 i32x4.dot_i16x8_s
 
+# CHECK: i8x16.bitmask # encoding: [0xfd,0xe4,0x01]
+i8x16.bitmask
+
+# CHECK: i16x8.bitmask # encoding: [0xfd,0xe5,0x01]
+i16x8.bitmask
+
+# CHECK: i32x4.bitmask # encoding: [0xfd,0xe6,0x01]
+i32x4.bitmask
+
 end_function
Index: llvm/test/CodeGen/WebAssembly/simd-intrinsics.ll
===
--- llvm/test/CodeGen/WebAssembly/simd-intrinsics.ll
+++ llvm/test/CodeGen/WebAssembly/simd-intrinsics.ll
@@ -95,6 +95,16 @@
   ret i32 %a
 }
 
+; CHECK-LABEL: bitmask_v16i8:
+; SIMD128-NEXT: .functype bitmask_v16i8 (v128) -> (i32){{$}}
+; SIMD128-NEXT: i8x16.bitmask $push[[R:[0-9]+]]=, $0{{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+declare i32 @llvm.wasm.bitmask.v16i8(<16 x i8>)
+define i32 @bitmask_v16i8(<16 x i8> %x) {
+  %a = call i32 @llvm.wasm.bitmask.v16i8(<16 x i8> %x)
+  ret i32 %a
+}
+
 ; CHECK-LABEL: bitselect_v16i8:
 ; SIMD128-NEXT: .functype bitselect_v16i8 (v128, v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $0, $1, $2{{$}}
@@ -208,6 +218,16 @@
   ret i32 %a
 }
 
+; CHECK-LABEL: bitmask_v8i16:
+; SIMD128-NEXT: .functype bitmask_v8i16 (v128) -> (i32){{$}}
+; SIMD128-NEXT: i16x8.bitmask $push[[R:[0-9]+]]=, $0{{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+declare i32 @llvm.wasm.bitmask.v8i16(<8 x i16>)
+define i32 @bitmask_v8i16(<8 x i16> %x) {
+  %a = call i32 @llvm.wasm.bitmask.v8i16(<8 x i16> %x)
+  ret i32 %a
+}
+
 ; CHECK-LABEL: bitselect_v8i16:
 ; SIMD128-NEXT: .functype bitselect_v8i16 (v128, v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $0, $1, $2{{$}}
@@ -317,6 +337,16 @@
   ret i32 %a
 }
 
+; CHECK-LABEL: bitmask_v4i32:
+; SIMD128-NEXT: .functype bitmask_v4i32 (v128) -> (i32){{$}}
+; SIMD128-NEXT: i32x4.bitmask $push[[R:[0-9]+]]=, $0{{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+declare i32 @llvm.wasm.bitmask.v4i32(<4 x i32>)
+define i32 @bitmask_v4i32(<4 x i32> %x) {
+  %a = call i32 @llvm.wasm.bitmask.v4i32(<4 x i32> %x)
+  ret i32 %a
+}
+
 ; CHECK-LABEL: bitselect_v4i32:
 ; SIMD128-NEXT: .functype bitselect_v4i32 (v128, v128, v128) -> (v128){{$}}
 ; SIMD128-NEXT: v128.bitselect $push[[R:[0-9]+]]=, $0, $1, $2{{$}}
Index: llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
===
--- llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
+++ llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
@@ -606,6 +606,18 @@
   (i32 (!cast(reduction[1]#"_"#ty) (ty V128:$x)))>;
 }
 
+multiclass SIMDBitmask simdop> {
+  defm _#vec_t : SIMD_I<(outs I32:$dst), (ins V128:$vec), (outs), (ins),
+ [(set I32:$dst,
+   (i32 (int_wasm_bitmask (vec_t V128:$vec)))
+ )],
+ vec#".bitmask\t$dst, $vec", vec#".bitmask", simdop>;
+}
+
+defm BITMASK : SIMDBitmask;
+defm BITMASK : SIMDBitmask;
+defm BITMASK : SIMDBitmask;
+
 //===--===//
 // Bit shifts
 //===--===//
Index: llvm/include/llvm/IR/IntrinsicsWebAssembly.td
===
--- llvm/include/llvm/IR/IntrinsicsWebAssembly.td
+++ llvm/include/llvm/IR/IntrinsicsWebAssembly.td
@@ -129,6 +129,10 @@
   Intrinsic<[llvm_i32_ty],
 [llvm_anyvector_ty],
 [IntrNoMem, IntrSpeculatable]>;
+def int_wasm_bitmask :
+  Intrinsic<[llvm_i32_ty],
+[llvm_anyvector_ty],
+[IntrNoMem, IntrSpeculatable]>;
 def int_wasm_qfma :
   Intrinsic<[llvm_anyvector_ty],
 [LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>],
Index: clang/test/CodeGen/builtins-wasm.c
===
--- clang/test/CodeGen/builtins-wasm.c
+++ clang/test/CodeGen/builtins-wasm.c
@@ -511,6 +511,24 @@
   // WEBASSEMBLY: ret
 }
 
+int

[PATCH] D76397: [WebAssembly] SIMD bitmask intrinsics and builtin functions

[PATCH] D76397: [WebAssembly] SIMD bitmask intrinsics and builtin functions

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