[PATCH] D81428: [ARM] Moving CMSE handling of half arguments and return to the backend

2020-06-18 Thread Lucas Prates via Phabricator via cfe-commits 
This revision was automatically updated to reflect the committed changes.
Closed by commit rG92ad6d57c218: [ARM] Moving CMSE handling of half arguments 
and return to the backend (authored by pratlucas).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D81428/new/

https://reviews.llvm.org/D81428

Files:
  llvm/lib/Target/ARM/ARMISelLowering.cpp
  llvm/test/CodeGen/ARM/cmse-clear-float-hard.ll

Index: llvm/test/CodeGen/ARM/cmse-clear-float-hard.ll
===
--- llvm/test/CodeGen/ARM/cmse-clear-float-hard.ll
+++ llvm/test/CodeGen/ARM/cmse-clear-float-hard.ll
@@ -4,13 +4,13 @@
 ; RUN: llc %s -o - -mtriple=thumbebv8m.main -mattr=+fp-armv8d16sp,+dsp -float-abi=hard | \
 ; RUN:   FileCheck %s --check-prefix=CHECK-8M --check-prefix=CHECK-8M-BE
 ; RUN: llc %s -o - -mtriple=thumbv8.1m.main -mattr=+fp-armv8d16sp,+dsp -float-abi=hard | \
-; RUN:   FileCheck %s --check-prefix=CHECK-81M --check-prefix=CHECK-81M-LE
+; RUN:   FileCheck %s --check-prefix=CHECK-81M --check-prefix=CHECK-NO-MVE --check-prefix=CHECK-81M-LE
 ; RUN: llc %s -o - -mtriple=thumbebv8.1m.main -mattr=+fp-armv8d16sp,+dsp -float-abi=hard | \
-; RUN:   FileCheck %s --check-prefix=CHECK-81M --check-prefix=CHECK-81M-BE
+; RUN:   FileCheck %s --check-prefix=CHECK-81M --check-prefix=CHECK-NO-MVE --check-prefix=CHECK-81M-BE
 ; RUN: llc %s -o - -mtriple=thumbv8.1m.main -mattr=+mve.fp -float-abi=hard | \
-; RUN:   FileCheck %s --check-prefix=CHECK-81M --check-prefix=CHECK-81M-LE
+; RUN:   FileCheck %s --check-prefix=CHECK-81M --check-prefix=CHECK-MVE --check-prefix=CHECK-81M-LE
 ; RUN: llc %s -o - -mtriple=thumbebv8.1m.main -mattr=+mve.fp -float-abi=hard | \
-; RUN:   FileCheck %s --check-prefix=CHECK-81M --check-prefix=CHECK-81M-BE
+; RUN:   FileCheck %s --check-prefix=CHECK-81M --check-prefix=CHECK-MVE --check-prefix=CHECK-81M-BE
 
 define float @f1(float (float)* nocapture %fptr) #0 {
 ; CHECK-8M-LABEL: f1:
@@ -809,3 +809,443 @@
   ret void
 }
 
+define half @h1(half (half)* nocapture %hptr) "cmse_nonsecure_entry" nounwind {
+; CHECK-8M-LABEL: h1:
+; CHECK-8M:   @ %bb.0:
+; CHECK-8M-NEXT:push {r7, lr}
+; CHECK-8M-NEXT:vldr s0, .LCPI11_0
+; CHECK-8M-NEXT:blx r0
+; CHECK-8M-NEXT:vmov r0, s0
+; CHECK-8M-NEXT:uxth r0, r0
+; CHECK-8M-NEXT:vmov s0, r0
+; CHECK-8M-NEXT:pop.w {r7, lr}
+; CHECK-8M-NEXT:mrs r12, control
+; CHECK-8M-NEXT:tst.w r12, #8
+; CHECK-8M-NEXT:beq .LBB11_2
+; CHECK-8M-NEXT:  @ %bb.1:
+; CHECK-8M-NEXT:vmrs r12, fpscr
+; CHECK-8M-NEXT:vmov s1, lr
+; CHECK-8M-NEXT:vmov d1, lr, lr
+; CHECK-8M-NEXT:vmov d2, lr, lr
+; CHECK-8M-NEXT:vmov d3, lr, lr
+; CHECK-8M-NEXT:vmov d4, lr, lr
+; CHECK-8M-NEXT:vmov d5, lr, lr
+; CHECK-8M-NEXT:vmov d6, lr, lr
+; CHECK-8M-NEXT:vmov d7, lr, lr
+; CHECK-8M-NEXT:bic r12, r12, #159
+; CHECK-8M-NEXT:bic r12, r12, #4026531840
+; CHECK-8M-NEXT:vmsr fpscr, r12
+; CHECK-8M-NEXT:  .LBB11_2:
+; CHECK-8M-NEXT:mov r0, lr
+; CHECK-8M-NEXT:mov r1, lr
+; CHECK-8M-NEXT:mov r2, lr
+; CHECK-8M-NEXT:mov r3, lr
+; CHECK-8M-NEXT:mov r12, lr
+; CHECK-8M-NEXT:msr apsr_nzcvqg, lr
+; CHECK-8M-NEXT:bxns lr
+; CHECK-8M-NEXT:.p2align 2
+; CHECK-8M-NEXT:  @ %bb.3:
+; CHECK-8M-NEXT:  .LCPI11_0:
+; CHECK-8M-NEXT:.long 0x4900 @ float 2.61874657E-41
+;
+; CHECK-NO-MVE-LABEL: h1:
+; CHECK-NO-MVE:   @ %bb.0:
+; CHECK-NO-MVE-NEXT:vstr fpcxtns, [sp, #-4]!
+; CHECK-NO-MVE-NEXT:push {r7, lr}
+; CHECK-NO-MVE-NEXT:sub sp, #4
+; CHECK-NO-MVE-NEXT:vldr s0, .LCPI11_0
+; CHECK-NO-MVE-NEXT:blx r0
+; CHECK-NO-MVE-NEXT:vmov r0, s0
+; CHECK-NO-MVE-NEXT:uxth r0, r0
+; CHECK-NO-MVE-NEXT:vmov s0, r0
+; CHECK-NO-MVE-NEXT:add sp, #4
+; CHECK-NO-MVE-NEXT:pop.w {r7, lr}
+; CHECK-NO-MVE-NEXT:vscclrm {s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15, vpr}
+; CHECK-NO-MVE-NEXT:vldr fpcxtns, [sp], #4
+; CHECK-NO-MVE-NEXT:clrm {r0, r1, r2, r3, r12, apsr}
+; CHECK-NO-MVE-NEXT:bxns lr
+; CHECK-NO-MVE-NEXT:.p2align 2
+; CHECK-NO-MVE-NEXT:  @ %bb.1:
+; CHECK-NO-MVE-NEXT:  .LCPI11_0:
+; CHECK-NO-MVE-NEXT:.long 0x4900 @ float 2.61874657E-41
+;
+; CHECK-MVE-LABEL: h1:
+; CHECK-MVE:   @ %bb.0:
+; CHECK-MVE-NEXT:vstr fpcxtns, [sp, #-4]!
+; CHECK-MVE-NEXT:push {r7, lr}
+; CHECK-MVE-NEXT:sub sp, #4
+; CHECK-MVE-NEXT:vmov.f16 s0, #1.00e+01
+; CHECK-MVE-NEXT:vmov.f16 r1, s0
+; CHECK-MVE-NEXT:vmov s0, r1
+; CHECK-MVE-NEXT:blx r0
+; CHECK-MVE-NEXT:vmov.f16 r0, s0
+; CHECK-MVE-NEXT:vmov s0, r0
+; CHECK-MVE-NEXT:add sp, #4
+; CHECK-MVE-NEXT:pop.w {r7, lr}
+; CHECK-MVE-NEXT:vscclrm {s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15, vpr}
+; CHECK-MVE-NEXT:vldr fpcxtns, [sp], #4
+; CHECK-MVE-NEXT:clrm {r0, r1, r2, r3, r12, apsr}
+; CHECK-MVE-NEXT:bxns lr
+  %call = call half %hptr(half 10.0)

[PATCH] D81428: [ARM] Moving CMSE handling of half arguments and return to the backend

2020-06-12 Thread Oliver Stannard (Linaro) via Phabricator via cfe-commits 
ostannard accepted this revision.
ostannard added a comment.
This revision is now accepted and ready to land.

LGTM


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D81428/new/

https://reviews.llvm.org/D81428



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[PATCH] D81428: [ARM] Moving CMSE handling of half arguments and return to the backend

2020-06-11 Thread Lucas Prates via Phabricator via cfe-commits 
pratlucas marked 4 inline comments as done.
pratlucas added inline comments.



Comment at: llvm/lib/Target/ARM/ARMISelLowering.cpp:2267
 
+// Mask f16 arguments if this is a CMSE nonsecure call
+auto ArgVT = Outs[realArgIdx].ArgVT;

ostannard wrote:
> Could this be done more efficiently by changing the ANY_EXTEND above to a 
> ZERO_EXTEND when this is a CMSE call?
Now that the `fp16` type convertion on D75169 was updated to use 
`VMOVhr`/`VMOVrh`, I've updated this patch to only use and `AND` masking when 
the argument are extended by `getCopyToParts`/`getCopyFromParts` prior to the 
calling convention lowering.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D81428/new/

https://reviews.llvm.org/D81428



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[PATCH] D81428: [ARM] Moving CMSE handling of half arguments and return to the backend

2020-06-11 Thread Lucas Prates via Phabricator via cfe-commits 
pratlucas updated this revision to Diff 270160.
pratlucas added a comment.

Addressing review comment.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D81428/new/

https://reviews.llvm.org/D81428

Files:
  llvm/lib/Target/ARM/ARMISelLowering.cpp
  llvm/test/CodeGen/ARM/cmse-clear-float-hard.ll

Index: llvm/test/CodeGen/ARM/cmse-clear-float-hard.ll
===
--- llvm/test/CodeGen/ARM/cmse-clear-float-hard.ll
+++ llvm/test/CodeGen/ARM/cmse-clear-float-hard.ll
@@ -4,13 +4,13 @@
 ; RUN: llc %s -o - -mtriple=thumbebv8m.main -mattr=+fp-armv8d16sp,+dsp -float-abi=hard | \
 ; RUN:   FileCheck %s --check-prefix=CHECK-8M --check-prefix=CHECK-8M-BE
 ; RUN: llc %s -o - -mtriple=thumbv8.1m.main -mattr=+fp-armv8d16sp,+dsp -float-abi=hard | \
-; RUN:   FileCheck %s --check-prefix=CHECK-81M --check-prefix=CHECK-81M-LE
+; RUN:   FileCheck %s --check-prefix=CHECK-81M --check-prefix=CHECK-NO-MVE --check-prefix=CHECK-81M-LE
 ; RUN: llc %s -o - -mtriple=thumbebv8.1m.main -mattr=+fp-armv8d16sp,+dsp -float-abi=hard | \
-; RUN:   FileCheck %s --check-prefix=CHECK-81M --check-prefix=CHECK-81M-BE
+; RUN:   FileCheck %s --check-prefix=CHECK-81M --check-prefix=CHECK-NO-MVE --check-prefix=CHECK-81M-BE
 ; RUN: llc %s -o - -mtriple=thumbv8.1m.main -mattr=+mve.fp -float-abi=hard | \
-; RUN:   FileCheck %s --check-prefix=CHECK-81M --check-prefix=CHECK-81M-LE
+; RUN:   FileCheck %s --check-prefix=CHECK-81M --check-prefix=CHECK-MVE --check-prefix=CHECK-81M-LE
 ; RUN: llc %s -o - -mtriple=thumbebv8.1m.main -mattr=+mve.fp -float-abi=hard | \
-; RUN:   FileCheck %s --check-prefix=CHECK-81M --check-prefix=CHECK-81M-BE
+; RUN:   FileCheck %s --check-prefix=CHECK-81M --check-prefix=CHECK-MVE --check-prefix=CHECK-81M-BE
 
 define float @f1(float (float)* nocapture %fptr) #0 {
 ; CHECK-8M-LABEL: f1:
@@ -809,3 +809,443 @@
   ret void
 }
 
+define half @h1(half (half)* nocapture %hptr) "cmse_nonsecure_entry" nounwind {
+; CHECK-8M-LABEL: h1:
+; CHECK-8M:   @ %bb.0:
+; CHECK-8M-NEXT:push {r7, lr}
+; CHECK-8M-NEXT:vldr s0, .LCPI11_0
+; CHECK-8M-NEXT:blx r0
+; CHECK-8M-NEXT:vmov r0, s0
+; CHECK-8M-NEXT:uxth r0, r0
+; CHECK-8M-NEXT:vmov s0, r0
+; CHECK-8M-NEXT:pop.w {r7, lr}
+; CHECK-8M-NEXT:mrs r12, control
+; CHECK-8M-NEXT:tst.w r12, #8
+; CHECK-8M-NEXT:beq .LBB11_2
+; CHECK-8M-NEXT:  @ %bb.1:
+; CHECK-8M-NEXT:vmrs r12, fpscr
+; CHECK-8M-NEXT:vmov s1, lr
+; CHECK-8M-NEXT:vmov d1, lr, lr
+; CHECK-8M-NEXT:vmov d2, lr, lr
+; CHECK-8M-NEXT:vmov d3, lr, lr
+; CHECK-8M-NEXT:vmov d4, lr, lr
+; CHECK-8M-NEXT:vmov d5, lr, lr
+; CHECK-8M-NEXT:vmov d6, lr, lr
+; CHECK-8M-NEXT:vmov d7, lr, lr
+; CHECK-8M-NEXT:bic r12, r12, #159
+; CHECK-8M-NEXT:bic r12, r12, #4026531840
+; CHECK-8M-NEXT:vmsr fpscr, r12
+; CHECK-8M-NEXT:  .LBB11_2:
+; CHECK-8M-NEXT:mov r0, lr
+; CHECK-8M-NEXT:mov r1, lr
+; CHECK-8M-NEXT:mov r2, lr
+; CHECK-8M-NEXT:mov r3, lr
+; CHECK-8M-NEXT:mov r12, lr
+; CHECK-8M-NEXT:msr apsr_nzcvqg, lr
+; CHECK-8M-NEXT:bxns lr
+; CHECK-8M-NEXT:.p2align 2
+; CHECK-8M-NEXT:  @ %bb.3:
+; CHECK-8M-NEXT:  .LCPI11_0:
+; CHECK-8M-NEXT:.long 0x4900 @ float 2.61874657E-41
+;
+; CHECK-NO-MVE-LABEL: h1:
+; CHECK-NO-MVE:   @ %bb.0:
+; CHECK-NO-MVE-NEXT:vstr fpcxtns, [sp, #-4]!
+; CHECK-NO-MVE-NEXT:push {r7, lr}
+; CHECK-NO-MVE-NEXT:sub sp, #4
+; CHECK-NO-MVE-NEXT:vldr s0, .LCPI11_0
+; CHECK-NO-MVE-NEXT:blx r0
+; CHECK-NO-MVE-NEXT:vmov r0, s0
+; CHECK-NO-MVE-NEXT:uxth r0, r0
+; CHECK-NO-MVE-NEXT:vmov s0, r0
+; CHECK-NO-MVE-NEXT:add sp, #4
+; CHECK-NO-MVE-NEXT:pop.w {r7, lr}
+; CHECK-NO-MVE-NEXT:vscclrm {s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15, vpr}
+; CHECK-NO-MVE-NEXT:vldr fpcxtns, [sp], #4
+; CHECK-NO-MVE-NEXT:clrm {r0, r1, r2, r3, r12, apsr}
+; CHECK-NO-MVE-NEXT:bxns lr
+; CHECK-NO-MVE-NEXT:.p2align 2
+; CHECK-NO-MVE-NEXT:  @ %bb.1:
+; CHECK-NO-MVE-NEXT:  .LCPI11_0:
+; CHECK-NO-MVE-NEXT:.long 0x4900 @ float 2.61874657E-41
+;
+; CHECK-MVE-LABEL: h1:
+; CHECK-MVE:   @ %bb.0:
+; CHECK-MVE-NEXT:vstr fpcxtns, [sp, #-4]!
+; CHECK-MVE-NEXT:push {r7, lr}
+; CHECK-MVE-NEXT:sub sp, #4
+; CHECK-MVE-NEXT:vmov.f16 s0, #1.00e+01
+; CHECK-MVE-NEXT:vmov.f16 r1, s0
+; CHECK-MVE-NEXT:vmov s0, r1
+; CHECK-MVE-NEXT:blx r0
+; CHECK-MVE-NEXT:vmov.f16 r0, s0
+; CHECK-MVE-NEXT:vmov s0, r0
+; CHECK-MVE-NEXT:add sp, #4
+; CHECK-MVE-NEXT:pop.w {r7, lr}
+; CHECK-MVE-NEXT:vscclrm {s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15, vpr}
+; CHECK-MVE-NEXT:vldr fpcxtns, [sp], #4
+; CHECK-MVE-NEXT:clrm {r0, r1, r2, r3, r12, apsr}
+; CHECK-MVE-NEXT:bxns lr
+  %call = call half %hptr(half 10.0) nounwind
+  ret half %call
+}
+
+define half @h2(half (half)* nocapture %hptr) nounwind {
+;

[PATCH] D81428: [ARM] Moving CMSE handling of half arguments and return to the backend

2020-06-11 Thread Lucas Prates via Phabricator via cfe-commits 
pratlucas updated this revision to Diff 270149.
pratlucas added a comment.

Rebasing and simplifying function attributes on test.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D81428/new/

https://reviews.llvm.org/D81428

Files:
  llvm/lib/Target/ARM/ARMISelLowering.cpp
  llvm/test/CodeGen/ARM/cmse-clear-float-hard.ll

Index: llvm/test/CodeGen/ARM/cmse-clear-float-hard.ll
===
--- llvm/test/CodeGen/ARM/cmse-clear-float-hard.ll
+++ llvm/test/CodeGen/ARM/cmse-clear-float-hard.ll
@@ -4,13 +4,13 @@
 ; RUN: llc %s -o - -mtriple=thumbebv8m.main -mattr=+fp-armv8d16sp,+dsp -float-abi=hard | \
 ; RUN:   FileCheck %s --check-prefix=CHECK-8M --check-prefix=CHECK-8M-BE
 ; RUN: llc %s -o - -mtriple=thumbv8.1m.main -mattr=+fp-armv8d16sp,+dsp -float-abi=hard | \
-; RUN:   FileCheck %s --check-prefix=CHECK-81M --check-prefix=CHECK-81M-LE
+; RUN:   FileCheck %s --check-prefix=CHECK-81M --check-prefix=CHECK-NO-MVE --check-prefix=CHECK-81M-LE
 ; RUN: llc %s -o - -mtriple=thumbebv8.1m.main -mattr=+fp-armv8d16sp,+dsp -float-abi=hard | \
-; RUN:   FileCheck %s --check-prefix=CHECK-81M --check-prefix=CHECK-81M-BE
+; RUN:   FileCheck %s --check-prefix=CHECK-81M --check-prefix=CHECK-NO-MVE --check-prefix=CHECK-81M-BE
 ; RUN: llc %s -o - -mtriple=thumbv8.1m.main -mattr=+mve.fp -float-abi=hard | \
-; RUN:   FileCheck %s --check-prefix=CHECK-81M --check-prefix=CHECK-81M-LE
+; RUN:   FileCheck %s --check-prefix=CHECK-81M --check-prefix=CHECK-MVE --check-prefix=CHECK-81M-LE
 ; RUN: llc %s -o - -mtriple=thumbebv8.1m.main -mattr=+mve.fp -float-abi=hard | \
-; RUN:   FileCheck %s --check-prefix=CHECK-81M --check-prefix=CHECK-81M-BE
+; RUN:   FileCheck %s --check-prefix=CHECK-81M --check-prefix=CHECK-MVE --check-prefix=CHECK-81M-BE
 
 define float @f1(float (float)* nocapture %fptr) #0 {
 ; CHECK-8M-LABEL: f1:
@@ -809,3 +809,443 @@
   ret void
 }
 
+define half @h1(half (half)* nocapture %hptr) "cmse_nonsecure_entry" nounwind {
+; CHECK-8M-LABEL: h1:
+; CHECK-8M:   @ %bb.0:
+; CHECK-8M-NEXT:push {r7, lr}
+; CHECK-8M-NEXT:vldr s0, .LCPI11_0
+; CHECK-8M-NEXT:blx r0
+; CHECK-8M-NEXT:vmov r0, s0
+; CHECK-8M-NEXT:uxth r0, r0
+; CHECK-8M-NEXT:vmov s0, r0
+; CHECK-8M-NEXT:pop.w {r7, lr}
+; CHECK-8M-NEXT:mrs r12, control
+; CHECK-8M-NEXT:tst.w r12, #8
+; CHECK-8M-NEXT:beq .LBB11_2
+; CHECK-8M-NEXT:  @ %bb.1:
+; CHECK-8M-NEXT:vmrs r12, fpscr
+; CHECK-8M-NEXT:vmov s1, lr
+; CHECK-8M-NEXT:vmov d1, lr, lr
+; CHECK-8M-NEXT:vmov d2, lr, lr
+; CHECK-8M-NEXT:vmov d3, lr, lr
+; CHECK-8M-NEXT:vmov d4, lr, lr
+; CHECK-8M-NEXT:vmov d5, lr, lr
+; CHECK-8M-NEXT:vmov d6, lr, lr
+; CHECK-8M-NEXT:vmov d7, lr, lr
+; CHECK-8M-NEXT:bic r12, r12, #159
+; CHECK-8M-NEXT:bic r12, r12, #4026531840
+; CHECK-8M-NEXT:vmsr fpscr, r12
+; CHECK-8M-NEXT:  .LBB11_2:
+; CHECK-8M-NEXT:mov r0, lr
+; CHECK-8M-NEXT:mov r1, lr
+; CHECK-8M-NEXT:mov r2, lr
+; CHECK-8M-NEXT:mov r3, lr
+; CHECK-8M-NEXT:mov r12, lr
+; CHECK-8M-NEXT:msr apsr_nzcvqg, lr
+; CHECK-8M-NEXT:bxns lr
+; CHECK-8M-NEXT:.p2align 2
+; CHECK-8M-NEXT:  @ %bb.3:
+; CHECK-8M-NEXT:  .LCPI11_0:
+; CHECK-8M-NEXT:.long 0x4900 @ float 2.61874657E-41
+;
+; CHECK-NO-MVE-LABEL: h1:
+; CHECK-NO-MVE:   @ %bb.0:
+; CHECK-NO-MVE-NEXT:vstr fpcxtns, [sp, #-4]!
+; CHECK-NO-MVE-NEXT:push {r7, lr}
+; CHECK-NO-MVE-NEXT:sub sp, #4
+; CHECK-NO-MVE-NEXT:vldr s0, .LCPI11_0
+; CHECK-NO-MVE-NEXT:blx r0
+; CHECK-NO-MVE-NEXT:vmov r0, s0
+; CHECK-NO-MVE-NEXT:uxth r0, r0
+; CHECK-NO-MVE-NEXT:vmov s0, r0
+; CHECK-NO-MVE-NEXT:add sp, #4
+; CHECK-NO-MVE-NEXT:pop.w {r7, lr}
+; CHECK-NO-MVE-NEXT:vscclrm {s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15, vpr}
+; CHECK-NO-MVE-NEXT:vldr fpcxtns, [sp], #4
+; CHECK-NO-MVE-NEXT:clrm {r0, r1, r2, r3, r12, apsr}
+; CHECK-NO-MVE-NEXT:bxns lr
+; CHECK-NO-MVE-NEXT:.p2align 2
+; CHECK-NO-MVE-NEXT:  @ %bb.1:
+; CHECK-NO-MVE-NEXT:  .LCPI11_0:
+; CHECK-NO-MVE-NEXT:.long 0x4900 @ float 2.61874657E-41
+;
+; CHECK-MVE-LABEL: h1:
+; CHECK-MVE:   @ %bb.0:
+; CHECK-MVE-NEXT:vstr fpcxtns, [sp, #-4]!
+; CHECK-MVE-NEXT:push {r7, lr}
+; CHECK-MVE-NEXT:sub sp, #4
+; CHECK-MVE-NEXT:vmov.f16 s0, #1.00e+01
+; CHECK-MVE-NEXT:vmov.f16 r1, s0
+; CHECK-MVE-NEXT:vmov s0, r1
+; CHECK-MVE-NEXT:blx r0
+; CHECK-MVE-NEXT:vmov.f16 r0, s0
+; CHECK-MVE-NEXT:vmov s0, r0
+; CHECK-MVE-NEXT:add sp, #4
+; CHECK-MVE-NEXT:pop.w {r7, lr}
+; CHECK-MVE-NEXT:vscclrm {s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15, vpr}
+; CHECK-MVE-NEXT:vldr fpcxtns, [sp], #4
+; CHECK-MVE-NEXT:clrm {r0, r1, r2, r3, r12, apsr}
+; CHECK-MVE-NEXT:bxns lr
+  %call = call half %hptr(half 10.0) nounwind
+  ret half %call
+}
+
+define half @h2(half (half)* nocapture

[PATCH] D81428: [ARM] Moving CMSE handling of half arguments and return to the backend

2020-06-10 Thread Oliver Stannard (Linaro) via Phabricator via cfe-commits 
ostannard added a comment.

Is this expected to work for the soft-float calling convention, or is clang 
still passing half-precision values as integer types for that? If the former, 
then this needs some tests for that case.




Comment at: llvm/lib/Target/ARM/ARMISelLowering.cpp:2267
 
+// Mask f16 arguments if this is a CMSE nonsecure call
+auto ArgVT = Outs[realArgIdx].ArgVT;

Could this be done more efficiently by changing the ANY_EXTEND above to a 
ZERO_EXTEND when this is a CMSE call?



Comment at: llvm/lib/Target/ARM/ARMISelLowering.cpp:2955
+
+// Mask f16 arguments if this is a CMSE nonsecure entry
+auto RetVT = Outs[realRVLocIdx].ArgVT;

Again, could this be done by using ZERO_EXTEND instead of ANY_EXTEND for CMSE 
entry functions?



Comment at: llvm/test/CodeGen/ARM/cmse-clear-float-hard.ll:812
 
+define arm_aapcs_vfpcc half @h1(half (half)* nocapture %hptr) #10 {
+; CHECK-8M-LABEL: h1:

The function attributes (`"cmse_nonsecure_entry" nounwind` in this case) can be 
placed here (replacing the `#10`) to make the tests easier to read.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D81428/new/

https://reviews.llvm.org/D81428



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[PATCH] D81428: [ARM] Moving CMSE handling of half arguments and return to the backend

2020-06-09 Thread Lucas Prates via Phabricator via cfe-commits 
pratlucas updated this revision to Diff 269452.
pratlucas added a comment.

Moving the clean-up of the Clang-side handling to a separate patch.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D81428/new/

https://reviews.llvm.org/D81428

Files:
  llvm/lib/Target/ARM/ARMISelLowering.cpp
  llvm/test/CodeGen/ARM/cmse-clear-float-hard.ll

Index: llvm/test/CodeGen/ARM/cmse-clear-float-hard.ll
===
--- llvm/test/CodeGen/ARM/cmse-clear-float-hard.ll
+++ llvm/test/CodeGen/ARM/cmse-clear-float-hard.ll
@@ -809,3 +809,379 @@
   ret void
 }
 
+define arm_aapcs_vfpcc half @h1(half (half)* nocapture %hptr) #10 {
+; CHECK-8M-LABEL: h1:
+; CHECK-8M:   @ %bb.0:
+; CHECK-8M-NEXT:push {r7, lr}
+; CHECK-8M-NEXT:vldr s0, .LCPI11_0
+; CHECK-8M-NEXT:blx r0
+; CHECK-8M-NEXT:vmov r0, s0
+; CHECK-8M-NEXT:uxth r0, r0
+; CHECK-8M-NEXT:vmov s0, r0
+; CHECK-8M-NEXT:pop.w {r7, lr}
+; CHECK-8M-NEXT:mrs r12, control
+; CHECK-8M-NEXT:tst.w r12, #8
+; CHECK-8M-NEXT:beq .LBB11_2
+; CHECK-8M-NEXT:  @ %bb.1:
+; CHECK-8M-NEXT:vmrs r12, fpscr
+; CHECK-8M-NEXT:vmov s1, lr
+; CHECK-8M-NEXT:vmov d1, lr, lr
+; CHECK-8M-NEXT:vmov d2, lr, lr
+; CHECK-8M-NEXT:vmov d3, lr, lr
+; CHECK-8M-NEXT:vmov d4, lr, lr
+; CHECK-8M-NEXT:vmov d5, lr, lr
+; CHECK-8M-NEXT:vmov d6, lr, lr
+; CHECK-8M-NEXT:vmov d7, lr, lr
+; CHECK-8M-NEXT:bic r12, r12, #159
+; CHECK-8M-NEXT:bic r12, r12, #4026531840
+; CHECK-8M-NEXT:vmsr fpscr, r12
+; CHECK-8M-NEXT:  .LBB11_2:
+; CHECK-8M-NEXT:mov r0, lr
+; CHECK-8M-NEXT:mov r1, lr
+; CHECK-8M-NEXT:mov r2, lr
+; CHECK-8M-NEXT:mov r3, lr
+; CHECK-8M-NEXT:mov r12, lr
+; CHECK-8M-NEXT:msr apsr_nzcvqg, lr
+; CHECK-8M-NEXT:bxns lr
+; CHECK-8M-NEXT:.p2align 2
+; CHECK-8M-NEXT:  @ %bb.3:
+; CHECK-8M-NEXT:  .LCPI11_0:
+; CHECK-8M-NEXT:.long 0x4900 @ float 2.61874657E-41
+;
+; CHECK-81M-LABEL: h1:
+; CHECK-81M:   @ %bb.0:
+; CHECK-81M-NEXT:vstr fpcxtns, [sp, #-4]!
+; CHECK-81M-NEXT:push {r7, lr}
+; CHECK-81M-NEXT:sub sp, #4
+; CHECK-81M-NEXT:vldr s0, .LCPI11_0
+; CHECK-81M-NEXT:blx r0
+; CHECK-81M-NEXT:vmov r0, s0
+; CHECK-81M-NEXT:uxth r0, r0
+; CHECK-81M-NEXT:vmov s0, r0
+; CHECK-81M-NEXT:add sp, #4
+; CHECK-81M-NEXT:pop.w {r7, lr}
+; CHECK-81M-NEXT:vscclrm {s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15, vpr}
+; CHECK-81M-NEXT:vldr fpcxtns, [sp], #4
+; CHECK-81M-NEXT:clrm {r0, r1, r2, r3, r12, apsr}
+; CHECK-81M-NEXT:bxns lr
+; CHECK-81M-NEXT:.p2align 2
+; CHECK-81M-NEXT:  @ %bb.1:
+; CHECK-81M-NEXT:  .LCPI11_0:
+; CHECK-81M-NEXT:.long 0x4900 @ float 2.61874657E-41
+  %call = call arm_aapcs_vfpcc half %hptr(half 10.0) #11
+  ret half %call
+}
+
+attributes #10 = { "cmse_nonsecure_entry" nounwind }
+attributes #11 = { nounwind }
+
+define arm_aapcs_vfpcc half @h2(half (half)* nocapture %hptr) #12 {
+; CHECK-8M-LABEL: h2:
+; CHECK-8M:   @ %bb.0: @ %entry
+; CHECK-8M-NEXT:push {r7, lr}
+; CHECK-8M-NEXT:vldr s0, .LCPI12_0
+; CHECK-8M-NEXT:push.w {r4, r5, r6, r7, r8, r9, r10, r11}
+; CHECK-8M-NEXT:bic r0, r0, #1
+; CHECK-8M-NEXT:sub sp, #136
+; CHECK-8M-NEXT:vmov r12, s0
+; CHECK-8M-NEXT:vlstm sp
+; CHECK-8M-NEXT:vmov s0, r12
+; CHECK-8M-NEXT:ldr r1, [sp, #64]
+; CHECK-8M-NEXT:bic r1, r1, #159
+; CHECK-8M-NEXT:bic r1, r1, #4026531840
+; CHECK-8M-NEXT:vmsr fpscr, r1
+; CHECK-8M-NEXT:mov r1, r0
+; CHECK-8M-NEXT:mov r2, r0
+; CHECK-8M-NEXT:mov r3, r0
+; CHECK-8M-NEXT:mov r4, r0
+; CHECK-8M-NEXT:mov r5, r0
+; CHECK-8M-NEXT:mov r6, r0
+; CHECK-8M-NEXT:mov r7, r0
+; CHECK-8M-NEXT:mov r8, r0
+; CHECK-8M-NEXT:mov r9, r0
+; CHECK-8M-NEXT:mov r10, r0
+; CHECK-8M-NEXT:mov r11, r0
+; CHECK-8M-NEXT:msr apsr_nzcvqg, r0
+; CHECK-8M-NEXT:blxns r0
+; CHECK-8M-NEXT:vmov r12, s0
+; CHECK-8M-NEXT:vlldm sp
+; CHECK-8M-NEXT:vmov s0, r12
+; CHECK-8M-NEXT:add sp, #136
+; CHECK-8M-NEXT:pop.w {r4, r5, r6, r7, r8, r9, r10, r11}
+; CHECK-8M-NEXT:pop {r7, pc}
+; CHECK-8M-NEXT:.p2align 2
+; CHECK-8M-NEXT:  @ %bb.1:
+; CHECK-8M-NEXT:  .LCPI12_0:
+; CHECK-8M-NEXT:.long 0x4900 @ float 2.61874657E-41
+;
+; CHECK-81M-LABEL: h2:
+; CHECK-81M:   @ %bb.0: @ %entry
+; CHECK-81M-NEXT:push {r7, lr}
+; CHECK-81M-NEXT:vldr s0, .LCPI12_0
+; CHECK-81M-NEXT:push.w {r4, r5, r6, r7, r8, r9, r10, r11}
+; CHECK-81M-NEXT:bic r0, r0, #1
+; CHECK-81M-NEXT:vpush {s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31}
+; CHECK-81M-NEXT:vscclrm {s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15, s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31, vpr}
+; CHECK-81M-NEXT:vstr fpcxts, [sp, #-8]!
+; CHECK-81M-NEXT:clrm {r1, r2, r3, r4, r5,

[PATCH] D81428: [ARM] Moving CMSE handling of half arguments and return to the backend

2020-06-08 Thread Lucas Prates via Phabricator via cfe-commits 
pratlucas created this revision.
Herald added subscribers: llvm-commits, cfe-commits, danielkiss, hiraditya, 
kristof.beyls.
Herald added projects: clang, LLVM.
pratlucas added reviewers: chill, rjmccall, ostannard.
pratlucas added a parent revision: D75169: [ARM] Enforcing calling convention 
for half-precision FP arguments and returns for big-endian AArch32.

As half-precision floating point arguments and returns were previously
coerced to either float or int32 by clang's codegen, the CMSE handling
of those was also performed in clang's side by zeroing the unused MSBs
of the coercer values.

This patch moves this handling to the backend's calling convention
lowering, making sure the high bits of the registers used by
half-precision arguments and returns are zeroed.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D81428

Files:
  clang/lib/CodeGen/CGCall.cpp
  clang/lib/CodeGen/CodeGenFunction.h
  clang/test/CodeGen/cmse-clear-fp16.c
  llvm/lib/Target/ARM/ARMISelLowering.cpp
  llvm/test/CodeGen/ARM/cmse-clear-float-hard.ll

Index: llvm/test/CodeGen/ARM/cmse-clear-float-hard.ll
===
--- llvm/test/CodeGen/ARM/cmse-clear-float-hard.ll
+++ llvm/test/CodeGen/ARM/cmse-clear-float-hard.ll
@@ -809,3 +809,379 @@
   ret void
 }
 
+define arm_aapcs_vfpcc half @h1(half (half)* nocapture %hptr) #10 {
+; CHECK-8M-LABEL: h1:
+; CHECK-8M:   @ %bb.0:
+; CHECK-8M-NEXT:push {r7, lr}
+; CHECK-8M-NEXT:vldr s0, .LCPI11_0
+; CHECK-8M-NEXT:blx r0
+; CHECK-8M-NEXT:vmov r0, s0
+; CHECK-8M-NEXT:uxth r0, r0
+; CHECK-8M-NEXT:vmov s0, r0
+; CHECK-8M-NEXT:pop.w {r7, lr}
+; CHECK-8M-NEXT:mrs r12, control
+; CHECK-8M-NEXT:tst.w r12, #8
+; CHECK-8M-NEXT:beq .LBB11_2
+; CHECK-8M-NEXT:  @ %bb.1:
+; CHECK-8M-NEXT:vmrs r12, fpscr
+; CHECK-8M-NEXT:vmov s1, lr
+; CHECK-8M-NEXT:vmov d1, lr, lr
+; CHECK-8M-NEXT:vmov d2, lr, lr
+; CHECK-8M-NEXT:vmov d3, lr, lr
+; CHECK-8M-NEXT:vmov d4, lr, lr
+; CHECK-8M-NEXT:vmov d5, lr, lr
+; CHECK-8M-NEXT:vmov d6, lr, lr
+; CHECK-8M-NEXT:vmov d7, lr, lr
+; CHECK-8M-NEXT:bic r12, r12, #159
+; CHECK-8M-NEXT:bic r12, r12, #4026531840
+; CHECK-8M-NEXT:vmsr fpscr, r12
+; CHECK-8M-NEXT:  .LBB11_2:
+; CHECK-8M-NEXT:mov r0, lr
+; CHECK-8M-NEXT:mov r1, lr
+; CHECK-8M-NEXT:mov r2, lr
+; CHECK-8M-NEXT:mov r3, lr
+; CHECK-8M-NEXT:mov r12, lr
+; CHECK-8M-NEXT:msr apsr_nzcvqg, lr
+; CHECK-8M-NEXT:bxns lr
+; CHECK-8M-NEXT:.p2align 2
+; CHECK-8M-NEXT:  @ %bb.3:
+; CHECK-8M-NEXT:  .LCPI11_0:
+; CHECK-8M-NEXT:.long 0x4900 @ float 2.61874657E-41
+;
+; CHECK-81M-LABEL: h1:
+; CHECK-81M:   @ %bb.0:
+; CHECK-81M-NEXT:vstr fpcxtns, [sp, #-4]!
+; CHECK-81M-NEXT:push {r7, lr}
+; CHECK-81M-NEXT:sub sp, #4
+; CHECK-81M-NEXT:vldr s0, .LCPI11_0
+; CHECK-81M-NEXT:blx r0
+; CHECK-81M-NEXT:vmov r0, s0
+; CHECK-81M-NEXT:uxth r0, r0
+; CHECK-81M-NEXT:vmov s0, r0
+; CHECK-81M-NEXT:add sp, #4
+; CHECK-81M-NEXT:pop.w {r7, lr}
+; CHECK-81M-NEXT:vscclrm {s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15, vpr}
+; CHECK-81M-NEXT:vldr fpcxtns, [sp], #4
+; CHECK-81M-NEXT:clrm {r0, r1, r2, r3, r12, apsr}
+; CHECK-81M-NEXT:bxns lr
+; CHECK-81M-NEXT:.p2align 2
+; CHECK-81M-NEXT:  @ %bb.1:
+; CHECK-81M-NEXT:  .LCPI11_0:
+; CHECK-81M-NEXT:.long 0x4900 @ float 2.61874657E-41
+  %call = call arm_aapcs_vfpcc half %hptr(half 10.0) #11
+  ret half %call
+}
+
+attributes #10 = { "cmse_nonsecure_entry" nounwind }
+attributes #11 = { nounwind }
+
+define arm_aapcs_vfpcc half @h2(half (half)* nocapture %hptr) #12 {
+; CHECK-8M-LABEL: h2:
+; CHECK-8M:   @ %bb.0: @ %entry
+; CHECK-8M-NEXT:push {r7, lr}
+; CHECK-8M-NEXT:vldr s0, .LCPI12_0
+; CHECK-8M-NEXT:push.w {r4, r5, r6, r7, r8, r9, r10, r11}
+; CHECK-8M-NEXT:bic r0, r0, #1
+; CHECK-8M-NEXT:sub sp, #136
+; CHECK-8M-NEXT:vmov r12, s0
+; CHECK-8M-NEXT:vlstm sp
+; CHECK-8M-NEXT:vmov s0, r12
+; CHECK-8M-NEXT:ldr r1, [sp, #64]
+; CHECK-8M-NEXT:bic r1, r1, #159
+; CHECK-8M-NEXT:bic r1, r1, #4026531840
+; CHECK-8M-NEXT:vmsr fpscr, r1
+; CHECK-8M-NEXT:mov r1, r0
+; CHECK-8M-NEXT:mov r2, r0
+; CHECK-8M-NEXT:mov r3, r0
+; CHECK-8M-NEXT:mov r4, r0
+; CHECK-8M-NEXT:mov r5, r0
+; CHECK-8M-NEXT:mov r6, r0
+; CHECK-8M-NEXT:mov r7, r0
+; CHECK-8M-NEXT:mov r8, r0
+; CHECK-8M-NEXT:mov r9, r0
+; CHECK-8M-NEXT:mov r10, r0
+; CHECK-8M-NEXT:mov r11, r0
+; CHECK-8M-NEXT:msr apsr_nzcvqg, r0
+; CHECK-8M-NEXT:blxns r0
+; CHECK-8M-NEXT:vmov r12, s0
+; CHECK-8M-NEXT:vlldm sp
+; CHECK-8M-NEXT:vmov s0, r12
+; CHECK-8M-NEXT:add sp, #136
+; CHECK-8M-NEXT:pop.w {r4, r5, r6, r7, r8, r9, r10, r11}
+; CHECK-8M-NEXT:pop {r7, pc}
+; CHECK-8M-NEXT:.p2align 2
+; CHECK-8M-NEXT:  @ %bb.1:
+; CHECK-8M-NEXT:  .LCPI12_0:
+;