[PATCH] D81442: [PowerPC] Add clang options to control MMA support
This revision was automatically updated to reflect the committed changes. Closed by commit rG512e256c0d8c: [PowerPC] Add clang options to control MMA support (authored by bsaleil). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D81442/new/ https://reviews.llvm.org/D81442 Files: clang/include/clang/Driver/Options.td clang/lib/Basic/Targets/PPC.cpp clang/lib/Basic/Targets/PPC.h clang/test/Driver/ppc-dependent-options.cpp clang/test/Preprocessor/init-ppc64.c llvm/lib/Target/PowerPC/PPC.td llvm/lib/Target/PowerPC/PPCInstrPrefix.td llvm/lib/Target/PowerPC/PPCScheduleP9.td llvm/lib/Target/PowerPC/PPCSubtarget.cpp llvm/lib/Target/PowerPC/PPCSubtarget.h llvm/test/CodeGen/PowerPC/future-check-features.ll Index: llvm/test/CodeGen/PowerPC/future-check-features.ll === --- llvm/test/CodeGen/PowerPC/future-check-features.ll +++ llvm/test/CodeGen/PowerPC/future-check-features.ll @@ -1,7 +1,7 @@ -; RUN: llc -mattr=pcrelative-memops,prefix-instrs,paired-vector-memops \ +; RUN: llc -mattr=pcrelative-memops,prefix-instrs,paired-vector-memops,mma \ ; RUN: -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown \ ; RUN: -ppc-asm-full-reg-names %s -o - 2>&1 | FileCheck %s -; RUN: llc -mattr=pcrelative-memops,prefix-instrs,paired-vector-memops \ +; RUN: llc -mattr=pcrelative-memops,prefix-instrs,paired-vector-memops,mma \ ; RUN: -verify-machineinstrs -mtriple=powerpc64-unknown-unknown \ ; RUN: -ppc-asm-full-reg-names %s -o - 2>&1 | FileCheck %s Index: llvm/lib/Target/PowerPC/PPCSubtarget.h === --- llvm/lib/Target/PowerPC/PPCSubtarget.h +++ llvm/lib/Target/PowerPC/PPCSubtarget.h @@ -107,6 +107,7 @@ bool HasP10Vector; bool HasPrefixInstrs; bool HasPCRelativeMemops; + bool HasMMA; bool HasFCPSGN; bool HasFSQRT; bool HasFRE, HasFRES, HasFRSQRTE, HasFRSQRTES; @@ -260,6 +261,7 @@ bool hasP10Vector() const { return HasP10Vector; } bool hasPrefixInstrs() const { return HasPrefixInstrs; } bool hasPCRelativeMemops() const { return HasPCRelativeMemops; } + bool hasMMA() const { return HasMMA; } bool pairedVectorMemops() const { return PairedVectorMemops; } bool hasMFOCRF() const { return HasMFOCRF; } bool hasISEL() const { return HasISEL; } Index: llvm/lib/Target/PowerPC/PPCSubtarget.cpp === --- llvm/lib/Target/PowerPC/PPCSubtarget.cpp +++ llvm/lib/Target/PowerPC/PPCSubtarget.cpp @@ -73,6 +73,7 @@ HasP8Crypto = false; HasP9Vector = false; HasP9Altivec = false; + HasMMA = false; HasP10Vector = false; HasPrefixInstrs = false; HasPCRelativeMemops = false; Index: llvm/lib/Target/PowerPC/PPCScheduleP9.td === --- llvm/lib/Target/PowerPC/PPCScheduleP9.td +++ llvm/lib/Target/PowerPC/PPCScheduleP9.td @@ -41,9 +41,9 @@ let CompleteModel = 1; // Do not support SPE (Signal Processing Engine), prefixed instructions on - // Power 9, paired vector mem ops, PC relative mem ops, or instructions + // Power 9, paired vector mem ops, MMA, PC relative mem ops, or instructions // introduced in ISA 3.1. - let UnsupportedFeatures = [HasSPE, PrefixInstrs, PairedVectorMemops, + let UnsupportedFeatures = [HasSPE, PrefixInstrs, PairedVectorMemops, MMA, PCRelativeMemops, IsISA3_1]; } Index: llvm/lib/Target/PowerPC/PPCInstrPrefix.td === --- llvm/lib/Target/PowerPC/PPCInstrPrefix.td +++ llvm/lib/Target/PowerPC/PPCInstrPrefix.td @@ -504,6 +504,7 @@ def PrefixInstrs : Predicate<"Subtarget->hasPrefixInstrs()">; def IsISA3_1 : Predicate<"Subtarget->isISA3_1()">; def PairedVectorMemops : Predicate<"PPCSubTarget->pairedVectorMemops()">; +def MMA : Predicate<"PPCSubTarget->hasMMA()">; let Predicates = [PrefixInstrs] in { let Interpretation64Bit = 1, isCodeGenOnly = 1 in { Index: llvm/lib/Target/PowerPC/PPC.td === --- llvm/lib/Target/PowerPC/PPC.td +++ llvm/lib/Target/PowerPC/PPC.td @@ -238,6 +238,10 @@ SubtargetFeature<"paired-vector-memops", "PairedVectorMemops", "true", "32Byte load and store instructions", [FeatureISA3_0]>; +def FeatureMMA : SubtargetFeature<"mma", "HasMMA", "true", + "Enable MMA instructions", + [FeatureP8Vector, FeatureP9Altivec, + FeaturePairedVectorMemops]>; def FeaturePredictableSelectIsExpensive : SubtargetFeature<"predictable-select-expensive", @@ -343,7 +347,8 @@ // still exist with the exception of those we know are Power9 specific. list P10AdditionalFeatures = [DirectivePwr10, FeatureISA3_1, FeaturePrefixInstrs, -
[PATCH] D81442: [PowerPC] Add clang options to control MMA support
bsaleil updated this revision to Diff 281381. bsaleil added a comment. Update diff so it can be applied to master. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D81442/new/ https://reviews.llvm.org/D81442 Files: clang/include/clang/Driver/Options.td clang/lib/Basic/Targets/PPC.cpp clang/lib/Basic/Targets/PPC.h clang/test/Driver/ppc-dependent-options.cpp clang/test/Preprocessor/init-ppc64.c llvm/lib/Target/PowerPC/PPC.td llvm/lib/Target/PowerPC/PPCInstrPrefix.td llvm/lib/Target/PowerPC/PPCScheduleP9.td llvm/lib/Target/PowerPC/PPCSubtarget.cpp llvm/lib/Target/PowerPC/PPCSubtarget.h llvm/test/CodeGen/PowerPC/future-check-features.ll Index: llvm/test/CodeGen/PowerPC/future-check-features.ll === --- llvm/test/CodeGen/PowerPC/future-check-features.ll +++ llvm/test/CodeGen/PowerPC/future-check-features.ll @@ -1,7 +1,7 @@ -; RUN: llc -mattr=pcrelative-memops,prefix-instrs,paired-vector-memops \ +; RUN: llc -mattr=pcrelative-memops,prefix-instrs,paired-vector-memops,mma \ ; RUN: -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown \ ; RUN: -ppc-asm-full-reg-names %s -o - 2>&1 | FileCheck %s -; RUN: llc -mattr=pcrelative-memops,prefix-instrs,paired-vector-memops \ +; RUN: llc -mattr=pcrelative-memops,prefix-instrs,paired-vector-memops,mma \ ; RUN: -verify-machineinstrs -mtriple=powerpc64-unknown-unknown \ ; RUN: -ppc-asm-full-reg-names %s -o - 2>&1 | FileCheck %s Index: llvm/lib/Target/PowerPC/PPCSubtarget.h === --- llvm/lib/Target/PowerPC/PPCSubtarget.h +++ llvm/lib/Target/PowerPC/PPCSubtarget.h @@ -107,6 +107,7 @@ bool HasP10Vector; bool HasPrefixInstrs; bool HasPCRelativeMemops; + bool HasMMA; bool HasFCPSGN; bool HasFSQRT; bool HasFRE, HasFRES, HasFRSQRTE, HasFRSQRTES; @@ -260,6 +261,7 @@ bool hasP10Vector() const { return HasP10Vector; } bool hasPrefixInstrs() const { return HasPrefixInstrs; } bool hasPCRelativeMemops() const { return HasPCRelativeMemops; } + bool hasMMA() const { return HasMMA; } bool pairedVectorMemops() const { return PairedVectorMemops; } bool hasMFOCRF() const { return HasMFOCRF; } bool hasISEL() const { return HasISEL; } Index: llvm/lib/Target/PowerPC/PPCSubtarget.cpp === --- llvm/lib/Target/PowerPC/PPCSubtarget.cpp +++ llvm/lib/Target/PowerPC/PPCSubtarget.cpp @@ -73,6 +73,7 @@ HasP8Crypto = false; HasP9Vector = false; HasP9Altivec = false; + HasMMA = false; HasP10Vector = false; HasPrefixInstrs = false; HasPCRelativeMemops = false; Index: llvm/lib/Target/PowerPC/PPCScheduleP9.td === --- llvm/lib/Target/PowerPC/PPCScheduleP9.td +++ llvm/lib/Target/PowerPC/PPCScheduleP9.td @@ -41,9 +41,9 @@ let CompleteModel = 1; // Do not support SPE (Signal Processing Engine), prefixed instructions on - // Power 9, paired vector mem ops, PC relative mem ops, or instructions + // Power 9, paired vector mem ops, MMA, PC relative mem ops, or instructions // introduced in ISA 3.1. - let UnsupportedFeatures = [HasSPE, PrefixInstrs, PairedVectorMemops, + let UnsupportedFeatures = [HasSPE, PrefixInstrs, PairedVectorMemops, MMA, PCRelativeMemops, IsISA3_1]; } Index: llvm/lib/Target/PowerPC/PPCInstrPrefix.td === --- llvm/lib/Target/PowerPC/PPCInstrPrefix.td +++ llvm/lib/Target/PowerPC/PPCInstrPrefix.td @@ -455,6 +455,7 @@ def PrefixInstrs : Predicate<"Subtarget->hasPrefixInstrs()">; def IsISA3_1 : Predicate<"Subtarget->isISA3_1()">; def PairedVectorMemops : Predicate<"PPCSubTarget->pairedVectorMemops()">; +def MMA : Predicate<"PPCSubTarget->hasMMA()">; let Predicates = [PrefixInstrs] in { let Interpretation64Bit = 1, isCodeGenOnly = 1 in { Index: llvm/lib/Target/PowerPC/PPC.td === --- llvm/lib/Target/PowerPC/PPC.td +++ llvm/lib/Target/PowerPC/PPC.td @@ -238,6 +238,10 @@ SubtargetFeature<"paired-vector-memops", "PairedVectorMemops", "true", "32Byte load and store instructions", [FeatureISA3_0]>; +def FeatureMMA : SubtargetFeature<"mma", "HasMMA", "true", + "Enable MMA instructions", + [FeatureP8Vector, FeatureP9Altivec, + FeaturePairedVectorMemops]>; def FeaturePredictableSelectIsExpensive : SubtargetFeature<"predictable-select-expensive", @@ -343,7 +347,8 @@ // still exist with the exception of those we know are Power9 specific. list P10AdditionalFeatures = [DirectivePwr10, FeatureISA3_1, FeaturePrefixInstrs, - FeaturePCRelativeMemops, FeatureP10Vector,
[PATCH] D81442: [PowerPC] Add clang options to control MMA support
amyk accepted this revision. amyk added a comment. I think overall it LGTM. Comment at: llvm/lib/Target/PowerPC/PPCScheduleP9.td:44 // Do not support QPX (Quad Processing eXtension), SPE (Signal Processing // Engine), prefixed instructions on Power 9, PC relative mem ops, or // instructions introduced in ISA 3.1. nit: I think it would be good to add `MMA` to the comment here. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D81442/new/ https://reviews.llvm.org/D81442 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D81442: [PowerPC] Add clang options to control MMA support
bsaleil updated this revision to Diff 277858. bsaleil added a comment. Add test to check that the `mma` option is supported by the targets. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D81442/new/ https://reviews.llvm.org/D81442 Files: clang/include/clang/Driver/Options.td clang/lib/Basic/Targets/PPC.cpp clang/lib/Basic/Targets/PPC.h clang/test/Driver/ppc-dependent-options.cpp clang/test/Preprocessor/init-ppc64.c llvm/lib/Target/PowerPC/PPC.td llvm/lib/Target/PowerPC/PPCInstrPrefix.td llvm/lib/Target/PowerPC/PPCScheduleP9.td llvm/lib/Target/PowerPC/PPCSubtarget.cpp llvm/lib/Target/PowerPC/PPCSubtarget.h llvm/test/CodeGen/PowerPC/future-check-features.ll Index: llvm/test/CodeGen/PowerPC/future-check-features.ll === --- llvm/test/CodeGen/PowerPC/future-check-features.ll +++ llvm/test/CodeGen/PowerPC/future-check-features.ll @@ -1,7 +1,7 @@ -; RUN: llc -mattr=pcrelative-memops,prefix-instrs,paired-vector-memops \ +; RUN: llc -mattr=pcrelative-memops,prefix-instrs,paired-vector-memops,mma \ ; RUN: -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown \ ; RUN: -ppc-asm-full-reg-names %s -o - 2>&1 | FileCheck %s -; RUN: llc -mattr=pcrelative-memops,prefix-instrs,paired-vector-memops \ +; RUN: llc -mattr=pcrelative-memops,prefix-instrs,paired-vector-memops,mma \ ; RUN: -verify-machineinstrs -mtriple=powerpc64-unknown-unknown \ ; RUN: -ppc-asm-full-reg-names %s -o - 2>&1 | FileCheck %s Index: llvm/lib/Target/PowerPC/PPCSubtarget.h === --- llvm/lib/Target/PowerPC/PPCSubtarget.h +++ llvm/lib/Target/PowerPC/PPCSubtarget.h @@ -108,6 +108,7 @@ bool HasP10Vector; bool HasPrefixInstrs; bool HasPCRelativeMemops; + bool HasMMA; bool HasFCPSGN; bool HasFSQRT; bool HasFRE, HasFRES, HasFRSQRTE, HasFRSQRTES; @@ -267,6 +268,7 @@ bool hasP10Vector() const { return HasP10Vector; } bool hasPrefixInstrs() const { return HasPrefixInstrs; } bool hasPCRelativeMemops() const { return HasPCRelativeMemops; } + bool hasMMA() const { return HasMMA; } bool pairedVectorMemops() const { return PairedVectorMemops; } bool hasMFOCRF() const { return HasMFOCRF; } bool hasISEL() const { return HasISEL; } Index: llvm/lib/Target/PowerPC/PPCSubtarget.cpp === --- llvm/lib/Target/PowerPC/PPCSubtarget.cpp +++ llvm/lib/Target/PowerPC/PPCSubtarget.cpp @@ -78,6 +78,7 @@ HasP8Crypto = false; HasP9Vector = false; HasP9Altivec = false; + HasMMA = false; HasP10Vector = false; HasPrefixInstrs = false; HasPCRelativeMemops = false; Index: llvm/lib/Target/PowerPC/PPCScheduleP9.td === --- llvm/lib/Target/PowerPC/PPCScheduleP9.td +++ llvm/lib/Target/PowerPC/PPCScheduleP9.td @@ -43,8 +43,8 @@ // Do not support QPX (Quad Processing eXtension), SPE (Signal Processing // Engine), prefixed instructions on Power 9, PC relative mem ops, or // instructions introduced in ISA 3.1. - let UnsupportedFeatures = [HasQPX, HasSPE, PrefixInstrs, PairedVectorMemops, - PCRelativeMemops, IsISA3_1]; + let UnsupportedFeatures = [HasQPX, HasSPE, PrefixInstrs, MMA, + PairedVectorMemops, PCRelativeMemops, IsISA3_1]; } Index: llvm/lib/Target/PowerPC/PPCInstrPrefix.td === --- llvm/lib/Target/PowerPC/PPCInstrPrefix.td +++ llvm/lib/Target/PowerPC/PPCInstrPrefix.td @@ -428,6 +428,7 @@ def PrefixInstrs : Predicate<"Subtarget->hasPrefixInstrs()">; def IsISA3_1 : Predicate<"Subtarget->isISA3_1()">; def PairedVectorMemops : Predicate<"PPCSubTarget->pairedVectorMemops()">; +def MMA : Predicate<"PPCSubTarget->hasMMA()">; let Predicates = [PrefixInstrs] in { let Interpretation64Bit = 1, isCodeGenOnly = 1 in { Index: llvm/lib/Target/PowerPC/PPC.td === --- llvm/lib/Target/PowerPC/PPC.td +++ llvm/lib/Target/PowerPC/PPC.td @@ -241,6 +241,10 @@ SubtargetFeature<"paired-vector-memops", "PairedVectorMemops", "true", "32Byte load and store instructions", [FeatureISA3_0]>; +def FeatureMMA : SubtargetFeature<"mma", "HasMMA", "true", + "Enable MMA instructions", + [FeatureP8Vector, FeatureP9Altivec, + FeaturePairedVectorMemops]>; def FeaturePredictableSelectIsExpensive : SubtargetFeature<"predictable-select-expensive", @@ -346,7 +350,8 @@ // still exist with the exception of those we know are Power9 specific. list P10AdditionalFeatures = [DirectivePwr10, FeatureISA3_1, FeaturePrefixInstrs, - FeaturePCRelativeMemops, FeatureP10Vector,
[PATCH] D81442: [PowerPC] Add clang options to control MMA support
nemanjai accepted this revision. nemanjai added a comment. This revision is now accepted and ready to land. Since clang will now add `+/-mma` to the TargetFeatures list, please add a test case that specifies `-mattr=+/-mma` to `llc` to show that `llc` accepts it. Other than that, LGTM. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D81442/new/ https://reviews.llvm.org/D81442 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[PATCH] D81442: [PowerPC] Add clang options to control MMA support
bsaleil updated this revision to Diff 277580. bsaleil added a comment. Herald added subscribers: llvm-commits, hiraditya. Also add target options with this patch Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D81442/new/ https://reviews.llvm.org/D81442 Files: clang/include/clang/Driver/Options.td clang/lib/Basic/Targets/PPC.cpp clang/lib/Basic/Targets/PPC.h clang/test/Driver/ppc-dependent-options.cpp clang/test/Preprocessor/init-ppc64.c llvm/lib/Target/PowerPC/PPC.td llvm/lib/Target/PowerPC/PPCInstrPrefix.td llvm/lib/Target/PowerPC/PPCScheduleP9.td llvm/lib/Target/PowerPC/PPCSubtarget.cpp llvm/lib/Target/PowerPC/PPCSubtarget.h Index: llvm/lib/Target/PowerPC/PPCSubtarget.h === --- llvm/lib/Target/PowerPC/PPCSubtarget.h +++ llvm/lib/Target/PowerPC/PPCSubtarget.h @@ -108,6 +108,7 @@ bool HasP10Vector; bool HasPrefixInstrs; bool HasPCRelativeMemops; + bool HasMMA; bool HasFCPSGN; bool HasFSQRT; bool HasFRE, HasFRES, HasFRSQRTE, HasFRSQRTES; @@ -267,6 +268,7 @@ bool hasP10Vector() const { return HasP10Vector; } bool hasPrefixInstrs() const { return HasPrefixInstrs; } bool hasPCRelativeMemops() const { return HasPCRelativeMemops; } + bool hasMMA() const { return HasMMA; } bool pairedVectorMemops() const { return PairedVectorMemops; } bool hasMFOCRF() const { return HasMFOCRF; } bool hasISEL() const { return HasISEL; } Index: llvm/lib/Target/PowerPC/PPCSubtarget.cpp === --- llvm/lib/Target/PowerPC/PPCSubtarget.cpp +++ llvm/lib/Target/PowerPC/PPCSubtarget.cpp @@ -78,6 +78,7 @@ HasP8Crypto = false; HasP9Vector = false; HasP9Altivec = false; + HasMMA = false; HasP10Vector = false; HasPrefixInstrs = false; HasPCRelativeMemops = false; Index: llvm/lib/Target/PowerPC/PPCScheduleP9.td === --- llvm/lib/Target/PowerPC/PPCScheduleP9.td +++ llvm/lib/Target/PowerPC/PPCScheduleP9.td @@ -43,8 +43,8 @@ // Do not support QPX (Quad Processing eXtension), SPE (Signal Processing // Engine), prefixed instructions on Power 9, PC relative mem ops, or // instructions introduced in ISA 3.1. - let UnsupportedFeatures = [HasQPX, HasSPE, PrefixInstrs, PairedVectorMemops, - PCRelativeMemops, IsISA3_1]; + let UnsupportedFeatures = [HasQPX, HasSPE, PrefixInstrs, MMA, + PairedVectorMemops, PCRelativeMemops, IsISA3_1]; } Index: llvm/lib/Target/PowerPC/PPCInstrPrefix.td === --- llvm/lib/Target/PowerPC/PPCInstrPrefix.td +++ llvm/lib/Target/PowerPC/PPCInstrPrefix.td @@ -428,6 +428,7 @@ def PrefixInstrs : Predicate<"Subtarget->hasPrefixInstrs()">; def IsISA3_1 : Predicate<"Subtarget->isISA3_1()">; def PairedVectorMemops : Predicate<"PPCSubTarget->pairedVectorMemops()">; +def MMA : Predicate<"PPCSubTarget->hasMMA()">; let Predicates = [PrefixInstrs] in { let Interpretation64Bit = 1, isCodeGenOnly = 1 in { Index: llvm/lib/Target/PowerPC/PPC.td === --- llvm/lib/Target/PowerPC/PPC.td +++ llvm/lib/Target/PowerPC/PPC.td @@ -241,6 +241,10 @@ SubtargetFeature<"paired-vector-memops", "PairedVectorMemops", "true", "32Byte load and store instructions", [FeatureISA3_0]>; +def FeatureMMA : SubtargetFeature<"mma", "HasMMA", "true", + "Enable MMA instructions", + [FeatureP8Vector, FeatureP9Altivec, + FeaturePairedVectorMemops]>; def FeaturePredictableSelectIsExpensive : SubtargetFeature<"predictable-select-expensive", @@ -346,7 +350,8 @@ // still exist with the exception of those we know are Power9 specific. list P10AdditionalFeatures = [DirectivePwr10, FeatureISA3_1, FeaturePrefixInstrs, - FeaturePCRelativeMemops, FeatureP10Vector, FeaturePairedVectorMemops]; + FeaturePCRelativeMemops, FeatureP10Vector, FeatureMMA, + FeaturePairedVectorMemops]; list P10SpecificFeatures = []; list P10InheritableFeatures = !listconcat(P9InheritableFeatures, P10AdditionalFeatures); Index: clang/test/Preprocessor/init-ppc64.c === --- clang/test/Preprocessor/init-ppc64.c +++ clang/test/Preprocessor/init-ppc64.c @@ -643,6 +643,7 @@ // PPCPOWER10:#define _ARCH_PWR7 1 // PPCPOWER10:#define _ARCH_PWR8 1 // PPCPOWER10:#define _ARCH_PWR9 1 +// PPCPOWER10:#define __MMA__ 1 // // RUN: %clang_cc1 -E -dM -ffreestanding -triple=powerpc64-none-none -target-cpu future -fno-signed-char < /dev/null | FileCheck -match-full-lines -check-prefix PPCFUTURE %s // @@ -660,6 +661,10 @@ // PPCFUTURE:#define _ARCH_PWR8 1 //
[PATCH] D81442: [PowerPC] Add clang options to control MMA support
bsaleil updated this revision to Diff 277466. Herald added a subscriber: dang. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D81442/new/ https://reviews.llvm.org/D81442 Files: clang/include/clang/Driver/Options.td clang/lib/Basic/Targets/PPC.cpp clang/lib/Basic/Targets/PPC.h clang/test/Driver/ppc-dependent-options.cpp clang/test/Preprocessor/init-ppc64.c Index: clang/test/Preprocessor/init-ppc64.c === --- clang/test/Preprocessor/init-ppc64.c +++ clang/test/Preprocessor/init-ppc64.c @@ -643,6 +643,7 @@ // PPCPOWER10:#define _ARCH_PWR7 1 // PPCPOWER10:#define _ARCH_PWR8 1 // PPCPOWER10:#define _ARCH_PWR9 1 +// PPCPOWER10:#define __MMA__ 1 // // RUN: %clang_cc1 -E -dM -ffreestanding -triple=powerpc64-none-none -target-cpu future -fno-signed-char < /dev/null | FileCheck -match-full-lines -check-prefix PPCFUTURE %s // @@ -660,6 +661,10 @@ // PPCFUTURE:#define _ARCH_PWR8 1 // PPCFUTURE:#define _ARCH_PWR9 1 // PPCFUTURE:#define _ARCH_PWR_FUTURE 1 +// PPCFUTURE:#define __MMA__ 1 +// +// RUN: %clang_cc1 -E -dM -ffreestanding -triple=powerpc64-none-none -target-feature +mma -target-cpu power9 -fno-signed-char < /dev/null | FileCheck -check-prefix PPC-MMA %s +// PPC-MMA:#define __MMA__ 1 // // RUN: %clang_cc1 -E -dM -ffreestanding -triple=powerpc64-none-none -target-feature +float128 -target-cpu power9 -fno-signed-char < /dev/null | FileCheck -check-prefix PPC-FLOAT128 %s // PPC-FLOAT128:#define __FLOAT128__ 1 Index: clang/test/Driver/ppc-dependent-options.cpp === --- clang/test/Driver/ppc-dependent-options.cpp +++ clang/test/Driver/ppc-dependent-options.cpp @@ -63,6 +63,14 @@ // RUN: -check-prefix=CHECK-DEFAULT-P10 // RUN: not %clang -target powerpc64le-unknown-unknown -fsyntax-only \ +// RUN: -mcpu=power10 -std=c++11 -mno-vsx -mmma %s 2>&1 | \ +// RUN: FileCheck %s -check-prefix=CHECK-NVSX-MMA + +// RUN: not %clang -target powerpc64le-unknown-unknown -fsyntax-only \ +// RUN: -mcpu=future -std=c++11 -mno-vsx -mmma %s 2>&1 | \ +// RUN: FileCheck %s -check-prefix=CHECK-NVSX-MMA + +// RUN: not %clang -target powerpc64le-unknown-unknown -fsyntax-only \ // RUN: -mcpu=power10 -std=c++11 -mno-vsx -mpower10-vector %s 2>&1 | \ // RUN: FileCheck %s -check-prefix=CHECK-NVSX-P10V @@ -98,5 +106,6 @@ // CHECK-NVSX-DMV: error: option '-mdirect-move' cannot be specified with '-mno-vsx' // CHECK-NVSX-MULTI: error: option '-mfloat128' cannot be specified with '-mno-vsx' // CHECK-NVSX-MULTI: error: option '-mpower9-vector' cannot be specified with '-mno-vsx' +// CHECK-NVSX-MMA: error: option '-mmma' cannot be specified with '-mno-vsx' // CHECK-NVSX: Neither enabled // CHECK-VSX: VSX enabled Index: clang/lib/Basic/Targets/PPC.h === --- clang/lib/Basic/Targets/PPC.h +++ clang/lib/Basic/Targets/PPC.h @@ -59,6 +59,7 @@ // Target cpu features. bool HasAltivec = false; + bool HasMMA = false; bool HasVSX = false; bool HasP8Vector = false; bool HasP8Crypto = false; Index: clang/lib/Basic/Targets/PPC.cpp === --- clang/lib/Basic/Targets/PPC.cpp +++ clang/lib/Basic/Targets/PPC.cpp @@ -64,6 +64,8 @@ LongDoubleFormat = ::APFloat::IEEEdouble(); } else if (Feature == "-hard-float") { FloatABI = SoftFloat; +} else if (Feature == "+mma") { + HasMMA = true; } // TODO: Finish this list and add an assert that we've handled them // all. @@ -195,6 +197,8 @@ Builder.defineMacro("__FLOAT128__"); if (HasP9Vector) Builder.defineMacro("__POWER9_VECTOR__"); + if (HasMMA) +Builder.defineMacro("__MMA__"); if (HasP10Vector) Builder.defineMacro("__POWER10_VECTOR__"); @@ -231,6 +235,7 @@ // - direct-move // - float128 // - power9-vector +// - mma // - power10-vector // then go ahead and error since the customer has expressed an incompatible // set of options. @@ -253,6 +258,7 @@ Found |= FindVSXSubfeature("+direct-move", "-mdirect-move"); Found |= FindVSXSubfeature("+float128", "-mfloat128"); Found |= FindVSXSubfeature("+power9-vector", "-mpower9-vector"); + Found |= FindVSXSubfeature("+mma", "-mmma"); Found |= FindVSXSubfeature("+power10-vector", "-mpower10-vector"); // Return false if any vsx subfeatures was found. @@ -354,6 +360,7 @@ void PPCTargetInfo::addP10SpecificFeatures( llvm::StringMap ) const { Features["htm"] = false; // HTM was removed for P10. + Features["mma"] = true; Features["power10-vector"] = true; Features["pcrelative-memops"] = true; return; @@ -382,6 +389,7 @@ .Case("power10-vector", HasP10Vector) .Case("pcrelative-memops", HasPCRelativeMemops) .Case("spe", HasSPE) + .Case("mma", HasMMA) .Default(false); } @@ -397,6 +405,7 @@