[PATCH] D81707: [PowerPC][Power10] Implement Vector Clear Left/Rightmost Bytes Builtins in LLVM/Clang

[Amy Kwan via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rGcc95635b1bf2: [PowerPC][Power10] Implement Vector Clear 
Left/Rightmost Bytes Builtins in… (authored by amyk).

Changed prior to commit:
  https://reviews.llvm.org/D81707?vs=270283=272281#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D81707/new/

https://reviews.llvm.org/D81707

Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/lib/Headers/altivec.h
  clang/test/CodeGen/builtins-ppc-p10vector.c
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/Target/PowerPC/PPCInstrPrefix.td
  llvm/test/CodeGen/PowerPC/p10-string-ops.ll
  llvm/test/MC/Disassembler/PowerPC/p10insts.txt
  llvm/test/MC/PowerPC/p10.s

Index: llvm/test/MC/PowerPC/p10.s
===
--- llvm/test/MC/PowerPC/p10.s
+++ llvm/test/MC/PowerPC/p10.s
@@ -15,3 +15,9 @@
 # CHECK-BE: pextd 1, 2, 4 # encoding: [0x7c,0x41,0x21,0x78]
 # CHECK-LE: pextd 1, 2, 4 # encoding: [0x78,0x21,0x41,0x7c]
 pextd 1, 2, 4
+# CHECK-BE: vclrlb 1, 4, 3# encoding: [0x10,0x24,0x19,0x8d]
+# CHECK-LE: vclrlb 1, 4, 3# encoding: [0x8d,0x19,0x24,0x10]
+vclrlb 1, 4, 3
+# CHECK-BE: vclrrb 1, 4, 3# encoding: [0x10,0x24,0x19,0xcd]
+# CHECK-LE: vclrrb 1, 4, 3# encoding: [0xcd,0x19,0x24,0x10]
+vclrrb 1, 4, 3
Index: llvm/test/MC/Disassembler/PowerPC/p10insts.txt
===
--- llvm/test/MC/Disassembler/PowerPC/p10insts.txt
+++ llvm/test/MC/Disassembler/PowerPC/p10insts.txt
@@ -12,3 +12,9 @@
 
 # CHECK: pextd 1, 2, 4
 0x7c 0x41 0x21 0x78
+
+# CHECK: vclrlb 1, 4, 3
+0x10 0x24 0x19 0x8d
+
+# CHECK: vclrrb 1, 4, 3
+0x10 0x24 0x19 0xcd
Index: llvm/test/CodeGen/PowerPC/p10-string-ops.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/p10-string-ops.ll
@@ -0,0 +1,29 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
+; RUN:   FileCheck %s
+
+; These test cases aim to test the vector string isolate builtins on Power10.
+
+declare <16 x i8> @llvm.ppc.altivec.vclrlb(<16 x i8>, i32)
+declare <16 x i8> @llvm.ppc.altivec.vclrrb(<16 x i8>, i32)
+
+define <16 x i8> @test_vclrlb(<16 x i8> %a, i32 %n) {
+; CHECK-LABEL: test_vclrlb:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:vclrlb v2, v2, r5
+; CHECK-NEXT:blr
+entry:
+  %tmp = tail call <16 x i8> @llvm.ppc.altivec.vclrlb(<16 x i8> %a, i32 %n)
+  ret <16 x i8> %tmp
+}
+
+define <16 x i8> @test_vclrrb(<16 x i8> %a, i32 %n) {
+; CHECK-LABEL: test_vclrrb:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:vclrrb v2, v2, r5
+; CHECK-NEXT:blr
+entry:
+  %tmp = tail call <16 x i8> @llvm.ppc.altivec.vclrrb(<16 x i8> %a, i32 %n)
+  ret <16 x i8> %tmp
+}
Index: llvm/lib/Target/PowerPC/PPCInstrPrefix.td
===
--- llvm/lib/Target/PowerPC/PPCInstrPrefix.td
+++ llvm/lib/Target/PowerPC/PPCInstrPrefix.td
@@ -516,4 +516,12 @@
def PEXTD : XForm_6<31, 188, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
"pextd $rA, $rS, $rB", IIC_IntGeneral,
[(set i64:$rA, (int_ppc_pextd i64:$rS, i64:$rB))]>;
+   def VCLRLB : VXForm_1<397, (outs vrrc:$vD), (ins vrrc:$vA, gprc:$rB),
+ "vclrlb $vD, $vA, $rB", IIC_VecGeneral,
+ [(set v16i8:$vD,
+   (int_ppc_altivec_vclrlb v16i8:$vA, i32:$rB))]>;
+   def VCLRRB : VXForm_1<461, (outs vrrc:$vD), (ins vrrc:$vA, gprc:$rB),
+ "vclrrb $vD, $vA, $rB", IIC_VecGeneral,
+ [(set v16i8:$vD,
+   (int_ppc_altivec_vclrrb v16i8:$vA, i32:$rB))]>;
 }
Index: llvm/include/llvm/IR/IntrinsicsPowerPC.td
===
--- llvm/include/llvm/IR/IntrinsicsPowerPC.td
+++ llvm/include/llvm/IR/IntrinsicsPowerPC.td
@@ -417,6 +417,14 @@
   def int_ppc_altivec_vpextd : GCCBuiltin<"__builtin_altivec_vpextd">,
   Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty],
 [IntrNoMem]>;
+
+   // P10 Vector Clear Bytes
+   def int_ppc_altivec_vclrlb :  GCCBuiltin<"__builtin_altivec_vclrlb">,
+   Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_i32_ty],
+ [IntrNoMem]>;
+   def int_ppc_altivec_vclrrb :  GCCBuiltin<"__builtin_altivec_vclrrb">,
+   Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_i32_ty],
+ [IntrNoMem]>;
 }
 
 // Vector average.
Index: 

[PATCH] D81707: [PowerPC][Power10] Implement Vector Clear Left/Rightmost Bytes Builtins in LLVM/Clang

[Lei Huang via Phabricator via cfe-commits]

lei accepted this revision as: lei.
lei added a comment.
This revision is now accepted and ready to land.

LGTM
Minor nit to be addressed during commit.




Comment at: llvm/lib/Target/PowerPC/PPCInstrPrefix.td:522
+ [(set v16i8:$vD,
+ (int_ppc_altivec_vclrlb v16i8:$vA, i32:$rB))]>;
+   def VCLRRB : VXForm_1<461, (outs vrrc:$vD), (ins vrrc:$vA, gprc:$rB),

nit: indentation.



Comment at: llvm/lib/Target/PowerPC/PPCInstrPrefix.td:526
+ [(set v16i8:$vD,
+ (int_ppc_altivec_vclrrb v16i8:$vA, i32:$rB))]>;
 }

nit: indentation


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D81707/new/

https://reviews.llvm.org/D81707



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[PATCH] D81707: [PowerPC][Power10] Implement Vector Clear Left/Rightmost Bytes Builtins in LLVM/Clang

[Amy Kwan via Phabricator via cfe-commits]

amyk created this revision.
amyk added reviewers: saghir, nemanjai, power-llvm-team, PowerPC, hfinkel.
amyk added projects: clang, LLVM, PowerPC.
Herald added subscribers: shchenz, hiraditya.

This patch implements builtins for the following prototypes:

  vector signed char vec_clrl (vector signed char a, unsigned int n);
  vector unsigned char vec_clrl (vector unsigned char a, unsigned int n);
  vector signed char vec_clrr (vector signed char a, unsigned int n);
  vector signed char vec_clrr (vector unsigned char a, unsigned int n);

Depends on D80935 


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D81707

Files:
  clang/include/clang/Basic/BuiltinsPPC.def
  clang/lib/Headers/altivec.h
  clang/test/CodeGen/builtins-ppc-p10vector.c
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/lib/Target/PowerPC/PPCInstrPrefix.td
  llvm/test/CodeGen/PowerPC/p10-string-ops.ll
  llvm/test/MC/Disassembler/PowerPC/p10insts.txt
  llvm/test/MC/PowerPC/p10.s

Index: llvm/test/MC/PowerPC/p10.s
===
--- llvm/test/MC/PowerPC/p10.s
+++ llvm/test/MC/PowerPC/p10.s
@@ -15,3 +15,9 @@
 # CHECK-BE: pextd 1, 2, 4 # encoding: [0x7c,0x41,0x21,0x78]
 # CHECK-LE: pextd 1, 2, 4 # encoding: [0x78,0x21,0x41,0x7c]
 pextd 1, 2, 4
+# CHECK-BE: vclrlb 1, 4, 3# encoding: [0x10,0x24,0x19,0x8d]
+# CHECK-LE: vclrlb 1, 4, 3# encoding: [0x8d,0x19,0x24,0x10]
+vclrlb 1, 4, 3
+# CHECK-BE: vclrrb 1, 4, 3# encoding: [0x10,0x24,0x19,0xcd]
+# CHECK-LE: vclrrb 1, 4, 3# encoding: [0xcd,0x19,0x24,0x10]
+vclrrb 1, 4, 3
Index: llvm/test/MC/Disassembler/PowerPC/p10insts.txt
===
--- llvm/test/MC/Disassembler/PowerPC/p10insts.txt
+++ llvm/test/MC/Disassembler/PowerPC/p10insts.txt
@@ -12,3 +12,9 @@
 
 # CHECK: pextd 1, 2, 4
 0x7c 0x41 0x21 0x78
+
+# CHECK: vclrlb 1, 4, 3
+0x10 0x24 0x19 0x8d
+
+# CHECK: vclrrb 1, 4, 3
+0x10 0x24 0x19 0xcd
Index: llvm/test/CodeGen/PowerPC/p10-string-ops.ll
===
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/p10-string-ops.ll
@@ -0,0 +1,29 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:   -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
+; RUN:   FileCheck %s
+
+; These test cases aim to test the vector string isolate builtins on Power10.
+
+declare <16 x i8> @llvm.ppc.altivec.vclrlb(<16 x i8>, i32)
+declare <16 x i8> @llvm.ppc.altivec.vclrrb(<16 x i8>, i32)
+
+define <16 x i8> @test_vclrlb(<16 x i8> %a, i32 %n) {
+; CHECK-LABEL: test_vclrlb:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:vclrlb v2, v2, r5
+; CHECK-NEXT:blr
+entry:
+  %tmp = tail call <16 x i8> @llvm.ppc.altivec.vclrlb(<16 x i8> %a, i32 %n)
+  ret <16 x i8> %tmp
+}
+
+define <16 x i8> @test_vclrrb(<16 x i8> %a, i32 %n) {
+; CHECK-LABEL: test_vclrrb:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:vclrrb v2, v2, r5
+; CHECK-NEXT:blr
+entry:
+  %tmp = tail call <16 x i8> @llvm.ppc.altivec.vclrrb(<16 x i8> %a, i32 %n)
+  ret <16 x i8> %tmp
+}
Index: llvm/lib/Target/PowerPC/PPCInstrPrefix.td
===
--- llvm/lib/Target/PowerPC/PPCInstrPrefix.td
+++ llvm/lib/Target/PowerPC/PPCInstrPrefix.td
@@ -516,4 +516,12 @@
def PEXTD : XForm_6<31, 188, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
"pextd $rA, $rS, $rB", IIC_IntGeneral,
[(set i64:$rA, (int_ppc_pextd i64:$rS, i64:$rB))]>;
+   def VCLRLB : VXForm_1<397, (outs vrrc:$vD), (ins vrrc:$vA, gprc:$rB),
+ "vclrlb $vD, $vA, $rB", IIC_VecGeneral,
+ [(set v16i8:$vD,
+ (int_ppc_altivec_vclrlb v16i8:$vA, i32:$rB))]>;
+   def VCLRRB : VXForm_1<461, (outs vrrc:$vD), (ins vrrc:$vA, gprc:$rB),
+ "vclrrb $vD, $vA, $rB", IIC_VecGeneral,
+ [(set v16i8:$vD,
+ (int_ppc_altivec_vclrrb v16i8:$vA, i32:$rB))]>;
 }
Index: llvm/include/llvm/IR/IntrinsicsPowerPC.td
===
--- llvm/include/llvm/IR/IntrinsicsPowerPC.td
+++ llvm/include/llvm/IR/IntrinsicsPowerPC.td
@@ -426,6 +426,14 @@
   def int_ppc_altivec_vpextd : GCCBuiltin<"__builtin_altivec_vpextd">,
   Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty],
 [IntrNoMem]>;
+
+   // P10 Vector Clear Bytes
+   def int_ppc_altivec_vclrlb :  GCCBuiltin<"__builtin_altivec_vclrlb">,
+   Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty, llvm_i32_ty],
+ [IntrNoMem]>;
+